阅读说明：本技术 抑制噪声的电路 (Circuit for suppressing noise ) 是由 刘利书 于 2021-06-09 设计创作，主要内容包括：本申请公开了一种抑制噪声的电路。该电路包括脉冲产生模块和电平移位模块。脉冲产生模块的输出端连接电平移位模块的输入端,电平移位模块的输出端输出电平移位信号。电平移位模块包括第一支路和第二支路。第一支路包括第一开关。第一开关的控制端连接于电平移位模块的第一输入端。第一开关的第一通路端经第一阻抗切换模块连接于工作电压。第二支路包括第二开关。第二开关的控制端经第一延迟模块连接于电平移位模块的第一输入端。第二开关的第一通路端还连接于第一阻抗切换模块的控制端。第一开关的第一通路端连接于电平移位模块的第一输出端。第二开关控制第一阻抗切换模块在第一阻抗状态和第二阻抗状态之间切换。(The application discloses a circuit for suppressing noise. The circuit comprises a pulse generation module and a level shift module. The output end of the pulse generation module is connected with the input end of the level shift module, and the output end of the level shift module outputs a level shift signal. The level shift module comprises a first branch and a second branch. The first branch includes a first switch. The control end of the first switch is connected to the first input end of the level shift module. The first path end of the first switch is connected to the working voltage through the first impedance switching module. The second branch comprises a second switch. The control end of the second switch is connected to the first input end of the level shift module through the first delay module. The first path end of the second switch is also connected to the control end of the first impedance switching module. The first pass end of the first switch is connected to the first output end of the level shift module. The second switch controls the first impedance switching module to switch between a first impedance state and a second impedance state.)

1. A circuit (10) for suppressing noise, the circuit (10) comprising a pulse generation module (210) and a level shift module (220), an output (2102, 2104) of the pulse generation module (210) being connected to an input (N1, N2) of the level shift module (220), an output (Set, Reset) of the level shift module (220) outputting a level shifted signal (Set, Reset), the level shift module (220) comprising:

a first branch connected between an operating Voltage (VB) and a ground voltage (GND), the first branch including a first switch (LD1), a control terminal of the first switch (LD1) being connected to a first input terminal (N1) of the level shift module (220), a first path terminal of the first switch (LD1) being connected to the operating Voltage (VB) via a first impedance switching module (RR1), a second path terminal of the first switch (LD1) being connected to the ground voltage (GND); and

a second branch comprising a second switch (LD2), a control terminal of the second switch (LD2) being connected to the first input terminal (N1) of the level shifting module (220) via a first delay module (DU1), a first pass terminal and a second pass terminal of the second switch (LD2) being connected to the operating Voltage (VB) and the ground voltage (GND), respectively,

wherein the first path terminal of the second switch (LD2) is further connected to the control terminal of the first impedance switching module (RR1),

wherein a first path terminal of the first switch (LD1) is connected to a first output terminal (Set) of the level shift module (220),

wherein the second switch (LD2) controls the first impedance switching module (RR1) to switch between a first impedance state in which the first impedance switching module (RR1) has a first impedance and a second impedance state in which the first impedance switching module (RR1) has a second impedance,

wherein a mode of the first impedance is larger than a mode of the second impedance.

2. The circuit (10) of claim 1, wherein the first impedance switching module (RR1) is in the first impedance state when the second switch (LD2) is off, and wherein the first impedance switching module (RR1) is in the second impedance state when the second switch (LD2) is on.

3. The circuit (10) according to claim 1, wherein the first impedance switching module (RR1) comprises a first voltage drop switch (MP1) and a first capacitor (C1) connected between a first path terminal and a second path terminal of the first voltage drop switch (MP1), the first path terminal of the first voltage drop switch (MP1) is connected to the operating Voltage (VB), the second path terminal of the first voltage drop switch (MP1) is connected to the first path terminal of the first switch (LD1), and the control terminal of the first impedance switching module (RR1) is the control terminal of the first voltage drop switch (MP 1).

4. The circuit (10) of claim 1, wherein the first impedance switching module (RR1) comprises a first voltage drop switch (MP1) and a fifth resistor (R5) connected between a first path terminal and a second path terminal of the first voltage drop switch (MP1), the second path terminal of the first voltage drop switch (MP1) is connected to the first path terminal of the first switch (LD1), and the control terminal of the first impedance switching module (RR1) is the control terminal of the first voltage drop switch (MP 1).

5. The circuit (10) according to claim 4, wherein the first path terminal of the first voltage drop switch (MP1) is connected to the operating Voltage (VB) via a seventh resistor (R7).

6. The circuit (10) of claim 3, wherein the first impedance switching module (RR1) further comprises a third resistor (R3), and the first capacitor (C1) and the third resistor (R3) are connected in series between the first path terminal and the second path terminal of the first droop switch (MP 1).

7. The circuit (10) of claim 1, wherein a first path terminal of the second switch (LD2) is connected to the operating Voltage (VB) via a first resistor (R1).

8. The circuit (10) of claim 3, wherein the first capacitor (C1) is connected in parallel with a first zener diode (D1).

9. The circuit (10) of claim 1, wherein the first switch (LD1) and the second switch (LD2) are laterally diffused metal oxide semiconductor switches.

10. The circuit (10) of claim 3, wherein the first droop switch (MP1) is a PMOS transistor.

11. The circuit (10) of claim 1, wherein the level shifting module (220) further comprises:

a third branch connected between the operating Voltage (VB) and the ground voltage (GND), the third branch including a third switch (LD3), a control terminal of the third switch (LD3) being connected to the second input terminal (N2) of the level shift module (220), a first path terminal of the third switch (LD3) being connected to the operating Voltage (VB) via a second impedance switching module (RR2), a second path terminal of the third switch (LD3) being connected to the ground voltage (GND), and

a fourth branch comprising a fourth switch (LD4), a control terminal of the fourth switch (LD4) being connected to the second input terminal (N2) of the level shifting module (220) via a second delay module (DU2), a first pass terminal and a second pass terminal of the fourth switch (LD4) being connected to the operating Voltage (VB) and the ground voltage (GND), respectively,

wherein a first path terminal of the fourth switch (LD4) is connected to a control terminal of the second impedance switching module (RR2),

wherein a first path terminal of the third switch (LD3) is connected to a second output terminal (Reset) of the level shift module (220),

wherein the fourth switch (LD4) controls the second impedance switching module (RR2) to switch between a third impedance state in which the second impedance switching module (RR2) has a third impedance and a fourth impedance state in which the second impedance switching module (RR2) has a fourth impedance, the modulus of the third impedance being greater than the modulus of the fourth impedance.

12. The circuit (10) of claim 11, wherein the second impedance switching module (RR2) is in the third impedance state when the fourth switch (LD4) is off, and wherein the second impedance switching module (RR2) is in the fourth impedance state when the fourth switch (LD4) is on.

13. The circuit (10) according to claim 11, wherein the second impedance switching module (RR2) comprises a second voltage drop switch (MP2) and a second capacitor (C2) connected between a first path terminal and a second path terminal of the second voltage drop switch (MP2), the first path terminal of the second voltage drop switch (MP2) is connected to the operating Voltage (VB), the second path terminal of the second voltage drop switch (MP2) is connected to the first path terminal of the third switch (LD3), and the control terminal of the second impedance switching module (RR2) is the control terminal of the second voltage drop switch (MP 2).

14. The circuit (10) according to claim 11, wherein the second impedance switching module (RR2) comprises a second voltage drop switch (MP2) and a sixth resistor (R6) connected between a first path terminal and a second path terminal of the second voltage drop switch (MP2), the first path terminal of the second voltage drop switch (MP2) is connected to the operating Voltage (VB), the second path terminal of the second voltage drop switch (MP2) is connected to the first path terminal of the third switch (LD3), and the control terminal of the second impedance switching module (RR2) is the control terminal of the second voltage drop switch (MP 2).

15. The circuit (10) of claim 13, wherein the second impedance switching module (RR2) further comprises a fourth resistor (R4), and the second capacitor (C2) and the fourth resistor (R4) are connected in series between the first path terminal and the second path terminal of the second droop switch (MP 2).

16. The circuit (10) according to claim 14, wherein the first path terminal of the second droop switch (MP2) is connected to the operating Voltage (VB) via an eighth resistor (R8).

17. The circuit (10) of claims 3 and 13,

the electrical parameters of the first switch (LD1) and the third switch (LD3) are the same,

the second switch (LD2) and the fourth switch (LD4) have the same electrical parameters,

the electrical parameters of the first voltage drop switch (MP1) and the second voltage drop switch (MP2) are the same,

the electrical parameters of the first capacitor (C1) and the second capacitor (C2) are the same.

18. The circuit (10) of claim 11,

a first input (N1) of the level shift module (220) is connected to a first output (2102) of the pulse generation module (210),

the second input (N2) of the level shift module (220) is connected to the second output (2104) of the pulse generation module (210).

19. The circuit (10) of claim 11, wherein the circuit (10) further comprises an RS flip-flop (230), a first trigger terminal (S) of the RS flip-flop (230) is connected to the first output terminal (Set) of the level shifting module (220), and a second trigger terminal (R) of the RS flip-flop (230) is connected to the second output terminal (Reset) of the level shifting module (220).

20. The circuit (10) of claim 19, wherein a first trigger terminal (S) of the RS flip-flop (230) is connected to a first output terminal (Set) of the level shift module (220) via a pulse filter (250), and a second trigger terminal (R) of the RS flip-flop (230) is connected to a second output terminal (Reset) of the level shift module (220) via a pulse filter (250).

Technical Field

The present invention relates to electronic circuit technology, and more particularly, to a circuit for suppressing dVs/dt noise.

Background

In a gate drive circuit such as an IGBT drive chip, voltage variation often occurs to cause dVs/dt noise, accompanied by on/off of switches in the circuit, lightning surge, noise of associated devices, and the like. Where Vs is the high side floating return voltage or the common voltage between the high side and the low side in the gate drive circuit. For this reason, the gate driving circuit generally includes a level shift circuit using a pulse in order to perform level conversion from a low voltage signal to a high voltage signal, for example. dVs/dt noise may cause displacement currents in the level shifting circuit. This shift current may cause a logic inversion of the output of the level shift circuit and may eventually cause a false output of the entire circuit.

The effect of the shift current is generally reduced by adding a filter circuit after the level shift circuit. However, the filter width of the filter circuit is limited, and sufficient dVs/dt noise suppression capability cannot be obtained.

Disclosure of Invention

The application provides a circuit for suppressing noise, which aims to solve the problem that the dVs/dt noise suppression capability of a gate driving circuit in the prior art is insufficient.

In order to solve the above problems, the present application adopts a technical solution that: a circuit for suppressing noise is provided. The circuit comprises a pulse generation module and a level shift module. The output end of the pulse generation module is connected with the input end of the level shift module, and the output end of the level shift module outputs a level shift signal. The level shift module comprises a first branch and a second branch. The first branch is connected between the operating voltage and the ground voltage. The first branch includes a first switch. The control end of the first switch is connected to the first input end of the level shift module. The first path end of the first switch is connected to the working voltage through the first impedance switching module. The second path end of the first switch is connected to the ground voltage. The second branch is connected between the operating voltage and the ground voltage. The second branch comprises a second switch. The control end of the second switch is connected to the first input end of the level shift module through the first delay module. The first path terminal and the second path terminal of the second switch are connected to the operating voltage and the ground voltage, respectively. The first path end of the second switch is also connected to the control end of the first impedance switching module. The first pass end of the first switch is connected to the first output end of the level shift module. . The second switch controls the first impedance switching module to switch between a first impedance state and a second impedance state. In a first impedance state, the first impedance switching module has a first impedance. In the second impedance state, the first impedance switching module has a second impedance. The mode of the first impedance is larger than the mode of the second impedance.

Different from the prior art, the first branch circuit comprising the first impedance switching module and the second branch circuit controlling the on-off of the first impedance switching module are arranged, so that the time length and voltage fluctuation of dVs/dt noise influencing the first branch circuit are reduced, and the dVs/dt noise suppression capability of the circuit is enhanced.

Drawings

To more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

FIG. 1 is a schematic circuit diagram according to one embodiment of the present application.

Fig. 2 is a schematic diagram of a Set signal over time according to an embodiment of the present application.

Fig. 3 is a schematic circuit diagram according to yet another embodiment of the present application.

Fig. 4 is a schematic circuit diagram according to another embodiment of the present application.

Fig. 5 is a schematic circuit diagram according to another embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring specifically to fig. 1, fig. 1 is a schematic circuit diagram illustrating a gate driving circuit 10 according to an embodiment of the present application.

As shown in fig. 1, the gate driving circuit 10 includes a high-side driving part 20 and a low-side driving part 30. The high side driver 240 of the high side driving part 20 outputs a high side driving output HO to control the high side switching element T₁. The low side driver 260 of the low side driving part 30 outputs the low side driving output LO to control the low side switching element T₂。

Optionally, a high-side switching element T₁And a low-side switching element T₂Connected in series between the bus voltage VH and the ground voltage GND. High-voltage side switching element T₁And a low-side switching element T₂The voltage at the connection point therebetween is the high-side floating return voltage Vs. Optionally, a high-side switching element T₁And a low-side switching element T₂Alternately conducting. When the high-voltage side switching element T₁Conducting and low-voltage side switch element T₂At shutdown, the high side floating return voltage Vs is substantially equal to the bus voltage VH, i.e., Vs is at a high potential. When the high-voltage side switch element T is used₁Off and low side switching element T₂At turn-on, the high-side floating return voltage Vs is substantially equal to the ground voltage GND.

Alternatively, a load (not shown in the drawings) is connected between the high-side floating return voltage Vs and the ground voltage GND.

Optionally, the floating voltage VB (also called the working voltage VB) on the high-voltage side is passed through a bootstrap diode D_{Bootstrapping}Connected to a supply voltage VCC. Optionally, the floating voltage VB at the high-voltage side passes through the bootstrap capacitor C_{Bootstrapping}Connected to the high side floating return voltage Vs. When the high-side floating return voltage Vs varies between the bus voltage VH and the ground voltage GND, a dVs/dt noise is generated in the high-side floating return voltage Vs. The dVs/dt noise is passed through a bootstrap capacitor C_{Bootstrapping}Conducted to the high side floating voltage VB, generating the same dVs/dt noise in VB.

The high-side driving portion 20 will be described in detail with continued reference to fig. 1. The present application does not limit the specific implementation form of the low pressure side driving portion 30.

As shown in fig. 1, the high side driving part 20 includes a pulse generating module 210, a level shifting module 220, an RS flip-flop 230, and a high side driver 240 connected in stages. Specifically, the pulse generation module 210 receives a logic input IN from the outside, and outputs a first pulse signal and a second pulse signal. The level shift module 220 receives the first pulse signal and the second pulse signal from the pulse generation module 110 and outputs a level shifted signal. The level shift signals include a Set signal and a Reset signal. The RS flip-flop 230 receives the Set signal and the Reset signal from the level shift module 220, and outputs a trigger signal SQ. High side driver 240 receives a trigger signal SQ from RS flip-flop 230 and outputs a high side driver output HO. When the high-side driving output HO is at high level (H), the high-side switching element T₁And conducting. When the high-side driving output HO is at a low level (L), the high-side switching element T₁And (6) turning off.

Optionally, the level shift module 220 is connected between the high-side floating voltage VB and the ground voltage GND. The RS flip-flop 230 and the high side driver 240 are each connected between the high side floating voltage VB and the high side floating return voltage Vs to obtain power required for operation.

The respective modules of the high-side driving part 20 are described in detail below.

As shown in fig. 1, the pulse generation module 210 includes an input 2100 and at least two outputs. The at least two output terminals are a first output terminal Set and a second output terminal Reset, respectively. The pulse generation module 210 receives a logic input IN from the outside from an input terminal 2100. The logic input IN is used to control the high-side switching element T via the high-side driver part 20₁. The pulse generating module 210 generates a corresponding first pulse signal and a second pulse signal according to the logic input IN. The first pulse signal is output from the first output terminal Set, and the second pulse signal is output from the second output terminal Reset. Optionally, pulses of the first pulse signal and the second pulse signalThe width is 100ns-600 ns. Optionally, the first pulse signal and the second pulse signal are both square wave signals. Optionally, the high-level portions of the first pulse signal and the second pulse signal do not overlap in time to prevent the RS flip-flop 230 from an unknown state.

As shown in fig. 1, the level shift module 220 is disposed at a next stage of the pulse generation module 210. The level shift module 220 includes a first input terminal N1 and a second input terminal N2. The first input terminal N1 is connected to the first output terminal Set of the pulse generating module 210 for receiving the first pulse signal. The second input terminal N2 is connected to the second output terminal Reset of the pulse generating module 210 for receiving the second pulse signal.

The level shift module 220 further includes a first branch and a second branch for outputting the Set signal.

The first branch is connected between the high-side floating voltage VB and the ground voltage GND. The first branch includes a first switch LD 1. The control terminal of the first switch LD1 is directly connected to the first input terminal N1 of the level shift module 220. A first path terminal of the first switch LD1 is connected to the operating voltage VB via the first impedance switching module RR1, and a second path terminal of the first switch LD1 opposite to the first path terminal is connected to the ground voltage GND. Optionally, the first switch LD1 is a Laterally Diffused Metal Oxide Semiconductor (LDMOS) switch. The first switch LD1 may be other types of switches, and the present application is not limited thereto. Optionally, the first path terminal of the first switch LD1 is a drain. Optionally, the first switch LD1 further includes a drain capacitor C_d1。

Optionally, the first impedance switching module RR1 includes a first capacitor C1, a first voltage drop switch MP1, and a first zener diode D1 connected in parallel between the first path terminal of the first switch LD1 and the high-side floating voltage VB. Optionally, the first zener diode D1 is a zener diode. Optionally, the first voltage drop switch MP1 is a PMOS transistor. Optionally, a first path terminal of the first voltage drop switch MP1 is connected to the operating voltage VB, and a second path terminal of the first voltage drop switch MP1 is connected to the first path terminal of the first switch LD 1. Optionally, two ends of the first capacitor C1 are respectively connected to the first path terminal of the first switch LD1 and the high-side floating voltage VB. Optionally, the anode of the first zener diode D1 is connected to the first path terminal of the first switch LD1, and the cathode of the first zener diode D1 is connected to the high-side floating voltage VB. Optionally, the clamping voltage of the first zener diode D1 is 15V, which is not limited in this application.

Alternatively, when the first droop switch MP1 is turned off, the first impedance switching module RR1 is in the first impedance state and has a first impedance between the first path terminal of the first switch LD1 and the high-side floating voltage VB. When the first droop switch MP1 is turned on, the first impedance switching module RR1 is in the second impedance state and has a second impedance between the first path terminal of the first switch LD1 and the high-side floating voltage VB. Optionally, the mode of the first impedance is larger than the mode of the second impedance. Those skilled in the art will readily appreciate that impedance generally includes three types of resistance, capacitive reactance, and inductive reactance. In this embodiment, the impedance of the first impedance switching module RR1 includes a resistance and a capacitive reactance.

Referring to fig. 1, when the first droop switch MP1 is turned off, a first impedance between the first path terminal of the first switch LD1 and the high-side floating voltage VB isWherein C1 is the capacitance of the first capacitor C1. ω is the frequency of the voltage across the first capacitor C1. Since the voltage across the first capacitor C1 is generally a dc voltage, i.e., ω is zero. Thus, the mode of the first impedance can be considered infinite. When the first droop switch MP1 is turned on, a second impedance between the first path terminal of the first switch LD1 and the high-side floating voltage VB is R_MP1. Obviously, the mode of the second impedance is smaller than the mode of the first impedance. The second branch is connected between the high-side floating voltage VB and the ground voltage GND. The second branch includes a second switch LD 2. Optionally, the second switch LD2 is an LDMOS switch. The control terminal of the second switch LD2 is connected to the first input terminal N1 of the level shift module 220 via the first delay unit DU 1. The first path terminal of the second switch LD2 is connected to the high side floating voltage VB via a first resistor R1. The second path terminal of the second switch LD2 is connected to the ground voltage GND. Optionally, the first path terminal of the second switch LD2 is further connectedThe control terminal of the first voltage drop switch MP1 is used for controlling the first voltage drop switch MP1 to turn on and off. The control terminal of the first voltage drop switch MP1 is the control terminal of the first impedance switching module RR 1. Optionally, when the second switch LD2 is turned off, the first voltage drop switch MP1 is turned off, and the first impedance switching module RR1 is in the first impedance state. Optionally, when the second switch LD2 is turned on, the first drop switch MP1 is turned on, and the first impedance switching module RR1 is in the second impedance state.

Optionally, the first delay unit DU1 is configured to convert the first pulse signal into a first delayed pulse signal with a certain delay with respect to the first pulse signal. Optionally, the first pulse signal and the first delayed pulse signal have the same waveform. The time length of the delay is, for example, 100ns to 600ns, which is not limited in this application. Optionally, the time length of the delay is greater than the pulse width of the first pulse signal. The first pulse signal is input to the control terminal of the first switch LD1 to control the turn-on and turn-off of the first switch LD1, and the first delayed pulse signal is input to the control terminal of the second switch LD2 to control the turn-on and turn-off of the second switch LD 2.

Optionally, the first output terminal Set of the level shifting module 220 is connected to the first output terminal of the first switch LD1 to output the Set signal. Optionally, the Set signal is used to control the high-side driver output HO to a high level, so that the high-side switching element T₁And conducting.

The level shifting module 220 further includes a third branch and a fourth branch for outputting a Reset signal.

The third branch is connected between the high-side floating voltage VB and the ground voltage GND. The third branch includes a third switch LD 3. The control terminal of the third switch LD3 is directly connected to the second input terminal N2 of the level shifting module 220. A first path terminal of the third switch LD3 is connected to the operating voltage VB via the second impedance switching module RR2, and a second path terminal of the third switch LD3 opposite to the first path terminal is connected to the ground voltage GND. Optionally, the third switch LD3 is an LDMOS switch. The third switch LD3 may be other types of switches, and the application is not limited in this respect. Optionally, the first pass end of the third switch LD3 is a drain. Optionally, a third openingThe switch LD3 also includes a drain capacitance C_d2。

Optionally, the second impedance switching module RR2 includes a second capacitor C2, a second voltage drop switch MP2, and a second zener diode D2 connected in parallel between the first path terminal of the third switch LD3 and the high-side floating voltage VB. Optionally, the second zener diode D2 is a zener diode. Optionally, the second voltage drop switch MP2 is a PMOS transistor. Optionally, a first path terminal of the second voltage drop switch MP2 is connected to the operating voltage VB, and a second path terminal of the second voltage drop switch MP2 is connected to the first path terminal of the third switch LD 3. Optionally, two ends of the second capacitor C2 are respectively connected to the first path terminal of the third switch LD3 and the high-side floating voltage VB. Optionally, the anode of the second zener diode D2 is connected to the first path terminal of the third switch LD3, and the cathode of the second zener diode D2 is connected to the high-side floating voltage VB. Optionally, the clamping voltage of the second zener diode D2 is 15V, which is not limited in this application.

Alternatively, when the second droop switch MP2 is turned off, the second impedance switching module RR2 is in the third impedance state and has a third impedance between the first path terminal of the third switch LD3 and the high-side floating voltage VB. When the second droop switch MP2 is turned on, the second impedance switching module RR2 is in the fourth impedance state and has a fourth impedance between the first path terminal of the third switch LD3 and the high-side floating voltage VB. Optionally, a mode of the third impedance is larger than a mode of the fourth impedance.

Referring to fig. 1, when the second droop switch MP2 is turned off, a third impedance between the first path terminal of the third switch LD3 and the high-side floating voltage VB is. Wherein C2 is the capacitance of the second capacitor C2. ω is the frequency of the voltage across the second capacitor C2. Since the voltage across the second capacitor C2 is generally a dc voltage, i.e., ω is zero. Therefore, the mode of the third impedance can be regarded as infinite. When the second droop switch MP2 is turned on, a fourth impedance between the first path terminal of the third switch LD3 and the high-side floating voltage VB is R_MP2. Obviously, the fourthThe mode of the impedance is smaller than the mode of the third impedance.

The fourth branch is connected between the high-side floating voltage VB and the ground voltage GND. The fourth branch includes a fourth switch LD 4. Optionally, the fourth switch LD4 is an LDMOS switch. The control terminal of the fourth switch LD4 is connected to the second input terminal N2 of the level shift module 220 via the second delay unit DU 2. The first path terminal of the fourth switch LD4 is connected to the high-side floating voltage VB via the second resistor R2. The second path terminal of the fourth switch LD4 is connected to the ground voltage GND. Optionally, the first path end of the fourth switch LD4 is further connected to the control end of the second voltage drop switch MP2, and is used for controlling the second voltage drop switch MP2 to be turned on and off. The control terminal of the second voltage drop switch MP2 is the control terminal of the second impedance switching module RR 2.

Optionally, the second delay unit DU2 is configured to convert the second pulse signal into a second delayed pulse signal with a delay relative to the second pulse signal. Optionally, the second pulse signal has the same waveform as the second delayed pulse signal. The time length of the delay is, for example, 100ns to 600ns, which is not limited in this application. Optionally, the time length of the delay is greater than the pulse width of the second pulse signal. Accordingly, the second pulse signal is input to the control terminal of the third switch LD3 to control the turn-on and turn-off of the third switch LD3, and the second delayed pulse signal is input to the control terminal of the fourth switch LD4 to control the turn-on and turn-off of the fourth switch LD 4.

Optionally, the second output terminal Reset of the level shifting module 220 is connected to the first output terminal of the second switch LD2 to output a Reset signal. Optionally, the Reset signal is used to control the high side driver output HO low to cause the high side switching element T₁And (6) turning off.

Optionally, the electrical parameters of the first switch LD1 and the second switch LD2 are the same. The electrical parameters of the first capacitor C1 and the second capacitor C2 are the same. The first and second buck switches MP1 and MP2 have the same electrical parameters. The electrical parameters of the first delay unit DU1 and the second delay unit DU2 are the same. The electrical parameters of the first resistor R1 and the second resistor R2 are the same. The electrical parameters of the first zener diode D1 and the second zener diode D2 are the same. Here, the electrical parameter refers to a parameter that affects the electrical property of the element, for example, resistance, capacitance, inductance, and material, all of which can affect the electrical property of the element.

Optionally, the electrical parameters of the first branch and the third branch are completely the same, and the electrical parameters of the second branch and the fourth branch are completely the same. This helps prevent fluctuations or noise due to asymmetry of current or voltage between the branches, etc.

Referring to fig. 1, the RS flip-flop 230 is disposed at the next stage of the level shift module 220. Optionally, the RS flip-flop 230 is an active low flip-flop, and includes a first trigger end S, a second trigger end R, and a flip-flop output end Q. Optionally, the first trigger terminal S receives the Set signal and changes a level state thereof. The second trigger terminal R receives the above Reset signal and changes its level state. The trigger output end Q outputs a driver control signal according to the level state of the first trigger end S and the level state of the second trigger end R. The present application is not limited to the relationship between the level state of the first trigger terminal S and the level state of the second trigger terminal R and the driver control signal.

As shown in fig. 1, optionally, a pulse filter 250 is further disposed between the RS flip-flop 230 and the level shift module 220. The pulse filter 250 serves to filter noise in the Set signal and the Reset signal and transmit the filtered Set signal and Reset signal to the RS flip-flop 230.

Referring to fig. 1, the high side driver 240 is disposed at the next stage of the RS flip-flop 230. Optionally, the high-side driver 240 receives the driver control signal and outputs a corresponding high-side driver output HO to control the high-side switching element T₁On and off. This application is not described in detail herein.

Referring to fig. 1 and fig. 2, the operation principle of the level shift module 220 is illustrated by using a first branch and a second branch as an example. Fig. 2 shows the time-varying relationship of the Set signal output by the level shift module 220. As shown in fig. 1, when the first switch LD1 is turned off, the first branch is opened, and the first output terminal Set of the level shift module 220 is connected to the high-side floating voltage VB through the first capacitor C1. At this time, the first output terminal Set of the level shift module 220 has the same potential as the high side floating voltage VB. As shown in fig. 2, at time 0, the first switch LD1 receives the first pulse signal and the first pulse signal is at a high level, and the first switch LD1 is turned on. The first capacitor C1 starts to be charged rapidly until the first capacitor C1 is away from the first switch LD1 at the same potential as the high-side floating voltage VB and the second terminal of the first capacitor C1 is at the low potential VL near the ground voltage GND. Alternatively, the low potential VL is slightly larger than the ground voltage GND due to the influence of the first switch LD 1. The potential of the first output terminal Set of the level shift module 220 or the potential of the Set signal is equal to the second terminal of the first capacitor C1, and also drops from the high-side floating voltage VB to the low potential VL.

Optionally, the time 0 is only used to refer to a time, and does not limit the specific time.

Optionally, during the charging process, the first zener diode D1 may prevent the voltage difference across the first capacitor C1 from being too large, so as to protect the first capacitor C1.

Optionally, the duration of the first pulse signal is te. Then at time te, the first pulse signal ends and the first switch LD1 turns off, as shown in fig. 2. Since the first capacitor C1 has no discharge path at this time, the potential across the first capacitor C1 remains unchanged. Therefore, as shown in fig. 2, the potential of the first output terminal Set of the level shift module 220 or the potential of the Set signal remains unchanged.

The delay time generated by the first delay unit DU1 is defined as td. Accordingly, at the time td, the first delay unit DU1 converts the first pulse signal into the first delayed pulse signal and inputs the first delayed pulse signal to the control terminal of the second switch LD2, and the second switch LD2 is turned on. The second branch starts to generate a current which causes a voltage drop across the first resistor R1. The voltage drop makes the control terminal of the first voltage drop switch MP1 connected to the second branch at a high voltage level, and the first voltage drop switch MP1 is turned on. At this time, the first capacitor C1 starts to discharge until the second terminal of the first capacitor C1 is at the high potential VG near the high side floating voltage VB. Alternatively, the high potential VG may be equal to the high side floating voltage VB. Alternatively, the high voltage VG may be slightly less than the high side floating voltage VB due to the influence of the first voltage drop switch MP1 and the influence of noise that may be present in the circuit. The potential of the first output terminal Set of the level shift module 220 or the potential of the Set signal rises from the low potential VL to the high potential VG, as the second terminal of the first capacitor C1 does.

Optionally, the duration te of the first pulse signal is smaller than the delay time td generated by the first delay unit DU 1.

Thus, through the above process, the Set signal that is active low as shown in fig. 2 is formed. The Set signal includes a rising edge and a falling edge with a low level segment therebetween. The low level segment is at a low voltage level VL, and the duration of the low voltage level VL is equal to the delay time td generated by the first delay unit DU1 minus the charging time of the first capacitor C1. The procedure for generating the Reset signal active low in the third branch and the fourth branch is similar to the procedure for generating the Set signal active low in the first branch and the second branch. And will not be described in detail herein.

The effects of dVs/dt noise described above will be described below with reference to FIG. 1, taking a first branch and a second branch as examples. The resulting effect of dVs/dt noise in the third and fourth branches is similar to the effect in the first and second branches and is therefore not described in detail herein.

In the first case: when the first switch LD1 is turned on and the second switch LD2 is turned off, i.e., in the time period between 0 and te shown in fig. 2, the first voltage drop switch MP1 of the first branch is not turned on either. The dVs/dt noise generated in the high side floating voltage VB at this time may generate a charging current or a discharging current in the first capacitor C1. However, the first output terminal Set of the level shift module 220 is always stabilized around the low potential VL. Therefore, the dVs/dt noise generated in the high-side floating voltage VB at this time does not affect the Set signal, and further does not affect the operation of the high-side driver 240 through the level shift module 220.

In the second case: when both the first switch LD1 and the second switch LD2 are turned off, i.e., in the time period between te and td shown in fig. 2, both the first branch and the second branch are opened. At this time, the Set signal terminal is disconnected from the high-side floating voltage VB, and the Set signal terminal in the level shift module 220 is kept near the low potential VL. Therefore, the dVs/dt noise generated in the high-side floating voltage VB does not affect the Set signal at this time, and further does not affect the operation of the high-side driver 240 through the level shift module 220.

In the third case: when the first switch LD1 is turned off and the second switch LD2 is turned on, i.e., in the portion after td shown in fig. 2, the first voltage drop switch MP1 of the first branch is turned on. At this time, the first output terminal Set of the level shift module 220 is connected to the high-side floating voltage VB through the turned-on first voltage drop switch MP 1. The dVs/dt noise generated in the high side floating voltage VB may be conducted to the first output terminal Set of the level shifting module 220. The dVs/dt noise is coupled to the capacitor C of the first switch LD1_d1The coupling, the displacement current generated in the first branch is:

the displacement current I₁The voltage drop generated at the first voltage drop switch MP1 is

Wherein R is_MP1The on-resistance of the first voltage drop switch MP1 after it is turned on.

Accordingly, in this case, a magnitude ofThe voltage of (2) fluctuates.

To prevent the logic inversion of the Set signal, which in turn causes the high-side switching element T₁Is that the voltage fluctuation in the Set signal cannot exceed the first voltage threshold V_T。V_TThe setting can be set by the user according to the actual situation, which is not limited in the present application. Then:

then, as can be seen from equation (1.3):

on-resistance R of switch MP1 due to first voltage drop_MP1Small, and therefore, the value on the right side in equation (1.4) is relatively large. That is to say that the first and second electrodes,the upper safety limit of (2) is greatly improved compared with the prior art.

As will be apparent from the foregoing description, with the circuitry of the present application,the noise affects the output of the Set signal only during a time period around td shown in fig. 2. That is to say that the first and second electrodes,the noise affects the output of the Set signal only during a period in which the first pulse signal is low and the first delayed pulse signal is high.Has a small influence time, andthe upper safety limit of (2) is greatly improved. Thus, by employing the first impedance switching module RR1, the present application reducesNoise-induced fluctuations in the Set signal.

Similarly, for the third branch and the fourth branch, similarly to the first branch and the second branch described above, we can also obtain,

wherein R is_MP2Is the on-resistance, C, of the second voltage drop switch MP2_d2Is the capacitance of the second switch.

Likewise, for the third branch and the fourth branch,the noise affects the output of the Reset signal only during a period in which the second pulse signal is low and the second delayed pulse signal is high.Has a smaller influence time, andthe upper safety limit of (2) is greatly improved. Thus, by employing the second impedance switching module RR2, the present application reducesNoise-induced fluctuations in the Reset signal.

Referring to fig. 3, fig. 3 shows a schematic circuit diagram according to a further embodiment of the present application. Fig. 3 is substantially the same as the circuit of fig. 1, with the main differences being: in fig. 3, one end of a first capacitor C1 is connected to the first path terminal of the first switch LD1, and the other end of the first capacitor C1 is connected to the high-side floating voltage VB via a third resistor R3; one end of the second capacitor C2 is connected to the first path terminal of the third switch LD3, and the other end of the second capacitor C2 is connected to the high-side floating voltage VB via the fourth resistor R4. In other words, the first capacitor C1 and the third resistor R3 are connected in series between the first path terminal and the second path terminal of the first voltage drop switch MP1, and the second capacitor C2 and the fourth resistor R4 are connected in series between the first path terminal and the second path terminal of the second voltage drop switch MP 2. By adding the third resistor R3 connected in series between the first capacitor C1 and the high-voltage side floating voltage VB to the first impedance switching module RR1, the charging and discharging time of the first capacitor C1 and the second capacitor C2 can be increased, the discharging curves of the first capacitor C1 and the second capacitor C2 are smoother, the total voltage change rate when the discharging process of the first capacitor C1 and the second capacitor C2 is overlapped with dV/dt noise is reduced, and therefore the noise reduction effect of the first impedance switching module RR1 and the second impedance switching module RR2 is improved.

Referring to fig. 3, when the first droop switch MP1 is turned off, a first impedance between the first path terminal of the first switch LD1 and the high-side floating voltage VB. Wherein C1 is the capacitance of the first capacitor C1, and R3 is the resistance of the third resistor R3. ω is the frequency of the voltage across the first capacitor C1. The voltage across the first capacitor C1 is typically a dc voltage, i.e., ω is 0. Thus, the mode of the first impedance can be considered infinite. When the first droop switch MP1 is turned on, a second impedance between the first path terminal of the first switch LD1 and the high-side floating voltage VB is R_MP1. Obviously, the mode of the second impedance is smaller than the mode of the first impedance.

Referring to fig. 3, when the second droop switch MP2 is turned off, a fourth impedance between the first path terminal of the third switch LD3 and the high-side floating voltage VB is. Wherein C2 is the capacitance of the second capacitor C2, and R4 is the resistance of the fourth resistor R4. ω is the frequency of the voltage across the second capacitor C2. Since the voltage across the second capacitor C2 is generally a dc voltage, i.e., ω is 0. Therefore, the mode of the third impedance can be regarded as infinite. When the second droop switch MP2 is turned on, a fourth impedance between the first path terminal of the third switch LD3 and the high-side floating voltage VB is R_MP2. Obviously, the mode of the fourth impedance is smaller than the mode of the third impedance.

Referring to fig. 4, fig. 4 shows a schematic circuit diagram according to a further embodiment of the present application. Fig. 4 is substantially the same as the circuit of fig. 1, with the main differences being: in fig. 4, the first capacitor C1 in fig. 1 is replaced with a fifth resistor R5, and the second capacitor C2 in fig. 1 is replaced with a sixth resistor R6. Specifically, one end of the fifth resistor R5 is connected to the first path terminal of the first switch LD1, and the other end of the fifth resistor R5 is connected to the high-side floating voltage VB. One end of the sixth resistor R6 is connected to the first path terminal of the third switch LD3, and the other end of the sixth resistor R6 is connected to the high-side floating voltage VB. In other words, the fifth resistor R5 is connected between the first path terminal and the second path terminal of the first voltage drop switch MP1, and the sixth resistor R6 is connected between the first path terminal and the second path terminal of the second voltage drop switch MP 2. In general, replacing the first capacitor C1 with the fifth resistor R5 and the second capacitor C2 with the sixth resistor R6 allows the corresponding first and second impedance switching modules RR1 and RR2 to be configured in a less costly manner. Meanwhile, the power consumption of the first impedance switching module RR1 and the second impedance switching module RR2 is lower.

Referring to fig. 4, when the first droop switch MP1 is turned off, a first impedance R5 between the first path terminal of the first switch LD1 and the high-side floating voltage VB. Wherein, R5 is the resistance of the fifth resistor R5. When the first droop switch MP1 is turned on, a second impedance between the first path terminal of the first switch LD1 and the high-side floating voltage VB isObviously, the mode of the second impedance is smaller than the mode of the first impedance.

Referring to fig. 4, when the second droop switch MP2 is turned off, a third impedance between the first path terminal of the third switch LD3 and the high-side floating voltage VB is R6. When the second droop switch MP2 is turned on, a fourth impedance between the first path terminal of the third switch LD3 and the high-side floating voltage VB isObviously, the mode of the fourth impedance is smaller than the mode of the third impedance.

Referring to fig. 5, fig. 5 shows a schematic circuit diagram according to a further embodiment of the present application. Fig. 5 is substantially the same as the circuit of fig. 4, with the main differences being: in fig. 5, the first path terminal of the first voltage drop switch MP1 is connected to the operating voltage VB through the seventh resistor R7, and the first path terminal of the second voltage drop switch MP2 is connected to the operating voltage VB through the eighth resistor R8. Similar to that described above with reference to fig. 4, for the embodiment of fig. 5, the mode of the second impedance is smaller than the mode of the first impedance, and the mode of the fourth impedance is smaller than the mode of the third impedance.

The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.