阅读说明：本技术 一种基于fpga的低延时、可配置无线快速跳频系统 (Low-delay configurable wireless rapid frequency hopping system based on FPGA ) 是由 卫增辉 郭钊 徐政珂 李丹华 乔志远 陈旭辉 李帅兵 李金凤 于 2021-06-30 设计创作，主要内容包括：本发明涉及一种基于FPGA的低延时、可配置无线快速跳频系统,包括上位机软件模块、基带处理模块、射频收发模块以及天线；所述基带处理模块包括FPGA以及与FPGA相连的FLASH芯片、数模转换模块、模数转换模块和接口模块,上位机软件模块与FPGA连接以实现对基带处理模块的参数配置,数模转换模块连接至射频收发处理模块的输入端,模数转换模块的输入端连接至射频收发处理模块的输出端,射频收发处理模块与天线相连,接口模块用于与本端测发控系统控制板连接。本发明能够实现测发控系统控制指令和数据的无电缆实时传输,高速跳频能够保障无线数据不被干扰和截获,还能实现主/从无线传输模块的参数配置,使系统具备互换性和灵活操作的能力。(The invention relates to a low-delay configurable wireless rapid frequency hopping system based on an FPGA (field programmable gate array), which comprises an upper computer software module, a baseband processing module, a radio frequency transceiving module and an antenna, wherein the upper computer software module is used for processing a baseband signal; the baseband processing module comprises an FPGA, and an FLASH chip, a digital-to-analog conversion module, an analog-to-digital conversion module and an interface module which are connected with the FPGA, an upper computer software module is connected with the FPGA to realize parameter configuration of the baseband processing module, the digital-to-analog conversion module is connected to the input end of the radio frequency transceiving processing module, the input end of the analog-to-digital conversion module is connected to the output end of the radio frequency transceiving processing module, the radio frequency transceiving processing module is connected with an antenna, and the interface module is used for being connected with a control panel of the local side testing and transmitting control system. The invention can realize the cable-free real-time transmission of control instructions and data of the test and launch control system, can ensure that wireless data is not interfered and intercepted by high-speed frequency hopping, and can also realize the parameter configuration of the master/slave wireless transmission module, so that the system has the interchangeability and the capability of flexible operation.)

1. A low-delay configurable wireless rapid frequency hopping system based on FPGA is characterized by comprising: the system comprises an upper computer software module, a baseband processing module, a radio frequency transceiving module and an antenna;

the baseband processing module comprises an FPGA, and an FLASH chip, a digital-to-analog conversion module, an analog-to-digital conversion module and an interface module which are respectively connected with the FPGA, wherein an upper computer software module is connected with the FPGA to realize parameter configuration of the baseband processing module, the output end of the digital-to-analog conversion module is connected to the input end of the radio frequency transceiving processing module, the input end of the analog-to-digital conversion module is connected to the output end of the radio frequency transceiving processing module, the radio frequency transceiving processing module is connected with an antenna, and the interface module is used for being connected with a control panel of a local side measurement and transmission control system;

when a transmission link service is carried out, a data signal from a control panel of the local side test and transmission control system is sent to the FPGA through an interface module for signal frequency hopping processing so as to obtain a frequency hopping signal, the frequency hopping signal obtained after processing is subjected to digital-to-analog conversion through a digital-to-analog conversion module so as to be converted into an analog signal, and then the analog signal is processed through a radio frequency transceiving processing module and then is sent to an opposite-end wireless device through an antenna;

when receiving link service, the antenna receives wireless data signals and sends the wireless data signals to the radio frequency transceiving processing module for processing, the processed data signals are sent to the analog-to-digital conversion module for analog-to-digital conversion so as to be converted into digital signals, the digital signals are sent to the FPGA for frequency hopping synchronous processing, and the processed data signals are transmitted to the control panel of the local test and transmission control system through the interface module.

2. The FPGA-based low-latency configurable wireless fast frequency hopping system according to claim 1, wherein: the interface module adopts an RS422 interface chip.

3. The FPGA-based low-latency configurable wireless fast frequency hopping system according to claim 2, wherein:

the FPGA comprises a filling module, an encryption module, a baseband scrambling module, an RS coding module, a framing module, a differential coding module, a DQPSK modulation module, a forming filtering module and a digital frequency hopping module which are connected in sequence; when a transmission link service is carried out, a data signal is input to the FPGA through an RS422 interface chip, and the data signal is processed by a filling module, an encryption module, a baseband scrambling module, an RS coding module, a framing module, a differential coding module, a DQPSK modulation module, a shaping filtering module and a digital frequency hopping module in sequence and then outputs a frequency hopping signal to a digital-to-analog conversion module;

the FPGA also comprises a DDC module, a matched filtering module, a frequency hopping synchronization module, a DQPSK demodulation module, an RS decoding module, a baseband descrambling module and a decryption module which are connected in sequence; when receiving link service, the data signal from the analog-to-digital conversion module is processed by the DDC module, the matched filtering module, the frequency hopping synchronization module, the DQPSK demodulation module, the RS decoding module, the baseband descrambling module and the decryption module in sequence and then is sent to the control panel of the local test and transmission control system through the RS422 interface chip.

4. The FPGA-based low-latency configurable wireless fast frequency hopping system according to claim 3, wherein: the frequency hopping synchronization module comprises initial frequency hopping synchronization and service time slot synchronization in the process of carrying out frequency hopping synchronization.

5. The FPGA-based low-latency configurable wireless fast frequency hopping system according to claim 4, wherein: the baseband processing module, the radio frequency transceiver module and the antenna form a wireless transmission module, and different initial frequency hopping synchronization steps are carried out according to whether the wireless transmission module is a master wireless transmission module or a slave wireless transmission module;

the step of initiating frequency hopping synchronization for the slave radio transmission module includes:

slowly sweeping frequency and capturing A CODE of the time slot 0;

demodulating and decoding B CODE, and checking CRC;

decoding is correct, CRC passes, TOD is obtained, and frequency hopping synchronization is completed, wherein TOD is time information;

shifting to frequency hopping synchronous tracking, capturing A CODE when each superframe time slot is 0, and maintaining tracking;

when the wireless transmission module is the main wireless transmission module, the step of initial frequency hopping synchronization comprises the following steps:

normally sweeping frequency and capturing the A CODE of the time slot 1;

completing frequency hopping synchronization in the capture process;

and (4) switching to frequency hopping synchronous tracking, acquiring the A CODE of each superframe time slot 1 and maintaining tracking.

6. The FPGA-based low-latency configurable wireless fast frequency hopping system according to claim 5, wherein: after the initial frequency hopping synchronization is finished, the service time slot synchronization is carried out, the service time slot synchronization carries out symbol synchronization and carrier synchronization on data, and then the data are output to the DQPSK demodulation module by the frequency hopping synchronization module.

7. The FPGA-based low-latency configurable wireless fast frequency hopping system according to claim 1, wherein: the radio frequency transceiver module comprises a transmitting channel and a receiving channel,

the transmitting channel comprises a transmitting and receiving switch connected with the output end of the digital-to-analog conversion module, and the output end of the transmitting and receiving switch is connected with the input end of the antenna after passing through a first amplifier, a first filter, a high-isolation radio frequency switch, a power amplifier, a common end transmitting and receiving switch and a common end filter in sequence; when the transmitting channel works, 150 MHz-390 MHz frequency hopping signals from a digital-to-analog conversion module pass through a receiving and transmitting switch to gate the transmitting channel, pass through a first amplifier and a first filter to be amplified and filtered, pass through a high-isolation radio frequency switch to gate a post-stage circuit, pass through a power amplifier to amplify the signals, and finally pass through a public end receiving and transmitting switch and a public end filter to output 150 MHz-390 MHz frequency hopping signals to an antenna;

the receiving channel comprises a common end filter connected with the output end of the antenna, the output of the common end filter is connected with the input end of the analog-to-digital conversion module after passing through a common end receiving and sending switch, a low noise amplifier, a second filter, a second amplifier, a mixer, a sound meter filter and an AGC amplifier in sequence, and the input end of the mixer is also connected with a DDS local oscillation source; when a receiving channel works, 150 MHz-390 MHz frequency hopping signals received by an antenna are firstly filtered by a common end filter, then the receiving channel is gated by a common end receiving and transmitting switch, the gated 150MHz-320MHz frequency hopping signals are amplified by a low noise amplifier, out-of-band interference signals are filtered by a second filter, then the frequency hopping signals are mixed with 220 MHz-390 MHz frequency hopping signals output by a DDS local vibration source through a mixer, the frequency hopping signals are down-converted to 70MHz intermediate frequency signals, and the intermediate frequency signals are adjusted and output to an analog-to-digital conversion module through a sound meter filter and an AGC amplifier; the receiving and transmitting switch, the high-isolation radio frequency switch and the public end receiving and transmitting switch are all controlled by the FPGA.

8. The FPGA-based low-latency configurable wireless fast frequency hopping system according to claim 1, wherein: the FPGA comprises a filling serial port processing module which is used for receiving the parameter configuration information sent by the upper computer software module and processing the parameter configuration information in the FPGA so as to complete the configuration or the replacement of the parameter information.

Technical Field

The invention belongs to the technical field of wireless communication, and particularly relates to a low-delay configurable wireless rapid frequency hopping system based on an FPGA.

Background

At present, data and control instructions of a measurement and launch control system are transmitted through cables, the maintenance and laying of the cables are a waste of energy and time for the measurement and launch control system, in order to solve the problem, a wireless communication system is used for replacing the original cables to transmit the data and the control instructions domestically, but the wireless communication system used for the measurement and launch control system still has the following problems and defects: (1) the wireless communication system adopted in the current test and launch control system has larger time delay and influences the sensitivity of the test and launch control system, thereby possibly influencing the launch task; (2) the device does not have a quick frequency hopping function, and the transmitted data information is easily interfered and intercepted; (3) the parameters of the system cannot be flexibly modified.

Disclosure of Invention

The invention aims to provide a low-delay wireless rapid frequency hopping system based on an FPGA (field programmable gate array), which enables a measurement and launch control system to transmit control instructions and data without cables, the system is designed to have very low delay, so that the control instructions with higher priority levels, such as emergency power failure and the like, can be strictly received by a main system on time, meanwhile, the rapid frequency hopping system can enable the control instructions and the data transmission not to be interfered and intercepted, and a user can freely configure information, such as launch power, a frequency band range, a secret key, a frequency meter number and the like, through an upper computer according to needs.

The purpose of the invention and the technical problem to be solved are realized by adopting the following technical scheme. The invention provides a low-delay configurable wireless rapid frequency hopping system based on an FPGA, which comprises: the system comprises an upper computer software module, a baseband processing module, a radio frequency transceiving module and an antenna;

the baseband processing module comprises an FPGA, and an FLASH chip, a digital-to-analog conversion module, an analog-to-digital conversion module and an interface module which are respectively connected with the FPGA, an upper computer software module is connected with the FPGA to realize parameter configuration of the baseband processing module, the output end of the digital-to-analog conversion module is connected to the input end of the radio frequency transceiving processing module, the input end of the analog-to-digital conversion module is connected to the output end of the radio frequency transceiving processing module, the radio frequency transceiving processing module is connected with an antenna, and the interface module is used for being connected with a control panel of a local side measurement and transmission control system;

when a transmission link service is carried out, a data signal from a control panel of the local side test and transmission control system is sent to the FPGA through an interface module for signal frequency hopping processing so as to obtain a frequency hopping signal, the frequency hopping signal obtained after processing is subjected to digital-to-analog conversion through a digital-to-analog conversion module so as to be converted into an analog signal, and then the analog signal is processed through a radio frequency transceiving processing module and then is sent to an opposite-end wireless device through an antenna;

when receiving link service, the antenna receives wireless data signals and sends the wireless data signals to the radio frequency transceiving processing module for processing, the processed data signals are sent to the analog-to-digital conversion module for analog-to-digital conversion so as to be converted into digital signals, the digital signals are sent to the FPGA for frequency hopping synchronous processing, and the processed data signals are transmitted to the control panel of the local test and transmission control system through the interface module.

Further, the interface module adopts an RS422 interface chip.

Furthermore, the FPGA comprises a filling module, an encryption module, a baseband scrambling module, an RS coding module, a framing module, a differential coding module, a DQPSK modulation module, a shaping filtering module and a digital frequency hopping module which are connected in sequence; when a transmission link service is carried out, a data signal is input to the FPGA through an RS422 interface chip, and the data signal is processed by a filling module, an encryption module, a baseband scrambling module, an RS coding module, a framing module, a differential coding module, a DQPSK modulation module, a shaping filtering module and a digital frequency hopping module in sequence and then outputs a frequency hopping signal to a digital-to-analog conversion module;

the FPGA also comprises a DDC module, a matched filtering module, a frequency hopping synchronization module, a DQPSK demodulation module, an RS decoding module, a baseband descrambling module and a decryption module which are connected in sequence; when receiving link service, the data signal from the analog-to-digital conversion module is processed by the DDC module, the matched filtering module, the frequency hopping synchronization module, the DQPSK demodulation module, the RS decoding module, the baseband descrambling module and the decryption module in sequence and then is sent to the control panel of the local test and transmission control system through the RS422 interface chip.

Further, the frequency hopping synchronization module includes initial frequency hopping synchronization and service time slot synchronization in the process of performing frequency hopping synchronization.

Further, the baseband processing module, the radio frequency transceiver module and the antenna form a wireless transmission module, and different initial frequency hopping synchronization steps are performed according to whether the wireless transmission module is a master wireless transmission module or a slave wireless transmission module;

the step of initiating frequency hopping synchronization for the slave radio transmission module includes:

slowly sweeping frequency and capturing A CODE of the time slot 0;

demodulating and decoding B CODE, and checking CRC;

decoding is correct, CRC passes, TOD is obtained, and frequency hopping synchronization is completed, wherein TOD is time information;

shifting to frequency hopping synchronous tracking, capturing A CODE when each superframe time slot is 0, and maintaining tracking;

when the wireless transmission module is the main wireless transmission module, the step of initial frequency hopping synchronization comprises the following steps:

normally sweeping frequency and capturing the A CODE of the time slot 1;

completing frequency hopping synchronization in the capture process;

and (4) switching to frequency hopping synchronous tracking, acquiring the A CODE of each superframe time slot 1 and maintaining tracking.

Further, after the initial frequency hopping synchronization is completed, service time slot synchronization is performed, the service time slot synchronization performs symbol synchronization and carrier synchronization on data, and then the data is output to the DQPSK demodulation module by the frequency hopping synchronization module.

Further, the radio frequency transceiver module comprises a transmitting channel and a receiving channel,

the transmitting channel comprises a transmitting and receiving switch connected with the output end of the digital-to-analog conversion module, and the output end of the transmitting and receiving switch is connected with the input end of the antenna after passing through a first amplifier, a first filter, a high-isolation radio frequency switch, a power amplifier, a common end transmitting and receiving switch and a common end filter in sequence; when the transmitting channel works, 150 MHz-390 MHz frequency hopping signals from a digital-to-analog conversion module pass through a receiving and transmitting switch to gate the transmitting channel, pass through a first amplifier and a first filter to be amplified and filtered, pass through a high-isolation radio frequency switch to gate a post-stage circuit, pass through a power amplifier to amplify the signals, and finally pass through a public end receiving and transmitting switch and a public end filter to output 150 MHz-390 MHz frequency hopping signals to an antenna;

the receiving channel comprises a common end filter connected with the output end of the antenna, the output of the common end filter is connected with the input end of the analog-to-digital conversion module after passing through a common end receiving and sending switch, a low noise amplifier, a second filter, a second amplifier, a mixer, a sound meter filter and an AGC amplifier in sequence, and the input end of the mixer is also connected with a DDS local oscillation source; when a receiving channel works, 150 MHz-390 MHz frequency hopping signals received by an antenna are firstly filtered by a common end filter, then the receiving channel is gated by a common end receiving and transmitting switch, the gated 150MHz-320MHz frequency hopping signals are amplified by a low noise amplifier, out-of-band interference signals are filtered by a second filter, then the frequency hopping signals are mixed with 220 MHz-390 MHz frequency hopping signals output by a DDS local vibration source through a mixer, the frequency hopping signals are down-converted to 70MHz intermediate frequency signals, and the intermediate frequency signals are adjusted and output to an analog-to-digital conversion module through a sound meter filter and an AGC amplifier; the receiving and transmitting switch, the high-isolation radio frequency switch and the public end receiving and transmitting switch are all controlled by the FPGA.

Furthermore, the FPGA comprises a filling serial port processing module, and the filling serial port processing module is used for receiving the parameter configuration information sent by the upper computer software module and processing the parameter configuration information in the FPGA so as to complete the configuration or the replacement of the parameter information.

By means of the technical scheme, compared with the prior art, the invention at least has the following beneficial effects:

1. the invention effectively solves the problems of time and labor cost for laying cables and maintaining the cables in each launching task, and enables the testing, launching and control system to be more flexible to use.

2. The invention adopts a frequency hopping synchronization mode to transmit data, and can improve the anti-interference capability, the anti-interception capability and the concealment capability of the system.

3. The invention can be configured according to the requirement, so that the master/slave module can be replaced more flexibly, and simultaneously, the information such as the frequency table, the secret key, the initial time and the like can be configured and replaced at any time according to the requirement, so that the confidentiality of the system is stronger.

4. The invention adopts parallel correlation in the frequency hopping synchronization process, so that the data processing speed in the correlation process is greatly improved, the efficiency of the synchronization and tracking process is higher, the processing time is reduced, the delay is reduced, the measurement and launch control system can more quickly respond to the instruction information, and the measurement and launch control system is more reliable and stable.

The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understandable, the following preferred embodiments are described in detail with reference to the accompanying drawings.

Drawings

Fig. 1 is a schematic diagram of the circuit of the present invention.

Fig. 2 is a processing flow chart of parameter configuration of the FPGA by the upper computer software module in the present invention.

Fig. 3 is a block diagram of the annotated serial port processing module of the present invention.

Fig. 4 is a block diagram of the processing flow of data signals during the transmission link service of the present invention.

Fig. 5 is a block diagram of the processing flow of data signals during the reception of link traffic according to the present invention.

Fig. 6 is a flow chart of the frequency hopping synchronization module in the initial frequency hopping synchronization process of the data signal according to the present invention.

Fig. 7 is a flowchart of the synchronization processing of the data signal by the frequency hopping synchronization module according to the present invention.

Fig. 8 is a diagram illustrating the signal slot structure in the hopping synchronization process of the present invention.

Fig. 9 is a block diagram of an rf transceiving processing module according to the present invention.

Detailed Description

The following detailed description is to be read in connection with the drawings and the preferred embodiments.

Referring to fig. 1 to 8, a low-latency configurable wireless fast frequency hopping system based on FPGA includes: the system comprises an upper computer software module, a baseband processing module, a radio frequency transceiving module and an antenna; the baseband processing module, the radio frequency transceiving module and the antenna form a wireless transmission module. The baseband processing module comprises an FPGA, and an FLASH chip, a digital-to-analog conversion module, an analog-to-digital conversion module and an interface module which are respectively connected with the FPGA, wherein the FPGA preferably uses an XS6LC45T chip of XILINX company, the FPGA completes all algorithm realization and data processing processes of baseband processing, and the interface module adopts an RS422 interface chip; the upper computer software module is connected with the FPGA to realize parameter configuration on the baseband processing module; the output end of the digital-to-analog conversion module is connected to the input end of the radio frequency transceiving processing module, the input end of the analog-to-digital conversion module is connected to the output end of the radio frequency transceiving processing module, the radio frequency transceiving processing module is connected with the antenna, and the interface module is used for being connected with the control panel of the local test and launch control system.

The upper computer software module can carry out master-slave mode configuration on the wireless transmission module through the filling serial port processing module, and the measurement and launch control system comprises a master wireless transmission module, a slave wireless transmission module and a measurement and launch control system control panel. In order to facilitate understanding of the working process and principle of the present invention, the master wireless transmission module is set to transmit a data signal to the peer wireless transmission module (slave wireless transmission module) first, and the slave wireless transmission module is set to receive the data signal. The hardware platform of the wireless transmission module, whether the wireless transmission module is a master or a slave, is the same as that shown in fig. 1. However, it should be noted that once the handshake between the master and slave wireless transmission modules is completed, the two-way wireless communication data interaction between the two parties can be realized; the parameters of the master and slave wireless transmission modules used in pairs can be configured, so that the wireless frequency hopping system has interchangeability and flexible operation capability, and meanwhile, information such as a frequency table, a secret key, initial time and the like can be configured and replaced at any time according to needs, so that the confidentiality of the system is higher.

Specifically, the FPGA processing part comprises a filling serial port processing module, and the filling serial port processing module processes data such as parameter configuration and the like sent by the upper computer in the FPGA. As shown in fig. 2, when the wireless fast frequency hopping system is initially powered on, the charging serial port processing module first reads parameters such as master-slave attributes, a frequency table number, a secret key, initial time and the like from the FLASH chip, and then reads the frequency table content of the corresponding frequency table number from the corresponding position of the FLASH chip according to the frequency table number.

The annotated serial port processing module is composed as shown in fig. 3, and comprises a serial port number receiving module, a frame detecting and analyzing module, a response frame framing module, a serial port number sending module, an initial parameter reading module and a FLASH read-write control module, wherein the serial port number receiving module is used for receiving data such as parameter configuration and the like sent by an upper computer software module, the serial port number receiving module, the frame detecting and analyzing module, the response frame framing module and the serial port number sending module are sequentially connected, a FLASH chip is connected with the initial parameter reading module through the FLASH read-write control module, and the initial parameter reading module is further connected with the response frame framing module.

Referring to fig. 2, the serial port receiving module monitors the serial port in real time and outputs the serial port after receiving one byte. When detect is equal to 0, that is, no frame is detected, serial sliding is performed to detect a frame header (0x55aa), after the frame header is detected, it is indicated that a frame is received, then the received bytes are extracted according to the protocol format at the corresponding positions for command words and frame length, and check byte calculation is performed. If the command word is 0x00, the frame is a system parameter frame, the frame detection and analysis module writes the subsequent system parameters into the FLASH chip; if the command word is 0x01, which indicates that the frame is a frequency hopping rate table frame, the following frequency hopping rate table contents are written into the FLASH chip. After receiving a frame according to the frame length, respectively organizing the error response frames after the correct response frames according to whether the check bytes are correct or not on one hand, setting the detect to 0 on the other hand, continuing the detection of the frame head, and receiving the next frame.

The second timer counts in the beat of the processing clock, when one second is counted, a module state frame and an error code test result frame are organized, the frames and the former response frame are sent to the serial port sending control part together, the response frame framing module forms a queue according to the sequence, bytes are taken from the queue according to the time corresponding to the baud rate and sent to the serial port sending module, and the serial port sending module changes the bytes into bit serial output.

When the system carries out a transmission link service, a data signal from a control panel of the local side test and transmission system is sent to the FPGA through an RS422 interface chip for signal frequency hopping processing, so that a frequency hopping signal is obtained; the processed frequency hopping signal is a digital signal, the digital signal is converted into an analog signal through digital-to-analog conversion by the digital-to-analog conversion module, and the analog signal is amplified, filtered and the like by the radio frequency transceiving processing module and then can be transmitted to the opposite-end wireless transmission module in a wireless communication mode through the antenna. When the system receives link service, the antenna receives wireless data signals and sends the wireless data signals to the radio frequency transceiving processing module for amplification, filtering and other processing, the processed data signals are sent to the analog-to-digital conversion module for analog-to-digital conversion so as to be converted into digital signals, the digital signals are further transmitted to the FPGA for frequency hopping synchronous processing, and the processed data signals are transmitted to the control panel of the local side test and launch control system through the interface module.

Specifically, when the transmitter is used to transmit a data signal, as shown in fig. 4, the FPGA includes a padding module, an encryption module, a baseband scrambling module, an RS coding module, a framing module, a differential coding module, a DQPSK modulation module, a shaping filtering module, and a digital frequency hopping module, which are connected in sequence, wherein an input end of the padding module is connected to the RS422 interface chip, and an output end of the digital frequency hopping module is connected to an input end of the digital-to-analog conversion module. When the transmission link service is carried out, data signals are input into the FPGA through the RS422 interface chip, and the data signals are sequentially processed through the following modules: the data transmission method comprises the steps that firstly, a filling module is used for filling, 0 is supplemented when a data signal is less than one frame when the data signal is filled, then an encryption module is used for encryption processing, a baseband scrambling module is used for baseband scrambling of the data signal, an RS coding module is used for RS coding of the data signal, a framing module is used for framing of the data signal, a differential coding module is used for differential coding of the data signal, a DQPSK modulation module is used for DQPSK modulation of the data signal, a forming filtering module is used for filtering of the data signal, a digital frequency hopping module is used for frequency hopping processing of the data signal to generate a frequency hopping signal, the generated frequency hopping signal is transmitted to a digital-to-analog conversion module for digital-to-analog conversion, finally, the radio frequency signal is obtained after amplification and filtering processing of a radio frequency transceiving module, and the radio frequency signal is transmitted through an antenna.

Preferably, when framing, each time slot is grouped to form an RS packet, the RS packet comprises 10 hops, each hop has frequency conversion protection time of 4 symbols, the hop rate is 4000h/s, the symbol rate is 400ksps, and RS (240, 144) is adopted by RS codes. Through the design of the waveforms, the system can meet the requirement of low delay under the condition of guaranteeing the speed and the error correction capability.

The processing flow of the receiver is the inverse process of the signal processing flow of the transmitter, and in combination with fig. 5, the FPGA further comprises a DDC module, a matched filtering module, a frequency hopping synchronization module, a DQPSK demodulation module, an RS decoding module, a baseband descrambling module and a decryption module which are connected in sequence, wherein the input end of the DDC module is connected to the output end of the analog-to-digital conversion module, and the output end of the decryption module is connected to the input end of the RS422 interface chip. When receiving link service, the data signal input by radio frequency is firstly simulated and demodulated to intermediate frequency in a radio frequency receiving and transmitting module, the intermediate frequency signal is collected by an analog-to-digital conversion module, then is processed by a DDC module, a matched filter module, a frequency hopping synchronization module, a DQPSK demodulation module, an RS decoding module, a baseband descrambling module and a decryption module in sequence and then is sent to a control panel of a local terminal test and transmission control system through an RS422 interface chip; wherein DDC module carries out Digital Down Conversion (DDC) with intermediate frequency signal to zero intermediate frequency, carries out frequency hopping synchronization module after the matched filter processing of matched filter module again, just carries out the most crucial step this moment: and frequency hopping synchronization, wherein the frequency hopping synchronization comprises two processes of initial frequency hopping synchronization and service time slot synchronization. After the frequency hopping synchronization is completed, the frequency hopping alignment can be realized, and the frequency hopping is completed. After the de-hopping is finished, the original data stream is recovered after DQPSK demodulation, RS decoding processing of an RS decoding module, baseband descrambling of a baseband descrambling module and decryption of a decryption module, and the original data stream is output to a control panel of the local side test and launch control system through an RSS422 interface chip.

The initial frequency hopping synchronization is carried out according to different initial frequency hopping synchronization steps of a main wireless transmission module (master station) or a slave wireless transmission module (slave station), for the slave wireless transmission module, A CODE (a group of fixed random data lasting 20 hops) frequency hopping acquisition, B CODE (composed of parameter information such as 40 bit time, 8-bit CRC check bit and 144-bit RS coding check bit) demodulation decoding, A CODE frequency hopping tracking and the like are carried out, and for the main wireless transmission module, A CODE frequency hopping acquisition, A CODE frequency hopping tracking and the like are carried out.

The flow chart of the initial frequency hopping synchronization process is shown in fig. 6: when the wireless transmission module is judged as the slave wireless transmission module, the step of initial frequency hopping synchronization comprises the following steps:

initial capture, firstly, slowly sweeping frequency to capture the A CODE of the time slot 0;

in capture, demodulating and decoding the B CODE, and performing CRC check; if the CRC fails, the method returns to the previous step to continue capturing.

Decoding is correct, if CRC passes, TOD is obtained, frequency hopping synchronization is completed, and alignment of frequency hopping frequencies at the transmitting end and the receiving end is realized; wherein TOD is time information.

Then, switching to frequency hopping synchronous tracking, capturing the A CODE when each superframe time slot is 0, and maintaining tracking; and 4 continuous superframes do not acquire the upper A CODE and shift to frequency hopping synchronous acquisition.

When the wireless transmission module is judged to be the main wireless transmission module, the step of initial frequency hopping synchronization comprises the following steps:

initial capture, performing normal frequency sweep, and capturing the A CODE of the time slot 1;

completing frequency hopping synchronization in the capture process;

and (4) switching to frequency hopping synchronous tracking, acquiring the A CODE of each superframe time slot 1 and maintaining tracking. And 4 continuous superframes do not acquire the upper A CODE and shift to frequency hopping synchronous acquisition.

After the initial frequency hopping synchronization is completed, the service time slot synchronization is performed, as shown in fig. 7, the service time slot synchronization further performs symbol synchronization and carrier synchronization on the data, and then the data signal is output to the DQPSK demodulation module by the frequency hopping synchronization module, thereby completing DQPSK demodulation.

Specifically, the system adopts a time division duplex and frequency hopping mode and point-to-point communication, and comprises a station A and a station B, wherein the station A is a master station, and the station B is a slave station. The signal consists of superframes in time, one superframe duration 500 ms. Each superframe is divided into 42 time slots, and the time slot labels are 0-41. The time slot 0 is a time service and synchronization time slot sent by a master station, wherein the effective data is 12ms, the guard interval is 0.5ms, and each superframe of the time slot 0 must be sent after the data is in the guard interval; the time slot 1 is a time service response and time synchronization time slot sent to the master station by the slave station, wherein the effective data is 2ms, the guard interval is 0.5ms, and the slave station can send the time slot only after the time slot 0 of the master station is received to complete time slot synchronization; and other time slots are service data time slots and are transmitted when data exist. For other time slots, the time slots 2-5 are allocated to the station A, the time slots 6-9 are allocated to the station B, the time slots 10-13 are allocated to the station A, the time slots 14-17 are allocated to the station B, and the like. Every 4 slots constitute an RS packet with valid data 48ms, guard interval 0.5ms, guard interval following the data.

The slave station does not send after being initially powered on, and only after the slave station receives the time slot 0 sent by the master station and completes time service and synchronization, the slave station responds in the time slot 1 and sends data in the service time slot. The signal slot structure is shown in fig. 8.

In summary, in the frequency hopping synchronization process, the data signal first performs synchronization header, that is, synchronization alignment of the flag information, and then symbol and carrier synchronization is performed on the data following the flag information again, so as to finally implement data transmission.

Preferably, in the frequency hopping synchronization process, the sliding correlation adopts parallel correlation, that is, an a CODE in a ROM is firstly read out to a fixed register in an FPGA, then data cycle shift after DBPSK demodulation is performed in each clock cycle, and the data cycle shift and the value in the register are subjected to the same or processing, so that the correlation value can be calculated in 11 clock cycles. The processing time can be reduced by adopting a parallel sliding correlation method, so that the time delay is reduced.

The radio frequency transceiving module comprises a transmitting channel and a receiving channel. A schematic block diagram of the radio frequency transceiver module is shown in fig. 9, wherein a transmitting channel comprises a transceiver switch connected with an output end of the digital-to-analog conversion module, and an output end of the transceiver switch is connected with an input end of an antenna after passing through a first amplifier, a first filter, a high-isolation radio frequency switch, a power amplifier, a common end transceiver switch and a common end filter in sequence; when the transmitting channel works, the wireless frequency hopping system outputs radio frequency signals, 150MHz-320MHz frequency hopping signals from the digital-to-analog conversion module pass through the transmitting and receiving switch to gate the transmitting channel, pass through the first amplifier and the first filter to be amplified and filtered, pass through the high-isolation radio frequency switch to gate the post-stage circuit, pass through the power amplifier to amplify the signals, and finally pass through the public end transmitting and receiving switch and the public end filter to output 150MHz-320MHz frequency hopping signals to the antenna.

The receiving channel comprises a common end filter connected with the output end of the antenna, the output of the common end filter is connected with the input end of the analog-to-digital conversion module after passing through a common end receiving and sending switch, a low noise amplifier, a second filter, a second amplifier, a mixer, a sound meter filter and an AGC amplifier in sequence, and the input end of the mixer is also connected with a DDS local oscillation source; when a receiving channel works, 150MHz-320MHz frequency hopping signals received by an antenna are firstly filtered by a public end filter, then the public end receiving switch is used for gating the receiving channel, the gated 150MHz-320MHz frequency hopping signals are amplified by a low noise amplifier, out-of-band interference signals are filtered by a second filter, then the frequency hopping signals are mixed with 220 MHz-390 MHz frequency output by a DDS local vibration source by a mixer, and then the mixed frequency is converted into 70MHz intermediate frequency signals, and the intermediate frequency signals are adjusted and output to an analog-to-digital conversion module by a sound meter filter and an AGC amplifier; the receiving and transmitting switch, the high-isolation radio frequency switch and the public end receiving and transmitting switch are all controlled by the FPGA. The acoustic meter filter and the AGC amplifier can be directly provided with an amplifier, and the output end of the AGC amplifier can be provided with the acoustic meter filter, the amplifier and the like, so that the further adjustment processing of the data signal is realized; in addition, the radio frequency transceiver module comprises a frequency clock source for outputting a clock, provides a clock required by the work for the FPGA, and also comprises conventional functions of PTT transceiver control, power supply conversion and the like.

The above description is only a preferred embodiment of the present invention, and any person skilled in the art can make any simple modification, equivalent change and modification to the above embodiments according to the technical essence of the present invention without departing from the scope of the present invention, and still fall within the scope of the present invention.