阅读说明：本技术 一种三电平pwm调制信号实现方法 (Three-level PWM signal implementation method ) 是由 刘永奎 曹立航 于 2020-12-15 设计创作，主要内容包括：发明公开了一种三电平PWM调制信号实现方法。基于DSP、FPGA和三电平功率电路,所述方法包括以下步骤：DSP产生每相两路PWM调制信号发送至FPGA；FPGA根据DSP产生的每相两路信号的电平状态,控制输出正、负、零电平的状态机,控制输出每相六路功率器件PWM驱动信号至三电平功率电路；FPGA根据窄脉冲滤波对PWM调制信号进行延迟,使得部分功率器件提前关断,并对不同功率器件调制信号的上升沿下降沿分别叠加不同时长的死区。针对不同功率器件的上升沿、下降沿分别加不同时长的死区,易于优化死区效应。该方法具有架构简单、方案灵活、运行可靠稳定,便于移植的特点。(The invention discloses a method for realizing a three-level PWM modulation signal. Based on a DSP, an FPGA and a three-level power circuit, the method comprises the following steps: the DSP generates two paths of PWM modulation signals of each phase and sends the PWM modulation signals to the FPGA; the FPGA controls a state machine for outputting positive, negative and zero levels according to the level states of each phase of two paths of signals generated by the DSP, and controls and outputs each phase of six paths of power device PWM driving signals to a three-level power circuit; and the FPGA delays the PWM modulation signal according to the narrow pulse filtering, so that part of power devices are turned off in advance, and dead zones with different durations are respectively superposed on the rising edges and the falling edges of the modulation signals of different power devices. Dead zones with different time lengths are added to the rising edge and the falling edge of different power devices respectively, so that the dead zone effect is easy to optimize. The method has the characteristics of simple architecture, flexible scheme, reliable and stable operation and convenience in transplantation.)

1. A three-level PWM modulation signal realization method is characterized in that based on a DSP, an FPGA and a three-level power circuit, the method comprises the following steps:

the DSP generates two paths of PWM modulation signals of each phase and sends the PWM modulation signals to the FPGA;

the FPGA controls a state machine for outputting positive, negative and zero levels according to the level states of each phase of two paths of signals generated by the DSP, and controls and outputs each phase of six paths of power device PWM driving signals to a three-level power circuit;

and the FPGA delays the PWM modulation signal according to the narrow pulse filtering, so that part of power devices are turned off in advance, and dead zones with different durations are respectively superposed on the rising edges and the falling edges of the modulation signals of different power devices.

2. The method for realizing the three-level PWM modulation signal according to claim 1, wherein the FPGA jumps to an output positive level state machine when the two in-phase laminated PWM modulation signals A, B of each phase generated by the DSP are 1 and 1; skipping to the output negative level state machine when the modulation signal A, B is 0 and 0; when the modulation signal A, B is 0 and 1, jumping to an output zero level state machine; when the modulation signal A, B is 1 or 0, it is in an abnormal state, and reset blocking is performed.

3. The method of claim 1, wherein the FPGA receives the two PWM modulation signals of each phase and performs a signal delay of a dead time duration by narrow pulse filtering, and the original signal and the delayed signal are respectively used for entering a positive/negative level state and a zero level state.

4. The method as claimed in claim 1, wherein the PWM driving signal of the power device is obtained by setting the switching tube G6 and the switching tube G5 to 1 when outputting positive/negative voltage, and the rising/falling edge of the signal needs to be different from the rising/falling edge of the switching tube G1/switching tube G4 modulation signal by a dead time.

5. The method as claimed in claim 1, wherein when the PWM driving signal of the power device passes through the zero level commutation state, the FPGA controls the output of the modulation signal, such that the switching tube G5/switching tube G6 is first turned on to perform short path commutation, and then the switching tube G2/switching tube G3 is turned on to maintain two commutation paths in a steady state.

6. The method as claimed in claim 1, wherein the six modulation signals per phase generated by the FPGA are generated by switching control of a state machine of the FPGA, the state machine has an intermediate state for transition during switching, the intermediate state is a dead zone for superimposing a rising edge and a falling edge of the output modulation signal, and dead zones for the rising edge and the falling edge of two groups of signals of switching tube G1/switching tube G4, switching tube G2 and switching tube G3 are configured respectively.

7. The method according to claim 1, wherein the method specifically comprises the following steps:

the FPGA acquires two paths of PWM modulation signals of each phase by the DSP, delays the signals by time T and acquires a signal EPWMIN _ SG; the signal without delay is denoted as EPWMIN _ SG 0; the two groups of signals are sent to an output PWM modulation signal control state machine;

the zero level state switch tube G2, the switch tube G3, the switch tube G5 and the switch tube G6 are conducted, and two follow current paths are provided:

when detecting that a is 1 and B is 1 in the non-delay signal EPWMIN _ SG0, sequentially executing intermediate state output corresponding signals: the positive level short-path freewheeling, the switch tube G1 on/off dead zone, the switch tube G6 clamping on/off dead zone, and finally the positive level output state is entered;

when detecting that a is 0 and B is 0 in the non-delay signal EPWMIN _ SG0, sequentially executing intermediate state output corresponding signals: the method comprises the following steps of enabling a negative level short-path to continue current, enabling/shutting off a dead zone of a switching tube G4, clamping the dead zone of the switching tube G5, and finally entering a negative level output state;

and when the zero level state has a fault, all output signals are switched off to carry out wave sealing treatment.

8. The method of claim 7, wherein the positive level output state sequentially performs intermediate state output corresponding signals when detecting that A ≠ 1 and B ≠ 1 in the EPWMIN _ SG of the delay signal:

the switching tube G6 clamps an on/off dead zone, the switching tube G1 an on/off dead zone, a positive level short path follow current, and finally enters a zero level output state, and the output time of each intermediate state is determined by the dead zone time of each intermediate state in the graph;

when the negative level output state detects that a is not equal to 0 and B is not equal to 0 in the delay signal EPWMIN _ SG, the intermediate state output corresponding signal is sequentially executed: the switching tube G5 clamps an on/off dead zone, the switching tube G4 an on/off dead zone, the negative level short-path follow current and finally enters a zero level output state, and the output time of each intermediate state is determined by the dead zone time of each intermediate state;

when the output positive/negative level fails, switching tube G1/switching tube G4 and switching tube G5/switching tube G6 are turned off, and then switching tube G2/switching tube G3 are turned off to carry out wave sealing treatment.

9. The method according to claim 1, wherein the two PWM modulation signals per phase generated by the DSP include PWM signals generated by in-phase stacked and reverse-phase stacked PWM modulation schemes.

10. The method of claim 1, wherein the three-level power circuit is in NPC topology, TNPC topology or ANPC topology.

Technical Field

The invention belongs to the technical field of power electronics, and particularly relates to a PWM (pulse-width modulation) signal implementation method of a three-level ANPC (analog to digital converter) power circuit topology.

Background

The Neutral Point Clamped (NPC) three-level technology is the most common power electronic power conversion technology in low-voltage (below 3 kV) application, the Active Neutral Point Clamped (ANPC) three-level technology is a power circuit topological structure developed on the basis of NPC topology, the advantages of no transformer, compact structure, low cost and the like of the NPC topology are kept, the problem that the loss of a power device is difficult to balance is solved, in addition, a clamping tube can be turned on to carry out voltage-sharing clamping on a pressure-bearing power device when positive/negative electricity is output, and the stability of a system is improved.

At present, the application of the ANPC topology three-level technology is mainly concentrated in the field of new energy, the specific implementation mode of the PWM modulation signal is greatly different from that of the NPC topology, the inheritance is not achieved, and when a DSP + FPGA typical system structure is adopted, a classical modulation mode inevitably needs to acquire the phase or the zero crossing point of a modulation wave, so that the ANPC topology three-level technology is used for on-off control of a power frequency tube and distinguishing of output high/low level signals.

Disclosure of Invention

Aiming at the explanation of the background technology, the invention provides a three-level PWM signal implementation method, which can effectively solve the problems of the existing modulation method and has survivability. The invention does not need to acquire the phase or the zero crossing point of the modulation wave; when the power device operates under the four-quadrant condition, the loss of each power device can be effectively balanced; when positive/negative electricity is output, a clamping tube is switched on to carry out voltage-sharing clamping on the pressure-bearing power device; dividing closed-loop control, carrier modulation and drive signal generation of specific type topology into two independent modules to realize the compatibility of NPC and ANPC control programs; dead zones with different time lengths can be respectively superposed on the rising edges and the falling edges of the modulation signals of different power devices, so that the dead zone effect is easily optimized.

In order to achieve the purpose, the invention provides the following technical scheme:

a three-level PWM modulation signal realization method is based on a DSP, an FPGA and a three-level power circuit, and comprises the following steps:

the DSP generates two paths of PWM modulation signals of each phase and sends the PWM modulation signals to the FPGA;

the FPGA controls a state machine for outputting positive, negative and zero levels according to the level states of each phase of two paths of signals generated by the DSP, and controls and outputs each phase of six paths of power device PWM driving signals to a three-level power circuit;

and the FPGA delays the PWM modulation signal according to the narrow pulse filtering, so that part of power devices are turned off in advance, and dead zones with different durations are respectively superposed on the rising edges and the falling edges of the modulation signals of different power devices.

As a further improvement of the invention, the FPGA jumps to an output positive level state machine when each phase two-way in-phase laminated PWM modulation signal A, B generated by the DSP is 1 and 1; skipping to the output negative level state machine when the modulation signal A, B is 0 and 0; when the modulation signal A, B is 0 and 1, jumping to an output zero level state machine; when the modulation signal A, B is 1 or 0, it is in an abnormal state, and reset blocking is performed.

As a further improvement of the invention, the FPGA receives two paths of PWM modulation signals of each phase and performs signal delay of one time dead zone duration by narrow pulse filtering, and the original signal and the delayed signal are respectively used for entering a positive/negative level state and entering a zero level state.

As a further improvement of the present invention, the PWM driving signal of the power device is obtained by setting the modulation signals of the switching tube G6 and the switching tube G5 to 1 when outputting positive/negative voltage, and the rising/falling edges of the modulation signals need to be different from the rising/falling edges of the modulation signals of the switching tube G1 and the switching tube G4 by a dead time.

As a further improvement of the present invention, when the PWM driving signal of the power device is in the zero level commutation state, the FPGA controls the output of the modulation signal, and first the switching tube G5/switching tube G6 is turned on first to perform short path commutation, and then the switching tube G2/switching tube G3 is turned on to maintain two commutation paths in a steady state.

As a further improvement of the invention, each phase of six modulation signals generated by the FPGA is generated by the switching control of the state machine of the FPGA, the state machine has an intermediate state for transition in the switching process, the intermediate state is a dead zone for superposing the rising edge and the falling edge of the output modulation signal, and the dead zone time of the rising edge and the falling edge of two groups of signals of the switching tube G1/the switching tube G4 and the switching tube G2/the switching tube G3 are respectively configured.

As a further improvement of the present invention, the method specifically comprises the steps of:

the FPGA acquires two paths of PWM modulation signals of each phase by the DSP, delays the signals by time T and acquires a signal EPWMIN _ SG; the signal without delay is denoted as EPWMIN _ SG 0; the two groups of signals are sent to an output PWM modulation signal control state machine;

the zero level state switch tube G2, the switch tube G3, the switch tube G5 and the switch tube G6 are conducted, and two follow current paths are provided:

when detecting that a is 1 and B is 1 in the non-delay signal EPWMIN _ SG0, sequentially executing intermediate state output corresponding signals: the positive level short-path freewheeling, the switch tube G1 on/off dead zone, the switch tube G6 clamping on/off dead zone, and finally the positive level output state is entered;

when detecting that a is 0 and B is 0 in the non-delay signal EPWMIN _ SG0, sequentially executing intermediate state output corresponding signals: the method comprises the following steps of enabling a negative level short-path to continue current, enabling/shutting off a dead zone of a switching tube G4, clamping the dead zone of the switching tube G5, and finally entering a negative level output state;

and when the zero level state has a fault, all output signals are switched off to carry out wave sealing treatment.

As a further improvement of the present invention, the positive level output state, when detecting that a ≠ 1, B ≠ 1 in the delay signal EPWMIN _ SG, sequentially executes intermediate state output correspondence signals:

the switching tube G6 clamps an on/off dead zone, the switching tube G1 an on/off dead zone, a positive level short path follow current, and finally enters a zero level output state, and the output time of each intermediate state is determined by the dead zone time of each intermediate state in the graph;

when the negative level output state detects that a is not equal to 0 and B is not equal to 0 in the delay signal EPWMIN _ SG, the intermediate state output corresponding signal is sequentially executed: the switching tube G5 clamps an on/off dead zone, the switching tube G4 an on/off dead zone, the negative level short-path follow current and finally enters a zero level output state, and the output time of each intermediate state is determined by the dead zone time of each intermediate state;

when the output positive/negative level fails, switching tube G1/switching tube G4 and switching tube G5/switching tube G6 are turned off, and then switching tube G2/switching tube G3 are turned off to carry out wave sealing treatment.

As a further improvement of the invention, each phase two-way PWM modulation signal generated by the DSP comprises PWM signals generated by in-phase laminated and anti-phase laminated PWM modulation modes.

As a further improvement of the invention, the three-level power circuit is an NPC topology, a TNPC topology or an ANPC topology.

Compared with the prior art, the invention has the beneficial effects that:

the implementation method is based on a typical system structure of DSP and FPGA, and the DSP has the main functions of three-phase closed-loop control, generating two paths of PWM modulation signals of each phase and sending the PWM modulation signals to the FPGA; the FPGA has the main functions of receiving two paths of PWM signals of each phase sent by the DSP and generating six paths of modulation signals of each phase which can be used for four-quadrant operation, and flexibly adding dead zones to the modulation signals. Compared with other methods applied at present, the PWM signal implementation method keeps the advantages of a typical DSP + FPGA architecture, the DSP chip program does not need to be modified, the generated PWM signal can be used for driving NPC, TNPC and ANPC topology power circuits, and no power device overvoltage risk exists during abnormal fault sealing. According to the implementation method, the FPGA outputs the modulation signal partially, so that the ANPC three-level power circuit has the four-quadrant operation capability, the loss of a power device can be well balanced under different power factors, a pressure-bearing power device outputting positive/negative voltage can be reliably clamped in a voltage equalizing manner, dead zones with different time lengths can be added to the rising edge and the falling edge of different power devices respectively, and the dead zone effect is easy to optimize. The method has the characteristics of simple architecture, flexible scheme, reliable and stable operation and convenience in transplantation.

Furthermore, the invention does not need to acquire the phase or the zero crossing point of the modulation wave; when the power device operates under the four-quadrant condition, the loss of each power device can be effectively balanced; when positive/negative electricity is output, a clamping tube is switched on to carry out voltage-sharing clamping on the pressure-bearing power device; dividing closed-loop control, carrier modulation and drive signal generation of specific type topology into two independent modules to realize the compatibility of NPC and ANPC control programs; dead zones with different time lengths can be respectively superposed on the rising edges and the falling edges of the modulation signals of different power devices, so that the dead zone effect is easily optimized.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a flow chart of a three-level PWM modulation signal implementation method.

Fig. 2 is a schematic diagram of an ANPC topology.

Fig. 3 is a diagram of DSP-generated in-phase stacked PWM modulation.

Fig. 4 is a flow chart of FPGA input PWM signal processing.

Fig. 5 is a logic diagram of the output PWM signal when the FPGA state machine switches from a zero level to a positive/negative level.

Fig. 6 is a logic diagram of the output PWM signal when the FPGA state machine switches from positive/negative level to zero level.

Fig. 7 is a schematic diagram of the FPGA outputting the PWM modulated signal.

Detailed Description

The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in fig. 1, the present invention relates to a PWM modulation signal implementation method suitable for three-level Active Neutral Point Clamped (ANPC) power circuit topology, based on a typical architecture of DSP + FPGA, DSP generates two PWM modulation signals per phase and sends them to FPGA; the FPGA receives the PWM signals sent by the DSP and generates six paths of three-level ANPC topological modulation signals with four-quadrant operation capability, balanced power device loss and active clamping function for each phase; in addition, the FPGA can respectively configure dead zones for the superposition duration of the rising edges and the falling edges of the modulation signals of different power devices.

And each phase two-path PWM modulation signal generated by the DSP comprises but is not limited to PWM signals generated by in-phase laminated and reverse-phase laminated PWM modulation modes. The modulation signal generation method can be applied to PWM of NPC, TNPC and ANPC topologies.

As shown in fig. 2, a three-level topology ANPC includes two capacitors and a plurality of power devices; two capacitors connected in series are arranged on the direct current side in series; the power device comprises a switching tube and an anti-parallel diode thereof;

two capacitors (C1, C2) connected in series, four switching tubes (switching tube G1, switching tube G2, switching tube G3, switching tube G4) connected with two ends of the two capacitors and anti-parallel diodes (diode D1, diode D2, diode D3, diode D4) of the switching tubes, two switching tubes (switching tube G5, switching tube G6) connected with midpoints of the two capacitors (C1, C2) and anti-parallel diodes (diode D5, diode D6) of the switching tubes;

the first power device, the second power device, the third power device and the fourth power device are sequentially connected in series, the first power device is connected with the positive end of the first capacitor, and the fourth power device is connected with the negative end of the second capacitor;

the fifth power device and the sixth power device are connected in parallel, the middle points of the fifth power device and the sixth power device are connected with the middle points of the two capacitors, and the fifth power device and the sixth power device are respectively connected with the middle points of the first power device and the second power device and the middle points of the third power device and the fourth power device;

the middle points of the second power device and the third power device are connected with the AC end of the output point.

In the technical scheme, each phase of two paths of in-phase laminated PWM modulation signals are generated by the DSP and sent to the FPGA, the FPGA receives the signals and delays the signals for 1 dead time in a narrow pulse filtering mode, the original signals and the delayed signals are respectively used for subsequent state machine control, and the balance of time lag of the original signals caused by the rising edge and the falling edge of the modulation signals of the switching tube G1/the switching tube G4 when high/low level is output is realized.

In the technical scheme, each phase of two paths of in-phase laminated PWM modulation signals are generated by the DSP and sent to the FPGA, the FPGA does not directly use the DSP to generate six paths of modulation signals, but uses the level states of the two paths of signals to control a state machine for outputting positive, negative and zero levels, and indirectly controls the output of the modulation signals. When the two PWM modulation signals A, B are 1 and 1, jumping to an output positive level state machine; skipping to the output negative level state machine when the modulation signal A, B is 0 and 0; jumping to an output zero level state machine when the delay signal of the modulation signal A, B is 0 and 1; when the modulation signal A, B is 1 or 0, it is in an abnormal state, and reset blocking is performed. In addition, to ensure reliability, the state transition of the positive level output, the negative level output or fault blocking wave must be carried out through the zero level state when the state is switched.

In the above technical solution, each phase of six modulation signals generated by the FPGA is generated by switching control of the FPGA program state machine, an intermediate state is generated in a switching process of the state machine for transition, a holding time of the intermediate state is controlled by a timer, a dead zone is superimposed on a rising edge and a falling edge of an output modulation signal in the intermediate state, and dead zones of the rising edge and the falling edge of two groups of signals of the switching tube G1/the switching tube G4 and the switching tube G2/the switching tube G3 can be configured respectively.

In the technical scheme, when the four-quadrant operation capability and the power device loss balance are realized in a zero-level current conversion state, the FPGA controls the output of a modulation signal, firstly, the switching tube G5/the switching tube G6 is switched on firstly, short-path current conversion is carried out firstly, and then the switching tube G2/the switching tube G3 are switched on and two current conversion paths are maintained in a steady state, so that the power device loss is balanced when the four-quadrant operation is realized.

In the technical scheme, the active clamping function is realized by carrying out voltage-sharing clamping on the pressure-bearing pipe by controlling the switching pipe G5/switching pipe G6 to be conducted in time through the FPGA when the positive/negative voltage is output.

The present invention will be described in detail with reference to specific examples, and one phase will be used as an example in the following.

Examples

Referring to fig. 3, the present invention describes two PWM modulation signals per phase generated by the DSP, and one way is the same-phase stacked PWM modulation shown in the figure. The positive half cycle and the negative half cycle of the modulation wave generated by the DSP closed-loop control are respectively compared and modulated with two in-phase carriers to generate two paths of PWM modulation signals A, B of each phase, and the signals are sent to a state machine which controls and outputs positive, negative and zero levels by the FPGA. When the FPGA detection A, B is 1, jumping to an output positive level state machine when 1; skipping to the output negative level state machine when the modulation signal A, B is 0 and 0; jumping to an output zero level state machine when the delay signal of the modulation signal A, B is 0 and 1; when the modulation signal A, B is 1 or 0, it is in an abnormal state, and reset blocking is performed.

According to the diagram shown in fig. 4, the FPGA obtains two PWM modulation signals of each phase from the DSP, and delays the signal by time T to obtain a signal EPWMIN _ SG; the signal without delay is denoted EPWMIN _ SG 0. The two groups of signals are sent to an output PWM modulation signal control state machine for judging the switching of the state machine. The specific state machine operating logic is shown in fig. 5, which is described below.

According to fig. 5, the zero-level state switch tube G2, the switch tube G3, the switch tube G5 and the switch tube G6 are turned on, so as to provide two freewheeling paths and balance the on-state loss of each power device; when detecting that a is 1 and B is 1 in the non-delay signal EPWMIN _ SG0, sequentially executing intermediate state output corresponding signals: the positive level short-path follow current, the switch tube G1 on/off dead zone, the switch tube G6 clamping on/off dead zone and finally enter a positive level output state, and the output time of each intermediate state is determined by the dead zone time of each intermediate state in the graph; when detecting that a is 0 and B is 0 in the non-delay signal EPWMIN _ SG0, sequentially executing intermediate state output corresponding signals: the output time of each intermediate state is also determined by the dead time of the switch tube G5. And when serious faults such as shutdown and the like occur in the zero level state, all output signals are shut off, and wave sealing processing is carried out.

According to fig. 6, the positive level output state sequentially executes intermediate state output corresponding signals when detecting that a ≠ 1 and B ≠ 1 in the delay signal EPWMIN _ SG: the switching tube G6 clamps an on/off dead zone, the switching tube G1 an on/off dead zone, a positive level short path follow current, and finally enters a zero level output state, and the output time of each intermediate state is determined by the dead zone time of each intermediate state in the graph; when the negative level output state detects that a is not equal to 0 and B is not equal to 0 in the delay signal EPWMIN _ SG, the intermediate state output corresponding signal is sequentially executed: the switching tube G5 clamps an on/off dead zone, the switching tube G4 an on/off dead zone, the negative level short-path follow current and finally enters a zero level output state, and the output time of each intermediate state is also determined by the dead zone time of each intermediate state in the graph; when the output positive/negative level is in shutdown fault, switching tube G1/switching tube G4 and switching tube G5/switching tube G6 are turned off, and then switching tube G2/switching tube G3 are turned off to carry out wave sealing treatment.

As shown in fig. 7, according to the PWM modulation signal generation, processing and state machine output shown in fig. 3 to 6, six PWM modulation signals per phase shown in fig. 7 are obtained, and the signals are used for driving a three-level ANPC topology power device, so that the beneficial effects of the present invention can be achieved.

In summary, the implementation method is based on a typical architecture of DSP + FPGA, and the DSP has the main functions of three-phase closed-loop control, generating two paths of PWM modulation signals of each phase and sending the PWM modulation signals to the FPGA; the FPGA has the main functions of receiving two paths of PWM signals of each phase sent by the DSP and generating six paths of modulation signals of each phase which can be used for four-quadrant operation, and flexibly adding dead zones to the modulation signals. Compared with other methods applied at present, the PWM signal implementation method keeps the advantages of a typical DSP + FPGA architecture, the DSP chip program does not need to be modified, the generated PWM signal can be used for driving NPC, TNPC and ANPC topology power circuits, and no power device overvoltage risk exists during abnormal fault sealing. According to the implementation method, the FPGA outputs the modulation signal partially, so that the ANPC three-level power circuit has the four-quadrant operation capability, the loss of a power device can be well balanced under different power factors, a pressure-bearing power device outputting positive/negative voltage can be reliably clamped in a voltage equalizing manner, dead zones with different time lengths can be added to the rising edge and the falling edge of different power devices respectively, and the dead zone effect is easy to optimize. The method has the characteristics of simple architecture, flexible scheme, reliable and stable operation and convenience in transplantation.

All articles and references disclosed above, including patent applications and publications, are hereby incorporated by reference for all purposes. The term "consisting essentially of …" describing a combination shall include the identified element, ingredient, component or step as well as other elements, ingredients, components or steps that do not materially affect the basic novel characteristics of the combination. The use of the terms "comprising" or "including" to describe combinations of elements, components, or steps herein also contemplates embodiments that consist essentially of such elements, components, or steps. By using the term "may" herein, it is intended to indicate that any of the described attributes that "may" include are optional.

A plurality of elements, components, parts or steps can be provided by a single integrated element, component, part or step. Alternatively, a single integrated element, component, part or step may be divided into separate plural elements, components, parts or steps. The disclosure of "a" or "an" to describe an element, ingredient, component or step is not intended to foreclose other elements, ingredients, components or steps.

It is to be understood that the above description is intended to be illustrative, and not restrictive. Many embodiments and many applications other than the examples provided would be apparent to those of skill in the art upon reading the above description. The scope of the present teachings should, therefore, be determined not with reference to the above description, but should instead be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. The disclosures of all articles and references, including patent applications and publications, are hereby incorporated by reference for all purposes. The omission in the foregoing claims of any aspect of subject matter that is disclosed herein is not intended to forego such subject matter, nor should the applicant consider that such subject matter is not considered part of the disclosed subject matter.