阅读说明：本技术 一种基于fpga的运动跟踪系统 (Motion tracking system based on FPGA ) 是由 侯占华 于 2019-10-18 设计创作，主要内容包括：一种基于FPGA的运动跟踪系统,包括采样模块、SDRAM控制模块、图像处理模块、视频转换模块、I2C控制模块以及TFT显示模块；图像处理模块由FPGA处理器单元构成,采样模块由CCD摄像头和视频解码芯片组成,输出接口与所述FPGA处理器单元连接,SDRAM控制模块由FPGA处理器单元控制数据的存取,视频转换模块转换从SDRAM控制模块读取的视频格式以便正常显示,I2C控制模块连接图像处理模块与TFT显示模块,TFT显示模块显示视频图像。本发明满足运动跟踪实时性的要求,系统运行速率高,结构简单,设计开发周期短。(A motion tracking system based on FPGA comprises a sampling module, an SDRAM control module, an image processing module, a video conversion module, an I2C control module and a TFT display module; the image processing module is composed of an FPGA processor unit, the sampling module is composed of a CCD camera and a video decoding chip, an output interface is connected with the FPGA processor unit, the SDRAM control module controls data access by the FPGA processor unit, the video conversion module converts a video format read from the SDRAM control module so as to be displayed normally, the I2C control module is connected with the image processing module and the TFT display module, and the TFT display module displays video images. The invention meets the requirement of motion tracking real-time performance, and has the advantages of high system running speed, simple structure and short design and development period.)

1. A motion tracking system based on FPGA comprises a sampling module, an SDRAM control module, an image processing module, a video conversion module, an I2C control module and a TFT display module; the image processing module is composed of an FPGA processor unit, the sampling module is composed of a CCD camera and a video decoding chip, an output interface is connected with the FPGA processor unit, the SDRAM control module controls data access by the FPGA processor unit, the video conversion module converts a video format read from the SDRAM control module so as to normally display, the I2C control module is connected with the image processing module and the TFT display module, and the TFT display module displays video images.

2. The motion tracking system of claim 1, wherein the sampling module collects an external image through a CCD camera, and the collected data is passed through a FIFO data buffer module to convert an original synchronous data stream at 25Hz frequency to 100MHz frequency, and then sent to a buffer FIFO of an SDRAM.

3. The motion tracking system of claim 2, wherein when the FIFO data buffer module is 160 pages full, the data is written to the corresponding address of the SDRAM, and another asynchronous FIFO is invoked to read the image from the SDRAM buffer.

4. The motion tracking system of claim 1, wherein the SDRAM control module enters an idle state after chip initialization, responding to commands upon request.

5. The motion tracking system of claim 1, wherein the FPGA processor unit comprises an FPGA chip, a clock, a power supply, and a configuration circuit.

6. The motion tracking system of claim 1, wherein the video conversion module converts the captured video stream signal format from YCbCr4:2:2 → YCbCr4:4:4 → RGB 888.

7. The motion tracking system of claim 1, wherein the TFT display module comprises an RGB three-channel D/a conversion chip, a display screen, and a VGA interface, and the D/a data input is connected to the FPGA processor unit.

Technical Field

The invention relates to a computer vision technology, in particular to a motion tracking system based on an FPGA.

Background

The moving target tracking system technology is widely applied to the fields of security monitoring, intelligent transportation, industrial detection, consumer electronics and the like, and target tracking is a new technology developed on the basis of artificial intelligence and computer vision and used for realizing image detection and target identification.

Object-based moving object analysis may be converted to analysis of moving objects in video images. Video images can be acquired through an image sensor, then the acquired analog images are quantized into digital images, the digital images are divided into matrix mathematical models in a computer, each point on the matrix represents the gray value of a pixel, the gray value of each pixel is expressed by an integer, and for the digital images expressed by the matrix, the digital images can be analyzed and processed by matrix theory and some other mathematical methods. For this reason, various algorithms are provided for image processing, so that image processing becomes flexible. There is also a common bottleneck in image processing, namely time, and bandwidth required to read images from and write resulting images to memory, whereas FPGA-based moving object tracking systems need to be real-time, i.e. a response to a time within the system must be completed within a given time, otherwise the system is considered to be failed, and for this purpose image acquisition and processing, a high-speed processor is required. The single chip microcomputer and the ARM are not suitable for image processing, and because the image information amount is large, clocks of the single chip microcomputer and the ARM are not suitable for image processing.

Disclosure of Invention

In order to solve at least one of the above technical problems, the present invention provides a motion tracking system based on an FPGA.

The specific technical scheme is as follows:

a motion tracking system based on FPGA comprises a sampling module, an SDRAM control module, an image processing module, a video conversion module, an I2C control module and a TFT display module; the image processing module is composed of an FPGA processor unit, the sampling module is composed of a CCD camera and a video decoding chip, an output interface is connected with the FPGA processor unit, the SDRAM control module controls data access by the FPGA processor unit, the video conversion module converts a video format read from the SDRAM control module so as to normally display, the I2C control module is connected with the image processing module and the TFT display module, and the TFT display module displays video images.

Preferably, the sampling module collects an external image through a CCD camera, and the collected data is converted into a synchronous data stream with a frequency of originally 25Hz into a frequency of 100MHz through an FIFO data buffer module, and then the data is sent to a buffer FIFO of the SDRAM.

Preferably, when the data in the FIFO data buffer module reaches 160 pages full, the data is written into the corresponding address of the SDRAM, and another asynchronous FIFO is called to read the image cached by the SDRAM.

Preferably, the SDRAM control module enters an idle state after chip initialization, and may respond to the command according to the request.

Preferably, the FPGA processor unit includes an FPGA chip, a clock, a power supply, and a configuration circuit.

Preferably, the video conversion module converts the format of the acquired video stream signal, which is formed by YCbCr4:2:2 → YCbCr4:4:4 → RGB 888.

Preferably, the TFT display module consists of an RGB three-channel D/A conversion chip, a display screen and a VGA interface, and the D/A data input is connected with the FPGA processor unit.

Has the advantages that: the FPGA has the advantages of low price, short design and development period, high flexibility, adoption of a multi-stage pipeline technology, high-efficiency parallel processing, parallel operation, repeated use and large number of usable soft cores, and can realize the change of a hardware structure at any time in the development process.

Drawings

FIG. 1 is a block diagram of the system architecture of the present invention;

FIG. 2 is a circuit diagram of the RTL of the present invention;

FIG. 3 is a block diagram of an image acquisition module;

fig. 4 is a flowchart of a moving object detection method.

Detailed Description

The invention is further illustrated by the following specific examples. The starting materials and methods employed in the examples of the present invention are those conventionally available in the market and conventionally used in the art, unless otherwise specified.

Example 1

As shown in fig. 1 to 3, an FPGA-based motion tracking system includes a sampling module, an SDRAM control module, an image processing module, a video conversion module, an I2C control module, and a TFT display module; the image processing module is composed of an FPGA processor unit, the sampling module is composed of a CCD camera and a video decoding chip, an output interface is connected with the FPGA processor unit, the SDRAM control module controls data access by the FPGA processor unit, the video conversion module converts a video format read from the SDRAM control module so as to normally display, the I2C control module is connected with the image processing module and the TFT display module, and the TFT display module displays video images.

The sampling module collects external images through the CCD camera, the collected data are converted into a frequency of 100MHz through an FIFO data cache module, and then the data are sent to a cache FIFO of the SDRAM, wherein the frequency of the synchronous data stream is originally 25 Hz.

When the data in the FIFO data buffer module reaches 160 pages full, the data is written into the corresponding address of the SDRAM, and the image cached by the SDRAM can be read by calling another asynchronous FIFO.

The SDRAM control module enters an idle state after the chip is initialized and can respond to the command according to the request.

The FPGA processor unit comprises an FPGA chip, a clock, a power supply and a configuration circuit.

The video conversion module converts the format of the collected video stream signal, namely YCbCr4:2:2 → YCbCr4:4:4 → RGB 565.

The TFT display module consists of an RGB three-channel D/A conversion chip, a display screen and a VGA interface, and the D/A data input is connected with the FPGA processor unit.

As shown in fig. 4, for this embodiment, a background subtraction method is selected as a feasible and effective moving target detection method flow, and a background is selected first, a model is built for a background image, then a subtraction is performed with a current frame image, and finally a pre-value comparison is performed, so as to detect a target object.

Has the advantages that: the FPGA has the advantages of low price, short design and development period, high flexibility, adoption of a multi-stage pipeline technology, high-efficiency parallel processing, parallel operation, repeated use and large number of usable soft cores, and can realize the change of a hardware structure at any time in the development process.

It should be understood that the above examples are only for clearly illustrating the technical solutions of the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.