阅读说明：本技术 光刻曝光方法 (Photoetching exposure method ) 是由 周曙亮 赵潞明 吴长明 姚振海 金乐群 李玉华 于 2020-12-07 设计创作，主要内容包括：本申请涉及半导体制造技术领域,具体涉及一种光刻曝光方法。所述光刻曝光方法包括：将晶片的目标面划分为曝光阵列,所述曝光阵列包括若干个曝光区域；确定曝光区域中的目标量测曝光区域和其他曝光区域；依次对所述其他曝光区域分别进行多次光刻曝光,在所述其他曝光区域处的晶片目标面上形成光刻图形；对所述目标量测曝光区域进行单次光刻曝光,在所述目标量测曝光区域处的晶片目标面上形成光刻图形。本申请提供的光刻曝光方法,可以解决相关技术中在开始进行光刻曝光的前期,因光学系统温度不稳定,导致机台对光刻表现的判断的问题。(The application relates to the technical field of semiconductor manufacturing, in particular to a photoetching exposure method. The photoetching exposure method comprises the following steps: dividing a target surface of a wafer into an exposure array, wherein the exposure array comprises a plurality of exposure areas; determining a target measurement exposure area and other exposure areas in the exposure area; sequentially and respectively carrying out multiple times of photoetching exposure on the other exposure areas, and forming photoetching patterns on the target surfaces of the wafers at the other exposure areas; and carrying out single photoetching exposure on the target measurement exposure area, and forming a photoetching pattern on the target surface of the wafer at the target measurement exposure area. The photoetching exposure method can solve the problem that in the prior art, the temperature of the optical system is unstable, so that the machine table judges the photoetching performance.)

1. A lithographic exposure method, comprising:

dividing a target surface of a wafer into an exposure array, wherein the exposure array comprises a plurality of exposure areas;

determining a target measurement exposure area and other exposure areas in the exposure area;

sequentially and respectively carrying out multiple times of photoetching exposure on the other exposure areas, and forming photoetching patterns on the target surfaces of the wafers at the other exposure areas;

and carrying out single photoetching exposure on the target measurement exposure area, and forming a photoetching pattern on the target surface of the wafer at the target measurement exposure area.

2. A lithographic exposure method according to claim 1, wherein, after completion of the step of forming a lithographic pattern on the target surface of the wafer at the target metrology exposure area, further performing:

the measurement target measures the critical dimension of the photoetching pattern at the exposure area.

3. The lithographic exposure method of claim 1 or 2, wherein the step of determining the target metrology exposure area and the other exposure areas in the exposure area comprises:

determining a target metrology exposure area in an exposure array; an exposure area for measuring the critical dimension of the photoetching pattern is a target measurement exposure area;

and determining an exposure area except the target measurement exposure area in the exposure array as the other exposure areas.

4. A lithographic exposure method according to claim 1, wherein the exposure arrays of a plurality of wafers are arranged identically, and the target metrology exposure fields are located identically in the exposure arrays.

5. The lithographic exposure method of claim 1, wherein if it is determined that the target metrology exposure field comprises a plurality of target metrology exposure fields, performing a single lithographic exposure of the target metrology exposure field to form a lithographic pattern on the target surface of the wafer at the target metrology exposure field, comprises:

and sequentially carrying out single photoetching exposure on each target measurement exposure area, and forming a photoetching pattern on the target surface of the wafer at the target measurement exposure area.

6. The lithographic exposure method of claim 1, wherein the exposure parameters of each of said lithographic exposures are consistent.

7. The lithographic exposure method according to claim 1, wherein the number of lithographic exposures to the other exposure region is 3 to 6.

Technical Field

The application relates to the technical field of semiconductor manufacturing, in particular to a photoetching exposure method.

Background

In the exposure, a pattern of a mask plate is projected onto a photoresist through an optical system by utilizing illumination to realize pattern transfer, and the exposure is one of important processes of a photoetching process in integrated circuit manufacturing. After the photolithography exposure is completed, it is necessary to reflect the photolithography performance by measuring the Critical Dimension (CD) of the pattern formed by photolithography and comparing the CD measurement value with a target value, for example: and verifying whether the exposure energy of the photoetching machine drifts or not so as to decide whether to compensate the exposure energy in subsequent operation or not. Usually, the deviation between the measured value and the target value of the graph CD is allowed to be within +/-8-10%.

However, before the photolithography exposure is performed by using the photolithography machine, if the standby time of the photolithography machine is long, the temperature of the optical system is low, and thus the temperature of the optical system of the photolithography machine gradually rises in the early stage of starting the photolithography exposure. In the wafer subjected to the lithography exposure operation in the period, the problem of large difference of the pattern CD between the front piece and the back piece can occur, namely, in the early stage of the lithography exposure, the formed pattern CD between the front piece and the back piece can show a gradually descending situation in the process that the temperature of the optical system gradually rises, so that the judgment of the machine table on the lithography performance is misled, and the subsequent operation is adversely affected.

Disclosure of Invention

The application provides a photoetching exposure method which can solve the problem that in the prior art, in the early stage of starting photoetching exposure, the temperature of an optical system is unstable, so that the machine table judges photoetching performance.

The application provides a photoetching exposure method, which comprises the following steps:

dividing a target surface of a wafer into an exposure array, wherein the exposure array comprises a plurality of exposure areas;

determining a target measurement exposure area and other exposure areas in the exposure area;

sequentially and respectively carrying out multiple times of photoetching exposure on the other exposure areas, and forming photoetching patterns on the target surfaces of the wafers at the other exposure areas;

and carrying out single photoetching exposure on the target measurement exposure area, and forming a photoetching pattern on the target surface of the wafer at the target measurement exposure area.

Optionally, after the step of forming the lithography pattern on the target surface of the wafer at the target measurement exposure area is completed, the following steps are further performed:

the measurement target measures the critical dimension of the photoetching pattern at the exposure area.

Optionally, the step of determining the target measurement exposure area and other exposure areas in the exposure area includes:

determining a target metrology exposure area in an exposure array; an exposure area for measuring the critical dimension of the photoetching pattern is a target measurement exposure area;

and determining an exposure area except the target measurement exposure area in the exposure array as the other exposure areas.

Optionally, the exposure arrays of the multiple wafers are arranged in the same manner, and the positions of the target measurement exposure areas in the exposure arrays are the same.

Optionally, if it is determined that the target measurement exposure area includes a plurality of target measurement exposure areas, performing a single lithography exposure on the target measurement exposure area, and forming a lithography pattern on the wafer target surface at the target measurement exposure area, including:

and sequentially carrying out single photoetching exposure on each target measurement exposure area, and forming a photoetching pattern on the target surface of the wafer at the target measurement exposure area.

Optionally, the exposure parameters of each lithography exposure are consistent.

Optionally, the number of photolithographic exposures on the other exposure regions is 3 to 6.

The technical scheme at least comprises the following advantages: the target surface of a wafer is divided into an exposure array, the exposure array comprises a plurality of exposure areas, and the exposure areas are arranged in an array form; determining a target measurement exposure area and other exposure areas in the exposure area; sequentially and respectively carrying out multiple times of photoetching exposure on the other exposure areas, and forming photoetching patterns on the target surfaces of the wafers at the other exposure areas; and photoetching exposure is carried out on the target measurement exposure area, and a photoetching pattern is formed on the target surface of the wafer at the target measurement exposure area. The photoetching patterns formed at the target measurement exposure areas of different wafers of the same batch are close in critical dimension, and the situation that the front and rear piece patterns CD gradually decline is avoided.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 illustrates a lithographic exposure method provided by an embodiment of the present application;

FIG. 2 shows a schematic diagram of a wafer target surface divided into an exposure array;

FIG. 3 shows a schematic distribution of other exposure areas and target metrology exposure areas on the exposure array in an embodiment of the exposure matrix;

FIG. 4 is a graph showing the trend of critical dimension variation of a lithographic pattern in an exposure area of an exposure array after metrology has been completed by a related art technique;

FIG. 5 is a graph showing the trend of the critical dimension of the lithography pattern in the target measurement exposure area of the exposure array after the exposure array is measured by the embodiment of the present application.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.

Fig. 1 illustrates a photolithography exposure method provided in an embodiment of the present application, and referring to fig. 1, the photolithography exposure method includes the following steps:

step S1: the target surface of the wafer is divided into an exposure array, the exposure array comprises a plurality of exposure areas, and the exposure areas are arranged in an array mode.

Fig. 2 shows a schematic diagram of the target surface 100 of the wafer divided into exposure arrays 200. referring to fig. 2, the exposure arrays cover the target surface 100 of the wafer, and the exposure arrays 200 include a plurality of exposure regions, which are arranged in an array. It should be noted that the exposure array in step S1 is pre-planned for the target surface of the wafer in the photolithography tool to guide the exposure plan, rather than the physical structures actually formed on the target surface of the wafer. Wherein the target side of the wafer refers to the side surface of the wafer that is used for exposure. The extent of the target surface of the wafer defined by each exposure field is the extent of one exposure.

For the exposure array, each exposure area has a unique position identification code, and the position identification code can represent the corresponding position of the exposure area in the exposure array.

Step S2: a target metrology exposure area and other exposure areas in the exposure area are determined.

The step S2: determining a target metrology exposure area and other exposure areas in the exposure area, including:

firstly, determining a target measurement exposure area in an exposure array; the exposure area for selecting photoetching pattern key size measurement is a target measurement exposure area; for the wafers exposed in the same batch, the exposure arrays are arranged in the same way, the specific positions of the target measurement exposure areas in the exposure arrays are the same, and the target measurement exposure areas are preset in the machine.

Then, in the exposure array, an exposure area other than the target measurement exposure area is determined as the other exposure area.

For the other exposure areas, the corresponding wafer target surface range can be subjected to multiple exposures, and the exposure parameters including exposure energy and the like are consistent during one exposure. In the subsequent steps, the number of times of the photolithography exposure on the other exposure regions may be determined according to specific situations, but it is necessary to keep the exposure temperature of the optical system stable after the exposure on the other exposure regions is completed.

FIG. 3 is a schematic diagram of the distribution of other exposure areas and target metrology exposure areas on the exposure array in one embodiment of the exposure matrix. Referring to fig. 3, the present embodiment determines nine target metrology exposure fields M1-M9 from the exposure matrix 200, the nine target metrology exposure fields M1-M9 being distributed at the center of the exposure matrix 200 and on the circumference of a circle centered at the center. Due to the target metrology exposure regions M1-M9, it is subsequently necessary to perform critical dimension metrology of the lithographic pattern. Taking a wafer as an example, the average critical dimension of the lithography pattern formed at the target measurement exposure area is used as the average critical dimension of the wafer, so that only a single exposure is performed on the target measurement exposure area to avoid affecting the measurement accuracy.

Step S3: and sequentially and respectively carrying out multiple times of photoetching exposure on the other exposure areas, and forming photoetching patterns on the target surfaces of the wafers at the other exposure areas.

In this embodiment, the other exposure regions 210 shown in fig. 3 may be subjected to four times of lithography exposure, and the exposure parameters including exposure energy and the like during one exposure are consistent, so that the exposure temperature of the optical system remains stable after the exposure is completed.

Step S4: and photoetching exposure is carried out on the target measurement exposure area, and a photoetching pattern is formed on the target surface of the wafer at the target measurement exposure area.

In step S4, if the target metrology exposure field includes a plurality of target metrology exposure fields, a single lithography exposure should be performed on each target metrology exposure field in sequence, and a lithography pattern is formed on the target surface of the wafer at the target metrology exposure field until all target metrology exposure fields of the wafer are lithographically exposed.

Since the exposure temperature of the optical system is kept stable before step S4, the critical dimensions of the lithography patterns formed at the target measurement exposure regions of the wafers of the same lot are similar, and the situation that the front and rear wafer patterns CD will gradually decrease is avoided.

The development is performed after step S4, and is further performed after the development in step S5: the measurement target measures the critical dimension of the photoetching pattern at the exposure area.

Fig. 4 is a graph showing a trend of a variation in a mean value of critical dimensions of a lithography pattern of a lot of wafers after exposure by related art lithography. The abscissa of fig. 4 represents the wafer sequence code, and the earlier the wafer sequence code is smaller, i.e. the abscissa becomes larger from left to right, and represents the time that the wafer corresponding to the sequence code is exposed is gradually later; the ordinate represents the average critical dimension in nanometers (nm) of the wafer lithographic pattern. As can be seen from fig. 4, as the wafer sequence code increases, the average cd of the wafer lithographic pattern tends to decrease, i.e., the average cd of the pattern of the previously exposed wafer is larger.

Fig. 5 is a graph comparing a trend of a variation of a critical dimension average value of a lithography pattern of a batch of wafers after lithography exposure by the lithography exposure method provided by the embodiment of the present application and the lithography exposure method provided by the related art.

The abscissa of fig. 5 represents the wafer sequence code, and the earlier the wafer sequence code is exposed, i.e. the abscissa becomes larger from left to right, and represents the time that the wafer corresponding to the sequence code is exposed is gradually later; the ordinate represents the average critical dimension in nanometers (nm) of the wafer lithographic pattern. In fig. 5, curve a shows the average cd variation curve of the lithographic pattern of the first wafer W1 to the eighth wafer W8 in a batch of wafers after the lithographic exposure method provided by the embodiment of the present application; curve B shows the average cd variation of the lithographic pattern of each wafer from wafer 1 to 8 in the sequence code of a lot of wafers after the lithographic exposure method provided by the related art.

As can be seen from curve B, in the wafers with sequence codes of 1 to 4, the average critical dimension of the lithography pattern of each wafer fluctuates from 416nm to 416 nm; and 5 to 8 wafers with the average critical dimension of the lithography pattern of each wafer fluctuating above and below 408 nm. The average critical dimension deviation of the photoetching patterns of the wafers with the sequence codes of 1 to 4 and the wafers with the sequence codes of 5 to 8 exceeds the allowable range of errors, so that the photoetching exposure method provided by the related technology is reflected to a certain extent, and the exposure effect is poor in stability in the early stage of photoetching exposure.

It can be seen from curve A that as the wafer sequence code becomes larger and larger, the average critical dimension of the lithographic pattern of each wafer does not change much, but fluctuates from 402nm up and down (399nm to 405 nm). Therefore, the photolithography exposure method provided by the embodiment of the application solves the problem that in the prior art, the judgment of the machine table on the photolithography performance is caused by unstable temperature of the optical system in the early stage of starting photolithography exposure. The exposure effect of the target measurement exposure area is stable, and judgment of the misguide machine platform on the photoetching performance is avoided.

According to the method, the target surface of the wafer is divided into the exposure array, the exposure array comprises a plurality of exposure areas, and the exposure areas are arranged in an array manner; determining a target measurement exposure area and other exposure areas in the exposure area; sequentially and respectively carrying out multiple times of photoetching exposure on the other exposure areas, and forming photoetching patterns on the target surfaces of the wafers at the other exposure areas; and photoetching exposure is carried out on the target measurement exposure area, and a photoetching pattern is formed on the target surface of the wafer at the target measurement exposure area. The photoetching patterns formed at the target measurement exposure areas of different wafers of the same batch are close in critical dimension, and the situation that the front and rear piece patterns CD gradually decline is avoided.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.