阅读说明：本技术 恒流控制电路及控制方法以及反激电路 (Constant current control circuit and control method and flyback circuit ) 是由 俞秀峰 张波 蓝舟 于 2019-10-09 设计创作，主要内容包括：本发明揭示了一种恒流控制电路及控制方法以及反激电路,在系统处于连续模式时,所述恒流控制电路控制原边电感中值电流与副边的第一导通占空比的乘积在设定第一阈值区间；在系统处于断续模式时,所述恒流控制电路控制原边电感峰值电流的一半与副边的第二导通占空比的乘积在所述第一阈值区间。本发明提出的恒流控制电路及控制方法以及反激电路,可以大大提高系统工作于高压输入在DCM模式下的恒流精度,避免因CS电压波形振荡而导致的采样误差,同时也消除了中值采样位置偏差对系统恒流的影响。(The invention discloses a constant current control circuit, a control method and a flyback circuit, wherein when a system is in a continuous mode, the constant current control circuit controls the product of the median current of a primary side inductor and the first conduction duty ratio of a secondary side to be within a set first threshold interval; when the system is in an intermittent mode, the constant current control circuit controls the product of half of the peak current of the primary side inductor and the second conduction duty ratio of the secondary side to be in the first threshold interval. The constant current control circuit, the control method and the flyback circuit provided by the invention can greatly improve the constant current precision of the system working in a DCM mode of high-voltage input, avoid sampling errors caused by CS voltage waveform oscillation, and simultaneously eliminate the influence of the deviation of a median sampling position on the constant current of the system.)

1. A constant current control circuit is characterized in that when a system is in a continuous mode, the constant current control circuit controls the product of a median current of a primary side inductor and a first conduction duty ratio of a secondary side to be in a set first threshold interval; when the system is in an intermittent mode, the constant current control circuit controls the product of half of the peak current of the primary side inductor and the second conduction duty ratio of the secondary side to be in the first threshold interval.

2. The constant current control circuit according to claim 1, wherein:

the constant current control circuit includes:

the first discharge path receives the first degaussing time signal and controls the working state of the first discharge path according to the state of the first degaussing time signal;

the second discharge path receives the second degaussing time signal and controls the working state of the second discharge path according to the state of the second degaussing time signal; and

and the output end of the charging circuit is respectively coupled with the first discharging path and the second discharging path and is used for charging the first discharging path and the second discharging path.

3. The constant current control circuit according to claim 2, wherein:

the first discharge path comprises a first switch, a first switch tube driving module and a first resistor; the first switch receives the first degaussing time signal and controls the on-off of the first switch according to the first degaussing time signal; the first end of the first switch is coupled with the charging circuit, and the second end of the first switch is coupled with the second end of the first switch tube; a first input end of the first switch tube driving module is coupled to a sampling resistor median voltage corresponding to a primary side inductor median current, a second input end of the first switch tube driving module is coupled to a third end of the first switch tube and a first end of the first resistor, and an output end of the first switch tube driving module is coupled to a first end of the first switch tube;

the second discharge path comprises a second switch, a second switch tube driving module and a second resistor; the second switch receives a second degaussing time signal and controls the on-off of the second switch according to the second degaussing time signal; the first end of the second switch is coupled with the charging circuit, and the second end of the second switch is coupled with the second end of the second switch tube; the first input end of the second switch tube driving module is coupled to the peak voltage of the sampling resistor corresponding to the peak current of the primary inductor, the second input end of the second switch tube driving module is coupled to the third end of the second switch tube and the first end of the second resistor, and the output end of the second switch tube driving module is coupled to the first end of the second switch tube.

4. The constant current control circuit according to claim 3, wherein:

the resistance value of the second resistor is 2 times of that of the first resistor.

5. The constant current control circuit according to claim 2, wherein:

the constant current control circuit comprises a discharge path control circuit and is used for controlling the states of a first degaussing time signal and a second degaussing time signal;

when the discharge passage control circuit controls the first demagnetization time signal to be effective, the first discharge passage carries out a discharge process;

and when the discharge passage control circuit controls the second demagnetization time signal to be effective, the second discharge passage carries out a discharge process.

6. The constant current control circuit according to claim 5, wherein:

the discharge path control circuit is further used for controlling the switching selection between the first degaussing time signal and the second degaussing time signal, and the switching selection logics of the first degaussing time signal and the second degaussing time signal are complementary.

7. The constant current control circuit according to claim 5, wherein:

the discharging path control circuit comprises a path interlocking circuit and is used for locking the states of the first degaussing time signal and the second degaussing time signal within a first set time when the first degaussing time signal or the second degaussing time signal is triggered.

8. The constant current control circuit according to claim 5, wherein:

and when the second discharge path is opened, delaying a second set time to offset an error signal brought by demagnetization detection.

9. The constant current control circuit according to claim 1, wherein:

when the system is stable, satisfy

Wherein, V_{mid_P}The system is a sampling resistor median voltage V corresponding to the primary side inductance median current in a continuous mode_{dcm_pk_P}The peak voltage of the sampling resistor, D, corresponding to the peak current of the primary inductor when the system is in the discontinuous mode_OFFIs the first on duty cycle of the secondary side when the system is in continuous mode, D_DEMThe second conduction duty ratio of the secondary side when the system is in the discontinuous mode;

when the system is in a transition process, the two discharge paths corresponding to the first demagnetization time and the second demagnetization time are opened and logically complemented.

10. A flyback circuit, characterized by: comprising a constant current control circuit as claimed in any one of claims 1 to 9.

11. A constant current control method is characterized by comprising the following steps:

when the system is in a continuous mode, controlling the product of the median current of the primary side inductor and the first conduction duty ratio of the secondary side to be in a set first threshold interval;

and when the system is in a discontinuous mode, controlling the product of half of the peak current of the primary inductor and the second conduction duty ratio of the secondary side to be in the first threshold interval.

12. The constant-current control method according to claim 11, characterized in that:

when the system is stable, satisfy

Wherein, V_{mid_P}The system is a sampling resistor median voltage V corresponding to the primary side inductance median current in a continuous mode_{dcm_pk_P}The peak voltage of the sampling resistor, D, corresponding to the peak current of the primary inductor when the system is in the discontinuous mode_OFFIs the first on duty cycle of the secondary side when the system is in continuous mode, D_DEMThe second conduction duty ratio of the secondary side when the system is in the discontinuous mode;

when the system is in a transition process, the two discharge paths corresponding to the first demagnetization time and the second demagnetization time are opened and logically complemented.

13. The constant-current control method according to claim 11, characterized in that:

the constant current control method comprises the following steps: controlling the states of the first demagnetization time signal and the second demagnetization time signal;

when the discharge passage control circuit controls the first demagnetization time signal to be effective, the first discharge passage carries out a discharge process;

and when the discharge passage control circuit controls the second demagnetization time signal to be effective, the second discharge passage carries out a discharge process.

14. The constant-current control method according to claim 13, characterized in that:

the constant current control method comprises the following steps: and controlling the switching selection between the first degaussing time signal and the second degaussing time signal, wherein the switching selection of the first degaussing time signal and the second degaussing time signal is complementary in logic.

15. The constant-current control method according to claim 13, characterized in that:

the constant current control method comprises the following steps: and when the second discharge path is controlled to be opened, delaying a second set time to offset an error signal brought by demagnetization detection.

Technical Field

The invention belongs to the technical field of circuit control, relates to a flyback circuit, and particularly relates to a constant current control circuit, a control method and a flyback circuit.

Background

Fig. 1 is a circuit schematic of a typical flyback circuit; referring to fig. 1, to realize the constant current function of the secondary output by the primary sampling, the CS median of the primary current and the on duty ratio of the secondary current need to be sampled.

Fig. 2a is a key waveform diagram of the flyback circuit operating in the discontinuous mode DCM, and fig. 2b is a key waveform diagram of the flyback circuit operating in the continuous mode CCM; referring to fig. 2a and 2b, the chip calculates the average value of the secondary side inductor current or the primary side inductor current sampled in each switching period to control the average output current:

wherein: is (t) is secondary side inductance real-time current and output diode real-time current; ip (t) is the primary side inductance real-time current; n-the turn ratio of the primary winding to the secondary winding of the transformer. The average current of the secondary side inductor can be expressed in a uniform form in a discontinuous mode and a continuous mode, namely the current discharge time T of the secondary side inductor_DISInductor current I corresponding to intermediate time of secondary side inductor current discharge time_{mid_S}The product of (a):

wherein: i is_{mid_P}The primary side inductance current is the primary side inductance current at the middle conduction moment of the primary side of the transformer.

Demagnetization time T of secondary side inductance current_DISCan be expressed in the following forms:

in equation 3: t is_DIS＝T_DEMIs in a DCM mode; t is_DIS＝T_OFFIn CCM mode

In conjunction with equations 1 through 3, the average output current can be expressed by the following equation:

wherein: r_CSA primary side current sampling resistor; v_{mid_P}For the system to be atWhen the continuous mode primary side switch is on, R_CSSampling a median voltage on a resistor; d_DIS＝T_DIS/T_SThe duty ratio is turned on for the secondary side. At a set R_CSWhile controlling V_{mid_P}And D_DISThe product of (A) and (B) is a constant value, and constant current output of the system can be realized.

In practical application, under the condition that the DCM operation mode usually occurs at the high voltage input, the following points will affect the sampling precision of the CS median voltage and the degaussing time T_DEMResulting in a decrease of the constant current accuracy in DCM:

(1) when high voltage is input, the CS waveform is easy to oscillate, so that the deviation of the median voltage sampling is large;

(2) due to high-voltage input, the primary side conduction time Ton is shortened, so that the deviation of the median position Ton/2 is increased;

(3) during demagnetization detection, the ratio T obtained by sampling is caused by oscillation factors_DEMThe actual value is somewhat larger.

In view of the above, there is a need to design a constant current control method for a flyback circuit so as to overcome the above-mentioned defects of the conventional constant current control method for the flyback circuit.

Disclosure of Invention

The invention provides a constant current control circuit, a control method and a flyback circuit, which can improve the constant current output precision.

In order to solve the technical problem, according to one aspect of the present invention, the following technical solutions are adopted:

when a system is in a continuous mode, the constant current control circuit controls the product of the median current of a primary side inductor and the first conduction duty ratio of a secondary side to be in a set first threshold interval; when the system is in an intermittent mode, the constant current control circuit controls the product of half of the peak current of the primary side inductor and the second conduction duty ratio of the secondary side to be in the first threshold interval.

As an embodiment of the present invention, the constant current control circuit includes:

the first discharge path receives the first degaussing time signal and controls the working state of the first discharge path according to the state of the first degaussing time signal;

the second discharge path receives the second degaussing time signal and controls the working state of the second discharge path according to the state of the second degaussing time signal; and

and the output end of the charging circuit is respectively coupled with the first discharging path and the second discharging path and is used for charging the first discharging path and the second discharging path.

As an embodiment of the present invention, the first discharge path includes a first switch, a first switch tube driving module, and a first resistor; the first switch receives the first degaussing time signal and controls the on-off of the first switch according to the first degaussing time signal; the first end of the first switch is coupled with the charging circuit, and the second end of the first switch is coupled with the second end of the first switch tube; a first input end of the first switch tube driving module is coupled to a sampling resistor median voltage corresponding to a primary side inductor median current, a second input end of the first switch tube driving module is coupled to a third end of the first switch tube and a first end of the first resistor, and an output end of the first switch tube driving module is coupled to a first end of the first switch tube;

the second discharge path comprises a second switch, a second switch tube driving module and a second resistor; the second switch receives a second degaussing time signal and controls the on-off of the second switch according to the second degaussing time signal; the first end of the second switch is coupled with the charging circuit, and the second end of the second switch is coupled with the second end of the second switch tube; the first input end of the second switch tube driving module is coupled to the peak voltage of the sampling resistor corresponding to the peak current of the primary inductor, the second input end of the second switch tube driving module is coupled to the third end of the second switch tube and the first end of the second resistor, and the output end of the second switch tube driving module is coupled to the first end of the second switch tube.

As an embodiment of the present invention, the resistance value of the second resistor is 2 times that of the first resistor.

As an embodiment of the present invention, the constant current control circuit includes a discharge path control circuit for controlling states of the first demagnetization time signal and the second demagnetization time signal;

when the discharge passage control circuit controls the first demagnetization time signal to be effective, the first discharge passage carries out a discharge process;

and when the discharge passage control circuit controls the second demagnetization time signal to be effective, the second discharge passage carries out a discharge process.

As an embodiment of the present invention, the discharge path control circuit is further configured to control a switching selection between the first degaussing time signal and the second degaussing time signal, and the switching selection of the first degaussing time signal and the second degaussing time signal are complementary.

As an embodiment of the present invention, the discharge path control circuit includes a path interlock circuit for locking states of the first demagnetization time signal and the second demagnetization time signal within a first set time when the first demagnetization time signal or the second demagnetization time signal is triggered.

In one embodiment of the present invention, when the second discharge path is opened, a second set time is delayed to cancel an error signal caused by demagnetization detection.

As an embodiment of the present invention, the discharge path control circuit includes a first flip-flop U1, a second flip-flop U2, a third flip-flop U3, a fourth flip-flop U4, an or gate, a first and gate, a second and gate, a third and gate, a fourth and gate, a fifth and gate, a sixth and gate, a first not gate, and a second not gate;

the falling edges of the Gate control input signal Gate are respectively coupled to the first input terminal of the first flip-flop U1, the input terminal of the first not Gate, the first input terminal of the second flip-flop U2, the input terminal of the second not Gate, and the first input terminal of the third flip-flop U3; the output end of the second NOT gate is coupled with the first input end of the first AND gate; the output end of the second NOT gate is coupled with the first input end of the second AND gate;

the rising edges of the Gate control input signals Gate are respectively coupled with the second input end of the first AND Gate, the first input end of the OR Gate and the first input end of the third AND Gate; the output end of the first AND gate is coupled with the second input end of the first flip-flop U1, and the output end of the second AND gate is coupled with the second input end of the second flip-flop U2;

the ZCD signal is respectively coupled with a second input end of the second AND gate, a second input end of the OR gate and a second input end of the fourth AND gate; an output terminal of the or gate is coupled to a second input terminal of the third flip-flop U3;

a first output terminal of the first flip-flop U1 is coupled to a first input terminal of a fifth and gate, and a first output terminal of the second flip-flop U2 is coupled to a first input terminal of a sixth and gate;

a first output end of the third flip-flop U3 is coupled to a second input end of the third and gate and a first input end of the fourth and gate, respectively, an output end of the third and gate is coupled to a first input end of the fourth flip-flop U4, and an output end of the third and gate is coupled to a second input end of the fourth flip-flop U4; a first output terminal of the fourth flip-flop U4 is coupled to a second input terminal of the fifth and gate, and a second output terminal of the fourth flip-flop U4 is coupled to a second input terminal of the sixth and gate.

As an embodiment of the present invention, the discharge path control circuit further includes a buffer, a seventh and gate;

the output end of the sixth AND gate is respectively coupled with the input end of the buffer and the second input end of the seventh AND gate, and the output end of the buffering period is coupled with the first input end of the seventh AND gate;

when the second discharge path is opened, the buffer delays for a set time to offset an error signal caused by demagnetization detection.

In one embodiment of the present invention, when the second discharge path is turned on, the buffer delays for a pulse period Td to cancel an error signal caused by demagnetization detection.

In one embodiment of the present invention, the fourth flip-flop U4 is set to have a first demagnetization time T_OFFSignal and second degaussing time T_DEMThe selection trigger of the signal selects the first degaussing time T when the fourth trigger U4 outputs high level_OFFSignal that the second degaussing time T is selected when the fourth flip-flop U4 outputs a low level_DEMSignal；

The third flip-flop U3 latches the signal for this period, and U3 outputs high level when the Gate control input signal Gate falls, and outputs high level when the first degaussing time T_OFFOr a second degaussing time T_DEMWhen the signal is triggered, the third flip-flop U3 outputs a low level to lock the trigger logic level in the period, that is, the fourth flip-flop U4 does not act any more in the period;

an output end of the first trigger U1 outputs a first demagnetization time T_OFFA signal, an output terminal of the second flip-flop U2 outputs a second demagnetization time T_DEMA signal.

As an embodiment of the invention, when the system is in a continuous mode CCM, the medium current of the primary side inductor and the first degaussing time T are controlled when the primary side switch is conducted_OFFThe product of (d) is a first constant value;

when the system is in the discontinuous mode DCM, controlling half of the peak voltage of the sampling resistor and the second degaussing time T when the primary side switch is conducted_DEMThe product of (d) is a second constant value.

As an embodiment of the present invention, when the system is stable, it is satisfiedWherein, V_{mid_P}The system is a sampling resistor median voltage V corresponding to the primary side inductance median current in a continuous mode_{dcm_pk_P}The peak voltage of the sampling resistor, D, corresponding to the peak current of the primary inductor when the system is in the discontinuous mode_OFFIs the first on duty cycle of the secondary side when the system is in continuous mode, D_DEMThe second conduction duty ratio of the secondary side when the system is in the discontinuous mode;

when the system is in the transition process, the first demagnetization time T_OFFAnd a second degaussing time T_DEMThe corresponding two discharge paths are complementary in open logic.

According to another aspect of the invention, the following technical scheme is adopted: a flyback circuit comprises the constant current control circuit.

According to another aspect of the invention, the following technical scheme is adopted: a constant current control method comprises the following steps:

when the system is in a continuous mode, controlling the product of the median current of the primary side inductor and the first conduction duty ratio of the secondary side to be in a set first threshold interval;

and when the system is in a discontinuous mode, controlling the product of half of the peak current of the primary inductor and the second conduction duty ratio of the secondary side to be in the first threshold interval.

As an embodiment of the present invention, when the system is stable, it is satisfiedWherein, V_{mid_P}The system is a sampling resistor median voltage V corresponding to the primary side inductance median current in a continuous mode_{dcm_pk_P}The peak voltage of the sampling resistor, D, corresponding to the peak current of the primary inductor when the system is in the discontinuous mode_OFFIs the first on duty cycle of the secondary side when the system is in continuous mode, D_DEMThe second conduction duty ratio of the secondary side when the system is in the discontinuous mode;

when the system is in a transition process, the two discharge paths corresponding to the first demagnetization time and the second demagnetization time are opened and logically complemented.

As an embodiment of the present invention, the constant current control method includes: controlling the states of the first demagnetization time signal and the second demagnetization time signal;

when the discharge passage control circuit controls the first demagnetization time signal to be effective, the first discharge passage carries out a discharge process;

and when the discharge passage control circuit controls the second demagnetization time signal to be effective, the second discharge passage carries out a discharge process.

As an embodiment of the present invention, the constant current control method includes: controlling the first demagnetization time T_OFFSignal and second degaussing time T_DEMThe switching between the signals is selected, and the switching selection logics of the first degaussing time signal and the second degaussing time signal are complementary.

As an embodiment of the present invention, the constant current control method includes: and when the second discharge path is controlled to be opened, delaying a second set time to offset an error signal brought by demagnetization detection.

The invention has the beneficial effects that: the constant current control circuit, the control method and the flyback circuit provided by the invention can greatly improve the constant current precision of the system working in a DCM mode of high-voltage input, avoid sampling errors caused by CS voltage waveform oscillation, and simultaneously eliminate the influence of the deviation of a median sampling position on the constant current of the system. Meanwhile, the invention can also specially add fixed delay in the DCM discharge path to counteract T caused by degaussing detection_DEMLarge errors; therefore, the precision of the constant current of the system is greatly improved, and particularly, the constant current characteristic of the system is improved when the high-voltage input works in DCM and the low-voltage input works in CCM under different input voltages.

Drawings

Fig. 1 is a circuit diagram of a typical flyback circuit.

Fig. 2a is a key waveform diagram of the flyback circuit operating in discontinuous mode DCM.

Fig. 2b is a key waveform diagram of the flyback circuit operating in the continuous mode CCM.

Fig. 3a is a topological waveform diagram of the constant current control method in discontinuous mode DCM according to an embodiment of the present invention.

Fig. 3b is a topology waveform diagram of the constant current control method in the continuous mode CCM according to an embodiment of the present invention.

Fig. 4a is a circuit diagram of a constant current control circuit in the prior art.

Fig. 4b is a circuit diagram of the constant current control circuit according to an embodiment of the invention.

Fig. 5 is a circuit diagram of a discharge path control circuit according to an embodiment of the invention.

Fig. 6 is a circuit diagram of a discharge path control circuit according to an embodiment of the invention.

Detailed Description

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

For a further understanding of the invention, reference will now be made to the preferred embodiments of the invention by way of example, and it is to be understood that the description is intended to further illustrate features and advantages of the invention, and not to limit the scope of the claims.

The description in this section is for several exemplary embodiments only, and the present invention is not limited only to the scope of the embodiments described. It is within the scope of the present disclosure and protection that the same or similar prior art means and some features of the embodiments may be interchanged.

"coupled" or "connected" in this specification includes both direct and indirect connections, such as through some active device, passive device, or electrically conductive medium; but also may include connections through other active or passive devices, such as through switches, follower circuits, etc., that are known to those skilled in the art for achieving the same or similar functional objectives.

"first demagnetization time T" in the specification_OFFSignal and second degaussing time T_DEMThe switching of the signals selects the logical complement' to mean that the first degaussing time T is selected if the first condition is met_OFFThe signal is valid; selecting a second degaussing time T in case the second condition is met_DEMThe signal is valid. The first condition is logically opposite to the second condition. If the first condition is that a certain signal is high level, the second condition is that a certain signal is low level. Illustratively, when the constant current control circuit selects the first demagnetization time T_OFFTime of signal, first degaussing time T_OFFSignal active, T in the current period_OFFWithin the time, the first switch is conducted; and a second degaussing time T_DEMThe signal is inactive, continuously closing the second switch. Similarly, when the constant current control circuit selects the second demagnetization time T_DEMTime of signal, second degaussing time T_DEMSignal active, T in the current period_DEMWithin the time, the second switch is conducted; and the first degaussing time T_OFFThe signal is inactive, continuously closing the first switch.

The invention discloses a constant current control circuit, which controls the product of the median current of a primary side inductor and the first conduction duty ratio of a secondary side to be in a set first threshold interval when a system is in a continuous mode CCM; when the system is in the discontinuous mode DCM, the constant current control circuit controls the product of half of the peak current of the primary side inductor and the second conduction duty ratio of the secondary side to be in the first threshold interval.

In an embodiment of the present invention, when the system is in the continuous mode CCM, the median current of the primary side inductor and the first degaussing time T when the primary side switch is controlled to be turned on are controlled_OFFThe product of (d) is a first constant value; when the system is in the discontinuous mode DCM, controlling half of the peak voltage of the sampling resistor and the second degaussing time T when the primary side switch is conducted_DEMThe product of (d) is a second constant value. The first constant value is equal or approximately equal to the second constant value.

In one embodiment of the invention, when the system is stable, it is satisfiedWherein, V_{mid_P}The system is a sampling resistor median voltage V corresponding to the primary side inductance median current in a continuous mode_{dcm_pk_P}The peak voltage of the sampling resistor, D, corresponding to the peak current of the primary inductor when the system is in the discontinuous mode_OFFIs the first on duty cycle of the secondary side when the system is in continuous mode, D_DEMThe second conduction duty ratio of the secondary side when the system is in the discontinuous mode; when the system is in the transition process, the first demagnetization time T_OFFAnd a second degaussing time T_DEMThe corresponding two discharge paths are complementary in open logic.

In an embodiment of the present invention, the constant current control circuit includes: the charging circuit comprises a first discharging path, a second discharging path and a charging circuit. The first discharge path receives a first degaussing time T_OFFSignal according to a first degaussing time T_OFFThe signal controls the working state of the first discharging path; the second discharge path receives a second degaussing time T_DEMSignal according to a second degaussing time T_DEMThe signal controls the operating state of the second discharge path. Illustratively, when the first discharge path receives the first degaussing time T_OFFSignalAccording to the first degaussing time T_OFFSignal control to make the first discharge path at T_OFFAnd the charging circuit is conducted in time to charge the first discharging path. When the second discharge path receives the second degaussing time T_DEMThe signal is then based on the second degaussing time T_DEMSignal control to make the second discharge path at T_DEMAnd the second discharge path is conducted within the time, and the charging circuit charges the second discharge path.

The output end of the charging circuit is respectively coupled with the first discharging path and the second discharging path, and the charging circuit is used for charging the first discharging path and the second discharging path. Illustratively, in the continuous mode, the charging charge of the charging circuit is balanced with the discharging charge of the first discharging path; in the discontinuous mode, the charging charge of the charging circuit is balanced with the discharging charge of the second discharging path. Based on charge-discharge balance, controlling the product of the median current of the primary side inductor and the first conduction duty ratio of the secondary side to be in a set first threshold interval when the product is in a continuous mode; and controlling to realize that the product of half of the peak current of the primary inductor and the second conduction duty ratio of the secondary inductor is in the first threshold interval in the intermittent mode, thereby realizing constant current control in the continuous mode and the intermittent mode.

In an embodiment of the invention, the constant current control circuit includes a discharge path control circuit for controlling the first degaussing time T_OFFSignal, second degaussing time T_DEMThe state of the signal; controlling a first degaussing time T in the discharge path control circuit_OFFWhen the signal is effective, the first discharging path carries out a discharging process; controlling a second degaussing time T in the discharge path control circuit_DEMWhen the signal is effective, the second discharging path carries out a discharging process.

In an embodiment of the invention, the discharge path control circuit is further configured to control the first degaussing time T_OFFSignal and second degaussing time T_DEMThe selection of the switching between the signals, and the first degaussing time T_OFFSignal and second degaussing time T_DEMThe switching of the signals selects the logical complement. In an embodiment of the present invention, the discharge is turned onThe path control circuit comprises a path interlocking circuit which is used for locking the states of the first degaussing time signal and the second degaussing time signal within a first set time when the first degaussing time signal or the second degaussing time signal is triggered. In an embodiment of the present invention, the first set time is a time length of a current switching period, and the switching period is a switching period of the primary side main switching tube. For example, when the first degaussing time signal is in the triggered state, the triggered logic levels of the first degaussing time signal and the second degaussing time signal are kept in the current switching period, that is, the state whether the first degaussing time signal and the second degaussing time signal are triggered in the current switching period does not change. So as to avoid frequently changing the trigger logic level of the first degaussing time signal and the second degaussing time signal due to the change of the circuit signal in a certain period. In an embodiment of the invention, when the second discharge path is turned on, a second set time is delayed to cancel an error signal caused by demagnetization detection.

In an embodiment of the present invention, the first discharge path includes a first switch, a first switch tube driving module, and a first resistor; the first switch receives a first degaussing time T_OFFSignal according to a first degaussing time T_OFFThe signal controls the on-off of the first switch; the first end of the first switch is coupled with the charging circuit, and the second end of the first switch is coupled with the second end of the first switch tube; the first input end of the first switch tube driving module is coupled to the median voltage of the sampling resistor corresponding to the median current of the primary inductor, the second input end of the first switch tube driving module is coupled to the third end of the first switch tube and the first end of the first resistor, and the output end of the first switch tube driving module is coupled to the first end of the first switch tube. The first switch tube driving module controls the conduction state of the first switch tube according to the magnitude relation between the median voltage of the sampling resistor and the first real-time sampling voltage. Wherein, the primary side inductance median current I_{mid_P}Corresponding sampling resistance median voltage V_{mid_P}The corresponding relation in (1) may be V_{mid_P}＝I_{mid_P}Rcs, Rcs are resistance values of the sampling resistors.

The second discharge path includesThe circuit comprises two switches, a second switch tube driving module and a second resistor; the second switch receives a second degaussing time T_DEMSignal according to a second degaussing time T_DEMThe signal controls the on-off of the second switch; the first end of the second switch is coupled with the charging circuit, and the second end of the second switch is coupled with the second end of the second switch tube; the first input end of the second switch tube driving module is coupled to the peak voltage of the sampling resistor corresponding to the peak current of the primary inductor, the second input end of the second switch tube driving module is coupled to the third end of the second switch tube and the first end of the second resistor, and the output end of the second switch tube driving module is coupled to the first end of the second switch tube. And the second switching tube driving module controls the conduction state of the second switching tube according to the magnitude relation between the peak voltage of the sampling resistor and the second real-time sampling voltage. Wherein, the primary side inductance peak current I_{dcm_pk_P}Corresponding sampling resistance peak voltage V_{dcm_pk_P}The corresponding relation in (1) may be V_{dcm_pk_P}＝I_{dcm_pk_P}Rcs, Rcs are resistance values of the sampling resistors. Illustratively, the charging circuit includes a current source.

FIG. 4b is a schematic circuit diagram of a constant current control circuit according to an embodiment of the present invention; referring to fig. 4b, in an embodiment of the present invention, the first discharge path 10 includes a first switch K1, a first switch Q1, a first comparator Comp1, and a first resistor; the first switch K1 receives a first degaussing time T_OFFSignal according to a first degaussing time T_OFFThe signal controls the on-off of the first switch K1; a first terminal of the first switch K1 is coupled to the current source, and a second terminal of the first switch K1 is coupled to a second terminal of the first switch transistor Q1; the positive phase input terminal of the first comparator Comp1 is coupled to the median voltage of the sampling resistor corresponding to the median current of the primary inductor, the negative phase input terminal of the first comparator Comp1 is coupled to the third terminal of the first switch Q1 and the first terminal of the first resistor, and the output terminal of the first comparator Comp1 is coupled to the first terminal of the first switch Q1.

The second discharge path 20 comprises a second switch K2, a second switching tube Q2, a second comparator Comp2, and a second resistor; the second switch K2 receives a second degaussing time T_DEMSignal according to a second degaussing time T_DEMThe signal controls the on-off of the second switch K2; a first terminal of the second switch K2 is coupled to the current source, and a second terminal of the second switch K2 is coupled to a second terminal of the second switch Q2; the positive phase input terminal of the second comparator Comp2 is coupled to the peak voltage of the sampling resistor corresponding to the peak current of the primary inductor, the negative phase input terminal of the second comparator Comp2 is coupled to the third terminal of the second switch Q2 and the first terminal of the second resistor, and the output terminal of the second comparator Comp2 is coupled to the first terminal of the second switch Q2.

In an embodiment of the present invention, the current source may be disposed inside the chip as shown in fig. 1. First degaussing time T_OFFAnd a second degaussing time T_DEMRespectively are degaussing time signals obtained by a degaussing detection circuit; wherein the first degaussing time T_OFFCorresponding to CCM mode, the second degaussing time T_DEMCorresponding to DCM mode. The positive phase input terminal of the first comparator Comp1 is coupled to the median voltage V of the sampling resistor corresponding to the median current of the primary inductor_{mid_P}The positive phase input terminal of the second comparator Comp2 is coupled to the peak voltage V of the sampled resistor corresponding to the peak current of the primary inductor_{dcm_pk_P}. The non-inverting input terminal of the first comparator Comp1 and the non-inverting input terminal of the second comparator Comp2 are respectively coupled to a sampling resistor Rcs shown in fig. 1, and V is obtained through the sampling resistor Rcs in CCM mode_{mid_P}(ii) a In DCM, V is obtained through sampling resistor Rcs_{dcm_pk_P}. The SEL voltage of the SEL port controls the conduction peak current of the primary side main switching tube, so that the output current is controlled, and the output constant current control is realized. And the primary side main switching tube is used for controlling the conduction state of the primary side circuit. Illustratively, when the on current flowing through the main switch tube reaches the on peak current, the main switch tube is controlled to be turned off, and the magnitude of the on peak current is determined by the SEL voltage.

As shown in fig. 4b, in an embodiment of the present invention, the resistance value (2R) of the second resistor is 2 times the resistance value (R) of the first resistor.

In an embodiment of the invention, the constant current control circuit includes a discharge path control circuit for controlling the first degaussing time T_OFFSignal, second degaussing time T_DEMThe signals are logically complementary.

FIG. 5 is a circuit diagram of a discharge path control circuit according to an embodiment of the present invention; referring to fig. 5, in an embodiment of the invention, the discharge path control circuit includes a first flip-flop U1, a second flip-flop U2, a third flip-flop U3, a fourth flip-flop U4, an or gate 52, a first and gate 501, a second and gate 502, a third and gate 503, a fourth and gate 504, a fifth and gate 505, a sixth and gate 506, a first not gate 511, and a second not gate 512.

The falling edges of the Gate control input signal Gate are respectively coupled to the first input terminal of the first flip-flop U1, the input terminal of the first not Gate 511, the first input terminal of the second flip-flop U2, the input terminal of the second not Gate 512, and the first input terminal of the third flip-flop U3; an output terminal of the second not gate 512 is coupled to a first input terminal of the first and gate 501; an output of the second not-gate 512 is coupled to a first input of the second and-gate 502.

The rising edges of the Gate input signals Gate are respectively coupled to the second input terminal of the first and Gate 501, the first input terminal of the or Gate 52, and the first input terminal of the third and Gate 503; the output of the first and gate 501 is coupled to the second input of the first flip-flop U1, and the output of the second and gate 502 is coupled to the second input of the second flip-flop U2.

The ZCD signal is coupled to a second input terminal of the second and gate 502, a second input terminal of the or gate 52, and a second input terminal of the fourth and gate 504, respectively; an output of the or gate 52 is coupled to a second input of the third flip-flop U3. Wherein, the ZCD signal is a zero-crossing detection signal and is used for detecting a secondary duty ratio signal in DCM.

A first output terminal of the first flip-flop U1 is coupled to a first input terminal of the fifth and gate 505, and a first output terminal of the second flip-flop U2 is coupled to a first input terminal of the sixth and gate 506.

A first output terminal of the third flip-flop U3 is coupled to a second input terminal of the third and gate 503 and a first input terminal of the fourth and gate 504, respectively, an output terminal of the third and gate 503 is coupled to a first input terminal of the fourth flip-flop U4, and an output terminal of the third and gate 503 is coupled to a second input terminal of the fourth flip-flop U4; a first output terminal of the fourth flip-flop U4 is coupled to a second input terminal of the fifth and gate 505, and a second output terminal of the fourth flip-flop U4 is coupled to a second input terminal of the sixth and gate 506.

FIG. 6 is a circuit diagram of a discharge path control circuit according to an embodiment of the present invention; referring to fig. 6, in an embodiment of the invention, compared to the discharge path control circuit in fig. 5, the discharge path control circuit further includes a buffer 53 and a seventh and gate 507. The output terminal of the sixth and gate 506 is coupled to the input terminal of the buffer 53 and the second input terminal of the seventh and gate 507, respectively, and the output terminal of the buffer 53 is coupled to the first input terminal of the seventh and gate 507.

In an embodiment of the present invention, when the second discharge path is turned on, the buffer 53 is delayed by a predetermined time to cancel an error signal caused by demagnetization detection. In an embodiment of the invention, when the second discharge path is turned on, the buffer delays for a pulse period Td to cancel an error signal caused by demagnetization detection.

In an embodiment of the present invention, the fourth flip-flop U4 is set to have a first demagnetization time T_OFFSignal and second degaussing time T_DEMThe selection trigger of the signal selects the first degaussing time T when the fourth trigger U4 outputs high level_OFFSignal that the second degaussing time T is selected when the fourth flip-flop U4 outputs a low level_DEMA signal.

The third flip-flop U3 latches the signal for this period, and U3 outputs high level when the Gate control input signal Gate falls, and outputs high level when the first degaussing time T_OFFOr a second degaussing time T_DEMWhen the signal is triggered, the third flip-flop U3 outputs a low level, locking the trigger logic level in this cycle, i.e., the fourth flip-flop U4 is not activated in this cycle. An output end of the first trigger U1 outputs a first demagnetization time T_OFFA signal, an output terminal of the second flip-flop U2 outputs a second demagnetization time T_DEMA signal.

The invention also discloses a constant current control method, which comprises the following steps: when the system is in a continuous mode CCM, controlling the median current of a primary side inductor and the first degaussing time T_OFFThe product of (a) is within a set first threshold interval; controlling when a system is in discontinuous mode DCMHalf of peak current of primary inductor and second degaussing time T_DEMIs within the first threshold interval.

In an embodiment of the present invention, when the system is in the continuous mode CCM, the median current of the primary side inductor and the first degaussing time T when the primary side switch is controlled to be turned on are controlled_OFFThe product of (d) is a first constant value; when the system is in the discontinuous mode DCM, controlling half of the peak voltage of the sampling resistor and the second degaussing time T when the primary side switch is conducted_DEMThe product of (d) is a second constant value.

In an embodiment of the invention, the first constant value is equal to the second constant value. In another embodiment of the invention, the first constant value is approximately equal to the second constant value.

In one embodiment of the invention, when the system is stable, it is satisfiedWherein, V_{mid_P}The system is a sampling resistor median voltage V corresponding to the primary side inductance median current in a continuous mode_{dcm_pk_P}The peak voltage of the sampling resistor, D, corresponding to the peak current of the primary inductor when the system is in the discontinuous mode_OFFIs the first on duty cycle of the secondary side when the system is in continuous mode, D_DEMThe second conduction duty ratio of the secondary side when the system is in the discontinuous mode; when the system is in the transition process, the first demagnetization time T_OFFAnd a second degaussing time T_DEMThe corresponding two discharge paths are complementary in open logic.

In an embodiment of the present invention, the constant current control method includes: controlling the first degaussing time T_OFFSignal, second degaussing time T_DEMThe state of the signal; controlling a first degaussing time T in the discharge path control circuit_OFFWhen the signal is effective, the first discharging path carries out a discharging process; controlling a second degaussing time T in the discharge path control circuit_DEMWhen the signal is effective, the second discharging path carries out a discharging process.

In an embodiment of the present invention, the constant current control method includes: controlling the first demagnetizationInter T_OFFSignal and second degaussing time T_DEMThe selection of the switching between the signals, and the first degaussing time T_OFFSignal and second degaussing time T_DEMThe switching of the signals selects the logical complement. In an embodiment of the present invention, the constant current control method includes: controlling the first degaussing time T_OFFSignal, second degaussing time T_DEMThe state of the signal is locked within the first set time and does not change. In an embodiment of the present invention, the constant current control method includes: and when the second discharge path is controlled to be opened, delaying a second set time to offset an error signal brought by demagnetization detection.

In an embodiment of the present invention, the principle of the constant current control method of the present invention is as follows:

the invention realizes the constant current scheme and integrates DCM and CCM algorithms to realize the constant current control of the output current. Fig. 3a is a topological waveform diagram of a constant current control method in discontinuous mode DCM according to an embodiment of the present invention, and fig. 3b is a topological waveform diagram of a constant current control method in continuous mode CCM according to an embodiment of the present invention; referring to FIG. 3a and FIG. 3b, in one embodiment of the present invention, when the system operates in DCM, I is the main factor_{mid_P}Has larger sampling error, and uses peak value I for improving constant current precision_{dcm_pk_P}In place of I_{mid_P}Implementing a constant current algorithm, and

in combination with equations 1-5, the average output current can be expressed by the following equation:

i.e. when the system is in CCM mode, control V_{mid_P}And D_OFFThe product of (d) is a constant value; and when the system is in DCM mode, control V_{dcm_pk_P}And D_DEMThe product of (d) is a constant value, and the condition is satisfied:

in an embodiment of the present invention, the constant current control is described by taking a fixed switching frequency system as an example. Fig. 4a is a schematic circuit diagram of a constant current control circuit in the prior art, referring to fig. 4a, the constant current control circuit controls the peak value of the output current with the SEL voltage, and when the system is stable, the following conditions are satisfied: v_{mid_P}×D_DISI0 × R. Where I0 is the magnitude of the current output by the current source.

FIG. 4b is a schematic circuit diagram of a constant current control circuit according to an embodiment of the present invention; referring to fig. 4b, in an embodiment of the present invention, when the system is stable, the following are satisfied:that is, following the conservation of charge, for example, in DCM, the charge in one cycle is I0 Ts, the discharge charge is Vdcm _ pk _ P/2R Tdem, and the charge is equal to the discharge charge. WhileIt can be seen that the constant current control circuit shown in FIG. 4b satisfies the requirement when the system is stableSimilarly, in the CCM mode, the system is in a steady state when the corresponding above formula is satisfied. When the system is in the transition process, T_OFFAnd T_DEMThe two discharge paths are logically complementary to each other.

FIG. 5 is a circuit diagram of a discharge path control circuit according to an embodiment of the present invention; referring to FIG. 5, the fourth flip-flop U4 is T_OFFAnd T_DEMThe signal selects the flip-flop, and when the fourth flip-flop U4 outputs a high level, T is selected_OFFSignal, when the fourth flip-flop U4 outputs a low level, T is selected_DEMA signal. The third flip-flop U3 latches the signal in this period, and the third flip-flop U3 outputs high level when the Gate falls, and outputs high level when T_OFFOr T_DEMWhen the signal is triggered, the third flip-flop U3 outputs a low level, locking the trigger logic level in this cycle, i.e., the fourth flip-flop U4 is not activated in this cycle. The first flip-flop U1 is T_OFFSignal that the second flip-flop U2 is T_DEMA signal; furthermore T_DEMAnd delaying the opening of the channel by a time Td so as to counteract error signals caused by demagnetization detection.

The invention also discloses a flyback circuit which comprises the constant current control circuit.

In summary, the constant current control circuit, the control method and the flyback circuit provided by the invention can greatly improve the constant current precision of the system working in the DCM mode of high voltage input, avoid sampling errors caused by CS voltage waveform oscillation, and simultaneously eliminate the influence of the median sampling position deviation on the system constant current. Meanwhile, the invention can also specially add fixed delay in the DCM discharge path to counteract T caused by degaussing detection_DEMLarge errors; therefore, the precision of the constant current of the system is greatly improved, and particularly, the constant current characteristic of the system is improved when the high-voltage input works in DCM and the low-voltage input works in CCM under different input voltages.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The description and applications of the invention herein are illustrative and are not intended to limit the scope of the invention to the embodiments described above. Variations and modifications of the embodiments disclosed herein are possible, and alternative and equivalent various components of the embodiments will be apparent to those skilled in the art. It will be clear to those skilled in the art that the present invention may be embodied in other forms, structures, arrangements, proportions, and with other components, materials, and parts, without departing from the spirit or essential characteristics thereof. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the invention.