阅读说明：本技术 半导体装置及其制造方法 (Semiconductor device and method for manufacturing the same ) 是由 押野雄一 于 2018-10-10 设计创作，主要内容包括：一种沟槽栅型IGBT,具备：第1导电型的第1半导体区(10)；第1导电型的第2半导体区(20),其配置在第1半导体区(10)的主面,并且杂质浓度比第1半导体区(10)高；第2导电型的第3半导体区(30),其配置在第2半导体区(20)的上表面,并且以沿着膜厚方向具有多个峰值的杂质浓度分布添加有杂质；以及第1导电型的第4半导体区(40),其配置在第3半导体区(30)的上表面。(A trench gate IGBT is provided with: a 1 st semiconductor region (10) of a 1 st conductivity type; a 2 nd semiconductor region (20) of the 1 st conductivity type, which is disposed on a main surface of the 1 st semiconductor region (10) and has an impurity concentration higher than that of the 1 st semiconductor region (10); a 3 rd semiconductor region (30) of a 2 nd conductivity type, which is disposed on an upper surface of the 2 nd semiconductor region (20), and to which an impurity is added in an impurity concentration distribution having a plurality of peaks along a film thickness direction; and a 4 th semiconductor region (40) of the 1 st conductivity type disposed on the upper surface of the 3 rd semiconductor region (30).)

1. A method for manufacturing a semiconductor device, comprising:

implanting an impurity from one main surface of a 1 st semiconductor region of a 1 st conductivity type to form a 2 nd semiconductor region of the 1 st conductivity type having an impurity concentration higher than that of the 1 st semiconductor region;

forming a 3 rd semiconductor region of a 2 nd conductivity type having an impurity concentration distribution having a plurality of peaks in a film thickness direction on the 2 nd semiconductor region;

forming a 4 th semiconductor region of the 1 st conductivity type on an upper surface of the 3 rd semiconductor region;

forming a gate insulating film on an inner wall of a trench extending from the 4 th semiconductor region and penetrating the 3 rd semiconductor region;

forming a control electrode inside the trench so as to face a side surface of the 3 rd semiconductor region with the gate insulating film interposed therebetween;

forming a 5 th semiconductor region of a 1 st conductivity type having an impurity concentration higher than that of the 1 st semiconductor region on the other main surface of the 1 st semiconductor region; and

a step of forming a 6 th semiconductor region of a 2 nd conductivity type on the other main surface of the 1 st semiconductor region with the 5 th semiconductor region interposed therebetween,

the step of forming the 3 rd semiconductor region includes a step of implanting impurities of the 2 nd conductivity type into the 1 st semiconductor region a plurality of times at different depths.

2. The method for manufacturing a semiconductor device according to claim 1,

the interval of the depth of the 2 nd conductivity type impurity implanted into the 3 rd semiconductor region is made shorter than the film thickness of the 2 nd semiconductor region along the groove.

3. The method for manufacturing a semiconductor device according to claim 2,

the film thickness of the 3 rd semiconductor region along the groove is made thicker than the film thickness of the 2 nd semiconductor region along the groove.

4. The method for manufacturing a semiconductor device according to claim 1,

the 3 rd semiconductor region is formed so that the impurity concentration of the peak value on a side closer to the 2 nd semiconductor region is higher than the impurity concentration of the peak value on a side closer to the 4 th semiconductor region in the impurity concentration distribution of the 3 rd semiconductor region along the groove.

5. The method for manufacturing a semiconductor device according to claim 1,

the diffusion of the impurity in the 2 nd semiconductor region, the diffusion of the impurity in the 3 rd semiconductor region, and the diffusion of the impurity in the 1 st semiconductor region are performed simultaneously by 1 heating step, without performing the diffusion of the impurity of the 1 st conductivity type implanted into the 2 nd semiconductor region, the diffusion of the impurity in the 3 rd semiconductor region, and the diffusion of the impurity in the 4 th semiconductor region separately.

6. A semiconductor device is characterized by comprising:

a 1 st semiconductor region of a 1 st conductivity type;

a 2 nd semiconductor region of the 1 st conductivity type, which is disposed on a 1 st main surface of the 1 st semiconductor region and has an impurity concentration higher than that of the 1 st semiconductor region;

a 3 rd semiconductor region of a 2 nd conductivity type, which is arranged on an upper surface of the 2 nd semiconductor region and to which an impurity is added in an impurity concentration distribution having a plurality of peaks along a film thickness direction;

a 4 th semiconductor region of the 1 st conductivity type, which is disposed on an upper surface of the 3 rd semiconductor region;

a gate insulating film disposed on an inner wall of the trench extending from an upper surface of the 4 th semiconductor region and penetrating the 3 rd semiconductor region;

a control electrode disposed inside the trench so as to face a side surface of the 3 rd semiconductor region with the gate insulating film interposed therebetween;

a 5 th semiconductor region of the 1 st conductivity type, which is disposed on a 2 nd main surface of the 1 st semiconductor region opposite to the 1 st main surface and has an impurity concentration higher than that of the 1 st semiconductor region; and

and a 6 th semiconductor region of a 2 nd conductivity type disposed on the 2 nd main surface of the 1 st semiconductor region with the 5 th semiconductor region interposed therebetween.

7. The semiconductor device according to claim 6,

the film thickness of the 3 rd semiconductor region along the groove is thicker than the film thickness of the 2 nd semiconductor region along the groove.

8. The semiconductor device according to claim 6,

when a convex region having an impurity concentration is set from a minimum value to an adjacent minimum value with one peak therebetween in the impurity concentration distribution of the 3 rd semiconductor region along the trench, the width of each of the plurality of convex regions included in the impurity concentration distribution in the film thickness direction is shorter than the film thickness of the 2 nd semiconductor region along the trench.

9. The semiconductor device according to claim 6,

in the impurity concentration distribution of the 3 rd semiconductor region along the groove, the impurity concentration of the peak value on a side close to the 2 nd semiconductor region is higher than the impurity concentration of the peak value on a side close to the 4 th semiconductor region.

10. The semiconductor device according to claim 6,

the film thickness of the 2 nd semiconductor region along the groove is less than 1 μm.

Technical Field

The present invention relates to a semiconductor device having a carrier storage layer adjacent to a base region.

Background

As a switching element (power semiconductor element) for performing a switching operation of a large current, an Insulated Gate Bipolar Transistor (IGBT) having a high input impedance and a low on-resistance is used. The IGBT is used in, for example, a motor drive circuit.

In the IGBT, a carrier storage layer having a higher impurity concentration than the drift region may be disposed between the base region and the drift region (see patent document 1.). With this structure, holes are accumulated in the drift region, and holes are prevented from reaching the emitter region from the collector region. Therefore, the on-resistance of the semiconductor device can be reduced.

Documents of the prior art

Patent document

Patent document 1: japanese laid-open patent publication No. 8-316479

Disclosure of Invention

Problems to be solved by the invention

However, when the base region is formed after the carrier stored layer is formed, there is a problem that impurities in the carrier stored layer also diffuse. This reduces the impurity concentration of the carrier stored layer. As a result, the accumulation amount of holes in the drift region cannot be sufficiently increased, and the decrease in on-resistance cannot be suppressed.

In view of the above problems, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device, which can suppress a decrease in the impurity concentration of a carrier stored layer during the manufacturing process.

Means for solving the problems

According to one embodiment of the present invention, there is provided a method for manufacturing a semiconductor device, including: implanting an impurity from one main surface of a 1 st semiconductor region of the 1 st conductivity type to form a 2 nd semiconductor region of the 1 st conductivity type having an impurity concentration higher than that of the 1 st semiconductor region; forming a 3 rd semiconductor region of a 2 nd conductivity type having a plurality of peaks in an impurity concentration distribution in a film thickness direction in the 2 nd semiconductor region by implanting impurities into the 1 st semiconductor region a plurality of times at different depths; and forming a 4 th semiconductor region of the 1 st conductivity type on the upper surface of the 3 rd semiconductor region.

According to another aspect of the present invention, there is provided a semiconductor device including: a 1 st semiconductor region of a 1 st conductivity type; a 2 nd semiconductor region of the 1 st conductivity type, which is disposed on the 1 st main surface of the 1 st semiconductor region and has an impurity concentration higher than that of the 1 st semiconductor region; a 3 rd semiconductor region of a 2 nd conductivity type, which is disposed on an upper surface of the 2 nd semiconductor region and to which an impurity is added in an impurity concentration distribution having a plurality of peaks along a film thickness direction; and a 4 th semiconductor region of the 1 st conductivity type disposed on an upper surface of the 3 rd semiconductor region.

Effects of the invention

According to the present invention, a semiconductor device and a method for manufacturing the semiconductor device can be provided, in which a decrease in the impurity concentration of a carrier storage layer during the manufacturing process can be suppressed.

Drawings

Fig. 1 is a schematic cross-sectional view showing a structure of a semiconductor device according to an embodiment of the present invention.

Fig. 2 is a graph showing an example of the impurity concentration distribution of the semiconductor device according to the embodiment of the present invention.

Fig. 3 is (a) a schematic process sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 4 is a schematic process sectional view (second) for explaining a method of manufacturing a semiconductor device according to the embodiment of the present invention.

Fig. 5 is a schematic process sectional view (third) for explaining a method of manufacturing a semiconductor device according to the embodiment of the present invention.

Fig. 6 is a schematic process sectional view (the fourth step) for explaining the method of manufacturing a semiconductor device according to the embodiment of the present invention.

Fig. 7 is a schematic process sectional view (the fifth step) for explaining the method of manufacturing a semiconductor device according to the embodiment of the present invention.

Fig. 8 is a schematic process sectional view (sixteenth) for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 9 is a graph showing an example of the impurity concentration distribution of the semiconductor device according to the modification of the embodiment of the present invention.

Fig. 10 is a schematic diagram showing an example of electrons moving in a channel region of a semiconductor device according to a modification of the embodiment of the present invention.

Fig. 11 is a schematic view showing another example of electrons moving in the channel region.

Fig. 12 is a schematic cross-sectional view showing a structure of a semiconductor device according to another embodiment of the present invention.

Detailed Description

Embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings below, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and it should be noted that the relationship between the thickness and the planar size, the ratio of the lengths of the respective portions, and the like are different from those in reality. Therefore, specific dimensions should be judged with reference to the following description. It is to be understood that the drawings include portions having different dimensional relationships and ratios from each other.

The embodiments described below illustrate an apparatus and a method for embodying the technical idea of the present invention, and the technical idea of the present invention does not specify the shape, structure, arrangement, and the like of the constituent elements as follows.

As shown in fig. 1, in the semiconductor device according to the embodiment of the present invention, a 1 st conductivity type 2 semiconductor region (carrier stored layer 20) having an impurity concentration higher than that of the 1 st semiconductor region is disposed on a 1 st main surface 11 of the 1 st conductivity type 1 semiconductor region (drift region 10). A 3 rd semiconductor region (base region 30) of the 2 nd conductivity type is disposed on the 2 nd semiconductor region, and a 4 th semiconductor region (emitter region 40) of the 1 st conductivity type is disposed on the upper surface of the 3 rd semiconductor region. In the base region 30, an impurity is added in an impurity concentration distribution having a plurality of peaks along the film thickness direction.

The semiconductor device shown in fig. 1 is a trench gate type IGBT, and a trench extending from the upper surface of the emitter region 40 and penetrating the emitter region 40, the base region 30, and the carrier storage layer 20 is formed, and a gate insulating film 70 is disposed on the inner wall of the trench. A control electrode (gate electrode 80) is disposed inside the trench so as to face a side surface of the base region 30 with the gate insulating film 70 interposed therebetween. The surface of the base region 30 facing the gate electrode 80 with the gate insulating film 70 interposed therebetween is a channel region for forming a channel. In the embodiment shown in fig. 1, the front end of the trench penetrating the carrier stored layer 20 reaches the drift region 10.

The 1 st conductivity type and the 2 nd conductivity type are opposite conductivity types to each other. That is, if the 1 st conductivity type is n-type, the 2 nd conductivity type is p-type, and if the 1 st conductivity type is p-type, the 2 nd conductivity type is n-type. Next, a case where the 1 st conductivity type is an n-type and the 2 nd conductivity type is a p-type will be described as an example.

A 5 th semiconductor region (field stop region 50) of the 1 st conductivity type having an impurity concentration higher than that of the drift region 10 is disposed on a 2 nd main surface 12 of the drift region 10 opposed to the 1 st main surface 11. A 6 th semiconductor region (collector region 60) of the 2 nd conductivity type is disposed on the 2 nd main surface 12 of the drift region 10 with the field stop region 50 interposed therebetween. The depletion layer extending from the lower surface of the base region 30 in the off state is prevented from reaching the collector region 60 by the field stop region 50. On the other main surface of the collector region 60, which is opposite to the one main surface connected to the field stop region 50, a collector electrode 220 electrically connected to the collector region 60 is arranged.

An emitter 210 electrically connected to the base region 30 and the emitter region 40 selectively disposed on the upper surface of the base region 30 is disposed above the gate electrode 80. Emitter electrode 210 is disposed on interlayer insulating film 90, and emitter electrode 210 is connected to base region 30 and emitter region 40 through an opening provided in interlayer insulating film 90. Gate electrode 80 is electrically insulated from emitter electrode 210 by interlayer insulating film 90.

Here, the operation of the semiconductor device shown in fig. 1 will be described. A predetermined collector voltage is applied between emitter 210 and collector 220, and a predetermined gate voltage is applied between emitter 210 and gate 80. For example, the collector voltage is about 300V to 1600V, and the gate voltage is about 10V to 20V. When the semiconductor device is turned on in this manner, the channel region is inverted from p-type to n-type to form a channel. Through the formed channel, electrons are injected from the emitter 210 to the drift region 10. The collector region 60 and the drift region 10 are biased in the forward direction, and holes (holes) move from the collector 220 through the collector region 60 in the order of the drift region 10, the carrier stored layer 20, and the base region 30. When the current is further increased, holes from the collector region 60 increase, and holes are accumulated in the drift region 10. As a result, the on-resistance is reduced by the conductivity modulation.

When the semiconductor device is turned from an on state to an off state, the gate voltage is controlled to be lower than the threshold voltage. For example, the gate voltage is made to be the same potential as the emitter voltage or a negative potential. This causes the channel of the base region 30 to disappear, and stops the injection of electrons from the emitter 210 into the drift region 10. Since the collector 220 has a higher potential than the emitter 210, the depletion layer spreads from the interface between the base region 30 and the carrier stored layer 20, and holes stored in the drift region 10 escape to the emitter 210. At this time, holes move through the semiconductor region between the grooves. That is, the region between the grooves is a suction port of the cavity.

In the semiconductor device shown in fig. 1, by disposing the carrier stored layer 20 having a higher impurity concentration than the drift region 10 between the drift region 10 and the base region 30, an electric field is generated from the carrier stored layer 20 toward the drift region 10 in the on state. As a result, holes are accumulated in the drift region 10 in the vicinity of the interface between the drift region 10 and the carrier stored layer 20. Therefore, more holes can be stored than in the case where the carrier stored layer 20 is not disposed. As a result, the on-resistance of the semiconductor device can be further reduced.

In addition, if the impurity concentration of the carrier stored layer 20 is too high, the spread of a depletion layer generated from a PN junction at the interface between the base region 30 and the carrier stored layer 20 in the off state is suppressed. As a result, the breakdown voltage of the semiconductor device is reduced. Therefore, the impurity concentration of the carrier stored layer 20 is preferably higher than the impurity concentration of the drift region 10 and lower than the impurity concentration of the base region 30.

However, if the impurity concentration of the carrier stored layer 20 is reduced, the amount of accumulated holes in the drift region 10 is not sufficiently increased, and the reduction in on-resistance is suppressed. That is, when a heating step (hereinafter, referred to as "base annealing") for diffusing the impurity implanted into the base region 30 is performed after the carrier stored layer 20 is formed, the longer the base annealing time is, the more the impurity of the carrier stored layer 20 is diffused. Further, the impurity concentration of the carrier stored layer 20 is reduced. For example, when the base region 30 is formed by diffusion after the carrier storage layer 20 is formed by diffusion by injecting an impurity into the semiconductor surface side, the impurity of the diffused carrier storage layer 20 and the impurity of the base region 30 cancel each other out, and the impurity concentration of the carrier storage layer 20 is lowered.

In contrast, in the semiconductor device of the embodiment, the base region 30 is formed by implanting the impurity of the 2 nd conductivity type into the semiconductor substrate a plurality of times at different depths. Therefore, in the semiconductor device of the embodiment, diffusion necessary for forming the base region 30 along the thickness of the trench can be performed in a short time so that the channel region has a predetermined length. That is, the time for base annealing can be shortened in the semiconductor device of the embodiment compared with the case where the base region 30 is formed by 1 time of impurity implantation. Therefore, according to the semiconductor device shown in fig. 1, the diffusion of impurities in the carrier stored layer 20 can be suppressed, and the on-resistance can be reduced. Further, by implanting the impurity plural times at different depths, the impurity concentration distribution of the base region 30 has plural peaks of the impurity concentration along the film thickness direction.

For example, the time for base annealing for forming the base region 30 having a film thickness of about 2.5 μm requires 2 to 3 hours when the impurity is implanted 1 time. In contrast, when the impurity is implanted 2 times at different depths, the base annealing time is several tens of seconds. Therefore, in the semiconductor device of the embodiment, the decrease in the impurity concentration of the carrier stored layer 20 due to the base annealing can be suppressed.

Fig. 2 shows an example of an impurity concentration distribution of the semiconductor device shown in fig. 1. Fig. 2 is an example of forming the base region 30 by two impurity implantations. The horizontal axis of the impurity concentration distribution is the impurity concentration, and the vertical axis is the depth in the film thickness direction of the upper surface of the emitter region 40 as the reference position 0.

In the impurity concentration distribution shown in fig. 2, the depth t1 is the position of the boundary between the drift region 10 and the carrier stored layer 20, and the depth t2 is the position of the boundary between the carrier stored layer 20 and the base region 30. The depth t3 is the position of the boundary between the 1 st base region 31 where the impurity implanted the 1 st time is diffused and the 2 nd base region 32 where the impurity implanted the 2 nd time is diffused in order to form the base region 30. The depth t4 is the location of the boundary of the base region 30 and emitter region 40. For example, the film thickness of the carrier storage layer 20 is about 1 μm, the film thickness of the base region 30 is about 2.5 μm, and the film thickness of the emitter region 40 is about 0.5 μm. At this time, the depth t1 was about 4 μm, the depth t2 was about 3 μm, and the depth t4 was about 0.5 μm. Depth t3 is intermediate between depth t2 and depth t 4.

Hereinafter, the region from the minimum value to the adjacent minimum value with one peak therebetween in the impurity concentration distribution of the base region 30 is referred to as a "convex region" of the impurity concentration. That is, the 1 st base region 31 and the 2 nd base region 32 are each formed of one convex region. The convex region of the 1 st base region 31 is a range from the boundary between the carrier stored layer 20 and the base region 30 to the boundary between the 1 st base region 31 and the 2 nd base region 32. The convex region of the 2 nd base region 32 is a range from the boundary between the 1 st base region 31 and the 2 nd base region 32 to the boundary between the base region 30 and the emitter region 40.

The narrower the width of the convex region in the film thickness direction, the shorter the time for base annealing for forming the base region 30 by impurity diffusion. For example, the width of each of the convex regions included in the impurity concentration distribution of the base region 30 in the film thickness direction is made shorter than the film thickness of the carrier storage layer 20 along the groove.

On the other hand, for example, the total film thickness Wb1 of the 1 st base region 31 and the film thickness Wb2 of the 2 nd base region 32 of the base region 30 may be made thicker than the film thickness Wc of the carrier storage layer 20. In the above, the case where the number of times of implantation of the impurity for forming the base region 30 is 2 times has been exemplified, but the number of times of implantation of the impurity may be 3 times or more. Therefore, according to the semiconductor device of the embodiment, the film thickness of the base region 30 can be set without worrying about the decrease of the impurity concentration of the carrier stored layer 20 due to the base annealing. The film thickness of the base region 30 affects the threshold value and short-circuit tolerance of the semiconductor device. According to the semiconductor device of the embodiment, the design margin can be improved.

Further, by shortening the base annealing time, the diffusion of impurities in the carrier stored layer 20 is suppressed. Therefore, a semiconductor device having a thin carrier storage layer 20 can be realized. For example, the thickness of the carrier stored layer 20 along the groove may be made smaller than 1 μm. This makes it possible to further expand the depletion layer toward the drift region 10, and suppress electric field concentration at the bottom of the trench or the like.

As described above, according to the semiconductor device of the embodiment, the on-resistance of the semiconductor device can be reduced by suppressing the decrease in the impurity concentration of the carrier stored layer 20.

Hereinafter, a method for manufacturing the semiconductor device shown in fig. 1 will be described with reference to the drawings. The following manufacturing method is an example, and it is needless to say that the semiconductor device shown in fig. 1 can be realized by various manufacturing methods other than the above-described manufacturing method including the modification.

As shown in FIG. 3, in n as a silicon semiconductor, for example^-In the region of drift region 10 where gate 80 is disposed, groove 100 extending in the film thickness direction is formed. The groove 100 is formed using, for example, a photolithography technique and an etching technique.

Then, n-type impurities are implanted from the front surface of the drift region 10 to a predetermined depth, and an n-type carrier stored layer 20 having a higher concentration than the drift region 10 is formed as shown in fig. 4. For example, the impurity concentration of the drift region 10 is 1E13cm^-3～1E14cm^-3To the extent that the impurity peak concentration of the carrier stored layer 20 was 8E14cm^-3～5E15cm^-3Degree of the disease. The n-type impurity is, for example, phosphorus (P) or arsenic (As). Further, the carrier stored layer 20 is formed such that the bottom surface of the carrier stored layer 20 is located above the bottom of the trench 100.

Then, an impurity is implanted into the carrier stored layer 20 so that the impurity concentration distribution along the film thickness direction has a plurality of peaks, thereby forming a p-type base region 30. Further, by implanting the p-type impurity a plurality of times at different depths, an impurity concentration distribution having a plurality of peaks along the film thickness direction can be easily realized. For example, as shown in fig. 5, p-type impurities are implanted into the 1 st implantation position D1 and the 2 nd implantation position D2 closer to the front surface than the 1 st implantation position D1. The 1 st implantation position D1 is a position of the peak of the impurity concentration of the 1 st base region 31 shown in fig. 2. The 2 nd implantation position D2 is a position of the peak of the impurity concentration of the 2 nd base region 32 shown in fig. 2. The depth of the implanted impurity is set by adjusting the energy of the implanted impurity by ion implantation, for example. For example, of base region 30The peak value of the impurity concentration was 5E16cm^-3～5E17cm^-3Degree of the disease. The p-type impurity is, for example, boron (B) or the like.

Further, as shown in fig. 6, n-type impurities are implanted into the upper surface of the base region 30 to selectively form n⁺And an emitter region 40. The impurity concentration of the emitter region 40 is, for example, 1E20cm^-3Degree of the disease. In addition, a gate insulating film 70 is formed on the inner wall of the trench 100. For example, as the gate insulating film 70, silicon oxide (SiO) having a film thickness of about 100nm to 300nm is formed by a thermal oxidation method₂) And (3) a membrane. After the gate insulating film 70 is formed, as shown in fig. 7, the gate electrode 80 is formed on the gate insulating film 70 so as to be buried inside the trench 100. For the gate 80, a polysilicon film or the like is used, for example.

Next, n-type impurities and p-type impurities are implanted from the back surface of the drift region 10 to a predetermined depth, and as shown in fig. 8, a field stop region 50 and a collector region 60 are formed. The field stop region 50 has a peak impurity concentration of 1E16cm^-3～1E17cm^-3To the extent that the impurity peak concentration of collector region 60 is 1E17cm^-3～1E18cm^-3Degree of the disease.

An interlayer insulating film 90 is formed to cover the upper surfaces of the emitter region 40, the base region 30, and the gate electrode 80. Then, an emitter 210 connected to the emitter region 40 and the base region 30 is formed on the interlayer insulating film 90. For example, an opening is provided in a part of the interlayer insulating film 90, the surface of the emitter region 40 and the base region 30 is exposed, and the emitter 210 is formed so as to fill the opening. In addition, a collector 220 is formed on the back surface of the collector region 60. Thereby, the semiconductor device shown in fig. 1 is completed.

The carrier stored layer 20, the base region 30, and the emitter region 40 are formed by an impurity diffusion method in which impurities are diffused by a heating process after the impurities are implanted. In this case, the diffusion of the n-type impurity implanted into the carrier storage layer 20, the diffusion of the p-type impurity implanted into the base region 30, and the diffusion of the n-type impurity implanted into the emitter region 40 may be performed by heating alone after the diffusion step of each region. Alternatively, the diffusion of the impurities in these regions may be performed simultaneously in the carrier stored layer 20, the base region 30, and the emitter region 40 in 1 heating step, instead of performing the diffusion of the impurities in the individual heating steps.

In the above, the method of forming the carrier stored layer 20, the base region 30, and the emitter region 40 after forming the groove 100 is described. However, the groove 100 may be formed after the carrier storage layer 20, the base region 30, and the emitter region 40 are formed. Further, the trench 100 and the emitter region 40 may be formed after the carrier stored layer 20 and the base region 30 are formed.

In the above-described method for manufacturing a semiconductor device, the base region 30 is formed by a plurality of impurity implantations having different depths. Therefore, according to the method for manufacturing a semiconductor device of the embodiment, the range in which the impurity of the base region 30 is diffused by the base annealing can be narrowed as compared with the case of 1-time impurity implantation. Therefore, the time for base annealing can be shortened, and the diffusion of impurities in the carrier stored layer 20 due to base annealing can be suppressed. As a result, the decrease in the impurity concentration of the carrier stored layer 20 during the manufacturing process can be suppressed, and the on-resistance of the semiconductor device can be reduced.

The narrower the width of the convex region in the film thickness direction, the shorter the base annealing time. Therefore, the interval of the depth of the p-type impurity implantation into the base region 30 may be made shorter than the film thickness of the carrier stored layer 20 along the groove. Thus, the width of each of the convex regions included in the impurity concentration distribution of the base region 30 in the film thickness direction is made shorter than the film thickness of the carrier storage layer 20 along the groove.

In addition, according to the method of manufacturing a semiconductor device of the embodiment, even if the thickness of the base region 30 is increased, the decrease in the impurity concentration of the carrier stored layer 20 due to the base annealing can be suppressed. Therefore, the film thickness of the base region 30 can be made thicker than the film thickness of the carrier stored layer 20.

The film thickness of the base region 30 affects the threshold value and short-circuit tolerance of the semiconductor device. According to the semiconductor device of the embodiment, the impurity concentration of the carrier stored layer 20 can be easily increased without reducing the film thickness of the base region 30.

In addition, by increasing the number of times of impurity implantation, the mutual interval of the depths of impurity implantation can be narrowed. This makes it possible to suppress the base annealing time even when the thickness of the base region 30 is increased. As a result, the decrease in the impurity concentration of the carrier stored layer 20 can be suppressed, and the on-resistance of the semiconductor device can be reduced.

In addition, when the base region 30 is formed by implanting impurities at a plurality of depths, the impurity concentration of the base region 30, which causes the threshold value, short-circuit tolerance, and Latch-up (Latch-up) of the IGBT, can be appropriately adjusted. Therefore, the design margin of the base region 30 can be improved. For example, by increasing the impurity concentration of the base region 30, short-circuit resistance and latch-up can be suppressed. On the other hand, if the impurity concentration of the base region 30 is increased, the on-resistance increases. Therefore, the impurity concentration distribution of the base region 30 is set in accordance with the characteristics required for the semiconductor device.

(modification example)

Fig. 2 shows an example of impurity concentration distributions in which the peaks of the impurity concentrations in the two convex regions have substantially the same magnitude. In contrast, as shown in fig. 9, in the impurity concentration distribution of the base region 30, the impurity concentration of the peak on the side close to the carrier stored layer 20 can be made higher than the impurity concentration of the peak on the side close to the emitter region 40.

That is, the base region 30 is formed so as to have the impurity concentration distribution shown in fig. 9. This makes it possible to keep the width of the channel region substantially constant along the gate insulating film 70. Therefore, as shown in fig. 10, the electrons e move to the carrier stored layer 20 along the gate insulating film 70.

In contrast, when annealing is performed by implanting a p-type impurity into the front surface of the drift region as in patent document 1, the impurity concentration of the base region 30 is lower in the region near the carrier stored layer 20 than in the region near the emitter region 40. At this time, as shown in fig. 11, the width of the channel region is widened in the region close to the carrier stored layer 20, and the electrons e also move in the region distant from the gate insulating film 70. Since the amount of injected electrons is increased below the base region 30 in this way, the time from the start of the flow of the short-circuit current to the destruction of the semiconductor device is short, and the short-circuit tolerance is degraded.

Therefore, by making the impurity concentration of the peak value on the side close to the carrier stored layer 20 higher than the impurity concentration of the peak value on the side close to the emitter region 40, the short-circuit tolerance of the semiconductor device can be improved.

(other embodiments)

As described above, the present invention has been described in the embodiments, but the present invention should not be construed as being limited by the description and drawings constituting a part of the disclosure. Various alternative embodiments, examples, and operational techniques will be apparent to those skilled in the art in light of this disclosure.

For example, in the above description, the embodiment in which the front end of the trench penetrating the base region 30 and the carrier stored layer 20 reaches the drift region 10 has been described. However, as shown in fig. 12, the groove may not penetrate the carrier stored layer 20. That is, the tip of the trench penetrating the base region 30 may reach at least the upper portion of the carrier stored layer 20.

Further, the carrier stored layer 20 may be formed by performing ion implantation at a deep position from the semiconductor surface at a high acceleration and then performing annealing treatment. This reduces the amount of the impurity in the carrier stored layer 20 and the impurity in the base region 30 that are diffused to cancel each other, and can further suppress a decrease in the impurity concentration of the carrier stored layer.

In the above description, the case where the semiconductor device is of an n-channel type is exemplified. However, the semiconductor device may be a p-channel type.

As described above, the present invention naturally includes various embodiments and the like not described herein.

Industrial applicability

The semiconductor device of the present invention can be applied to the electronic equipment industry including the manufacturing industry of manufacturing semiconductor devices having a carrier stored layer.

Description of the reference symbols

10: drift region

20: carrier accumulation layer

30: base region

40: emission area

50: field stop zone

60: collector region

70: gate insulating film

80: grid electrode