Techniques for setting a level 2 auto-close timer to access a memory device

文档序号：809170 发布日期：2021-03-26 浏览：36次中文

阅读说明：本技术 用于设置2级自动关闭定时器以访问存储器装置的技术 (Techniques for setting a level 2 auto-close timer to access a memory device ) 是由 V.科兹科图 S.奇拓尔 E.乔克斯 S.G.拉马苏布拉马尼安于 2020-06-24 设计创作，主要内容包括：用于设置2级自动关闭定时器以访问存储器装置的技术包含设置用于所述2级自动关闭定时器的第一和第二时间值以在对存储器装置的存储阵列的排进行的高速缓存行访问之后促使被访问的排自动关闭的示例。对于这些示例,所述高速缓存行访问响应于促使对存储器装置的所述存储阵列进行连续或非连续高速缓存行访问的多通道地址交错策略。(Techniques for setting a level 2 auto-close timer to access a memory device include examples of setting first and second time values for the level 2 auto-close timer to cause an accessed bank to auto-close following a cache line access to a bank of a storage array of the memory device. For these examples, the cache line access is in response to a multi-channel address interleaving policy that causes consecutive or non-consecutive cache line accesses to the storage array of a memory device.)

1. An apparatus, comprising:

an interface to access a memory controller of a memory device via a plurality of channels; and

circuitry of the memory controller to:

setting a first time value for a first level of a level 2 auto-close timer, the first level of the level 2 auto-close timer to cause a bank of a storage array of a first memory device to auto-close after a first cache line access to the bank, the first cache line access responsive to a multi-channel address interleaving policy that causes successive cache line accesses to the storage array of the first memory device via a first channel of the plurality of channels; and

setting a second time value for a second level of the level 2 auto-close timer, the second level of the level 2 auto-close timer to cause the rank to auto-close after a second cache line access to the rank, the second cache line access responsive to the multi-channel address interleaving policy that causes non-sequential cache line accesses to the storage array of a first memory device via the first channel.

2. The apparatus of claim 1, the multi-channel address interleaving policy to comprise a 2-channel address interleaving policy, the 2-channel address interleaving policy to include a first 4-way interleaving that maps physical memory addresses of the storage array of a first memory device to a first set of four cache lines of a string of cache lines to the first channel to cause the consecutive cache line accesses to the storage array of the first memory device.

3. The apparatus of claim 2, further comprising the circuitry to:

monitoring cache line accesses of the first set of four cache lines of the string of cache lines;

determining a moving average inter-arrival time of at least two consecutive cache line accesses of the first set of four cache lines; and

adjusting the first time value for the first level of the level 2 auto-close timer to increase a likelihood of a page hit for a subsequent cache line access to the storage array of a first memory device via the first channel.

4. The apparatus of claim 2, further comprising the circuitry to:

monitoring cache line accesses of the first set of four cache lines of the string of cache lines;

determining a moving average inter-arrival time of at least two consecutive cache line accesses of the first set of four cache lines; and

adjusting the first time value for the first level of the level 2 auto-close timer to reduce a likelihood of a page miss for a subsequent cache line access to the storage array of a first memory device via the first channel.

5. The apparatus of claim 2, comprising the 2-lane address interleaving policy to further comprise:

a second 4-way interleave that maps a physical memory address of a rank of a storage array of a second memory device to a next set of four cache lines of the string of cache lines to a second channel of the plurality of channels;

a third 4-way interleave that maps a physical memory address of the bank of the storage array of the first memory device to a third set of four cache lines of the string of cache lines to the first channel; and

causing the non-sequential cache line accesses to the storage array of the first memory device includes the 2-way address interleaving policy to cause a last cache line access to the first 4-way interleave and a first cache line access to the third 4-way interleave.

6. The apparatus of claim 5, further comprising the circuitry to:

monitoring accesses to the last cache line of the first 4-way interleave and accesses to the first cache line of the third 4-way interleave;

determining a moving average inter-arrival time between accesses to the last cache line and the first cache line; and

adjusting the second time value for the second level of the level 2 auto-close timer to increase a likelihood of a page hit for a subsequent cache line access to the storage array of a first memory device via the first channel when the subsequent cache line access is preceded by a cache line access to the storage array of a second memory device via the second channel.

7. The apparatus of claim 5, further comprising the circuitry to:

monitoring accesses to the last cache line of the first 4-way interleave and accesses to the first cache line of the third 4-way interleave;

determining a moving average inter-arrival time between an access to the last cache line and an access to the first cache line; and

adjusting the second time value for the second level of the level 2 auto-close timer to reduce a likelihood of a page miss for a subsequent cache line access to the storage array of the first memory device via the first channel when the subsequent cache line access is preceded by a cache line access to the storage array of a second memory device.

8. The apparatus of claim 5, the memory array comprising a first memory device comprising a plurality of first memory dies disposed on a first Dual Inline Memory Module (DIMM) and the memory array of the second memory device comprising a plurality of second memory dies disposed on a second DIMM.

9. The apparatus of claim 1, comprising the first and second cache line accesses to access 64 bytes of data separately from the rank of the storage array of the first memory device.

10. The apparatus of claim 1, the storage array of a first memory device comprising a plurality of memory dies arranged on a dual in-line memory module (DIMM).

11. The apparatus of claim 1, comprising the first memory device comprising a dynamic random access memory.

12. A method, comprising:

13. The method of claim 12, the multi-channel address interleaving policy comprising a 2-channel address interleaving policy, the 2-channel address interleaving policy including a first 4-way interleaving that maps physical memory addresses of the storage array of a first memory device to a first set of four cache lines of a series of cache lines to the first channel to facilitate the consecutive cache line accesses to the storage array of the first memory device.

14. The method of claim 13, further comprising:

monitoring cache line accesses of the first set of four cache lines of the string of cache lines;

determining a moving average inter-arrival time of at least two consecutive cache line accesses of the first set of four cache lines; and

15. The method of claim 13, further comprising:

monitoring cache line accesses of the first set of four cache lines of the string of cache lines;

determining a moving average inter-arrival time of at least two consecutive cache line accesses of the first set of four cache lines; and

16. The method of claim 13, including the 2-way address interleaving policy to further comprise:

a second 4-way interleave that maps a physical memory address of a rank of a storage array of a second memory device to a next set of four cache lines of the series of cache lines to a second channel coupled with the processor;

17. The method of claim 16, further comprising:

monitoring accesses to the last cache line of the first 4-way interleave and accesses to the first cache line of the third 4-way interleave;

determining a moving average inter-arrival time between accesses to the last cache line and the first cache line; and

18. The method of claim 17, further comprising:

monitoring accesses to the last cache line of the first 4-way interleave and accesses to the first cache line of the third 4-way interleave;

determining a moving average inter-arrival time between an access to the last cache line and an access to the first cache line; and

19. The method of claim 16, comprising the memory array of a first memory device including a plurality of first memory dies disposed on a first dual in-line memory module (DIMM) and the memory array of the second memory device including a plurality of second memory dies disposed on a second DIMM.

20. The method of claim 12, comprising the first and second cache line accesses being to access 64 bytes of data separately from the rank of the storage array of the first memory device.

21. The method of claim 12, the memory array of a first memory device comprising a plurality of memory dies arranged on a dual in-line memory module (DIMM).

22. The method of claim 12, comprising the first memory device comprising a dynamic random access memory.

23. At least one machine readable medium comprising a plurality of instructions that in response to being executed by a system, cause the system to carry out a method according to any one of claims 12-22.

24. An apparatus comprising means for performing the method of any one of claims 12-22.

Technical Field

The description generally relates to techniques for accessing memory.

Background

Computing platforms containing Dynamic Random Access Memory (DRAM) systems may arrange DRAM systems with multiple channels (channels), memory modules (rank), and memory arrays (bank) to enable parallel access to the DRAM devices of the DRAM systems. This parallel access may increase memory access bandwidth to better meet the stringent latency and memory capacity needs of a computing platform, which may contain a central processing unit with multiple cores and/or processor sockets coupled with a DRAM system via multiple channels. These DRAM devices of a DRAM system may contain a plurality of DRAM chips or dies contained in a memory module arranged in a plurality of memory arrays. The memory array may be further divided into multiple ranks across multiple DRAM chips to provide greater memory address capacity for accessing the DRAM system. Each storage array may be further divided into a plurality of columns to provide locality.

In operating a DRAM system, a given memory array may have banks that are open or banks that are not open. The memory elements or cells within a rank are typically identified as pages or memory pages. In some examples, to access data within a page, the page is opened or activated. The opening of the page causes data held in memory cells of the page to be loaded into a buffer (e.g., sense amplifier) associated with the memory array being accessed. This allows access to data within the page to be read or written. Accessing an already open rank/page of a given storage array is commonly referred to as a "page hit". Accessing a storage array without any open ranks is commonly referred to as "empty". Accessing a non-open bank of a storage array while a separate bank of the storage array is still open is commonly referred to as a "page miss". A page hit will have a lower access latency than a blank because there is no need to open or activate a page before a request access can proceed during a page hit. Meanwhile, for a blank, the page needs to be opened and the contents of the page loaded into the buffer before the memory unit can be accessed. Also, blanks have lower access latency compared to page misses, because in the case of a page miss, the still open page needs to be closed before the non-open bank can be opened.

Drawings

FIG. 1 illustrates an example system.

FIG. 2 illustrates an example memory module.

FIG. 3 illustrates an example address interleaving policy.

Fig. 4A-B illustrate an example scenario.

Fig. 5 illustrates an example cache string (cache stream).

FIG. 6 illustrates an example state machine.

Fig. 7 illustrates an example first logic flow.

FIG. 8 illustrates an example device.

Fig. 9 illustrates an example second logic flow.

FIG. 10 illustrates an example storage medium.

FIG. 11 illustrates an example computing platform.

Detailed Description

The operating performance of a DRAM system may depend closely on when an open rank/page is closed for the memory array of the DRAM device. Some DRAM devices implement an auto-off timer to close a rank after a predetermined time from the last access to the memory array. In the example, a rank of a storage array is accessed "x". The next access to the storage array can be to the same rank "x'Or to different ranks'y". For this example, if a pair-wise ranking occurs "x"another access of, and arrange"x"has been closed due to the auto-close timer, then the other access is typically referred to as a blank, and if the auto-close timer is set to a higher time value, then the blank may be a page hit. This would be the reason for increasing the time value of the auto-close timer so that the open bank remains open long enough to remain open for another access and thus generate a page hit. This first type of access may be referred to as "type I access". On the other hand, if in the row of pairs "x"after visiting, select Pair Row"y"make access, but arrange"x' is composed ofA page miss occurs when the auto-close timer has not expired and is still on, and the hit miss may be blank if the auto-close timer is set to a lower time value. This page miss, which could be blank, would be the reason for reducing the time value of the auto-off timer. This type of access may be referred to as "type II access". Accesses involving blanks have lower access latency than type II accesses involving page misses. The goal of the auto-close policy would be to have a higher incidence of type I accesses than type II accesses.

A technique known as address interleaving may be implemented (e.g., by a memory controller) to access DRAM devices of a DRAM system. Address interleaving may involve accessing different channels, memory arrays, and memory modules to obtain data bandwidth benefits via memory array level parallelism. Physical memory addresses may be stripped across multiple channels in some manner to balance between page hits and storage array level parallelism. For example, physical memory addresses for a string of cache lines (e.g., 64 byte cache line size) may be stripped across multiple channels.

In some examples, stripping physical memory addresses for a string of cache lines across the first and second ways may cause physical addresses of a first number of cache lines in the string of cache lines to be distributed across ranks of the first storage array mapped to the first way, and physical addresses of a second number of cache lines in the string of cache lines to be distributed across ranks of the second storage array mapped to the second way. Thus, upon receiving a request to access a physical address for a cache line stream, the first and second storage arrays may be accessed in an interleaved manner to increase memory access bandwidth. The staggered manner of these accesses produces a 2-level inter-arrival time between accesses to the same memory array. The first level is the time for accessing a cache line distributed across a given bank of the storage array, and the second level is the time for subsequently accessing the or another bank of the given storage array.

According to some examples, the address interleaving policy may include a 4-way interleaving that maps physical addresses of a first four adjacent cache lines of a string of cache lines to a first lane and a first storage array, maps physical addresses of a next four adjacent cache lines of the string to a second lane and a second storage array, maps physical addresses of a next four adjacent cache lines of the string to the first lane and the first storage array, and so on. For this example, the level 2 interarrival time will have a first level of approximately the amount of time to access a cache line at the first storage array via the first channel and a second level of approximately the amount of time to access all four cache lines at the second storage array via the second channel. In other words, the second level is the approximate time that the cache line is interleaved from the first way to the second way and the access returns to the first way. If a DRAM access is made according to this address interleaving policy, then the access to the first channel and the next four adjacent cache lines of the string of the first storage array can potentially be a page hit, but the auto-off timer needs to keep the previously accessed bank of the first storage array open long enough to account for the amount of time used to access the four cache lines at the second storage array via the second channel. In other words, the auto-off timer needs to keep the rank open long enough for the 4-way interleaving of the address interleaving policy to roll back to accessing the rank of the first storage array mapped to the first channel.

In some DRAM systems, accesses to a DRAM device may see cache line strings of different lengths. The different lengths of the cache line strings may be an attribute of single core access requests made by cores of a Central Processing Unit (CPU) coupled with these DRAM systems. Conflicts between access requests from different cores of the CPU may also result in varying lengths. The above-mentioned level 2 inter-arrival timing for rank/storage array access makes it a challenge to have a single level auto-off timer that can adapt to the level 2 inter-arrival time. Depending on the learning rate of this single-stage auto-close timer, the single-stage auto-close timer may oscillate between timer values that are too low or too high, or simply remain somewhere in between. This oscillation may reduce type I accesses and produce an increase for less desirable type II accesses. Reducing type I accesses and increasing type II accesses increases overall access latency. Thus, a single level auto-off timer may be problematic for DRAM systems implementing address interleaving policies.

Fig. 1 illustrates an example system 100. In some examples, as shown in FIG. 1, system 100 includes a processor 110 coupled with slots 122-1/2, 132-1/2, 142-1/2, 152-1/2, 162-1/2, and 172-1/2 via respective channels 120, 130, 140, 150, 160, and 170. For these examples, processor 110 may include a first memory controller 112-1 to control access to memory devices (e.g., disposed on dual in-line memory modules (DIMMs)) when inserted in slots 122-1/2, 132-1/2, or 142-1/2 and a second memory controller 112-2 to control access to memory devices when inserted in slots 152-1/2, 162-1/2, or 172-1/2.

According to some examples, each slot depicted in fig. 1 may be arranged to receive a memory device arranged on a separate DIMM. Such as a memory device included in DIMM 105-1 to be inserted in slot 142-2 or DIMM 105-2 to be inserted in slot 152-2. For these examples, a separate DIMM may contain a memory device with non-volatile or volatile types of memory. Volatile type memory may include, but is not limited to, DRAM type volatile memory. As described further below, memory devices, such as those included in DIMMs 105-1 or 105-2, may be arranged in one or more memory modules that may connect multiple memory chips or dies to the same memory bus (address + data). Each memory module may be divided into a plurality of memory arrays spanning multiple memory chips or dies. As also described further below, the memory array may be further divided into multiple ranks across multiple DRAM chips to provide greater memory address capacity for accessing the DRAM system. In addition, the respective storage array may be further divided into a plurality of columns to provide locality for identifying a particular physical memory address for a given rank.

In some examples, as shown in FIG. 1, processor 110 includes memory controller 112-1 coupled to channels 120, 130, and 140 and memory controller 112-2 coupled to channels 150, 160, and 170. Examples are not limited to processors that include two separate memory controllers coupled to three data channels. An example may include a processor with a single memory controller coupled with more or less than 3 data lanes coupled to the single memory controller. Other examples may contain more than two memory controllers and more or less than 6 data lanes. For the example shown in fig. 1, to reduce memory access request bottlenecks, multiple channels 120, 130, 140, 150, 160, and 170 may be employed in the system 100. According to some examples, processor 110 may represent a single-core or multi-core processor.

According to some examples, a 2-channel address interleaving policy 101 may be implemented that includes stripping physical memory addresses stored to a string of cache lines (e.g., 64 bytes per line size) of memory devices included in DIMMs 105-1 and 105-2 across channels 140 and 150 in a manner to balance between page hits and storage array level parallelism. As described in more detail below, logic and/or features of a memory controller, such as the timer logic 114, may be capable of setting and adjusting a multi-level auto-close timer to close a rank of a memory array accessed according to an address interleaving policy, such as the 2-lane address interleaving policy 101, to accommodate a 2-level inter-arrival time created as a result of implementing a multi-lane address interleaving policy.

According to some examples, one or more memory devices included in a DIMM to be inserted in slots 122-1/2, 132-1/2, 142-1/2, 152-1/2, 162-1/2, or 172-1/2 and at least some of channels 120, 130, 140, 150, 160, or 170 to access these memory devices may be designed to operate in accordance with various memory technologies. The various memory technologies may include, but are not limited to, DDR4 (DDR version 4, initial specification published by JEDEC in 9 months 2012), LPDDR4 (low power double data rate (LPDDR) version 4, JESD209-4, originally published by JEDEC in 8 months 2014), WIO2 (wide I/O2 (WideIO 2), JESD229-2, originally published by JEDEC in 8 months 2014), HBM (high bandwidth memory DRAM, JESD235, originally published by JEDEC in 10 months 2013), HBM2 (version 2, JESD235A, originally published by JEDEC in 2016 1 months) and/or other technologies based on derivatives or extensions of such specifications. The various memory technologies may also include currently under development memory technologies including, but not limited to, DDR5 (DDR version 5, currently under discussion by JEDECC), LPDDR5 (LPDDR version 5, currently under discussion by JEDEC), HBM3 (HBM version 3, currently under discussion by JEDEC), non-volatile DIMM-persistent (NVDIMM-P, currently under discussion by JEDEC), and/or other new technologies based on derivatives or extensions of these under development memory technologies.

According to some examples, a DIMM (such as DIMM 105-1 or 105-2) to be inserted in slot 122-1/2, 132-1/2, 142-1/2, 152-1/2, 162-1/2, or 172-1/2 may be designed to function as a Registered DIMM (RDIMM), a reduced load DIMM (LRDIMM), a fully buffered DIMM (FB-DIMM), an Unbuffered DIMM (UDIMM), or a Small Outline DIMM (SODIMM). Examples are not limited to only these DIMM designs.

In some examples, the memory devices or dies included in the DIMMs to be inserted in slots 122-1/2, 132-1/2, 142-1/2, 152-1/2, 162-1/2, or 172-1/2 may include non-volatile and/or volatile types of memory. Volatile types of memory may include, but are not limited to, Random Access Memory (RAM), Dynamic RAM (DRAM), double data rate synchronous dynamic RAM (DDR SDRAM), Static Random Access Memory (SRAM), thyristor RAM (T-RAM), or zero capacitor RAM (Z-RAM). The non-volatile type of memory may comprise a byte or block addressable type of non-volatile memory having a three-dimensional (3D) cross-point memory structure including, but not limited to, a chalcogenide phase change material (e.g., chalcogenide glass) hereinafter referred to as a "3D cross-point memory". Non-volatile types of memory may also include other types of byte or block addressable non-volatile memory, such as, but not limited to, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), antiferroelectric memory, resistive memory including metal oxide based, oxygen vacancy based, and conductive bridge random access memory (CB-RAM), spintronic magnetic junction memory, Magnetic Tunnel Junction (MTJ) memory, Domain Wall (DW) and Spin Orbit Transfer (SOT) memory, thyristor-based memory, Magnetoresistive Random Access Memory (MRAM) incorporating memristor technology, spin transfer torque MARM (STT-MRAM), or a combination of any of the above.

FIG. 2 illustrates an example memory module 200 for DIMM 105-1. In some examples, as mentioned previously, the memory may be spatially organized into channels, memory modules, memory arrays, rows, and columns. As shown in fig. 2, in some examples, memory module 200 may be organized to have four memory arrays 220-1 to 220-4 (examples are not limited to four memory arrays) spanning multiple memory dies. For example, memory array 220-1 may span memory dies 205-1, 205-8, 205-9, and 205-n, where "n" is any all positive integer greater than 12. In performing a memory access to memory array 220-1, the channel, memory module, and memory array are identified. An entire row or page of "Row x" (e.g., 8 Kilobytes (KB) in size) depicted in FIG. 2 as storage array 220-1 may then be loaded onto a set of sense amplifiers, shown in FIG. 2 as sense amplifiers 222-1. The set of sense amplifiers may also be referred to as a bank buffer. The corresponding column address for this memory access then identifies the locality reference for data read or write to memory array 220-1.

According to some examples, if a bank is left open for at least a period of time and a subsequent memory access is to the same open bank (page hit), access latency is reduced because the subsequently accessed bank does not need to be reloaded into sense amplifier 222-1. However, if the subsequent access is to a different bank of memory array 220-1 (page miss), sense amplifier 222-1 needs to be flushed before the different bank is loaded, which increases access latency. As mentioned above, a page miss has a higher access latency than a blank access because the flush of sense amplifier 222-1 and subsequent loading of a different bank takes longer than if bank x is no longer open, then only loading a different bank. To minimize access latency, rank x should be kept open long enough to maximize the likelihood of a page hit, but short enough to minimize a page miss. As previously mentioned, some techniques may use a single level auto-close timer that is started once rank x is opened and then auto-closes rank x once the single level auto-close timer expires. A single level auto-off timer can be problematic when implementing a multi-channel address interleaving policy.

In some examples, as mentioned above with respect to FIG. 1, the 2-channel address interleaving policy 101 may involve the use of DIMMs 105-1. For these examples, striping physical memory addresses for a string of cache lines across two lanes may yield a level 2 inter-arrival time. As mentioned previously, multiple inter-arrival times can make using a single-stage auto-close timer problematic. The use of a single level auto-off timer is also problematic where cache line strings may differ in length based on the type of applications executed by the processor 110 when accessing those cache line strings or due to interference between access requests from different cores of the processor 110 (if configured as a multi-core processor). As described further below, logic and/or features of a memory controller at a processor (such as timer logic 114 of memory controller 112-1 or 112-2) may set and adjust two separate auto-off times with two levels of auto-off timers for what is referred to hereinafter as a "level 2 auto-off timer". The level 2 auto-close timer may, for example, accommodate a level 2 inter-arrival time formed by the implementation of the 2-channel address interleaving policy 101.

FIG. 3 illustrates an example address interleaving policy 300. In some examples, the address interleaving policy 300 may represent physical address interleaving for a first 4-way interleaving that maps physical memory addresses of a first four rows of a series of cache lines to a first channel and a first memory array as part of a 2-channel address interleaving policy. For these examples, the least significant 6 bits of the example 12-bit physical memory address are not part of the address interleaving policy 300, since the memory is accessed at a cache line granularity of 64 bytes. Further, as shown in FIG. 3, bits 6, 7, and 9 are used for column mapping, while bits 8, 10, 11, and 12 are used for channel mapping. This means that in the cache string, the first four cache lines (e.g., cache lines 0-3) are mapped to the same first way and the same first storage array. The second 4-way interleave that maps the physical memory address of the next set of four cache lines (e.g., cache lines 4-7) of the string is then mapped to the second way. The next four cache lines (e.g., cache lines 8-11) are then mapped to the first way and the first storage array, and so on. More details on how this type of 4-way interleaving policy can be implemented are described in more detail below.

In some examples, the address interleaving policy 300 allows memory addresses for a string of cache lines to be stripped across multiple channels in some manner to balance between page hits and storage array level parallelism. This is done by using some lower bits for the columns and then striping across multiple lanes. Although address interleaving policy 300 is for 4-way interleaving, examples are not limited to 4-way interleaving for mapping cache lines to the same way and storage array.

Fig. 4A and 4B illustrate an example scenario 400. In some examples, scheme 400 may depict how address interleaving policy 300 may be implemented for 4-way interleaving of cache lines 410-1 through 410-16 contained in cache string 405. In some examples, as shown in FIGS. 4A-B, implementation of address interleaving policy 300 may cause cache lines 410-1 through 410-4 with respective logical memory spaces 420-1 through 420-4 and cache lines 410-9 through 410-12 with respective logical memory spaces 420-9 through 420-12 to be mapped to channel 430-1 and to storage array 440-1. At the same time, cache lines 410-5 through 410-8 with corresponding logical memory spaces 420-5 through 420-8 and cache lines 410-13 through 410-16 with corresponding logical memory spaces 420-13 through 420-16 are mapped to channel 430-2 and to storage array 440-2.

FIG. 5 illustrates an example cache string 405. In some examples, cache string 405 is depicted in a manner that illustrates how 4-way interleaving of cache lines 410-1 through 410-16 that map to channels 430-1 and 430-2 and are interleaved between these channels may have different inter-arrival times. For these examples, different inter-arrival times may be used to determine the time value for the level 2 auto-close timer. The interleaving between channels 430-1 and 430-2 results in a short inter-arrival time 510 and a large inter-arrival time 520 for accessing the same memory array. For example, short inter-arrival time 510 may be the arrival time between accesses to storage array 440-1 for cache lines 410-1 through 410-4 and 410-9 through 410-12 or between accesses to storage array 440-2 for cache lines 410-5 through 410-8 and 410-13 through 410-16. Large inter-arrival time 520 may be the arrival time between the time of accessing the last cache line mapped to the 4-way interleave of memory array 440-1 and the time of accessing the subsequent 4-way interleave mapped to memory array 440-1.

In some examples, for cache string 405, consecutive accesses to cache lines mapped to the same storage array (such as cache lines 410-1 through 410-4 to storage array 440-1) may have the first level of the level 2 auto-close timer set to increase the likelihood of a blank access compared to a page miss for accesses to a different rank, or to increase the likelihood of a page hit for accesses to the same rank. In other words, the first level may be set to a time value that increases the likelihood of type I accesses (page hits) or decreases the likelihood of type II accesses (page misses/ranks remain open for too long). For these examples, the first level should be set to a time value similar to the time of the short inter-arrival time 510 to increase the likelihood of type I accesses and decrease the likelihood of type II accesses.

According to some examples, for cache string 405, an access to cache lines 410-1 through 410-4 mapped to storage array 440-1 and subsequently an access to cache lines 410-9 through 410-12 mapped to storage array 440-1 may potentially be a page hit, but only when the bank being accessed for cache lines 410-1 through 410-4 remains open long enough to capture a large inter-arrival time 520. In other words, the second level of the level 2 auto-close timer may be set to a time value that increases the likelihood of a page hit. For these examples, the second level of the level 2 auto-close timer may be set to a time similar to the large inter-arrival time 520.

Fig. 6 illustrates an example state machine 600. According to some examples, as shown in fig. 6, state machine 600 contains state 610 (empty), state 620 (page/line open with short auto-close), and state 630 (page/line open with long auto-close). For these examples, state machine 600 depicts a manner in which logic and/or features of a memory controller (e.g., timer logic 114) may implement a level 2 auto-off timer when faced with a level 2 inter-arrival time resulting from using address interleaving policy 300 and 4-way interleaving of cache lines contained in cache string 405 as shown in fig. 4A-B and 5.

According to some examples, at state 610, an initial access to a cache line mapped to the first channel (e.g., cache line 410-1) results in a blank access. Then at state 620, for the first 3 accesses in the cache string, the page/bank accessed after the subsequent page miss may continue to trigger the first level timer to close the bank accessed, increasing the likelihood of blank accesses each time the first level time is triggered after the access as state machine 600 moves back and forth between states 610 and 620. However, if a fourth access to the mapped cache line (e.g., cache line 410-4) results in a page hit, state 630 is entered and the bank/page of this fourth access is opened with a long auto-close that triggers the second level timer to keep the bank open after the fourth access to accommodate longer or greater inter-arrival times when accessing other cache lines (e.g., cache lines 410-5 through 410-8) in cache string 405 via the second mapped way, and then the access returns to the cache line mapped to the first way.

Fig. 7 illustrates an example logic flow 700. In some examples, the logic flow 700 may be implemented by logic and/or features of a memory controller, such as the timer logic 114 included in the memory controller 112-1 or the memory controller 112-2 shown in fig. 1, to adaptively modify or adapt the time values for the short or long auto-off times of the level 2 auto-off timer. For these examples, the level 2 auto-off timer may be based on an expected level 2 inter-arrival timing for rank/storage array accesses associated with implementing a 2-lane address interleaving policy.

Beginning in block 705, timer logic 114 of memory controller 112-1 monitors cache line accesses to DIMM 105-1 mapped to channel 140 and DIMM 105-2 mapped to channel 150. In some examples, cache line accesses may be made according to an address interleaving policy, such as address interleaving policy 300. As part of the monitoring of cache line accesses, timer logic 114 may monitor the arrival time of cache line accesses made to the storage array of the memory device for cache lines mapped to channels 140 and 150. For example, a cache line used to access memory array 220-1 of memory module 200 contained on DIMM 105-1 is mapped to channel 140. Timer logic 114 may distinguish between short inter-arrival times (e.g., during physical address interleaving to memory array 220-1) and long inter-arrival times (e.g., caused by channel interleaving between channels 140 and 150).

Moving to block 710, the timer logic 114 may determine a moving average for the inter-arrival access time to compare to the target auto-off time. According to some examples, the moving average may be based on an arrival time of each 2 cache line accesses to the storage array of the memory device for a cache line mapped to either channel 140 or channel 150 monitored by timer logic 114.

Moving to decision block 715, the timer logic 114 may determine whether the moving average is associated with a short or long inter-arrival access. In some examples, the moving average is associated with a short inter-arrival access if 2 cache line accesses are during consecutive or consecutive accesses to the same storage array. For these examples, the moving average is associated with a long inter-arrival access if the 2 cache line accesses are not consecutive or consecutive accesses to the same storage array. In other words, the 2 cache line accesses used to determine the moving average are based on a first cache line access to the first storage array mapped to the first lane interleaved with a cache line access to the second storage array mapped to the second lane prior to a second cache line access to the first storage array. If the moving average is associated with a short inter-arrival access, the logic flow 700 moves to decision block 720. If the moving average is associated with a long inter-arrival access, the logic flow 700 moves to decision block 730.

Moving from decision block 715 to decision block 720, the timer logic 114 determines whether the moving average of short level (short level) times for the level 2 timer results in a missed opportunity for a page hit or a missed opportunity for a blank access. According to some examples, the target short level time value may represent an ideal auto-close time for the first (short) level time of the level 2 auto-close timer in order to increase the likelihood of page hits and decrease the likelihood of page misses. For these examples, a miss opportunity for a page hit access occurs if the short stage time of the level 2 timer is too short and results in the rank being closed before a subsequent access to the rank that would have been a page hit. If the short stage time is too long and results in a bank being opened during a subsequent access to a different bank, where the subsequent access is a page miss (which may be blank if the bank is not opened during the subsequent access), a miss opportunity for a blank access occurs. If there is no chance of a miss, the logic flow 700 moves to block 725. Otherwise, logic flow 700 moves to decision block 740.

Moving from decision block 720 to block 725, the timer logic 114 maintains a short time value for the short stage time of the stage 2 timer. The logic flow 700 may then return to block 705.

Moving from decision block 715 to decision block 720, the timer logic 114 determines whether the moving average of long level (long level) times for the level 2 timer results in a missed opportunity for a page hit access or a missed opportunity for a blank access. According to some examples, the target short level time value may represent an ideal auto-close time for the second (long) level time of the level 2 auto-close timer in order to increase the likelihood of page-hit accesses and decrease the likelihood of page-miss accesses. For these examples, a miss opportunity for a page hit access occurs if the long stage time of the 2-stage timer is too short and results in the rank being closed before a subsequent access to the rank that would otherwise be a page hit. If the long stage time is too long and results in a bank being opened during a subsequent access to a different bank that results in a page miss (which may be blank if the bank is not opened during the subsequent access), a miss opportunity for a blank access occurs. If there is no chance for a miss, logic flow 700 moves to block 735. Otherwise, logic flow 700 moves to decision block 740.

Moving from decision block 730 to block 735, the timer logic 114 maintains a short time value for the short stage time of the stage 2 timer. The logic flow 700 may then return to block 705.

Moving from decision block 720 or 730, the timer logic 114 determines whether the miss opportunity resulted in a type I access or a type II access. If the miss opportunity results in a type I access, the logic flow 700 moves to block 745. If the miss opportunity results in a type II access, the logic flow 700 moves to block 750.

Moving from decision block 740 to block 745, the timer logic 114 may increase the time value. If the opportunity is a short level time for the level 2 timer that resulted in a missed opportunity, the short level time is increased to increase the likelihood of page hit accesses to short inter-arrival cache line accesses. If the opportunity is a long level time for the level 2 timer that resulted in a missed opportunity, the long level time is increased to increase the likelihood of page hit accesses to long inter-arrival cache line accesses. The logic flow 700 then loops to block 705.

Moving from decision block 740 to block 750, timer logic 114 may decrease the time value. If the opportunity is a short level time for the level 2 timer that resulted in a missed opportunity, the short level time is reduced to reduce the likelihood of page miss accesses to short inter-arrival cache line accesses. If the opportunity is a long level time for the level 2 timer that resulted in a missed opportunity, the long level time is reduced to reduce the likelihood of page miss accesses to long inter-arrival cache line accesses. The logic flow 700 then loops to block 705.

Fig. 8 illustrates an example device 800. Although the device 800 shown in fig. 8 has a limited number of elements in a certain topology, it may be appreciated that the device 800 may include more or less elements in alternative topologies as desired for a given implementation.

According to some examples, device 800 may be timer logic of a memory controller (such as timer logic 114 of memory controller 112-1 or 112-2 shown in fig. 1) and may be supported by circuitry 820. For these examples, circuitry 820 may be an ASIC, FPGA, configurable logic, processor circuit, or one or more cores of a processor, such as processor 110. Circuitry 820 may be arranged to execute logic or one or more software or firmware implemented modules, components, or features of logic. It is worth noting that "a”、“b”、“c"and similar designators, as used herein, are intended to be variables representing any positive integer. Thus, for example, if settings are implementedaA value of =4, then the complete set of software or firmware for the modules, components of logic 822-a may comprise logic 822-1, 822-2, 822-3, or 822-4. The examples presented are not limited in this context, and different variables used throughout may represent the same or different integer values. Furthermore, "module," "component," or "feature" may also comprise software stored in a computer-readable or machine-readable medium orFirmware, and while the types of features are illustrated in fig. 8 as separate blocks, this does not limit these types of features to storage in different computer-readable media components (e.g., separate memories, etc.).

According to some examples, the apparatus 800 may include a channel interface 805 to access a memory device via a plurality of channels. For example, as described further below, logic to enable apparatus 800 sets a level 2 auto-off timer or monitors cache line accesses across banks of a storage array of a memory device coupled to multiple channels.

In some examples, device 800 may also contain setup logic 822-1. Setting logic 822-1 may be executed or supported by circuitry 820 to set a first time value for a first stage of a level 2 auto-off timer. For these examples, a first level of the level 2 auto-close timer may be included in the short time value 830 and set to cause the rank of the storage array of the first memory device to auto-close after a first cache line access to the rank in response to the multi-channel address interleaving policy. A multi-channel address interleaving policy may be included in policy 810 and this policy causes consecutive cache line accesses included in cache line string 840 to a storage array of a first memory device via a first channel of the multiple channels.

In some examples, the setting logic 822-1 may also be executed or supported by the circuit 820 to set a second time value for a second stage of the level 2 auto-close timer. For these examples, a second level of the level 2 auto-close timer may be included in the short time value 835 and arranged to cause the rank to auto-close after a second cache line access to the rank in response to a multi-lane interleaving policy that causes non-sequential cache line accesses to a storage array of the first memory device via the first lane.

According to some examples, device 800 may also include monitoring logic 822-2. Monitoring logic 822-2 may be executed or supported by circuitry 820 to monitor cache line accesses of cache line string 840 and to collect access timing information contained in access information 845. For these examples, the multi-channel address interleaving policy included in policy 810 may be a 2-channel address interleaving policy, the 2-channel address interleaving policy including a first 4-way interleave that maps a physical memory address of the storage array of the first memory device to a first set of four cache lines of cache line string 840 of the first channel to facilitate consecutive cache line accesses to the storage array of the first memory device.

In some examples, device 800 may also include averaging logic 822-3. Averaging logic 822-3 may be executed or supported by circuitry 820 to determine a moving average inter-arrival time for at least two consecutive cache line accesses of the first set of four cache lines based on the access time information contained in access information 845.

According to some examples, device 800 may also include adjustment logic 822-4. Adjustment logic 822-4 may be executed or supported by circuitry 820 to adjust a first time value for a first level of the level 2 auto-close timer to increase a likelihood of a page hit or decrease a likelihood of a page miss for a subsequent cache line access to a storage array of a first memory device via a first channel. For this example, adjustment logic 822-4 increases short time value 830 to increase the likelihood of a page hit, or may decrease short time value 830 to decrease the likelihood of a page miss.

In some examples, the 2-way address interleaving policy may further include a second 4-way interleaving that maps physical memory addresses of a bank of a storage array of the second memory device to a next set of four cache lines of cache line string 840 to a second one of the plurality of ways coupled to way interface 805. The 2-way address interleaving policy may also include a third 4-way interleaving that maps physical memory addresses of the ranks of the storage array of the first memory device to a third set of four cache lines of the cache line string 840 to the first way. For these examples, the 2-way address interleaving policy to cause non-sequential cache line accesses to the storage array of the first memory device includes a 2-way address interleaving policy to cause accesses to a last cache line of the first 4-way interleave and accesses to a first cache line of the third 4-way interleave. Further, for these examples, monitoring logic 822-2 may monitor accesses to the last cache line of the first 4-way interleave and accesses to the first cache line of the third 4-way interleave to collect access timing information contained in access information 845. Averaging logic 822-3 may then determine a moving average inter-arrival time between accesses to the last cache line and the first cache line, and adjusting logic 822-4 may adjust a second time value for the second level of the level 2 auto-close timer to increase a likelihood of a page hit or decrease a likelihood of a page miss for a subsequent cache line access to the storage array of the first memory device via the first channel when the subsequent cache line access is preceded by a cache line access to the storage array of the second memory device via the second channel. For this example, adjustment logic 822-4 increases short time value 835 to increase the likelihood of a page hit, or may decrease short time value 835 to decrease the likelihood of a page miss.

The various components of device 800 may be communicatively coupled to each other by various types of communications media to coordinate operations. Coordination may involve the unidirectional or bidirectional exchange of information. For example, a component may communicate information in the form of signals communicated over the communications media. Information can be implemented as signals distributed to various signal lines. In such an allocation, each message is a signal. However, other embodiments may alternatively employ data messages. Such data messages may be sent across various connections. Example connections include parallel interfaces, serial interfaces, and bus interfaces.

Contained herein is a set of logic flows representing example methods for performing novel aspects of the disclosed architecture. While, for purposes of simplicity of explanation, the one or more methodologies shown herein are shown and described as a series of acts, those skilled in the art will understand and appreciate that the methodologies are not limited by the order of acts. Some acts may occur in different orders and/or concurrently with other acts from that shown and described herein, depending upon the context in which the acts are performed. For example, those skilled in the art will understand and appreciate that a methodology could alternatively be represented as a series of interrelated states or events, such as in a state diagram. Moreover, not all acts illustrated in a methodology may be required for a novel implementation.

The logic flow may be implemented in software, firmware, and/or hardware. In software and firmware embodiments, the logic flows may be implemented by computer-executable instructions stored on at least one non-transitory computer-readable medium or machine-readable medium (such as an optical, magnetic, or semiconductor memory device). The embodiments are not limited in this context.

Fig. 9 illustrates an example logic flow 900. The logic flow 900 may be representative of some or all of the operations executed by one or more logic, features, or apparatus described herein (such as the device 800). More specifically, logic flow 900 may be implemented by setup logic 822-1.

According to some examples, logic flow 900 at block 902 may set a first time value for a first level of a level 2 auto-close timer to cause a bank of a storage array of a first memory device to automatically close after a first cache line access to the bank in response to a multi-channel address interleaving policy that causes consecutive cache line accesses to the storage array of the first memory device via a first channel coupled with a processor. For these examples, the setup logic 822-1 may set a first level of the level 2 auto-off timer to establish a short time value associated with a short inter-arrival time for a cache line access to a storage array of the first memory device.

In some examples, logic flow 900 at block 904 may set a second time value for a second level of the level 2 auto-close timer to cause the rank to auto-close after a second cache line access to the rank in response to a multi-lane interleaving policy that causes non-sequential cache line accesses to a storage array of the first memory device via the first lane. For these examples, the setup logic 822-1 may set a second level of the level 2 auto-close timer to establish a short time value associated with a long inter-arrival time for a cache line access to the storage array of the first memory device.

Fig. 10 illustrates an example storage medium 1000. In some examples, storage medium 1400 may be an article of manufacture. The storage medium 1000 may include any non-transitory computer-readable or machine-readable medium, such as an optical, magnetic, or semiconductor storage device. Storage medium 1000 may store various types of computer-executable instructions, such as instructions that implement logic flow 900. Examples of a computer-readable or machine-readable storage medium may include any tangible medium capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. Examples of computer-executable instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, visual code, and the like. Examples are not limited in this context.

FIG. 11 illustrates an example computing platform 1100. In some examples, as shown in fig. 11, computing platform 1100 may contain processing components 1140, other platform components 1150, or communication interfaces 1160.

According to some examples, processing component 1140 may perform or implement processing operations or logic for device 800 and/or storage medium 1000. Processing component 1140 may comprise various hardware elements, software elements, or a combination of both to implement a processor, such as processor 110 shown in fig. 1. Examples of hardware elements may include devices, logic devices, components, processors, microprocessors, management controllers, companion dies (companion dies), circuits, processor circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, ASICs, Programmable Logic Devices (PLDs), Digital Signal Processors (DSPs), FPGAs, memory units, logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. Examples of software elements may include software components, programs, applications, computer programs, application programs, device drivers, system programs, software development programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, Application Program Interfaces (API), instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether to implement examples using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, thermal tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints, as desired for a given example.

In some examples, other platform components 1150 may include common computing elements, memory units (including system memory), chipsets, controllers, peripherals, interfaces, oscillators, timing devices, video cards, audio cards, multimedia input/output (I/O) components (e.g., digital displays), power supplies, and so forth. Examples of memory units or memory devices may include, but are not limited to, various types of computer-readable and machine-readable storage media in the form of one or more higher speed memory units, such as read-only memory (ROM), random-access memory (RAM), dynamic RAM (dram), double-data-rate dram (ddram), synchronous dram (sdram), static RAM (sram), programmable ROM (prom), erasable programmable ROM (eprom), electrically erasable programmable ROM (eeprom), flash memory, polymer memory (such as ferroelectric polymer memory), ovonic memory, phase-change or ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, magnetic or optical cards, arrays of devices, such as Redundant Array of Independent Disks (RAID) drives, solid state memory devices (e.g., USB memory), or memory, Solid State Drives (SSDs) and any other type of storage medium suitable for storing information.

In some examples, communication interface 1160 may contain logic and/or features to support a communication interface. For these examples, communication interface 1160 may include one or more communication interfaces operating in accordance with various communication protocols or standards to communicate over direct or network communication links. Direct communication may occur through the use of communication protocols or standards described in one or more industry standards (including progeny and variants) such as the industry standard associated with the PCIe specification, NVMe specification, or I3C specification. Network communications may occur using a communication protocol or standard, such as those described in one or more ethernet standards promulgated by the Institute of Electrical and Electronics Engineers (IEEE). For example, one such ethernet standard promulgated by IEEE may include, but is not limited to, IEEE 802.3-2018, published 2018, "Carrier sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer specification" (Carrier sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications) (hereinafter "IEEE 802.3 specification"). Network communication may also occur in accordance with one or more OpenFlow specifications, such as the OpenFlow hardware abstraction API specification. Network communications may also occur according to one or more Infiniband architecture specifications.

The computing platform 1100 may be implemented in a server or client computing device. Accordingly, as suitably desired for a server or client computing device, the functions and/or specific configurations of computing platform 1100 described herein may be included or omitted in various embodiments of computing platform 1100.

The components and features of computing platform 1100 may be implemented using any combination of discrete circuitry, ASICs, logic gates and/or single chip architectures. Further, the features of computing platform 1100 may be implemented using microcontrollers, FPGAs, and/or microprocessors or any combination of the foregoing where suitably appropriate. Note that hardware, firmware, and/or software elements may be referred to herein, collectively or individually, as "logic" or "circuitry".

It should be appreciated that the exemplary computing platform 1100 shown in the block diagram of fig. 11 may represent one functionally described example of many potential implementations. Accordingly, division, omission or inclusion of block functions depicted in the accompanying figures does not imply that hardware components, circuits, software, and/or elements for implementing these functions will necessarily be divided, omitted, or included in the embodiments.

One or more aspects of at least one example may be implemented by representative instructions stored on at least one machine-readable medium which represent various logic within a processor, which when read by a machine, computing device, or system, causes the machine, computing device, or system to fabricate logic to perform the techniques described herein. Such a representation is referred to as an "IP core" and may be similar to an IP block. The IP cores may be stored on a tangible, machine-readable medium and supplied to various customers or manufacturing facilities to load into the manufacturing machines that actually make the logic or processor.

Various examples may be implemented using hardware elements, software elements, or a combination of both. In some examples, a hardware element may include a device, component, processor, microprocessor, circuit element (e.g., transistor, resistor, capacitor, inductor, etc.), integrated circuit, ASIC, PLD, DSP, FPGA, memory unit, logic gate, register, semiconductor device, chip, microchip, chipset, or the like. In some examples, a software element may include a software component, a program, an application, a computer program, an application program, a system program, a machine program, operating system software, middleware, firmware, a software module, a routine, a subroutine, a function, a method, a procedure, a software interface, an API, an instruction set, computing code, computer code, a code segment, a computer code segment, a word, a value, a symbol, or any combination thereof. Determining whether to implement examples using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, thermal tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints, as desired for a given implementation.

Some examples may include an article of manufacture or at least one computer readable medium. The computer readable medium may include a non-transitory storage medium to store logic. In some examples, a non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. In some examples, logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.

According to some examples, a computer-readable medium may include a non-transitory storage medium to store or retain instructions that, when executed by a machine, computing device, or system, cause the machine, computing device, or system to perform a method and/or operations in accordance with the described examples. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. The instructions may be implemented according to a predefined computer language, manner or syntax, for instructing a machine, computing device or system to perform a certain function. The instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language.

Some examples may be described using the expression "in one example" or "example" along with their derivatives. These terms are intended to encompass a particular feature, structure, or characteristic described in connection with the example in at least one example. The appearances of the phrase "in one example" in various places in the specification are not necessarily all referring to the same example.

Some examples may be described using the expression "coupled" and "connected" along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, descriptions using the terms "connected" and/or "coupled" may indicate that two or more elements are in direct physical or electrical contact with each other. The term "couple" or "and.. couple," however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

To the extent that various operations or functions are described herein, they can be described or defined as software code, instructions, configurations, and/or data. The content can be directly executable ("object" or "executable" form), source code, or difference code ("delta" or "patch" code). The software content of the embodiments described herein can be provided via an article of manufacture having the content stored thereon, or via a method of operating a communication interface to transmit data via the communication interface. A machine-readable storage medium can cause a machine to perform the functions or operations described, and includes any mechanism for storing information in a form accessible by a machine (e.g., a computing device, an electronic system, etc.), such as recordable/non-recordable media (e.g., Read Only Memory (ROM), Random Access Memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communication interface includes any mechanism that interfaces with any hardwired, wireless, optical, etc. medium to communicate with another device, such as a memory bus interface, a processor bus interface, an internet connection, a disk controller, etc. The communication interface can be configured by providing configuration parameters and/or sending signals to prepare the communication interface for providing data signals describing the software content. The communication interface can be accessed via one or more commands or signals sent to the communication interface.

The following examples pertain to additional examples of the technology disclosed herein.

Example 1 an example apparatus may include an interface to access a memory controller of a memory device via a plurality of channels; and circuitry of the memory controller. The circuit may set a first time value for a first stage of a 2-stage auto-close timer. The first level of the level 2 auto-close timer is to cause a bank of a storage array of a first memory device to auto-close after a first cache line access to the bank, the first cache line access responsive to a multi-channel address interleaving policy that causes consecutive cache line accesses to the storage array of the first memory device via a first channel of the plurality of channels. The circuit may also set a second time value for a second stage of the 2-stage auto-close timer. The second level of the level 2 auto-close timer is to cause the rank to auto-close after a second cache line access to the rank, the second cache line access responsive to the multi-channel address interleaving policy that causes non-sequential cache line accesses to the storage array of a first memory device via the first channel.

Example 2 the apparatus of example 1, the multi-lane address interleaving policy may be a 2-lane address interleaving policy, the 2-lane address interleaving policy including a first 4-way interleaving that maps physical memory addresses of the storage array of a first memory device to a first set of four cache lines of a string of cache lines to the first lane to cause the consecutive cache line accesses to the storage array of the first memory device.

Example 3 the apparatus of example 2, the circuitry to further monitor cache line accesses of the first set of four cache lines of the string of cache lines. The circuitry may also determine a moving average inter-arrival time of at least two consecutive cache line accesses of the first set of four cache lines. The circuitry may also adjust the first time value for the first level of the level 2 auto-close timer to increase a likelihood of a page hit for a subsequent cache line access to the storage array of a first memory device via the first channel.

Example 4 the apparatus of example 2, the circuitry to further monitor cache line accesses of the first set of four cache lines of the string of cache lines. The circuitry may also determine a moving average inter-arrival time of at least two consecutive cache line accesses of the first set of four cache lines. The circuitry may also adjust the first time value for the first level of the level 2 auto-close timer to reduce a likelihood of a page miss for a subsequent cache line access to the storage array of a first memory device via the first channel.

Example 5 the apparatus of example 2, the 2-way address interleaving policy further to include a second 4-way interleaving that maps physical memory addresses of a rank of a storage array of a second memory device to a next set of four cache lines of the string of cache lines to a second way of the plurality of ways. The 2-way address interleaving policy may also include a third 4-way interleaving that maps physical memory addresses of the rank of the storage array of the first memory device to a third set of four cache lines of the string of cache lines to the first way. For this example, causing the non-sequential cache line accesses to the storage array of the first memory device includes the 2-way address interleaving policy to cause a last cache line access to the first 4-way interleave and a first cache line access to the third 4-way interleave.

Example 6 the apparatus of example 5, the circuitry to further monitor access to the last cache line of the first 4-way interleave and access to the first cache line of the third 4-way interleave. The circuitry may also determine a moving average inter-arrival time between accesses to the last cache line and the first cache line. The circuitry may also adjust the second time value for the second level of the level 2 auto-close timer to increase a likelihood of a page hit for a subsequent cache line access to the storage array of a first memory device via the first channel when the subsequent cache line access is preceded by a cache line access to the storage array of a second memory device via the second channel.

Example 7 the apparatus of example 5, the circuitry to further monitor access to the last cache line of the first 4-way interleave and access to the first cache line of the third 4-way interleave. The circuitry may also determine a moving average inter-arrival time between accesses to the last cache line and accesses to the first cache line. The circuitry may also adjust the second time value for the second level of the level 2 auto-close timer to reduce a likelihood of a page miss for a subsequent cache line access to the storage array of the first memory device via the first channel when the subsequent cache line access is preceded by a cache line access to the storage array of a second memory device.

Example 8 the apparatus of example 5, the storage array of the first memory device to include a plurality of first memory dies disposed on a DIMM and the storage array of the second memory device to include a plurality of second memory dies disposed on a second DIMM.

Example 9 the apparatus of example 1, the first and second cache line accesses may access 64 bytes of data separately from the rank of the storage array of the first memory device.

Example 10 the apparatus of example 1, the storage array of the first memory device may be a plurality of memory dies disposed on a DIMM.

Example 11 the apparatus of example 1, the first memory device to include a dynamic random access memory.

Example 12 an example method may include setting a first time value for a first stage of a level 2 auto-close timer. The first level of the level 2 auto-close timer may cause a bank of a storage array of a first memory device to auto-close after a first cache line access to the bank, the first cache line access responsive to a multi-channel address interleaving policy that causes consecutive cache line accesses to the storage array of the first memory device via a first channel coupled with a processor. The method may also include setting a second time value for a second stage of the level 2 auto-close timer. The second level of the level 2 auto-close timer may cause the rank to auto-close after a second cache line access to the rank responsive to the multi-channel address interleaving policy that causes non-sequential cache line accesses to the storage array of a first memory device via the first channel.

Example 13 the method of example 12, the multi-lane address interleaving policy may be a 2-lane address interleaving policy, the 2-lane address interleaving policy including a first 4-way interleaving that maps physical memory addresses of the storage array of a first memory device to a first set of four cache lines of a string of cache lines to the first lane to cause the consecutive cache line accesses to the storage array of the first memory device.

Example 14 the method of example 13 may further include monitoring cache line accesses of the first set of four cache lines of the string of cache lines. The method may also include determining a moving average inter-arrival time of at least two consecutive cache line accesses of the first set of four cache lines. The method may also include adjusting the first time value for the first level of the level 2 auto-close timer to increase a likelihood of a page hit for a subsequent cache line access to the storage array of a first memory device via the first channel.

Example 15 the method of example 13 may further include monitoring cache line accesses of the first set of four cache lines of the string of cache lines. The method may also include determining a moving average inter-arrival time of at least two consecutive cache line accesses of the first set of four cache lines. The method may also include adjusting the first time value for the first level of the level 2 auto-close timer to reduce a likelihood of a page miss for a subsequent cache line access to the storage array of a first memory device via the first channel.

Example 16 the method of example 13, the 2-way address interleaving policy further comprising a second 4-way interleaving that maps physical memory addresses of a bank of a storage array of a second memory device to a next four cache lines of the string of cache lines to a second way coupled with the processor. The 2-way address interleaving policy also includes a third 4-way interleave that maps a physical memory address of the bank of the storage array of the first memory device to a third set of four cache lines of the string of cache lines to the first way. For this example, causing the non-sequential cache line accesses to the storage array of the first memory device includes the 2-way address interleaving policy to cause a last cache line access to the first 4-way interleave and a first cache line access to the third 4-way interleave.

Example 17 the method of example 16 may further include monitoring accesses to the last cache line of the first 4-way interleave and accesses to the first cache line of the third 4-way interleave. The method may also include determining a moving average inter-arrival time between accesses to the last cache line and the first cache line. The method may also include adjusting the second time value for the second level of the level 2 auto-close timer to increase a likelihood of a page hit for a subsequent cache line access to the storage array of a first memory device via the first channel when the subsequent cache line access is preceded by a cache line access to the storage array of a second memory device via the second channel.

Example 18 the method of example 17 may further include monitoring accesses to the last cache line of the first 4-way interleave and accesses to the first cache line of the third 4-way interleave. The method may also include determining a moving average inter-arrival time between accesses to the last cache line and accesses to the first cache line. The method may also include adjusting the second time value for the second level of the level 2 auto-close timer to reduce a likelihood of a page miss for a subsequent cache line access to the storage array of the first memory device via the first channel when the subsequent cache line access is preceded by a cache line access to the storage array of a second memory device.

Example 19 the method of example 16, the storage array of the first memory device may include a plurality of first memory dies disposed on a first DIMM and the storage array of the second memory device includes a plurality of second memory dies disposed on a second DIMM.

Example 20 the method of example 12, the first and second cache line accesses may access 64 bytes of data separately from the rank of the storage array of the first memory device.

Example 21 the method of example 12, the storage array of the first memory device may be a plurality of memory dies disposed on a DIMM.

Example 22 the method of example 12, the first memory device may include a dynamic random access memory.

Example 23, one example, at least one machine readable medium comprising a plurality of instructions that in response to being executed by a system, may cause the system to carry out a method according to any one of examples 12-22.

Example 24. an example apparatus may include means for performing the method of any of examples 12-22.

Example 25, one example, the at least one machine readable medium may contain a plurality of instructions that in response to being executed by the system may cause the system to set a first time value for a first stage of a level 2 auto-off timer. The first level of the level 2 auto-close timer may cause a bank of a storage array of a first memory device to auto-close after a first cache line access to the bank, the first cache line access responsive to a multi-channel address interleaving policy that causes consecutive cache line accesses to the storage array of the first memory device via a first channel coupled with a processor. The instructions may also cause the system to set a second time value for a second stage of the level 2 auto-close timer. The second level of the level 2 auto-close timer may cause the rank to auto-close after a second cache line access to the rank responsive to the multi-channel address interleaving policy that causes non-sequential cache line accesses to the storage array of a first memory device via the first channel.

Example 26 the at least one machine readable medium of example 25, the multi-channel address interleaving policy may be a 2-channel address interleaving policy, the 2-channel address interleaving policy to include a first 4-way interleaving that maps physical memory addresses of the storage array of the first memory device to a first set of four cache lines of a series of cache lines to the first channel to cause the consecutive cache line accesses to the storage array of the first memory device.

Example 27 the at least one machine readable medium of example 26, the instructions to further cause the system to monitor cache line accesses of the first set of four cache lines of the string of cache lines. The instructions may also cause the system to determine a moving average inter-arrival time for at least two consecutive cache line accesses of the first set of four cache lines. The instructions may also cause the system to adjust the first time value for the first level of the level 2 auto-close timer to increase a likelihood of a page hit for a subsequent cache line access to the storage array of a first memory device via the first channel.

Example 28 the at least one machine readable medium of example 26, the instructions to further cause the system to monitor cache line accesses of the first set of four cache lines of the string of cache lines. The instructions may also cause the system to determine a moving average inter-arrival time for at least two consecutive cache line accesses of the first set of four cache lines. The instructions may also cause the system to adjust the first time value for the first level of the level 2 auto-close timer to reduce a likelihood of a page miss for a subsequent cache line access to the storage array of a first memory device via the first channel.

Example 29 the at least one machine readable medium of example 26, the 2-way address interleaving policy to further include a second 4-way interleaving that maps physical memory addresses of a bank of a storage array of a second memory device to a next set of four cache lines of the string of cache lines to a second way coupled with the processor. The 2-way address interleaving policy may also include a third 4-way interleaving that maps physical memory addresses of the rank of the storage array of the first memory device to a third set of four cache lines of the string of cache lines to the first way. For this example, causing the non-sequential cache line accesses to the storage array of the first memory device may include the 2-way address interleaving policy to cause a last cache line access to the first 4-way interleave and a first cache line access to the third 4-way interleave.

Example 30 the at least one machine readable medium of example 29, the instructions to further cause the system to monitor accesses to the last cache line of the first 4-way interleave and accesses to the first cache line of the third 4-way interleave. The instructions may also cause the system to determine a moving average inter-arrival time between accesses made to the last cache line and the first cache line. The instructions may also cause the system to adjust the second time value for the second level of the level 2 auto-close timer to increase a likelihood of a page hit for a subsequent cache line access to the storage array of a first memory device via the first channel when the subsequent cache line access is preceded by a cache line access to the storage array of a second memory device via the second channel.

Example 31 the at least one machine readable medium of example 30, the instructions to further cause the system to monitor accesses to the last cache line of the first 4-way interleave and accesses to the first cache line of the third 4-way interleave. The instructions may also cause the system to determine a moving average inter-arrival time between accesses to the last cache line and accesses to the first cache line. The instructions may also cause the system to adjust the second time value for the second level of the level 2 auto-close timer to reduce a likelihood of a page miss for a subsequent cache line access to the storage array of the first memory device via the first channel when the subsequent cache line access is preceded by a cache line access to the storage array of a second memory device.

Example 32 the at least one machine readable medium of example 29, the storage array of the first memory device to include a plurality of first memory dies disposed on a first DIMM and the storage array of the second memory device to include a plurality of second memory dies disposed on a second DIMM.

Example 33 the at least one machine readable medium of example 25, the first and second cache line accesses may access 64 bytes of data separately from the rank of the storage array of the first memory device.

Example 34 the at least one machine readable medium of example 25, the storage array of the first memory device may be a plurality of memory dies disposed on a DIMM.

Example 35 the at least one machine readable medium of example 25, the first memory device may include dynamic random access memory.

It is emphasized that the abstract of the present disclosure is provided to comply with 37 c.f.r. section 1.72 (b), which requires an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Additionally, in the foregoing detailed description, it can be seen that various features are grouped together in a single example for the purpose of streamlining the disclosure. The disclosed method is not to be understood as reflecting the intent: the claimed examples require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed example. Thus, the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate example. In the appended claims, the terms "comprising" and "in which" are used as the plain-english equivalents of the respective terms "comprising" and "wherein," respectively. In addition, the terms "first," "second," "third," and the like are merely labeled and are not intended to impose numerical requirements on their objects.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

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Techniques for setting a level 2 auto-close timer to access a memory device

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