阅读说明：本技术 失真补偿设备、无线通信器、预失真器、失真补偿方法和计算机程序 (Distortion compensation apparatus, wireless communicator, predistorter, distortion compensation method, and computer program ) 是由 持田英史 于 2019-07-18 设计创作，主要内容包括：根据本发明的失真补偿电路包括：第一失真补偿电路,其具有用于补偿在放大器的输出中产生的第一失真的第一失真补偿特性,并且补偿所述第一失真；第二失真补偿电路,其具有用于补偿在所述放大器的输出中产生的第二失真的第二失真补偿特性,并且补偿所述第二失真；以及更新单元,其更新所述第二失真补偿特性。所述第一失真包括非线性失真和存储效果失真,并且所述第二失真是比第一失真具有更短时间变化的失真。更新单元以比所述第一失真补偿特性的更新频率高的频率来更新所述第二失真补偿特性。(The distortion compensation circuit according to the present invention includes: a first distortion compensation circuit having a first distortion compensation characteristic for compensating for a first distortion generated in an output of the amplifier and compensating for the first distortion; a second distortion compensation circuit having a second distortion compensation characteristic for compensating for a second distortion generated in an output of the amplifier and compensating for the second distortion; and an updating unit that updates the second distortion compensation characteristic. The first distortion includes nonlinear distortion and memory effect distortion, and the second distortion is distortion having a shorter time variation than the first distortion. The updating unit updates the second distortion compensation characteristic at a frequency higher than an update frequency of the first distortion compensation characteristic.)

1. A distortion compensation apparatus comprising:

a first distortion compensation circuit having a first distortion compensation characteristic for compensating for a first distortion generated in an output of an amplifier, the first distortion compensation circuit being configured to compensate for the first distortion;

a second distortion compensation circuit having a second distortion compensation characteristic for compensating for a second distortion generated in the output of the amplifier, the second distortion compensation circuit being configured to compensate for the second distortion; and

an updating unit configured to update the second distortion compensation characteristic, wherein,

the first distortion comprises a non-linear distortion and a memory effect distortion,

the second distortion is a distortion whose temporal change is faster than the first distortion, an

The update unit updates the second distortion compensation characteristic at a frequency higher than an update frequency of the first distortion compensation characteristic.

2. The distortion compensation apparatus of claim 1, wherein,

the second distortion comprises at least one of the nonlinear distortion and the storage effect distortion.

3. The distortion compensation apparatus of claim 1 or 2,

the first distortion compensation characteristic is specified by a first characteristic formula of a predetermined order, an

The second distortion compensation characteristic is specified by a second characteristic formula having a lower order than the first characteristic formula.

4. The distortion compensation apparatus according to any one of claims 1 to 3,

the first distortion compensation circuit outputs an output signal having a first frequency bandwidth, an

The second distortion compensation circuit outputs an output signal having a second frequency bandwidth narrower than the first frequency bandwidth.

5. The distortion compensation apparatus according to any one of claims 1 to 4,

the updating unit includes a first updating unit configured to update the first distortion compensation characteristic; and a second updating unit configured to update the second distortion compensation characteristic;

the first updating unit updates the first distortion compensation characteristic based on a first monitor signal obtained from an output signal of the amplifier,

the second updating unit updates the first distortion compensation characteristic based on a second monitor signal obtained from the output signal of the amplifier, an

The frequency bandwidth of the second monitoring signal is narrower than the frequency bandwidth of the first monitoring signal.

6. A wireless communicator, comprising:

an amplifier configured to amplify a signal having a radio frequency;

a first distortion compensation circuit having a first distortion compensation characteristic for compensating for a first distortion generated in an output of the amplifier, the first distortion compensation circuit being configured to compensate for the first distortion;

a second distortion compensation circuit having a second distortion compensation characteristic for compensating for a second distortion generated in the output of the amplifier, the second distortion compensation circuit being configured to compensate for the second distortion; and

an updating unit configured to update the second distortion compensation characteristic, wherein,

the first distortion comprises a non-linear distortion and a memory effect distortion,

the second distortion is a distortion whose temporal change is faster than the first distortion, an

The update unit updates the second distortion compensation characteristic at a frequency higher than an update frequency of the first distortion compensation characteristic.

7. The wireless communicator of claim 6, further comprising:

a first filter configured to convert a monitor signal obtained from an output signal of the amplifier into a first monitor signal; and

a second filter configured to convert the monitoring signal into a second monitoring signal having a narrower frequency bandwidth than a frequency bandwidth of the first monitoring signal, wherein,

the update unit includes:

a first updating unit configured to update the first distortion compensation characteristic based on the first monitoring signal output from the first filter, an

A second updating unit configured to update the second distortion compensation characteristic based on the second monitoring signal output from the second filter.

8. A predistorter connected to an external distortion compensation circuit configured to compensate for a first distortion produced in an output of an amplifier, the predistorter comprising:

a distortion compensation circuit having a distortion compensation characteristic for compensating for a second distortion different from the first distortion among distortions generated in the output of the amplifier; and

an updating unit configured to update the distortion compensation characteristic, wherein,

the first distortion comprises a non-linear distortion and a memory effect distortion,

the second distortion is a distortion whose temporal change is faster than the first distortion, an

The updating unit updates the distortion compensation characteristic at a frequency higher than an update frequency of the external distortion compensation circuit.

9. A distortion compensation method comprising the steps of:

performing a first distortion compensation process of compensating for a first distortion generated in an output of an amplifier;

performing a second distortion compensation process that compensates for a second distortion generated in the output of the amplifier; and

performing an update process at a predetermined frequency, the update process updating a second distortion compensation characteristic for compensating for the second distortion in the second distortion compensation process, wherein,

the first distortion comprises a non-linear distortion and a memory effect distortion,

the second distortion is a distortion whose temporal change is faster than the first distortion, an

The predetermined frequency is a frequency higher than an update frequency of a first distortion compensation characteristic for compensating for the first distortion in the first distortion compensation process.

10. A distortion compensation method to be performed by a predistorter connected to an external predistorter configured to compensate for a first distortion generated in an output of an amplifier, the distortion compensation method comprising the steps of:

compensating for a second distortion different from the first distortion among distortions generated in the output of the amplifier; and

performing an update process at a predetermined frequency, the update process updating a second distortion compensation characteristic for compensating for the second distortion, wherein,

the first distortion comprises a non-linear distortion and a memory effect distortion,

the second distortion is a distortion whose temporal change is faster than the first distortion, an

The predetermined frequency is a frequency higher than an update frequency of a first distortion compensation characteristic for compensating the first distortion.

11. A computer program for setting a first distortion compensation circuit having a first distortion compensation characteristic for compensating a first distortion generated in an output of an amplifier, the first distortion compensation circuit being configured to compensate the first distortion, and a second distortion compensation circuit having a second distortion compensation characteristic for compensating a second distortion generated in the output of the amplifier, the second distortion compensation circuit being configured to compensate the second distortion;

the computer program causes a computer to execute the following steps at a predetermined frequency:

calculating parameters for setting the second distortion compensation characteristic; and

setting the calculated parameters to the second distortion compensation circuit, wherein,

the first distortion comprises a non-linear distortion and a memory effect distortion,

the second distortion is a distortion whose temporal change is faster than the first distortion, an

The predetermined frequency is a frequency higher than an update frequency of the first distortion compensation characteristic.

12. A computer program for setting a second distortion compensation circuit connected to a first distortion compensation circuit configured to compensate for a first distortion generated in an output of an amplifier, the computer program causing a computer to execute the following steps at a predetermined frequency:

calculating a parameter for setting a distortion compensation characteristic of the second distortion compensation circuit; and

setting the calculated parameters to the second distortion compensation circuit, wherein,

the first distortion comprises a non-linear distortion and a memory effect distortion,

the second distortion compensation circuit is a circuit configured to compensate for a second distortion,

the second distortion is a distortion whose temporal change is faster than the first distortion, an

The predetermined frequency is a frequency higher than an update frequency of the distortion compensation characteristic of the first distortion compensation circuit.

Technical Field

The invention relates to a distortion compensation apparatus, a wireless communicator, a predistorter, a distortion compensation method and a computer program. The present application claims priority from japanese patent application No.2018-160463, filed on 29.8.2018, the entire contents of which are incorporated herein by reference.

Background

The amplifier has a non-linear characteristic. Distortion compensation techniques are used to compensate for signal distortion caused by non-linear characteristics. An example of a distortion compensation technique is disclosed in patent document 1.

Reference list

[ patent document ]

Patent document 1: japanese laid-open patent publication No.2014-204148

Disclosure of Invention

A distortion compensation apparatus of a mode according to the present disclosure includes: a first distortion compensation circuit having a first distortion compensation characteristic for compensating for a first distortion generated in an output of an amplifier, the first distortion compensation circuit being configured to compensate for the first distortion; a second distortion compensation circuit having a second distortion compensation characteristic for compensating for a second distortion generated in an output of the amplifier, the second distortion compensation circuit being configured to compensate for the second distortion; and an updating unit configured to update the second distortion compensation characteristic. The first distortion includes nonlinear distortion and memory effect distortion, the second distortion is distortion whose temporal change is faster than the first distortion, and the update unit updates the second distortion compensation characteristic at a frequency higher than an update frequency of the first distortion compensation characteristic.

A wireless communicator according to one mode of the present disclosure includes: an amplifier configured to amplify a signal having a radio frequency; a first distortion compensation circuit having a first distortion compensation characteristic for compensating for a first distortion generated in an output of the amplifier, the first distortion compensation circuit being configured to compensate for the first distortion; a second distortion compensation circuit having a second distortion compensation characteristic for compensating for a second distortion generated in an output of the amplifier, the second distortion compensation circuit being configured to compensate for the second distortion; and an updating unit configured to update the second distortion compensation characteristic. The first distortion includes nonlinear distortion and memory effect distortion, the second distortion is distortion whose temporal change is faster than the first distortion, and the update unit updates the second distortion compensation characteristic at a frequency higher than an update frequency of the first distortion compensation characteristic.

A predistorter of one mode according to the present disclosure is connected to an external distortion compensation circuit configured to compensate for a first distortion generated in an output of an amplifier. The predistorter includes a distortion compensation circuit having a distortion compensation characteristic for compensating for a second distortion different from the first distortion among distortions generated in an output of the amplifier; and an updating unit configured to update the distortion compensation characteristic. The first distortion includes nonlinear distortion and memory effect distortion, the second distortion is distortion whose temporal change is faster than the first distortion, and the updating unit updates the distortion compensation characteristic at a frequency higher than an update frequency of the external distortion compensation circuit.

A distortion compensation method of a pattern according to the present disclosure includes the steps of: performing a first distortion compensation process of compensating for a first distortion generated in an output of an amplifier; performing a second distortion compensation process of compensating for a second distortion generated in an output of the amplifier; and performing an update process at a predetermined frequency, the update process updating a second distortion compensation characteristic for compensating for the second distortion in the second distortion compensation process. The first distortion includes a nonlinear distortion and a memory effect distortion, the second distortion is a distortion whose temporal change is faster than the first distortion, and the predetermined frequency is a frequency higher than an update frequency of a first distortion compensation characteristic for compensating the first distortion at the first distortion compensation process.

A distortion compensation method according to another mode of the present disclosure is to be performed by a predistorter connected to an external predistorter configured to compensate for a first distortion generated in an output of an amplifier. The distortion compensation method includes the steps of: compensating for a second distortion different from the first distortion among the distortions generated in the output of the amplifier; and performing an update process at a predetermined frequency, the update process updating a second distortion compensation characteristic for compensating for the second distortion. The first distortion includes a nonlinear distortion and a memory effect distortion, the second distortion is a distortion whose temporal change is faster than the first distortion, and the predetermined frequency is a frequency higher than an update frequency of a first distortion compensation characteristic for compensating the first distortion.

A computer program according to one mode of the present disclosure is for setting a first distortion compensation circuit having a first distortion compensation characteristic for compensating for a first distortion generated in an output of an amplifier, the first distortion compensation circuit being configured to compensate for the first distortion, and a second distortion compensation circuit having a second distortion compensation characteristic for compensating for a second distortion generated in the output of the amplifier, the second distortion compensation circuit being configured to compensate for the second distortion. The computer program causes a computer to execute the following steps at a predetermined frequency: calculating parameters for setting the second distortion compensation characteristic; and setting the calculated parameter to the second distortion compensation circuit. The first distortion includes a nonlinear distortion and a memory effect distortion, the second distortion is a distortion whose temporal change is faster than the first distortion, and the predetermined frequency is a frequency higher than an update frequency of the first distortion compensation characteristic.

A computer program according to another mode of the present disclosure is for setting a second distortion compensation circuit connected to a first distortion compensation circuit configured to compensate for a first distortion generated in an output of an amplifier. The computer program causes a computer to execute the following steps at a predetermined frequency: calculating a parameter for setting a distortion compensation characteristic of the second distortion compensation circuit; and setting the calculated parameter to the second distortion compensation circuit. The first distortion includes nonlinear distortion and memory effect distortion, the second distortion compensation circuit is a circuit configured to compensate for second distortion that is distortion whose temporal change is faster than the first distortion, and the predetermined frequency is a frequency higher than an update frequency of a distortion compensation characteristic of the first distortion compensation circuit.

Drawings

Fig. 1 is a block diagram of a wireless communicator including a distortion compensation apparatus according to an embodiment.

Fig. 2 is a block diagram of a distortion compensation apparatus according to an embodiment.

Fig. 3 is a functional block diagram of a distortion compensation apparatus according to an embodiment.

Fig. 4 is a flowchart illustrating an example of a process of operations performed by the first predistorter according to an embodiment.

Fig. 5 is a flowchart showing an example of the first update process.

Fig. 6 is a flowchart illustrating an example of a process of operations performed by the second predistorter according to an embodiment.

Fig. 7 is a flowchart showing an example of the second update process.

Fig. 8 is a block diagram of an improved distortion compensation apparatus according to an embodiment.

Fig. 9 is a block diagram of an improved distortion compensation apparatus according to an embodiment.

Fig. 10 is a block diagram of an improved distortion compensation apparatus according to an embodiment.

Fig. 11 is a block diagram of an improved wireless communicator according to an embodiment.

Fig. 12 is a block diagram of an improved wireless communicator according to an embodiment.

Fig. 13 is a block diagram of an improved wireless communicator according to an embodiment.

Fig. 14 is a block diagram of an improved wireless communicator according to an embodiment.

Fig. 15 is a block diagram of a wireless communicator including an improved distortion compensation apparatus according to an embodiment.

Fig. 16 is a block diagram of an improved distortion compensation apparatus according to an embodiment.

Fig. 17 is a flowchart illustrating a procedure of an operation performed by the improved distortion compensating apparatus according to the embodiment.

Fig. 18 is a block diagram of an improved distortion compensation apparatus according to an embodiment.

Detailed Description

< problems to be solved by the present disclosure >

For example, a transient distortion change may occur in a compound semiconductor amplifier (GaN amplifier) formed of gallium nitride. In GaN amplifiers, there is a transient response known as Idq drift. Idq-drift is the transient response of the drain current becoming below a set value when the amplifier transitions from a high power state to a power-down state. In the GaN amplifier, distortion instantaneously varies in response to signal power fluctuation due to Idq drift. In particular, signal power fluctuation is likely to occur in a communication system in which transmission and reception are alternately performed, such as Time Division Duplex (TDD), for example.

For example, changes in distortion in an amplifier are sometimes handled by updating distortion compensation coefficients used in a distortion compensation apparatus in response to changes in distortion. By updating the distortion compensation coefficient, the distortion compensation characteristic of the distortion compensation apparatus is updated in response to a change in distortion.

In order to track the instantaneous change in distortion caused by Idq drift or the like, it is considered that the update of the distortion compensation characteristic is frequently performed. However, since the processing load for updating the distortion compensation characteristics is large, it is not always easy to frequently perform updating of the distortion compensation characteristics in preparation for a change in distortion.

< effects of the present disclosure >

According to the present disclosure, variations in distortion may be handled.

< overview of embodiments of the present disclosure >

Hereinafter, an overview of embodiments of the present disclosure is listed and described.

(1) The distortion compensation apparatus according to the present embodiment includes: a first distortion compensation circuit having a first distortion compensation characteristic for compensating for a first distortion generated in an output of an amplifier, the first distortion compensation circuit being configured to compensate for the first distortion; a second distortion compensation circuit having a second distortion compensation characteristic for compensating for a second distortion generated in an output of the amplifier, the second distortion compensation circuit being configured to compensate for the second distortion; and an updating unit configured to update the second distortion compensation characteristic. The first distortion includes nonlinear distortion and memory effect distortion, the second distortion is distortion whose temporal change is faster than the first distortion, and the update unit updates the second distortion compensation characteristic at a frequency higher than an update frequency of the first distortion compensation characteristic. Thus, the temporal variation of the second distortion can be handled. In addition, both of the non-linear distortion and the memory effect distortion included in the first distortion may be processed. Therefore, distortion compensation with high accuracy can be achieved. "nonlinear distortion" refers to a phenomenon in which an output signal having a waveform similar to that of an input signal cannot be obtained due to the nonlinear input/output characteristics of an amplifier. "memory effect distortion" refers to a phenomenon of obtaining an output signal having a waveform that depends not only on the current input signal but also on the history of past input signals. Further, "the second distortion compensation characteristic is updated at a frequency higher than the update frequency of the first distortion compensation characteristic" includes not only the case where the first distortion compensation characteristic is updated at a specific frequency but also the case where the first distortion compensation characteristic is not updated. That is, when the first distortion compensation characteristic is not updated, updating the second distortion compensation characteristic at an arbitrary frequency corresponds to "updating the second distortion compensation characteristic at a higher frequency than the first distortion compensation characteristic".

(2) In the distortion compensating apparatus according to the present embodiment, the second distortion may include at least one of the nonlinear distortion and the memory effect distortion. Therefore, also in the second distortion compensation circuit, the nonlinear distortion and the memory effect distortion can be simultaneously handled, and the distortion compensation of higher accuracy can be realized.

(3) In the distortion compensation apparatus according to the present embodiment, the first distortion compensation characteristic may be specified by a first characteristic formula of a predetermined order, and the second distortion compensation characteristic may be specified by a second characteristic formula of a lower order than the first characteristic formula. Therefore, even when the update of the second distortion compensation characteristic is performed at a high frequency, the processing load can be suppressed.

(4) In the distortion compensation apparatus according to the present embodiment, the first distortion compensation circuit may output an output signal having a first frequency bandwidth, and the second distortion compensation circuit may output an output signal having a second frequency bandwidth narrower than the first frequency bandwidth. The processing load is increased according to the increase of the frequency bandwidth of the output signal. Therefore, when the second frequency bandwidth is set to be narrow, even when the update of the second distortion compensation characteristic is performed at a high frequency, the processing load can be suppressed.

(5) In the distortion compensation apparatus according to the present embodiment, the updating unit may include a first updating unit configured to update the first distortion compensation characteristic; and a second updating unit configured to update the second distortion compensation characteristic. The first updating unit may update the first distortion compensation characteristic based on a first monitor signal obtained from an output signal of the amplifier, the second updating unit may update the first distortion compensation characteristic based on a second monitor signal obtained from the output signal of the amplifier, and a frequency bandwidth of the second monitor signal may be narrower than a frequency bandwidth of the first monitor signal. Therefore, the second distortion compensation characteristic can be appropriately updated by using the second monitor signal for which the frequency band that is not used in the distortion compensation of the second distortion compensation circuit is cancelled.

(6) The wireless communicator according to the present embodiment includes: an amplifier configured to amplify a signal having a radio frequency; a first distortion compensation circuit having a first distortion compensation characteristic for compensating for a first distortion generated in an output of the amplifier, the first distortion compensation circuit being configured to compensate for the first distortion; a second distortion compensation circuit having a second distortion compensation characteristic for compensating for a second distortion generated in an output of the amplifier, the second distortion compensation circuit being configured to compensate for the second distortion; and an updating unit configured to update the second distortion compensation characteristic. The first distortion includes nonlinear distortion and memory effect distortion, the second distortion is distortion whose temporal change is faster than the first distortion, and the update unit updates the second distortion compensation characteristic at a frequency higher than an update frequency of the first distortion compensation characteristic. Thus, the temporal variation of the second distortion can be handled. In addition, both the non-linear distortion and the memory effect distortion included in the first distortion may be processed. Therefore, distortion compensation with high accuracy can be achieved.

The wireless communicator according to the present embodiment may further include: a first filter configured to convert a monitor signal obtained from an output signal of the amplifier into a first monitor signal; and a second filter configured to convert the monitoring signal into a second monitoring signal having a narrower frequency bandwidth than that of the first monitoring signal. The updating unit may include a first updating unit configured to update the first distortion compensation characteristic based on the first monitor signal output from the first filter, and a second updating unit configured to update the second distortion compensation characteristic based on the second monitor signal output from the second filter. Therefore, the second distortion compensation characteristic can be appropriately updated by using the second monitor signal for which the frequency band that is not used in the distortion compensation of the second distortion compensation circuit is cancelled.

(8) The predistorter according to the present embodiment is connected to an external distortion compensation circuit configured to compensate for a first distortion generated in an output of an amplifier. The predistorter comprises: a distortion compensation circuit having a distortion compensation characteristic for compensating for a second distortion different from the first distortion among distortions generated in an output of the amplifier; and an updating unit configured to update the distortion compensation characteristic. The first distortion includes nonlinear distortion and memory effect distortion, the second distortion is distortion whose temporal change is faster than the first distortion, and the updating unit updates the distortion compensation characteristic at a frequency higher than an update frequency of the external distortion compensation circuit. Thus, the temporal variation of the second distortion can be handled. In addition, both the non-linear distortion and the memory effect distortion included in the first distortion may be processed. Therefore, distortion compensation with high accuracy can be achieved.

(9) The distortion compensation method according to the present embodiment includes the steps of: performing a first distortion compensation process of compensating for a first distortion generated in an output of an amplifier; performing a second distortion compensation process of compensating for a second distortion generated in an output of the amplifier; and performing an update process at a predetermined frequency, the update process updating a second distortion compensation characteristic for compensating for the second distortion in the second distortion compensation process. The first distortion includes a nonlinear distortion and a memory effect distortion, the second distortion is a distortion whose temporal change is faster than the first distortion, and the predetermined frequency is a frequency higher than an update frequency of a first distortion compensation characteristic for compensating the first distortion in the first distortion compensation process. Thus, the temporal variation of the second distortion can be handled. In addition, both the non-linear distortion and the memory effect distortion included in the first distortion may be processed. Therefore, distortion compensation with high accuracy can be achieved.

(10) The distortion compensation method according to the present embodiment is to be performed by a predistorter connected to an external predistorter configured to compensate for a first distortion generated in an output of an amplifier. The distortion compensation method includes the steps of: compensating for a second distortion different from the first distortion among the distortions generated in the output of the amplifier; and performing an update process at a predetermined frequency, the update process updating a second distortion compensation characteristic for compensating for the second distortion. The first distortion includes a nonlinear distortion and a memory effect distortion, the second distortion is a distortion whose temporal change is faster than the first distortion, and the predetermined frequency is a frequency higher than an update frequency of a first distortion compensation characteristic for compensating the first distortion. Thus, the temporal variation of the second distortion can be handled. In addition, both the non-linear distortion and the memory effect distortion included in the first distortion may be processed. Therefore, distortion compensation with high accuracy can be achieved.

A computer program according to the present embodiment is for providing a first distortion compensation circuit having a first distortion compensation characteristic for compensating for a first distortion generated in an output of an amplifier, the first distortion compensation circuit being configured to compensate for the first distortion, and a second distortion compensation circuit having a second distortion compensation characteristic for compensating for a second distortion generated in the output of the amplifier, the second distortion compensation circuit being configured to compensate for the second distortion. The computer program causes a computer to execute the following steps at a predetermined frequency: calculating parameters for setting the second distortion compensation characteristic; and setting the calculated parameter to the second distortion compensation circuit. The first distortion includes a nonlinear distortion and a memory effect distortion, the second distortion is a distortion whose temporal change is faster than the first distortion, and the predetermined frequency is a frequency higher than an update frequency of the first distortion compensation characteristic. Thus, the temporal variation of the second distortion can be handled. In addition, both the non-linear distortion and the memory effect distortion included in the first distortion may be processed. Therefore, distortion compensation with high accuracy can be achieved.

(12) A computer program according to the present embodiment is for providing a second distortion compensation circuit connected to a first distortion compensation circuit configured to compensate for a first distortion generated in an output of an amplifier, the computer program causing a computer to execute the following steps at a predetermined frequency: calculating a parameter for setting a distortion compensation characteristic of the second distortion compensation circuit; and setting the calculated parameter to the second distortion compensation circuit. The first distortion includes nonlinear distortion and memory effect distortion, the second distortion compensation circuit is a circuit configured to compensate for second distortion that is distortion whose temporal change is faster than the first distortion, and the predetermined frequency is a frequency higher than an update frequency of a distortion compensation characteristic of the first distortion compensation circuit. Thus, the temporal variation of the second distortion can be handled. In addition, both the non-linear distortion and the memory effect distortion included in the first distortion may be processed. Therefore, distortion compensation with high accuracy can be achieved.

< details of embodiments of the present disclosure >

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. At least a portion of the embodiments described below may be combined as desired.

[1. configuration of distortion compensating apparatus ]

Fig. 1 shows a wireless communicator 100 including a distortion compensation apparatus 20. The wireless communicator 100 is, for example, a base station or a mobile station for mobile communication. The distortion compensation apparatus 20 performs predistortion compensation on a baseband signal x [ n ] output from a baseband processing unit (not shown), and outputs a distortion compensation signal y [ n ]'. The distortion compensation signal y n' is converted into an analog signal by a digital-to-analog converter (DAC)30 and converted into a radio frequency signal by an up-converter 40. The signal output from the up-converter 40 is amplified by a Power Amplifier (PA) 50. The signal output from the amplifier 50 is transmitted through the antenna 60.

The power amplifier 50 is, for example, a compound semiconductor amplifier (hereinafter, referred to as "GaN amplifier") formed of gallium nitride. In GaN amplifiers, Idq drift causes transient distortion variations in the amplifier 50. The power amplifier 50 is not limited to a GaN amplifier, and may be any amplifier in which Idq drift or high-speed drift occurs. Idq drift may occur in a High Electron Mobility Transistor (HEMT) device formed of compound semiconductors using not only GaN but also AlN (aluminum nitride), InN (indium nitride) and AlGaN, InAIN and InGaN based on these crystal systems. Further, high-speed drift occurs in a compound semiconductor amplifier formed of GaAs, InAs, InP, or the like. That is, the above drift is observed in an amplifier which is a HEMT device formed of a group III-V or its crystal system compound semiconductor.

Communicator 100 includes a coupler 36 for monitoring the output of amplifier 50. Coupler 36 outputs a monitoring number z n]. Monitoring signal z [ n ]]Down converted by a down converter 70 and converted to a digital signal by an analog-to-digital converter (ADC) 80. Assume that ADC 80 has a sampling frequency f_s. Monitoring signal z [ n ]]At a sampling frequency f_sIs sampled as discrete sample data.

The sampled data z n is provided to the distortion compensation device 20. The distortion compensation apparatus 20 updates the distortion compensation characteristic based on the sample data z [ n ].

The distortion compensation apparatus 20 shown in fig. 1 includes a plurality of predistorters a and B. The plurality of predistorters each perform predistortion. In fig. 1, predistorter a and predistorter B are cascaded with each other. Although in fig. 1 the distortion compensation apparatus 20 comprises two predistorters a and B, the distortion compensation apparatus 20 may comprise three or more predistorters.

The predistorter a is used to compensate for distortion that does not change over time or whose time change is gradual in the distortion in the amplifier 50. The distortion whose temporal change is gentle is, for example, a change portion of the distortion due to a temperature change.

For distortion compensation, predistorter B complements predistorter a. That is, the predistorter B is used to compensate for distortion components that cannot be compensated by the predistorter a. The predistorter B according to the embodiment compensates for distortions whose time variation is fast than the time variation of the distortion to be compensated by the predistorter a. For example, the distortion whose time variation is fast is, for example, distortion that instantaneously varies due to Idq drift.

In order to compensate for distortion that does not vary with time or whose temporal variation is gradual, the predistorter a does not update the distortion compensation characteristic or updates the distortion compensation characteristic at a low frequency. On the other hand, in order to deal with distortion whose temporal change is fast, the predistorter B updates the distortion compensation characteristic at a high frequency. Hereinafter, the distortion compensated by the predistorter a is also referred to as "first nonlinear distortion", and the distortion to be compensated by the predistorter B is also referred to as "second nonlinear distortion".

Fig. 2 shows an example of predistorter a and an example of predistorter B. In fig. 2, the predistorter 21A is an example of the predistorter a shown in fig. 1. In fig. 2, the predistorter 21B is an example of the predistorter B shown in fig. 1.

The predistorter 21A is configured to perform Digital Predistortion (DPD). The predistorter 21A includes a first distortion compensation circuit 210. The first distortion compensation circuit 210 performs predistortion on a baseband signal (signal y [ n ] output from the predistorter 21B). The first distortion compensation circuit 210 is implemented, for example, as a wired logic circuit such as a Field Programmable Gate Array (FPGA). Distortion compensation is performed based on the first distortion compensation coefficient 215 a. The first distortion compensation coefficient 215a is a parameter that determines the distortion compensation characteristic of the predistorter 21A. The wired logic circuits may be reconfigurable logic circuits, such as FPGAs, or may be non-reconfigurable logic circuits.

The distortion compensation characteristic (hereinafter, referred to as "first distortion compensation characteristic") of the first distortion compensation circuit 210 is specified by a model (hereinafter, referred to as "first distortion compensation characteristic model") represented by, for example, the following formula (1) (hereinafter, also referred to as "first characteristic formula").

[ mathematical formula 1]

Where y denotes an input signal of the first distortion compensating circuit 210, y' denotes an output signal of the first distortion compensating circuit 210, k1 denotes an index related to a compensation function for nonlinear distortion, and m1 denotesIndexes related to a compensation function for storing effect distortion, K1 and M1 represent constants, n represents discrete time, and h_k1,m1Denotes a coefficient (hereinafter, referred to as "first distortion compensation coefficient"). That is, the first distortion compensation circuit 210 having the first distortion compensation characteristic has a function of compensating each of the nonlinear distortion and the memory effect distortion. By specifying a first distortion compensation coefficient h_k1,m1A first distortion compensation characteristic is determined. The first characteristic formula is a first polynomial for compensating for the first nonlinear distortion, and the first distortion compensation coefficient h_k1,m1Corresponding to each term of the first polynomial.

Fig. 3 is a functional block diagram showing the functions of the distortion compensating apparatus 20 according to the embodiment. The first distortion compensation circuit 210 has a function as the first nonlinearity compensation unit 221 and a function as the first memory effect compensation unit 231. The first nonlinear compensation unit 221 corresponds to a compensation function for nonlinear distortion, and the first memory effect compensation unit 231 corresponds to a compensation function for memory effect distortion. The first distortion compensation characteristic is a distortion compensation characteristic including those corresponding distortion compensation characteristics of the first nonlinear compensation unit 221 and the first memory effect compensation unit 231.

The first distortion compensation characteristic specified by the above first characteristic formula is an example. The first distortion compensation characteristic may be specified by a model different from equation (1).

Reference is again made to fig. 2. When K1 increases, the order of the first characteristic formula increases. The distortion compensation by the predistorter 21A compensates for relatively high-order distortion (high-order nonlinearity) up to 5 th order or 7 th order distortion, for example. That is, K1 is set to a relatively large value, such as 5 or greater. Since distortion up to high-order distortion can be compensated, distortion compensation with high accuracy can be achieved, but the number of first distortion compensation coefficients 215a is increased.

The predistorter 21A includes a first updating unit 213 that updates the first distortion compensation coefficients 215 a. In this embodiment, the first updating unit 213 is implemented as a computer comprising a processor 211 and a memory 212. The processor 211 executes a coefficient update program 214, the coefficient update program 214 being a computer program stored in the memory 212. Each function of the first updating unit 213 is exposed by the processor 211, and the processor 211 executes a coefficient updating program 214, the coefficient updating program 214 being a computer program stored in the memory 212 of the computer. The coefficient update program 214 may be stored in a storage medium such as a CD-ROM. The processor 211 executes the coefficient update program 214 to perform a first update process described later.

The coefficient update program 214 includes program code for causing the processor 211 to execute a first update process for updating the first distortion compensation coefficient 215 a. The first update process is performed based on, for example, the sampled data 215b indicating the output z [ n ] of the amplifier 50. The sample data 215b obtained by the predistorter 21A is stored in the memory 212.

In the first update process, for example, the processor 211 solves the normal equation according to the least square method based on several thousands of sample data 215b obtained by sampling within a predetermined time (for example, several minutes), thereby calculating the first distortion compensation coefficient 215 a. The calculated first distortion compensation coefficient 215a is supplied to the first distortion compensation circuit 210 to update the distortion compensation coefficient used in the first distortion compensation circuit 210.

A calculation method such as the least square method can calculate coefficients with high accuracy, but the processing load is large and the processing time is long. In addition, the number of coefficients to be calculated is large, which further increases the processing load. In addition, when a calculation method such as a least square method that requires a large amount of sample data 215b for coefficient update is used, time is required to obtain the large amount of sample data 215 b.

However, the above problem does not constitute a problem in the predistorter 21A. Since the first update process is performed by the processor 211 at a low frequency, for example, once every several minutes, a sufficient time margin for coefficient update is ensured, and therefore, the time taken for this process does not cause a problem. Further, since the change in distortion caused by the temperature change occurs smoothly, the smooth change in distortion can be tracked even if the coefficient update is performed at a low frequency. However, the predistorter 21A cannot track instantaneous changes in distortion caused by Idq drift or the like. The instantaneous change in distortion is handled by predistorter 21B.

The calculation function of the first distortion compensation coefficient 215a by the least square method is an example. For example, the first distortion compensation coefficient 215a may be calculated by another algorithm such as LMS, RMS (root mean square), or RLS (recursive least square). Alternatively, the first distortion compensation coefficient 215a may be derived by using a correspondence table between the sample data and the first distortion compensation coefficient.

The predistorter 21A may not necessarily have the first updating unit 213. That is, the predistorter 21A may have a first distortion compensation characteristic that does not change. In this case, the predistorter 21A does not need to obtain the sample data 215 b. When the predistorter 21A does not have the first updating unit 213, the temporal variation of the distortion is processed by the predistorter 21B.

As described above, the predistorter 21B handles a change in distortion, particularly an instantaneous change in distortion, which cannot be handled by the predistorter 21A. The predistorter 21B shown in fig. 2 is configured to perform Digital Predistortion (DPD). In fig. 2, a predistorter 21B is connected to the input side of the predistorter a (between the predistorter a and the baseband processing unit). The predistorter 21B is implemented as wired logic circuitry such as a Field Programmable Gate Array (FPGA), for example. The wired logic circuits may be reconfigurable logic circuits, such as FPGAs, or may be non-reconfigurable logic circuits.

The predistorter 21B includes a circuit serving as the second distortion compensation circuit 217. The second distortion compensating circuit 217 includes a wired logic circuit for performing predistortion on a baseband signal (here, a signal x [ n ] output from the baseband processing unit). Distortion compensation is performed based on the second distortion compensation coefficients 219a stored in the coefficient storage unit in the predistorter 21B. The second distortion compensation coefficient 219a is a parameter that determines the distortion compensation characteristics of the predistorter 21B.

The distortion compensation characteristic (hereinafter, referred to as "second distortion compensation characteristic") of the second distortion compensation circuit 217 is specified by a model (hereinafter, referred to as "second distortion compensation characteristic model") represented by, for example, the following formula (2) (hereinafter, also referred to as "second characteristic formula").

[ mathematical formula 2]

Where x denotes an input signal of the second distortion compensating circuit 217, y denotes an output signal of the second distortion compensating circuit 217, K2 denotes an index relating to a compensation function for nonlinear distortion, M2 denotes an index relating to a compensation function for memory effect distortion, K2 and M2 denote constants, n denotes a discrete time, and h denotes a discrete time_k2,m2Denotes a coefficient (hereinafter, referred to as "second distortion compensation coefficient"). That is, the second distortion compensation circuit 217 having the second distortion compensation characteristic has a function of compensating each of the nonlinear distortion and the memory effect distortion. By specifying a second distortion compensation coefficient h_k2,m2To determine a second distortion compensation characteristic. The second characteristic formula is a second polynomial for compensating for the second nonlinear distortion, and the second distortion compensation coefficient h_k2,m2Corresponding to each term of the second polynomial.

Refer to fig. 3. The second distortion compensation circuit 217 has a function as the second nonlinearity compensation unit 222 and a function as the second memory effect compensation unit 232. The second nonlinear compensation unit 222 corresponds to a compensation function for nonlinear distortion, and the second memory effect compensation unit 232 corresponds to a compensation function for memory effect distortion. The second distortion compensation characteristic is a distortion compensation characteristic including those of the second nonlinear compensation unit 222 and the second memory effect compensation unit 232.

The second distortion compensation characteristic specified by the above-described second characteristic formula is an example. The second distortion compensation characteristic may be a characteristic of compensating for one of the nonlinear distortion or the memory effect distortion, or may be a characteristic of compensating for a distortion different from the nonlinear distortion and the memory effect distortion. In this case, the second distortion compensation characteristic is specified by a model different from equation (2).

Reference is again made to fig. 2. The distortion compensation of the predistorter 21B compensates for, for example, a relatively low-order distortion (low-order nonlinearity) such as a third-order distortion. That is, K2 is a constant less than K1, and is set to a relatively low value, such as 3 or less. Since the low-order distortion is compensated, less second distortion compensation coefficients 219a are required. Therefore, the processing load in the predistorter 21B is small. Therefore, an increase in the circuit scale of the predistorter 21B is suppressed.

As the non-linear order of the distortion compensation characteristic model increases, the frequency bandwidth of the output signal of the distortion compensation circuit increases. The first distortion compensation circuit 210 and the second distortion compensation circuit 217 are formed by a plurality of nonlinear Volterra operators. As the signal passes through the nonlinear Volterra operator, the signal bandwidth increases in proportion to the order of the nonlinearity. For example, the third order nonlinear Volterra operator extends the signal bandwidth by a factor of three. The final bandwidth of the output signal is therefore dependent on the highest order nonlinear Volterra operator. Therefore, since the first distortion compensation circuit 210 has the first distortion compensation characteristic specified by the first characteristic formula of a relatively high order, the frequency bandwidth of the output signal is relatively wide. In contrast, since the second distortion compensation circuit 217 has the second distortion compensation characteristic specified by the second characteristic formula of a relatively low order, the frequency bandwidth of the output signal is relatively narrow.

When viewed from the predistorter 21B side, only distortion components that are not compensated by the predistorter 21A out of the distortion of the amplifier 50 exist, and therefore, the nonlinearity of the distortion to be compensated by the predistorter 21B is not particularly strong. Therefore, even when the predistorter 21B compensates only the low-order distortion, no serious problem is caused.

The predistorter 21B includes a circuit serving as a second updating unit 218, and the second updating unit 218 is configured to update the second distortion compensation coefficients 219 a. The second updating unit 218 includes wired logic circuits for performing a second updating process to update the second distortion compensation coefficients 219 a. The second update process is performed based on, for example, the sample data 219b indicating the output z [ n ] of the amplifier 50. The sample data 219B obtained by the predistorter 21B is stored in a sample data storage unit of the second updating unit 218.

The second update unit 218 is at a higher frequency than the predistorter aThe frequency performs calculation for updating the second distortion compensation coefficient 219 a. For example, the second update unit 218 updates 1/f per sampling period for the sampling data 219b_s[s]Or for the sampling period 1/f, or the second distortion compensation coefficient 219a, or for the sampling period 1/f_s[s]A second distortion compensation coefficient 219a for each period of several times the length of (a). In the following, 1/f for each sampling period is described_s[s]An example of the second distortion compensation coefficient 219a is updated. For example, the second updating unit 218 calculates the second distortion compensation coefficient 219a by Least Mean Square (LMS) based on the one or more sample data 219 b. The calculated second distortion compensation coefficient 219a is supplied to the second distortion compensation circuit 217 to update the distortion compensation coefficient used in the second distortion compensation circuit 217.

The number of sample data 219b used by the second updating unit 218 for one coefficient update is small. Therefore, some of the flip-flops provided in the second updating unit 218 are sufficient as a coefficient storage unit for storing therein the sample data 219 b. The coefficient storage unit need not be a mass memory.

For example, the LMS-based second distortion compensation coefficient is calculated based on the following equations (3) and (4). Based on equation (2), distortion compensation using the calculated second distortion compensation coefficient is performed.

[ mathematical formula 3]

[ mathematical formula 4]

In the above formula, n is discrete time, α is a predetermined coefficient, K is a polynomial vector for distortion compensation, z [ n-1] is sample data at discrete time n-1, h [ n ] and h [ n-1] are second distortion compensation coefficient vectors at discrete time n and discrete time n-1, respectively, y [ n ] and y [ n-1] are outputs (distortion compensation signals) of the predistorter 21B at discrete time n and discrete time n-1, respectively, and λ is a weight (0 < λ < 1). The coefficient vector h [ n ] and the polynomial vector K (z [ n ]) at time n are defined by the following equations (5) and (6). T denotes transpose and H denotes conjugate transpose.

[ math figure 5]

h[n]＝(h_1，0[n]，h_1，1[n]，…，h_1，M[n]，h_2，0[n]，…，h_2，M[n]，…，h_K，0[n]，…，h_K，M[n])^T····(5)

[ mathematical formula 6]

K(z[n])＝(z[n]，z[n-1]，…，z[n-M]，|z[n]|·z[n]，…，|z[n-M]|·z[n-M]，…，|z[n]|^K-1·z[n]，…，|z[n-M]|^K-1·z[n-M])····(6)

Equation (3) is based on the sampled data z [ n-1]]And the output y [ n-1] of the predistorter 21B]Calculating a second distortion compensation coefficient vector h [ n-1]]The update value of (2). Equation (4) calculates the time average of the values updated by equation (3). The calculation of equation (2) is performed by using the time average value of the second distortion compensation coefficient calculated by equation (3). When the predistorter 21B acquires the sample data, if it occurs, it is not less than one sampling period 1/f_s[s]The "n-1" in equations (3) and (4) can be replaced by "n-d".

The calculation method such as LMS has lower calculation accuracy than the least square method, but has a smaller processing load than the least square method because the calculation is relatively simple. In addition, the number of coefficients to be calculated and the number of sample data 219b required for coefficient update are both smaller than the least square method.

For example, 1/f for each sampling period_s[s]Or as a sampling period 1/f_s[s]Is performed at a high frequency, the coefficient update by the second updating unit 218 is performed at every period of several times the length of the second updating unit. In addition, the second update unit 218 is a wired logic circuit and thus can perform calculation at high speed. Accordingly, the second updating unit 218 can track the instantaneous change in distortion caused by Idq drift or the like to quickly update the second distortion compensation coefficient 219 a.

Although the second updating unit 218 updates the coefficient at a high frequency, since the processing load per update is not so large, the processing load can be reduced and the circuit scale can also be reduced as compared with the case where the coefficient updating processing with a large processing load is performed at a high frequency.

According to the distortion compensation apparatus 20 shown in fig. 2, the predistorter 21A compensates for distortion during normal operation, rather than compensating for distortion when an instantaneous distortion change occurs due to Idq drift or the like, and at the same time, the predistorter 21B tracks the instantaneous change in distortion due to Idq drift or the like in real time to perform distortion compensation. Further, since the predistorter 21A is provided, an increase in the processing load of the predistorter 21B is suppressed, thereby suppressing an increase in the hardware scale.

The LMS as the calculation algorithm of the second distortion compensation coefficient 219a may be NLMS (normalized least mean square). The calculation function of the second distortion compensation coefficient 219a by the LMS is an example of the second updating unit 218 shown in fig. 3. For example, the second distortion compensation coefficient 219a may be calculated by another algorithm such as least squares, RMS, or RLS. Alternatively, the second distortion compensation coefficient 219a may be derived by using a correspondence table between the sample data and the second distortion compensation coefficient.

In the example shown in fig. 2, the predistorter 21B is implemented as a wired logic circuit. However, regarding the update of the distortion compensation coefficients, the predistorter 21B may be implemented as a computer having a processor and a memory, just like the predistorter 21A. In this case, the coefficient update processing in the predistorter 21B is performed by a processor executing a computer program stored in a memory.

[2. operation of distortion compensating apparatus ]

Next, the operation of the distortion compensating apparatus 20 according to the present embodiment is described. Fig. 4 is a flowchart showing an example of an operation procedure performed by the predistorter 21A.

The processor 211 of the predistorter 21A performs a first update process (step S101). Through the first update process, the first distortion compensation coefficient 215a is determined, and the first distortion compensation characteristic of the first distortion compensation circuit 210 is set.

The first distortion compensation circuit 210, to which the first distortion compensation characteristic has been set, performs a first distortion compensation process (step S102). The first distortion compensation process is a process in which the first distortion compensation circuit 210 receives an input signal y [ n ], performs distortion compensation on the input signal y [ n ] in accordance with a first distortion compensation characteristic to generate an output signal y [ n ] ', and outputs the output signal y [ n ]'.

The processor 211 determines whether the update timing for the first distortion compensation characteristic has been reached (step S103). The first update process is performed at a low frequency. Therefore, the interval between updates is set to a relatively long time. For example, the sampling period is 1/f_s[s]Is performed every cycle several tens to several hundreds times as long.

When the update timing has not been reached (no in step S103), the processing returns to step S102, and the first distortion compensation circuit 210 executes the first distortion compensation processing. For each sampling period f_sA first distortion compensation process is performed.

When the update timing has reached (yes in step S103), the processing returns to step S101, and the processor 211 executes the first update processing again.

By repeatedly performing the above-described operations, the first distortion compensation characteristic is updated at a low frequency, and each sampling period f_sA first distortion compensation process is performed.

Fig. 5 is a flowchart showing an example of the first update process.

The processor 211 receives the sample data 215b (step S111), and stores the sample data 215b in the memory 212 (step S112). The sample data 215b corresponding to the past predetermined period of time is accumulated in the memory 212. That is, in step S112, newly received sample data is added and stored in the memory 212 in which the past sample data 215b is stored.

The processor 211 reads out the sample data 215b corresponding to a predetermined period of time from the memory 212 (step S113). The processor 211 solves the normal equation by the least square method using the read sample data 215b, thereby calculating a first distortion compensation coefficient 215a (step S114).

The processor 211 transmits the first distortion compensation coefficient 215a to the first distortion compensation circuit 210 to set the first distortion compensation circuit 210 (step S115). Accordingly, the first distortion compensation characteristic is updated. Then, the first update processing ends.

Next, the operation of the predistorter 21B is described. Fig. 6 is a flowchart showing an example of an operation procedure performed by the predistorter 21B.

The second updating unit 218 of the predistorter 21B performs a second updating process (step S201), determines the second distortion compensation coefficient 219a through the second updating process, and sets the second distortion compensation characteristic of the second distortion compensation circuit 217.

The second distortion compensation circuit 217 having set the second distortion compensation characteristic performs the second distortion compensation process (step S202). The second distortion compensation process is a process in which the second distortion compensation circuit 217 receives the input signal z [ n ], performs distortion compensation on the input signal z [ n ] in accordance with a second distortion compensation characteristic to generate an output signal y [ n ], and outputs the output signal y [ n ].

When the second distortion compensation process ends, the second update process is executed again (step S201). That is, in this example, the second update process and the second distortion compensation process are repeatedly performed. For example, 1/f for each sampling period_s[s]The second update process and the second distortion compensation process are performed.

As described above, the second update process is performed at a high frequency. For example, the sampling period may be 1/f_s[s]Is performed every period of several times the length of the first update process.

By repeatedly performing the above-described operations, the second distortion compensation characteristic is updated at a high frequency, and each sampling period f_sA second distortion compensation process is performed.

Fig. 7 is a flowchart showing an example of the second update process.

The second updating unit 218 receives the sample data 219b (step S211), and stores the sample data 219b (step S212). The sample data 219b corresponding to a predetermined period of time in the past (a period of time shorter than the storage period of the sample data 215 b) is accumulated in the second updating unit 218. That is, in step S212, newly received sample data is added and stored in the sample data storage unit that stores past sample data 219 b.

The second updating unit 218 reads out the sample data 219b corresponding to the predetermined period from the sample data storage unit (step S213). The second updating unit 218 solves the normal equation by LMS using the read sample data 219b, thereby calculating a second distortion compensation coefficient 219a (step S214).

The second updating unit 218 sends the second distortion compensation coefficient 219a to the second distortion compensation circuit 217 to set the second distortion compensation circuit 217 (step S215). Thus, the second distortion compensation characteristic is updated. Then, the second update processing ends.

In the distortion compensation apparatus 20 according to the present embodiment, the first distortion compensation circuit 210 handles distortion that does not vary with time or that varies smoothly with time due to the state of the amplifier 50 such as temperature, operating time, or power, while the second distortion compensation circuit 217 handles distortion that varies quickly with time due to high-speed drift such as Idq drift. That is, the distortion caused by the amplifier 50 includes a first distortion that does not change over time or that changes gradually over time, and a second distortion that changes faster than the first distortion. The second updating unit 218 updates the second distortion compensation characteristic at a higher frequency than the first updating unit 213. Thus, the temporal variation of the second distortion can be handled. In addition, the first distortion compensation circuit 210 compensates for both the nonlinear distortion and the memory effect distortion. Accordingly, both the non-linear distortion and the memory effect distortion included in the first distortion can be processed. Therefore, distortion compensation with high accuracy can be achieved.

The second distortion compensation circuit 217 may compensate for both the non-linear distortion and the memory effect distortion. Therefore, distortion compensation with higher accuracy can be realized.

The second distortion compensation characteristic of the second distortion compensation circuit 217 may be specified by a second characteristic formula having a lower order than the first characteristic formula. Therefore, even when the update of the second distortion compensation characteristic is performed at a high frequency, the processing load can be suppressed.

The frequency bandwidth of the output signal of the second distortion compensation circuit 217 may be narrower than the frequency bandwidth of the output signal of the first distortion compensation circuit 210. According to the increase of the frequency bandwidth of the output signal, the processing load is increased. Therefore, when the second frequency bandwidth is set to be narrow, even when the update of the second distortion compensation characteristic is performed at a high frequency, the processing load can be suppressed.

[3. other examples of distortion compensating apparatus ]

Fig. 8 shows another example of the distortion compensation apparatus 20. The distortion compensation apparatus 20 shown in fig. 8 includes a predistorter 22A and a predistorter 22B cascaded with each other. In fig. 8, the predistorter 22A is an example of the predistorter a shown in fig. 1. In fig. 8, the predistorter 22B is an example of the predistorter B shown in fig. 1.

The predistorter 22A shown in fig. 8 performs Analog Predistortion (APD). The predistorter 22A is implemented as an analog circuit having inverse characteristics of the amplification characteristics of the amplifier 50. The predistorter 22A shown in fig. 8 is functionally equivalent to the predistorter 21A shown in fig. 2 with the coefficient update function eliminated. The predistorter 22A shown in fig. 8 does not have an update function of the distortion compensation characteristic, and therefore cannot cope with temporal changes in distortion. Predistorter 22B handles temporal changes in distortion, including instantaneous changes in distortion.

Predistorter 22B is configured to perform Digital Predistortion (DPD). The configuration and function of the predistorter 22B are the same as those of the predistorter 21B shown in fig. 2. The coefficient update module in the predistorter 22B may be implemented as a computer having a memory and a processor.

According to the distortion compensation apparatus 20 shown in fig. 8, the predistorter 22A compensates for distortion of the amplifier 50 with a distortion component of a portion corresponding to a temporal change excluded, and at the same time, the predistorter 22B tracks the temporal change of distortion in real time to perform distortion compensation. Further, since the predistorter 22A is provided, an increase in the processing load of the predistorter 22B is suppressed, thereby suppressing an increase in the hardware scale.

In fig. 8, a DAC 22C is provided between the predistorter 22B and the predistorter 22A. The digital distortion compensation signal output from the predistorter 22B is converted into an analog signal by the DAC 22C. The analog distortion compensation signal is provided to predistorter 22A. Since the output of the predistorter 22A is an analog signal, in fig. 8, there is no need to provide a DAC 30 between the distortion compensation apparatus 20 and the up-converter 40 of fig. 1.

Fig. 9 shows yet another example of the distortion compensation apparatus 20. The distortion compensation apparatus 20 shown in fig. 9 includes a predistorter a and a predistorter B cascaded with each other. In fig. 9, the arrangement of the predistorter a and the predistorter B is the reverse of the arrangement shown in fig. 1, and the predistorter B is connected to the output side of the predistorter a.

Also in the distortion compensation apparatus 20 shown in fig. 9, the predistorter a compensates for distortion during normal operation, rather than compensating for distortion when an instantaneous distortion change occurs due to Idq drift or the like, while the predistorter B tracks instantaneous changes in distortion due to Idq drift or the like in real time to perform distortion compensation. Further, since the predistorter a is provided, an increase in the processing load of the predistorter B is suppressed, thereby suppressing an increase in the hardware scale.

Fig. 10 shows yet another example of the distortion compensation apparatus 20. The distortion compensation apparatus 20 shown in fig. 10 includes a predistorter a and a predistorter B connected in parallel. In fig. 10, the baseband signal x n is provided to predistorter a and predistorter B. Predistorter a compensates for distortion during normal operation rather than when instantaneous distortion changes due to Idq drift or the like. The predistorter a outputs a first distortion compensation signal y1[ n ]. The predistorter B processes instantaneous distortion change due to Idq drift or the like, and outputs a second distortion compensation signal y2[ n ]. The first distortion compensation signal y1[ n ] and the second distortion compensation signal y2[ n ] are added by an adder. The distortion compensation device 20 outputs a distortion compensation signal y [ n ] obtained by addition.

Also in the distortion compensation apparatus 20 shown in fig. 10, the predistorter a compensates for distortion during normal operation, rather than compensating for distortion when an instantaneous distortion change occurs due to Idq drift or the like, while the predistorter B tracks the instantaneous distortion change due to Idq drift or the like in real time to perform distortion compensation. Further, since the predistorter a is provided, an increase in the processing load of the predistorter B is suppressed, thereby suppressing an increase in the hardware scale.

Fig. 11 shows another example of a wireless communicator. The wireless communicator 100 shown in fig. 11 includes a first filter 401 and a second filter 402 that convert the monitoring signal z n.

The signal line on the output side of the ADC 80 is branched. A first filter 401, being a digital filter, is connected to one branch and a second filter 402, being a digital filter, is connected to the other branch.

Each of the first filter 401 and the second filter 402 may be a filter that allows a signal in a specific frequency band to pass through, and may be, for example, one of a low-pass filter, a band-pass filter, and a high-pass filter. The type of filter (passband) may be determined based on the frequency band for which the downconverter 70 performs downconversion. For example, when the wireless communicator 100 is of the zero intermediate frequency type, i.e., a direct conversion receiver, the first filter 401 and the second filter 402 may be implemented as low pass filters, respectively. In the case of a zero intermediate frequency wireless communicator, the center frequency of the output signal of the ADC 80 is generally direct current (frequency ═ 0), and when the first filter 401 and the second filter 402 are respectively implemented as low-pass filters, signals in the signal band and the adjacent band are allowed to pass therethrough.

The output side of the first filter 401 is connected to the first updating unit 213. The first monitor signal z1[ n ] which is the output signal from the first filter 401 is input to the first updating unit 213. The first updating unit 213 obtains sampling data from the input first monitor signal z1[ n ], and updates the first distortion compensation coefficient to be supplied to the first distortion compensation circuit 210 by the first updating process based on the sampling data.

The output side of the second filter 402 is connected to the second updating unit 218. The second monitor signal z2[ n ] which is the output signal from the second filter 402 is input to the second updating unit 218. The second updating unit 218 obtains sampling data from the input second monitor signal z2[ n ], and updates the second distortion compensation coefficient to be supplied to the second distortion compensation circuit 217 through a second updating process based on the sampling data.

The passband of the second filter 402 is narrower than the passband of the first filter 401. That is, the frequency bandwidth of the second monitor signal z2[ n ], which is the output signal from the second filter 402, is narrower than the frequency bandwidth of the first monitor signal z1[ n ], which is the output signal from the first filter 401. Since the second distortion compensation circuit 217 compensates for distortion of a relatively low order (low order nonlinearity), an outer band corresponding to high order distortion in the entire frequency band of the monitor signal z [ n ] is not required. In addition, the signal component in the outer band may cause instability of the second distortion compensation coefficient. In the present modification, since the passband of the second filter 402 is narrower than the passband of the first filter 401, the second monitor signal z2[ n ] from which the signal component of the outer band is eliminated can be obtained, and the instability of the second distortion compensation coefficient can be suppressed.

When compared with the second distortion compensation circuit 320, the first distortion compensation circuit 310 compensates for distortion up to high-order distortion (high-order nonlinearity), and thus an outer band corresponding to the high-order distortion is required. Conversely, the absence of the signal component of the outer band may cause instability of the first distortion compensation coefficient. In the present modification, since the passband of the first filter 401 is wider than the passband of the second filter 402, the first monitor signal z1[ n ] containing the signal component in the outer band can be obtained, thereby suppressing the instability of the first distortion compensation coefficient.

The first filter 401 may not necessarily be a filter that allows a specific frequency band to pass, such as a low pass filter, a band pass filter, or a high pass filter. For example, the first filter 401 may be a filter that allows passage of the entire bandwidth, such as an all-pass filter.

Each of the first filter 401 and the second filter 402 may be an analog filter. Fig. 12 shows an example of a wireless communicator, in which a first filter 401 and a second filter 402 are respectively implemented as analog filters.

The signal line on the output side of the down-converter 70 is branched. A first filter 401, being an analog filter, is connected to one branch and a second filter 402, being an analog filter, is connected to the other branch. The anti-aliasing filter 411 and the ADC 421 are connected in series on the output side of the first filter 401. The anti-aliasing filter 412 and the ADC 422 are connected in series on the output side of the second filter 402.

Each of the first filter 401 and the second filter 402 may be a filter that allows a signal in a specific frequency band to pass through, and may be, for example, one of a low-pass filter, a band-pass filter, and a high-pass filter. The type of filter (passband) may be determined based on the frequency band for which the downconverter 70 performs downconversion. For example, when the wireless communicator 100 is of the zero intermediate frequency type, i.e., a direct conversion receiver, the first filter 401 and the second filter 402 may be implemented as low pass filters, respectively. In the case of a zero intermediate frequency wireless communicator, the center frequency of the output signal of the ADC 80 is generally direct current (frequency ═ 0), and when the first filter 401 and the second filter 402 are respectively implemented as low-pass filters, signals in the signal band and the adjacent band are allowed to pass therethrough.

The output side of the ADC 421 is connected to the first updating unit 213. The first monitor signal z1[ n ] which is an output signal from the ADC 421 is input to the first updating unit 213. The first updating unit 213 obtains sampling data from the input first monitor signal z1[ n ], and updates the first distortion compensation coefficient to be supplied to the first distortion compensation circuit 310 by the first updating process based on the sampling data.

The output side of the ADC 422 is connected to the second updating unit 218. The second monitor signal z2[ n ] which is the output signal from the ADC 422 is input to the second update unit 218. The second updating unit 218 obtains sampling data from the input second monitor signal z2[ n ], and updates the second distortion compensation coefficient to be supplied to the second distortion compensation circuit 320 by the second updating process based on the sampling data.

The passband of the second filter 402 is narrower than the passband of the first filter 401. That is, the frequency bandwidth of the second monitor signal z2[ n ] as the output signal from the ADC 422 is narrower than the frequency bandwidth of the first monitor signal z1[ n ] as the output signal from the ADC 421. In the present modification, since the passband of the second filter 402 is narrower than the passband of the first filter 401, the second monitor signal z2[ n ] from which the signal component of the outer band is eliminated can be obtained, and the instability of the second distortion compensation coefficient can be suppressed. In addition, since the passband of the first filter 401 is wider than the passband of the second filter 402, the first monitor signal z1[ n ] containing the signal component in the outer band can be obtained, and the instability of the first distortion compensation coefficient can be suppressed.

Fig. 13 shows another example of a wireless communicator, in which a first filter 401 and a second filter 402 are respectively implemented as analog filters.

The signal line on the output side of the down-converter 70 is branched. A first filter 401 is connected to one branch and a second filter 402 is connected to the other branch. The first filter 401 is an anti-aliasing filter. The ADC 421 is connected to the output side of the first filter 401. The second filter 402 is a filter that allows a signal in a specific frequency band to pass through, and may be, for example, one of a low-pass filter, a band-pass filter, and a high-pass filter. The anti-aliasing filter 412 and the ADC 422 are connected in series on the output side of the second filter 402.

Fig. 14 shows another example of a wireless communicator, in which a first filter 401 and a second filter 402 are respectively implemented as analog filters.

The signal line on the output side of the coupler 36 is branched, and the downconverters 471, 472 are connected to the respective branches. The first filter 401 is connected to the output side of the down-converter 471, and the second filter 402 is connected to the output side of the down-converter 472. The anti-aliasing filter 411 and the ADC 421 are connected in series on the output side of the first filter 401. The anti-aliasing filter 412 and the ADC 422 are connected in series on the output side of the second filter 402.

Fig. 15 shows still another example of the distortion compensation apparatus. The distortion compensating apparatus 300 shown in fig. 15 includes a first distortion compensating circuit 310, a second distortion compensating circuit 320, and an updating unit 330. The updating unit 330 updates the first distortion compensation characteristic of the first distortion compensation circuit 310 and the second distortion compensation characteristic of the second distortion compensation circuit 320.

The first distortion compensation circuit 310 has a first distortion compensation characteristic expressed by a first characteristic equation of equation (1), for example. The second distortion compensation circuit 320 has a second distortion compensation characteristic expressed by a second characteristic equation of equation (2), for example.

Fig. 16 is a block diagram showing an example of the configuration of the distortion compensating apparatus 300 in the present modification. The distortion compensation device 300 in this example comprises an update unit 330 implemented as a computer having a processor 331 and a memory 332. The processor 331 executes a coefficient update program 333, the coefficient update program 333 being a computer program stored in the memory 332. Each function of the update unit 330 is shown by the processor 331, the processor 331 executing a coefficient update program 333, the coefficient update program 333 being a computer program stored in the memory 332 of the computer. The coefficient update program 333 may be stored in a storage medium such as a CD-ROM. The processor 331 executes the coefficient update program 333 to perform a first update process and a second update process described later.

The coefficient update program 333 includes program codes causing the processor 331 to perform a first update process for updating the first distortion compensation coefficient 334a and a second update process for updating the second distortion compensation coefficient 334 b. The first update process and the second update process are performed based on, for example, the sample data 335 indicating the output z [ n ] of the amplifier 50. The sampled data 335 obtained by the distortion compensation apparatus 300 is stored in the memory 332.

In the first update process, for example, the processor 331 solves the normal equation according to the least square method based on thousands of sample data 335 obtained by sampling within a predetermined time (for example, several minutes), thereby calculating the first distortion compensation coefficient 334 a. The calculated first distortion compensation coefficient 334a is supplied to the first distortion compensation circuit 310 to update the distortion compensation coefficient used in the first distortion compensation circuit 310.

In the second update process, for example, the processor 331 solves the LMS according to, for example, equations (3) and (4) based on a part of the sample data 335, thereby calculating the second distortion compensation coefficient 334 b. The calculated second distortion compensation coefficient 334b is supplied to the second distortion compensation circuit 320 to update the distortion compensation coefficient used in the second distortion compensation circuit 320.

The number of the second distortion compensation coefficients 334b is smaller than the number of the first distortion compensation coefficients 334 a. Therefore, the processing load for calculating the second distortion compensation coefficient 334b is smaller than that for calculating the first distortion compensation coefficient 334 a. The first update process is performed at a low frequency, and the second update process is performed at a high frequency.

Next, the operation of the distortion compensating apparatus 300 in the present example is described. Fig. 17 is a flowchart showing an example of a procedure of an operation performed by the distortion compensation apparatus 300.

The processor 331 performs a first update process (step S301). Through the first update process, the first distortion compensation coefficient 334a is determined, and the first distortion compensation characteristic of the first distortion compensation circuit 310 is set.

The processor 331 performs a second update process (step S302). Through the second update process, the second distortion compensation coefficient 334b is determined, and the second distortion compensation characteristic of the second distortion compensation circuit 320 is set.

The first distortion compensation circuit 310, which has set the first distortion compensation characteristic, performs the first distortion compensation process (step S303). The first distortion compensation process is a process in which the first distortion compensation circuit 310 receives an input signal y [ n ], performs distortion compensation on the input signal y [ n ] in accordance with a first distortion compensation characteristic to generate an output signal y [ n ] ', and outputs the output signal y [ n ]'.

The second distortion compensation circuit 320, to which the second distortion compensation characteristic has been set, performs a second distortion compensation process (step S304). The second distortion compensation process is a process in which the second distortion compensation circuit 320 receives the input signal z [ n ], performs distortion compensation on the input signal z [ n ] in accordance with a second distortion compensation characteristic to generate an output signal y [ n ], and outputs the output signal y [ n ].

The processor 331 determines whether the update timing for the first distortion compensation characteristic has been reached (step S335). The first update process is performed at a low frequency. Therefore, the interval between updates is set to a relatively long time.

When the update has not been reachedAt the timing (no in step S305), the process returns to step S302, the processor 331 performs the second update process (step S302), the first distortion compensation circuit 310 performs the first distortion compensation process (step S303), and the second distortion compensation circuit 320 performs the second distortion compensation process (step S304). For example, for each sampling period f_sThe second update process is executed. For each sampling period f_sFirst and second distortion compensation processes are performed.

When the update timing has been reached (yes in step S305), the process returns to step S101, and the processor 331 executes the first update processing. For example, the sampling period is sampling period 1/f_s[s]Is performed every cycle several tens to several hundreds times as long.

The first update process S301 and the second update process S302 may be processes similar to the first update process and the second update process shown in fig. 5 and 7, respectively, for example.

By repeatedly performing the above-described operations, the first distortion compensation characteristic is updated at a low frequency, and the second distortion compensation characteristic is updated at a high frequency. For each sampling period f_sFirst and second distortion compensation processes are performed.

Fig. 18 is a block diagram showing another example of the configuration of the distortion compensation apparatus 300. In the present example, the update unit 330 is implemented as a wired logic circuit such as an FPGA or an ASIC (application specific integrated circuit), instead of a computer.

The updating unit 330 includes a partial circuit that performs a first updating process for updating the first distortion compensation coefficient 334a and a partial circuit that performs a second updating process for updating the second distortion compensation coefficient 334 b. The first update process is performed based on the sampled data 335 indicating the output z [ n ] of the amplifier 50, and the second update process is performed based on, for example, a part of the sampled data 335. The sample data 335 obtained by the distortion compensating apparatus 300 is stored in the sample data storage unit of the updating unit 330.

The number of the second distortion compensation coefficients 334b is smaller than the number of the first distortion compensation coefficients 334 a. Therefore, the processing load for calculating the second distortion compensation coefficient 334b is smaller than that for calculating the first distortion compensation coefficient 334 a. In the update process, the first distortion compensation coefficient 334a is calculated at a low frequency, and the second distortion compensation coefficient 334b is calculated at a high frequency.

[4. appendix ]

It should be noted that the embodiments disclosed herein are illustrative only and not restrictive in all respects. The scope of the invention is defined by the scope of the claims, and is intended to include meanings equivalent to the scope of the claims and all modifications within the scope.

REFERENCE SIGNS LIST

100 wireless communicator

20, 300 distortion compensation apparatus

30, 22C digital-to-analog converter

36 coupler

40 up converter

50 power amplifier

60 antenna

70, 471, 472 down converter

80 analog-to-digital converter

21A, 22A, A first predistorter

21B, 22B, B second predistorter

210, 310 first distortion compensation circuit

211, 331 processor

212, 332 memory

213 first update unit

214, 333 coefficient update program

215a, 334a first distortion compensation coefficient

215b, 219b, 335 sample data

217, 320 second distortion compensation circuit

218 second update unit

219a, 334b second distortion compensation coefficients

221 first non-linearity compensation unit

222 second non-linear compensation unit

231 first memory effect compensation unit

232 second memory effect compensation unit

330 updating unit

401 first filter

402 second filter

411, 412 anti-aliasing filter