阅读说明：本技术 用于将输入电流与电流阈值的集合比较的装置和方法 (Apparatus and method for comparing an input current to a set of current thresholds ) 是由 M·麦高恩 I·米雷亚 于 2019-07-22 设计创作，主要内容包括：一种电流比较器,包括：第一比较器,被配置为基于第一电流与至少第二电流的比较生成第一输出信号；第二比较器,被配置为基于第一电流与至少第三电流的比较生成第二输出信号；以及电路,被配置为：当阻挡第一电流被施加到第二比较器时,将第一电流引导至第一比较器以执行第一电流与至少第二电流的比较；或者当阻挡第一电流被施加到第一比较器时,将第一电流引导至第二比较器以执行第一电流与至少第三电流的比较。(A current comparator, comprising: a first comparator configured to generate a first output signal based on a comparison of the first current and at least the second current; a second comparator configured to generate a second output signal based on a comparison of the first current and at least a third current; and circuitry configured to: directing the first current to the first comparator to perform a comparison of the first current to at least the second current when the first current is blocked from being applied to the second comparator; or directing the first current to the second comparator to perform a comparison of the first current to at least the third current when the first current is blocked from being applied to the first comparator.)

1. An apparatus, comprising:

a first comparator having a first input for receiving an input signal, a second input for receiving a reference signal, and an output; and

a set of one or more switches having inputs coupled to the output of the first comparator, wherein the set of one or more switches operates in response to a first output signal from the first comparator to select a threshold current from a set of one or more threshold currents.

2. The apparatus of claim 1, further comprising a second comparator to generate a second output signal based on a comparison of the input signal to the selected threshold current, the selected threshold current corresponding to the first output signal in a first state.

3. The apparatus of claim 2, further comprising a third comparator to generate a third output signal based on a comparison of the input signal to the selected threshold current, the selected threshold current corresponding to the first output signal in a second state.

4. The apparatus of claim 1, wherein the set of one or more switches comprises an n-channel metal-oxide-semiconductor field-effect transistor (NMOS), wherein the set of one or more switches comprises a p-channel metal-oxide-semiconductor field-effect transistor (PMOS), or wherein the set of one or more switches comprises an NMOS and a PMOS.

5. The apparatus of claim 4, further comprising:

a current source to generate one of the set of one or more threshold currents; and

a first current sink to sink another threshold current of the set of one or more threshold currents;

wherein the current source, the NMOS, the PMOS, and the first current sink are coupled in series between a high voltage rail and a low voltage rail, wherein the first input of the first comparator is coupled to a node between the NMOS and the PMOS, and wherein gates of the NMOS and PMOS are coupled to the output of the first comparator.

6. The apparatus of claim 5, further comprising a second current sink to sink another threshold current of the set of one or more threshold currents, wherein the second current sink is coupled between the first input of the first comparator and the low voltage rail.

7. The apparatus of claim 1, further comprising a current source to generate one of the set of one or more threshold currents.

8. The apparatus of claim 1, further comprising a current sink to sink one of the set of one or more threshold currents.

9. The apparatus of claim 1, wherein the input signal comprises an input current.

10. The apparatus of claim 1, further comprising a current device to generate the set of three threshold currents to compare with the input signal.

11. An apparatus, comprising:

a first comparator having a first input for receiving an input signal, a second input for receiving a reference signal, and an output;

a current source for providing a first threshold current;

a first current sink to provide a second threshold current;

a second current sink to provide a third threshold current; and

a set of one or more switches coupled between the current source and the first and second current sinks, the set of one or more switches having an input coupled to the output of the first comparator.

12. The apparatus of claim 11, wherein the set of one or more switches comprises an n-channel metal-oxide-semiconductor field-effect transistor (NMOS) and a p-channel metal-oxide-semiconductor field-effect transistor (PMOS).

13. The apparatus of claim 12, wherein the current source, the NMOS, the PMOS, and the first current sink are coupled in series between a high voltage rail and a low voltage rail, wherein the first input of the first comparator is coupled to a node between the NMOS and the PMOS, and gates of the NMOS and PMOS are coupled to the output of the first comparator.

14. The device of claim 13, wherein the second current sink is coupled between the first input of the first comparator and the low voltage rail.

15. The apparatus of claim 11, further comprising a second comparator to compare the input signal to a difference between the second threshold current and the first threshold current.

16. The apparatus of claim 15, further comprising a third comparator to compare the input signal to a sum of the first threshold current and the second threshold current.

17. The apparatus of claim 11, further comprising a second comparator configured to compare the input signal to a sum of the first threshold current and the second threshold current.

18. An apparatus, comprising:

a current source;

a first switching device;

a second switching device;

a first current sink, wherein the current source, the first switching device, the second switching device, and the first current sink are coupled in series between a first voltage rail and a second voltage rail;

a first comparator comprising: a first input coupled to a node between the current source and the first switching device, and a second input to receive a reference signal;

a second comparator comprising: a first input coupled to a node between the second switching device and the first current sink, and a second input to receive the reference signal; and

a third comparator comprising: a first input to receive an input signal and coupled to a node between the first switching device and the second switching device, a second input to receive the reference signal, and an output coupled to control inputs of the first switching device and the second switching device.

19. The apparatus of claim 18, further comprising a second current sink coupled between the first input of the third comparator and the second voltage rail.

20. The apparatus of claim 18, wherein the first switching device and the second switching device each comprise a Field Effect Transistor (FET).

Technical Field

Aspects of the present disclosure relate generally to current comparators and, more particularly, to an apparatus and method for comparing an input current to a set of current thresholds.

Background

A current comparator may be used to generate the input signal based on a comparison of the input current to a set of current thresholds. For example, if the input current is below all current thresholds in the set of current thresholds, the current comparator generates an output signal having a particular value. If the input current is higher than all current thresholds in the set of current thresholds, the current comparator generates an output signal having another particular value. In a similar manner, if the input current is below some of the set of current thresholds but above other of the set of current thresholds, the current comparator generates an output signal having yet another particular value. The output signal of the current comparator may be used to control one or more other components.

As with many devices, designers are concerned with the accuracy of the comparisons performed by the current comparators. Additionally, the component count and power consumption of the current comparator is another consideration for the designer.

Disclosure of Invention

The following presents a simplified summary of one or more embodiments in order to provide a basic understanding of such embodiments. This summary is not an extensive overview of all contemplated embodiments, and is intended to neither identify key or critical elements of all embodiments nor delineate the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.

One aspect of the present disclosure relates to an apparatus, comprising: a first comparator having a first input receiving an input signal, a second input receiving a reference signal, and an output; and a set of one or more switches having inputs coupled to the outputs of the first comparators, wherein the set of one or more switches operates in response to the output signals from the first comparators to select a threshold current from the set of one or more threshold currents for comparison with the input signals.

Another aspect of the disclosure relates to an apparatus comprising: a first comparator having a first input receiving an input signal, a second input receiving a reference signal, and an output; a current source providing a first threshold current; a first current sink providing a second threshold current; a second current sink providing a third threshold current; and a set of one or more switches coupled between the current source and the first and second current sinks, the set of one or more switches having an input coupled to the output of the first comparator.

Another aspect of the disclosure relates to an apparatus, comprising: the current source, the first switching device, the second switching device, and the first current sink are coupled in series between the first voltage rail and the second voltage rail. The apparatus further comprises: a first comparator comprising a first input coupled to a node between the current source and the first switching device and a second input receiving a reference signal; a second comparator comprising a first input coupled to a node between the second switching device and the first current sink and a second input receiving a reference signal; and a third comparator comprising a first input receiving an input signal and coupled to a node between the first switching device and the second switching device, a second input receiving a reference signal, and an output coupled to control inputs of the first switching device and the second switching device.

Another aspect of the disclosure relates to an apparatus comprising: a first comparator configured to generate a first output signal based on a comparison of a first current and at least a second current; a second comparator configured to generate a second output signal based on a comparison of the first current and at least a third current; and circuitry configured to: the first current is directed to the first comparator to perform a comparison of the first current to at least a second current when the first current is blocked from being applied to the second comparator, or to perform a comparison of the first current to at least a third current when the first current is blocked from being applied to the first comparator.

Another aspect of the disclosure relates to a method comprising: generating a first output signal based on a comparison of the first current and at least the second current; generating a second output signal based on a comparison of the first current and at least a third current; and enabling the comparison of the first current to the at least second current when the comparison of the first current to the at least third current is disabled; or enabling the comparison of the first current to the at least third current when the comparison of the first current to the at least second current is disabled.

Another aspect of the disclosure relates to an apparatus comprising: means for generating a first output signal based on a comparison of the first current to at least the second current; means for generating a second output signal based on a comparison of the first current and at least a third current; and means for enabling the means for comparing the first current to at least the second current when the means for comparing the first current to at least the third current is disabled; or means for enabling the means for comparing the first current with at least a third current when the means for comparing the first current with at least a second current is disabled.

To the accomplishment of the foregoing aspects and related ends, the one or more embodiments comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more embodiments. These aspects are indicative, however, of but a few of the various ways in which the principles of various embodiments may be employed and the described embodiments are intended to include all such aspects and their equivalents.

Drawings

Fig. 1 illustrates a schematic diagram of an example current comparator in accordance with an aspect of the present disclosure.

Fig. 2 illustrates a schematic diagram of another example current comparator in accordance with another aspect of the present disclosure.

Fig. 3A-3B illustrate schematic diagrams of exemplary equivalent circuits of the current comparator of fig. 2 based on different comparison results according to another aspect of the present disclosure.

Fig. 4A illustrates a block diagram of an exemplary voltage control circuit in accordance with another aspect of the present disclosure.

Fig. 4B illustrates a schematic diagram of another example current comparator in accordance with another aspect of the present disclosure.

Fig. 4C illustrates a table mapping current comparator output to decoder output to DC-to-DC converter output voltage according to another aspect of the disclosure.

Fig. 4D illustrates another table mapping decoder outputs to DC-to-DC converter output voltages in accordance with another aspect of the disclosure.

Fig. 4E illustrates a graph of various signals associated with operation of a voltage control circuit versus time, in accordance with another aspect of the disclosure.

Fig. 4F illustrates a state diagram of various signals associated with operation of a voltage control circuit in accordance with another aspect of the present disclosure.

Fig. 5 illustrates a flow chart of an exemplary method of comparing an input current to a set of current thresholds in accordance with another aspect of the disclosure.

Detailed Description

The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. It will be apparent, however, to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

Fig. 1 illustrates a schematic diagram of an example current comparator 100 in accordance with an aspect of the present disclosure. The current comparator 100 receives an input current signal I_sigTo input a current signal I_sigSet I of current threshold values_TH1-I_TH3A comparison is made and a set of output currents D3-D1 are generated based on the comparison.

As an example, if the current signal I is input_sigSet I below current threshold_TH1-I_TH3Then the output signals D3-D1 may have a value of 000. If the current signal I is input_sigAbove current threshold I_TH1But below the current threshold I_TH2-I_TH3Then the output signals D3-D1 may have a value of 001. If the current signal I is input_sigAbove current threshold I_TH1-I_TH2But below the current threshold I_TH3The output signals D3-D1 may have values of 011. And, if the current signal I is input_sigAll sets I of the sets above the current threshold_TH1-I_TH3Then the output signals D3-D1 may have a value of 111.

In particular, the current comparator 100 includes a first current path between a high voltage rail Vdd and a low voltage rail Vss (e.g., ground). The first current path comprises a first current source I coupled in series with a first transistor M1₀₁The first transistor M1 may be configured as an n-channel metal oxide semiconductor field effect transistor (NMOSFET). A current source (such as a first current source I)₀₁And other current sources described herein) provide a substantially constant current and may include a transistor, such as a p-channel metal-oxide-semiconductor field effect transistor (PMOSFET), having a control terminal (e.g., gate) biased with a substantially constant voltage. The drain and gate of the first transistor M1 are electrically coupled together to form a current mirror with the other current paths described herein. Input current signal I_sigIs applied toAt a first current source I₀₁And the first transistor M1.

The current comparator 100 further includes a second current path between the high voltage rail Vdd and the low voltage rail Vss. The second current path comprises a second current source I coupled in series with a second transistor M2₀₂The second transistor M2 may also be configured as an NMOSFET. The gate of transistor M2 is electrically coupled to the gate and drain of transistor M1 to form a current mirror relationship between the first current path and the second current path.

Similarly, the current comparator 100 further includes a third current path between the high voltage rail Vdd and the low voltage rail Vss. The third current path comprises a third current source I coupled in series with a third transistor M3₀₃The third transistor M3 may also be configured as an NMOSFET. The gate of transistor M3 is electrically coupled to the gate and drain of transistor M1 to form a current mirror relationship between the first current path and the third current path.

In a similar manner, the current comparator 100 further includes a fourth current path between the high voltage rail Vdd and the low voltage rail Vss. The fourth current path comprises a fourth current source I coupled in series with a fourth transistor M4₀₄The fourth transistor M4 may also be configured as an NMOSFET. The gate of transistor M4 is electrically coupled to the gate and drain of transistor M1 to form a current mirror relationship between the first current path and the fourth current path.

The current comparator 100 further comprises a set I of threshold current sinks_TH1-I_TH3. Current sink (such as current sink I)_TH1-I_TH3As well as other current sinks described herein) sink a substantially constant current and may include a transistor (such as an NMOSFET) having a control terminal (e.g., a gate) biased with a substantially constant voltage. Collective first threshold current sink I_TH1A second current source I coupled in the second current path₀₂And a second transistor M₂Between the node and the low voltage rail Vss. Second threshold current sink I of the set_TH2Is coupled at the firstThird current source I with three current paths₀₃And a third transistor M₃Between the node and the low voltage rail Vss. And, a third threshold current sink I of the set_TH3A fourth current source I coupled in the fourth current path₀₄And a fourth transistor M₄Between the node and the low voltage rail Vss. In this example, the third threshold current sink I_TH3Sink ratio second threshold current sink I_TH2High current, and a second threshold current sink I_TH2Absorption ratio first threshold current sink I_TH1High current (e.g. I)_TH3＞I_TH2＞I_TH1)。

The current comparator 100 additionally comprises a set of comparators CMP1-CMP 3. The first comparator CMP1 comprises a second current source I coupled to the second current path₀₂And a second transistor M₂The positive input terminal of the node in between. The second comparator CMP2 comprises a third current source I coupled to the third current path₀₃And a third transistor M₃The positive input terminal of the node in between. The third comparator CMP3 comprises a fourth current source I coupled to the fourth current path₀₄And a fourth transistor M₄The positive input terminal of the node in between. The sets of comparators CMP1-CMP3 each include a negative input terminal configured to receive a threshold voltage, which may be set to Vdd/2. The set of comparators CMP1-CMP3 includes outputs configured to generate bits of the output signals D1-D3, respectively.

Current source I of the first current path₀₁A current source I of a second current path₀₂A current source I of a third current path₀₃And a current source I of a fourth current path₀₄Configured to generate substantially the same current. Similarly, the transistor M1 of the first current path, the transistor M2 of the second current path, the transistor M3 of the third current path, and the transistor M4 of the fourth current path are configured to have substantially the same size (e.g., substantially the same channel width W and channel length L). As a result, and due to the fact that the current flows in the first current path and the second current path, the third current path anda current mirror relationship between fourth current paths, the second current path, the third current path and the fourth current path being configured to generate and input the current signal I respectively_sigSubstantially identical replica currents I_sig1、I_sig2And I_sig3。

The positive terminal of the comparator has a very high impedance; therefore, substantially all of the replica current flows into the threshold current sink I, respectively_TH1-I_TH3. If the replica current is below the corresponding threshold current, the voltage on the corresponding positive terminal of the corresponding comparator is substantially Vss (voltage at the low voltage rail). Conversely, if the replica current is higher than the corresponding threshold current, the voltage on the corresponding positive terminal of the corresponding comparator is substantially Vdd (the voltage at the high voltage rail). As described above, the current sink is configured such that the current threshold I_TH3Greater than a current threshold I_TH2And in turn causing a threshold current I_TH2Greater than a threshold current I_TH1。

The reason why the voltage at the positive terminal of the corresponding comparator is Vss when the replica current is lower than the corresponding threshold current, and the voltage at the positive terminal of the corresponding comparator is Vdd when the replica current is higher than the corresponding threshold current is as follows: if the replica current is higher than the corresponding threshold current (e.g., I)_sig1-I_TH1> 0), the excess current flows through the equivalent resistance, which is the corresponding current source/sink (I) connected in parallel₀₂、M₂And I_TH1) The internal resistance of (1). Because the equivalent resistance of the current source/sink is relatively high, the small amount of excess current flowing through these devices causes the voltage at the positive terminal of the corresponding comparator (e.g., CMP1) to rise substantially to the rail voltage Vdd. On the other hand, if the replica current is below the corresponding threshold current (e.g., I)_sig1-I_TH1< 0), no excess current flows through the current source/sink (I)₀₂、M₂And I_TH1) The internal resistance of (1). Thus, the voltage at the positive terminal of the corresponding comparator (e.g., CMP1) is substantially Vss.

Thus, it is possible to provideIf a current signal I is input_sigBelow all current threshold I_TH1-I_TH3Then the voltage at the corresponding positive terminal of the comparator CMP1-CMP3 is substantially Vss, which is less than the threshold voltage Vdd/2 applied to the negative terminal of the comparator. Therefore, the output signals D3-D1 generated by the comparators CMP1-CMP3 are 000.

If the current signal I is input_sigAbove the first current threshold I_TH1But below the current threshold I_TH2And I_TH3Then the voltage at the positive terminal of comparator CMP1 is substantially Vdd and the voltages at the positive terminals of comparators CMP2 and CMP3 are substantially Vss. Thus, the comparator CMP1 output D1 is a logic one (1) and the comparators CMP2-CMP3 output D2-D3 are a logic zero (00). Thus, the output signals D3-D1 have a value of 001.

If the current signal I is input_sigAbove the first current threshold I_TH1And a second current threshold I_TH2But below the third current threshold I_TH3Then the voltage at the positive terminal of the comparator CMP1-CMP2 is substantially Vdd and the voltage at the positive terminal of the comparator CMP3 is substantially Vss. Thus, the comparator CMP1-CMP2 outputs D1-D2 are 11, and the comparator CMP3 output D3 is 0. Thus, the output signal has a value of 011.

Similarly, if the current signal I is input_sigAbove all current threshold I_TH1-I_TH3The voltage at the positive terminal of the comparator CMP1-CMP3 is then substantially Vdd, all above the threshold voltage Vdd/2 applied to the negative terminal of the comparator. Thus, the comparators CMP3-CMP1 generate output signals D3-D1 having a value of 111.

The current comparator 100 has several disadvantages. First, due to process variations, the current source I₀₁To I₀₄Substantially the same current is not generated and there is a mismatch between the transistors M1 through M4. As a result, the replica current I generated by the second current path, the third current path and the fourth current path_sig1To I_sig3May not be in contact with the input current signal I_sigAre substantially the same. Because the replica current I is generated_sig1To I_sig3There may be errors and thus the comparisons made by the comparators CMP1-CMP3 may also be erroneous. Thus, the output signals D3-D1 may not be as accurate as desired.

Secondly, for generating a replica current I_sig1To I_sig3Require a large number of components (e.g. current source I)₀₂-I₀₄And transistors M2-M4). This significantly increases the component count of the current comparator 100; thus, the integrated circuit footprint used to implement current comparator 100 may be undesirably large. Furthermore, current comparator 100 consumes a large amount of power due to the large number of components. Therefore, there is a need to improve accuracy, reduce the number of components, and reduce power consumption of current comparators.

Fig. 2 illustrates a schematic diagram of another example current comparator 200 in accordance with another aspect of the present disclosure. In summary, the current comparator 200 performs substantially the same operation as the current comparator 100 (e.g., inputs the current signal I_sigAnd three current thresholds I_TH1-I_TH3A comparison is made and an output signal is generated based on the comparison). However, as compared to using three current paths in the current comparator 100, the current comparator 200 uses only a single current path; therefore, the current comparator 200 is less likely to generate an output signal error because of the possible replica current mismatch in the current comparator 100. Additionally, because there is only a single current path in the current comparator 200, the current comparator 200 requires fewer components and consumes less power.

In particular, the current comparator 200 includes a first transistor M1 (e.g., NMOSFET), a second transistor M2 (e.g., p-channel MOSFET or PMOSFET), and a threshold current sink I between the high voltage rail Vdd and the low voltage rail Vss_TH3Threshold current source I coupled in series_TH1. The current comparator 200 further comprises a further threshold current sink I_TH2The threshold current sink I_TH2Is coupled between the input node (between the first transistor M1 and the second transistor M2) and the low voltage rail Vss. Similar to the current comparator 100, the threshold current sink I_TH3Absorbed electricityCurrent sink I with current greater than threshold_TH2Absorbed current and current source I_TH1Current sink I for sinking current less than threshold_TH2And I_TH3Current sink (e.g. I)_TH3＞I_TH2＞I_TH1). Input current signal I_sigIs applied to an input node between the first transistor M1 and the second transistor M2. Although the input current I is shown in FIG. 2_sigInto the current comparator 200, but it should be understood that the input current I_sigMay flow into and/or out of the current comparator 200.

The current comparator 200 further comprises a set of comparators CMP1-CMP 3. Comparators CMP1-CMP3 each include a negative input terminal configured to receive a threshold voltage, which may be set to Vdd/2. The positive terminal of the comparator CMP1 is coupled to a current source I at the threshold_TH1And the first transistor M1. The positive terminal of the comparator CMP2 is coupled to the input node between the first transistor M1 and the second transistor M2. The positive terminal of the comparator CMP3 is coupled to the second transistor M2 and the threshold current sink I_TH3A node in between. The comparators CMP3-CMP1 are configured to generate bits of the output signals D3-D1, respectively.

Additionally, the current comparator 200 includes an inverter I having an input coupled to the output of the second comparator CMP 2. The inverter I includes an output coupled to the gates of the first transistor M1 and the second transistor M2.

In operation, if the current signal I_sigBelow a second threshold current I_TH2Then the voltage at the positive input terminal of the second comparator CMP2 is substantially Vss, which is lower than the threshold voltage Vdd/2 applied to the negative input terminal of the second comparator CMP 2. Thus, the second comparator CMP2 output D2 is a "0" or low logic voltage (e.g., substantially Vss). Inverter I inverts "0" and generates a "1" or high logic voltage (e.g., substantially Vdd). The high logic voltage generated by inverter I and applied to the gates of transistors M1 and M2 causes transistor M1 to turn on and transistor M2 to turn off.

FIG. 3A illustrates the input current signal I_sigBelow a second current threshold I_TH2A schematic diagram of an exemplary equivalent circuit of the current comparator 200. When the transistor M2 is turned off, the transistor M2, the threshold current sink I_TH3And the third comparator CMP3 is effectively disabled; and thus these devices can be removed from the equivalent circuit. Additionally, since transistor M1 is on, it can be represented in an equivalent circuit as a threshold current source I_TH1Directly coupled to a threshold current sink I_TH2Short-circuiting of (2). Since the states of the comparator CMP2 and the output of inverter I are known, these devices can also be removed from the equivalent circuit.

Thus, the equivalent circuit includes a threshold current sink I between the high voltage rail Vdd and the low voltage rail Vss_TH2Threshold current source I coupled in series_TH1. Input signal I_sigIs applied to a current source I at the threshold value_TH1And a threshold current sink I_TH2An input node in between. The positive input terminal of the first comparator CMP1 is coupled to the input node. The negative input terminal of the first comparator CMP1 receives a threshold voltage Vdd/2.

Thus, the first comparator CMP1 generates D1 as a logical one (1) if the following relationship applies:

I_sig+I_TH1>I_TH2or I_sig>I_TH2–I_TH1

Otherwise, the first comparator CMP1 generates D1 as a logic zero (0). Therefore, when inputting the signal I_sigBelow a second current threshold I_TH2The states D2 and D3 of the output signal are logic zero (0), and the state D1 of the output signal depends on the input current signal I_sigWhether or not it is greater than the current threshold I_TH2And I_TH1The difference between them.

If the current signal I_sigAbove a second threshold current I_TH2Then the voltage at the positive input terminal of the second comparator CMP2 is substantially Vdd, which is higher than the threshold voltage Vdd/2 applied to the negative input terminal of the second comparator CMP 2. Thus, the output D2 of the second comparator CMP2 is "1 "or a high logic voltage (e.g., substantially Vdd). Inverter I inverts the "1" and generates a "0" or low logic voltage (e.g., substantially Vss). The low logic voltage generated by inverter I and applied to the gates of transistors M1 and M2 causes transistor M1 to turn off and transistor M2 to turn on.

FIG. 3B illustrates the input current signal I_sigAbove a second current threshold I_TH2A schematic diagram of an exemplary equivalent circuit of the time current comparator 200. When the transistor M1 is turned off, the transistor M1, the threshold current source I_TH1And the first comparator CMP1 is effectively disabled; therefore, these devices can be removed from the equivalent circuit. Additionally, since transistor M2 is on, it may be represented in an equivalent circuit as directly coupling the input node to the threshold current sink I_TH3Short-circuiting of (2). Since the states of the comparator CMP2 and the output of inverter I are known, these devices can also be removed from the equivalent circuit.

Thus, the equivalent short circuit includes a threshold current sink I coupled in parallel between the input node and the low voltage rail Vss_TH2And I_TH3. Input signal I_sigIs applied to the input node. The positive input terminal of the third comparator CMP3 is coupled to the input node. The negative input terminal of the third comparator CMP3 receives the threshold voltage Vdd/2.

Thus, the third comparator CMP3 generates D3 as a logical one (1) if the following relationship applies:

I_sig＞I_TH2+I_TH3

otherwise, the third comparator CMP3 generates D3 as a logic zero (0). Therefore, when inputting the signal I_sigAbove a second current threshold I_TH2The states D1 and D2 of the output signal are logic ones (1), and the state D3 of the output signal depends on the input current signal I_sigWhether or not it is greater than current threshold I_TH2And I_TH3The sum of (a) and (b).

Referring again to FIG. 2, the current comparator 200 is based on the input current and the current threshold I_TH2Is compared with the input current I_sigRedirection to the appropriate comparator CMP1 or CMP3. For example, if the input current I is determined_sigBelow a second threshold current I_TH2The second comparator CMP2 directs the input current to the first comparator CMP1 via the inverter I and the first and second transistors M1 and M2 for matching (when blocking the input current applied to the third comparator CMP 3) the input current with the threshold current I_TH2And I_TH1The difference in (a) is compared. Similarly, if the input current I is determined_sigAbove a second threshold current I_TH2The second comparator CMP2 inputs the current I via the inverter I and the first and second transistors M1 and M2_sigIs directed to the third comparator CMP3 for comparing the input current (when the blocking input current is applied to the first comparator CMP1) with the threshold current I_TH2And I_TH3The sum of (a) and (b) are compared.

It can be seen that the current comparator 200 has a single current path, which may be based on the input current I_sigAnd a second threshold current I_TH2Is reconfigured. This will result in a more accurate comparison since there is no need to copy the input current, which, as discussed, is prone to errors, and the input current I_sigIs used directly to perform the required comparison. Furthermore, since there is only a single current path, current comparator 200 includes fewer components than current comparator 100. Thus, current comparator 200 requires less integrated circuit footprint to implement and consumes less power than current comparator 100.

Although in the above example the input current is compared to three (3) thresholds, it will be appreciated that a current comparator implementing the concepts described above may be adapted to compare the input current to more than three (3) thresholds.

Fig. 4 illustrates a block diagram of an exemplary voltage control circuit 400 in accordance with another aspect of the present disclosure. In this example, the voltage control circuit 400 is configured to control or regulate a supply voltage for a Power Amplifier (PA). However, it should be understood that voltage control circuit 400 may be configured to control or regulate any voltage at a particular node.

The current comparator 200 discussed above may be used in many applications, one of which is to control the supply voltage Vs for a Power Amplifier (PA). More specifically, the current comparator 200 may be used to control the supply voltage Vs for the PA such that the supply voltage Vs substantially tracks the envelope of the input or output signal of the PA, or varies the supply voltage Vs in any desired manner.

In particular, the voltage control circuit 400 includes: a Power Amplifier (PA)410 (which may be generally any load); a controller 420; a linear amplifier 430 including an output capacitor C and having a feedback capacitor C_fbParallel coupled feedback resistor R_fbThe feedback network of (2); a current comparator 440; a decoder 450; a DC-to-DC converter 460 including an inductor L; and an antenna 470. In this example, current comparator 440 may be configured similar to current comparator 200 but with some modifications as described below.

Input voltage signal V_inIs applied to the input of the PA 410. The PA 410 is configured to amplify an input voltage signal V_inTo generate an output voltage signal V_out. Output voltage signal V_outIs applied to the antenna 470 for generating wireless signals. PA 410 is coupled between a high voltage rail and a low voltage rail Vss, the high voltage rail receiving a variable supply voltage Vs. The remaining components of the voltage control circuit 400 generate and control the supply voltage Vs such that the supply voltage Vs may substantially track the input voltage signal V_inEnvelope or output voltage signal V_outIf the gain of the PA is substantially constant, for example, or in any desired manner. Such variation of the supply voltage Vs may be performed in a manner that improves power efficient operation of the PA 410.

To generate the supply voltage Vs for the PA 410, an input voltage signal V is applied, for example, using a directional coupler_inSample V of_isIs provided to the controller 420. The controller 420 processes the sampled signal V_isTo determine the input voltage signal V_inThe envelope of (c). Power controller 420 is based on input voltage signal V_inEnvelope generation control voltage V_tgt/G，And will control the voltage V_tgtthe/G is applied to the positive input terminal of the linear amplifier 430, where V_tgtIs the target supply voltage for supply voltage Vs and G is the gain of linear amplifier 430. As discussed further herein, the controller 420 also generates a threshold control signal th _ set and sends the threshold control signal th _ set to the current comparator 440 to set its current threshold. The linear amplifier 430 is based on a feedback voltage at the negative input of the linear amplifier 430 and a control voltage V_tgtComparison of/G to generate or sink a current I_ampTo keep track of the input voltage signal V_inThe power supply voltage Vs of the envelope PA 410.

Current I_ampSample I of_{amp_scaled}Is applied to the input of current comparator 440. Can be derived from the current I via current mirroring_ampGenerating a sampled current I_{amp_scaled}In which the current I is sampled_{amp_scaled}And current I_ampThe ratio is less than one (1) to reduce power consumption for the voltage control circuit 400. The current comparator 440 will sample the current I_{amp_scaled}And a low current threshold I_{TH_N}And a high current threshold I_{TH_P}A comparison is made and an output signal is generated that includes bits cmp _ h, cmp _ m, and cmp _ l. Low current threshold I_{TH_N}And a high current threshold I_{TH_P}Is programmable and is set by a threshold control signal th _ set generated by the controller 420. The decoder 450 decodes the bits cmp _ h, cmp _ m, cmp _ l from the output of the current comparator 440 and generates the control signal etdrv for the DC-to-DC converter 460<1:0>. As discussed in further detail below, the DC-to-DC converter 460 may be configured as a buck converter or a Switched Mode Power Supply (SMPS), and generates most of the power for the PA 410, based on the control signal etdrv<1:0>Generating a voltage VSW.

Fig. 4B illustrates a schematic diagram of a current comparator 440 in accordance with another aspect of the present disclosure. Current comparator 440 is similar to current comparator 200 except for threshold current sink I_TH2Set to zero (0) current; or, in fact, a threshold current sink I_TH2Not present in current comparator 440. At the intermediate threshold currentI_TH2With the setting to zero (0), the current comparator 440 will sample the amplifier current I_{amp_scaled}And positive threshold current I_{TH_P}And a negative threshold current I_{TH_N}A comparison is made.

In particular, the current comparator 440 includes a threshold current source I_{TH_N}A first transistor M1 (e.g., NMOSFET), a second transistor M2 (e.g., PMOSFET), and a threshold current sink I_{TH_P}All devices are coupled in series between a high voltage rail Vdd and a low voltage rail Vss. The current comparator 440 further includes a set of comparators CMP1-CMP3, each comparator including a negative input terminal configured to receive a threshold voltage, the threshold voltage being set at Vdd/2.

The first comparator CMP1 comprises a positive input terminal coupled to a current source I at threshold value_{TH_N}And the first transistor M1. The second comparator CMP2 comprises a positive input terminal coupled to the input node between the first transistor M1 and the second transistor M2, the sampled amplifier current I_{amp_scaled}Is applied at the node. The third comparator CMP3 comprises a positive input terminal coupled to the second transistor M2 and the threshold current sink I_{TH_P}A node in between. The first comparator CMP1, the second comparator CMP2, and the third comparator CMP3 generate bits CMP _ l, CMP _ m, and CMP _ h of the output signal of the current comparator 440, respectively.

The current comparator 440 further comprises an inverter I comprising an input coupled to the output of the second comparator CMP2 and an output coupled to the gates of the transistor M1 and the transistor M2.

In operation, if the amplifier current I is sampled_{amp_scaled}Being negative (flowing from the current comparator 440), the second comparator CMP2 generates CMP _ m as a logic zero (0) (e.g., substantially Vss) that is applied to the input of the inverter I. Inverter I inverts logic zero (0) to generate a logic one (1) (e.g., substantially Vdd), which is applied to the gates of transistors M1 and M2. As a result, the transistor M1 turns on and the transistor M2 turns off. Therefore, the temperature of the molten metal is controlled,the comparison performed by the first comparator CMP1 is the sampled amplifier current I_{amp_scaled}Whether or not to exceed the current threshold I_{TH_N}More negative. If sampled amplifier current I_{amp_scaled}Specific current threshold I_{TH_N}More negative, the first comparator CMP1 generates CMP _ l as a logic zero (0). If sampled amplifier current I_{amp_scaled}Specific current threshold I_{TH_N}Weakly negative, the first comparator CMP1 generates CMP _ l as a logic one (1).

If sampled amplifier current I_{amp_scaled}Being positive (flowing into current comparator 440), second comparator CMP2 generates CMP _ m as a logic one (1) (e.g., substantially Vdd) that is applied to the input of inverter I. Inverter I inverts logic one (1) to generate a logic zero (0) (e.g., substantially Vss), which is applied to the gates of transistors M1 and M2. As a result, the transistor M1 turns off and the transistor M2 turns on. The comparison performed by the third comparator CMP3 is thus the sampled amplifier current I_{amp_scaled}Whether or not to exceed the current threshold I_{TH_P}And (6) correcting. If sampled amplifier current I_{amp_scaled}Less than current threshold I_{TH_P}Then the third comparator CMP3 generates CMP _ h as logic zero (0). If sampled amplifier current I_{amp_scaled}Greater than the current threshold ITH _ P, the third comparator CMP3 generates CMP _ h as a logic one (1).

Fig. 4C illustrates a table for mapping the output signals (cmp _ h, cmp _ m, cmp _ l) of the current comparator 440 to the output signals (etdrv <1> and etdrv <0>) of the decoder 450 to the output voltage VSW of the DC-to-DC converter 460 according to another aspect of the present disclosure.

As indicated, when the output signals (cmp _ h, cmp _ m, cmp _ l) of the current comparator 440 are 000, it means that the amplifier 430 is sinking beyond the sinking threshold (corresponding to I_{TH_N}) The decoder 450 generates its output signal (etdrv)<1:0>) At 00, to instruct the DC-to-DC converter 460 to generate its output voltage VSW at zero (0) volts. When the supply voltage Vs is significantly higher than the target supply voltage V_tgtAnd linear amplifier 430 is sinking current above the sinking current threshold and voltage VSW is zero (0) volts, this occurs such thatThe current provided by the DC-to-DC converter 460 to the PA 410 is decreasing, and these two actions work together to decrease the supply voltage Vs.

When the output signal (cmp _ h, cmp _ m, cmp _ l) of the current comparator 440 changes state from 000 to 001, meaning that the amplifier 430 is sinking current but not exceeding the sinking threshold, and the sinking current is decreasing, the decoder 450 keeps its output signal (etdrv)<1:0>) 00 to continue to instruct the DC-to-DC converter 460 to generate its output voltage VSW at zero (0) volts. Thirdly, when the power voltage Vs is higher than the target power voltage V_tgtAnd both the amplifier 430 and the DC-to-DC converter 460 work together to further reduce the supply voltage Vs.

When the output signals (cmp _ h, cmp _ m, cmp _ l) of the current comparators 440 change state from 001 to 011, meaning that the amplifier 430 has stopped sinking current and is providing current, the decoder 450 generates its output signal (etdrv)<1:0>) To 01, the DC-to-DC converter 460 is instructed to generate the output voltage VSW at a voltage substantially equal to the battery voltage VBAT. When the power supply voltage Vs is less than the target power supply voltage V_tgtThis occurs. The voltage VSW is brought to VBAT such that the current provided to the PA 410 by the DC-to-DC converter 460 does not decrease rapidly (it may or may not increase). This will reduce the rate at which the amplifier 430 must supply current. Both actions work together to reduce the voltage V relative to the target supply voltage_tgtIs detected in the power supply voltage Vs.

When the output signals (cmp _ h, cmp _ m, cmp _ l) of the current comparators 440 change state from 011 to 111, meaning that the amplifier 430 is providing current exceeding the supply threshold, the decoder 450 generates its output signal (etdrv)<1:0>) To 11, to instruct the DC-to-DC converter 460 to generate its output voltage VSW at an auxiliary voltage VAUX that is higher than the battery voltage VBAT. When the supply voltage VS is significantly lower than the target supply voltage V_tgtAnd linear amplifier 430 is providing current above the supply current threshold and voltage VSW is VAUX, such that the current provided to PA 410 by DC-to-DC converter 460 is increasing, both actions working together to increase supply voltage Vs.

When the output signals (cmp _ h, cmp _ m, cmp _ l) of the current comparators 440 change state from 111 to 011, meaning that the amplifier 430 is providing current but not exceeding the supply threshold and the supply current is decreasing, the decoder 450 keeps its output signal (etdrv)<1:0>) To 11, to instruct the DC-to-DC converter 460 to maintain its output voltage VSW at VAUX. When the power supply voltage Vs is lower than the target power supply voltage V_tgtBut is increasing and linear amplifier 430 is providing current and voltage VSW is VAUX, such that the current provided to PA 410 by DC-to-DC converter 460 is increasing, both actions working together to increase supply voltage Vs.

When the output signals (cmp _ h, cmp _ m, cmp _ l) of the current comparators 440 change state from 011 to 001, meaning that the amplifier 430 has stopped providing current and is sinking current, the decoder 450 generates its output signal (etdrv)<1:0>) To 01, to instruct the DC-to-DC converter to generate its output voltage VSW at VBAT. When the power supply voltage Vs is greater than the target power supply voltage V_tgtThis occurs. The voltage VSW is brought to VBAT so that the current provided by the DC-to-DC converter 460 to the PA 410 does not increase rapidly (it may or may not decrease). This will reduce the rate at which the amplifier 430 must sink current. Both actions work together to reduce the voltage V relative to the target supply voltage_tgtIs detected in the power supply voltage Vs.

When the output signals (cmp _ h, cmp _ m, cmp _ l) of the current comparators 440 change state from 001 to 000, meaning that the amplifier 430 is sinking a current that exceeds the sinking threshold, the decoder 450 generates its output signal (etdrv <1:0>) to 00 to instruct the DC-to-DC converter 460 to generate its output voltage VSW at 0V. The process continues to repeat.

Fig. 4D illustrates another table mapping the output of the decoder 450, etdrv <1:0>, to the output voltage VSW of the DC-to-DC converter 460, according to another aspect of the present disclosure. The table summarizes only the above description regarding mapping the output of the decoder 450 to the output voltage VSW of the DC-to-DC converter 460. That is, when the decoder 450 generates etdrv <1:0> as 00, this instructs the DC-DC converter 460 to generate its output voltage VSW at 0V. When the decoder 450 generates etdrv <1:0> as 01, this instructs the DC-DC converter 460 to generate its output voltage VSW at VBAT. When the decoder 450 generates etdrv <1:0> as 11, this instructs the DC-to-DC converter 460 to generate its output voltage VSW at VAUX.

Fig. 4E illustrates a graph of the various signals described above with respect to the operation of voltage control circuit 400 versus time, in accordance with another aspect of the present disclosure. The top part of the graph illustrates the current threshold I relative to positive_{TH_P}And a negative current threshold I_{TH_N}Sampled amplifier current I_{amp_scaled}A change in (c). As discussed above, when the amplifier current I is sampled_{amp_scaled}Greater than 0 or positive, amplifier 430 is drawing current I_ampTo the high voltage rail of PA 410. When the amplifier current I is sampled_{amp_scaled}Less than 0 or negative, amplifier 430 is sourcing current I_ampSinking away from the high voltage rail of PA 410.

The second part from the top of the graph illustrates the state of the output signals (cmp _ h, cmp _ m, cmp _ l) of the current comparator 440. As discussed, when the output signal of current comparator 440 is 000, amplifier 430 is sinking past the sinking threshold (I)_{TH_N}) The current of (2). This is indicated in the first and seventh columns of the graph. When the output signal of current comparator 440 is 001, amplifier 430 is sinking no more than the sinking threshold (I)_{TH_N}) The current of (2). This is indicated in the second and sixth columns of the graph. When the output signal of the current comparator 440 is 011, the amplifier 430 is providing no more than the supply threshold (I)_{TH_P}) The current of (2). This is indicated in the third and fifth columns of the graph. Also, when the output signal of the current comparator 440 is 111, the amplifier 430 is providing a voltage exceeding the supply threshold (I)_{TH_P}) The current of (2). This is indicated in the fourth column of the graph.

The bottom part of the graph illustrates the output signal etdrv of the decoder 450<1:0>And the state of the corresponding output voltage VSW of the DC-to-DC converter 460. As discussed, when amplifier 430 is absorbing beyond the absorption threshold (I), as indicated in the first and seventh columns of the graph_{TH_N}) At the current of (d), the output signal etdrv of the decoder 450<1:0>00 to instruct the DC-to-DC converter 460 to generate its output voltage VSW at 0V. Additionally, as indicated in the second column of the graph, when the amplifier 430 is absorbing no more than the absorption threshold (I)_{TH_N}) And the sink current is decreasing, the output signal etdrv of the decoder 450<1:0>Also 00, to instruct the DC-to-DC converter 460 to maintain its output voltage VSW at 0V.

As indicated in the third column of the graph, when the amplifier 430 is providing no more than the supply threshold (I)_{TH_P}) And the supply current is increasing, the output signal etdrv of the decoder 450<1:0>To 01, to instruct the DC-to-DC converter 460 to maintain its output voltage VSW at VBAT. As indicated in the fourth column of the graph, when the amplifier 430 is providing more than the supply threshold (I)_{TH_P}) At the current of (d), the output signal etdrv of the decoder 450<1:0>To 11, to instruct the DC-to-DC converter 460 to generate its output voltage VSW at VAUX. As indicated in the fifth column of the graph, when the amplifier 430 is providing no more than the supply threshold (I)_{TH_P}) And the supply current is decreasing, the output signal etdrv of the decoder 450<1:0>To 11, to instruct the DC-to-DC converter 460 to maintain its output voltage VSW at VAUX. As indicated in the sixth column of the graph, when amplifier 430 is absorbing no more than the absorption threshold (I)_{TH_N}) And the sink current is increasing, the output signal etdrv of the decoder 450<1:0>Is 01 to instruct the DC-to-DC converter 460 to generate its output voltage VSW at VBAT.

Fig. 4F illustrates a state diagram of various signals associated with the voltage control circuit 400 in accordance with another aspect of the disclosure. The state diagram also summarizes the operations discussed above. Each state (represented by an ellipse) includes three vertically stacked parameters. The top parameters are the output signals (cmp _ h, cmp _ m, cmp _ l) of the current comparator 440. The intermediate parameter is the output signal etdrv <1:0> of the decoder 450. And, the bottom parameter is the output voltage VSW of the DC-to-DC converter 460.

The first (leftmost ellipse) state relates to the amplifier 430 being operatedAbsorption exceeds the absorption threshold (I)_{TH_N}) Time period of the current. In this state, the output signals (cmp _ h, cmp _ m, cmp _ l) of the current comparator 440 are 000, and the output signal etdrv of the decoder 450<1:0>Is 00 and the output voltage VSW of the DC-to-DC converter 460 is 0V. From this state, voltage control circuit 400 enters the state where amplifier 430 is absorbing no more than the absorption threshold (I)_{TH_N}) And sink the state in which the current is decreasing (upper left ellipse). In this state, the output signals (cmp _ h, cmp _ m, cmp _ l) of the current comparator 440 are 001, and the output signal etdrv of the decoder 450 is<1:0>Still 00 and the output voltage VSW of the DC-to-DC converter 460 is still 0V.

From this state, voltage control circuit 400 enters amplifier 430 and is providing no more than the supply threshold (I)_{TH_P}) And the supply current is increasing (upper right ellipse). In this state, the output signals (cmp _ h, cmp _ m, cmp _ l) of the current comparators 440 are 011, and the output signal etdrv of the decoder 450 is 011<1:0>Is 01, and the output voltage VSW of the DC-to-DC converter 460 is now VBAT. From this state, voltage control circuit 400 enters amplifier 430 and is providing a voltage exceeding the supply threshold (I)_{TH_P}) The current state (rightmost ellipse). In this state, the output signals (cmp _ h, cmp _ m, cmp _ l) of the current comparator 440 are 111, and the output signal etdrv of the decoder 450 is 111<1:0>Is 11 and the output voltage VSW of the DC-to-DC converter 460 is now VAUX.

From this state, voltage control circuit 400 enters amplifier 430 and is providing no more than the supply threshold (I)_{TH_P}) And the supply current is decreasing (lower right ellipse). In this state, the output signals (cmp _ h, cmp _ m, cmp _ l) of the current comparators 440 are 011, and the output signal etdrv of the decoder 450 is 011<1:0>Still 11, and the output voltage VSW of the DC-to-DC converter 460 is still VAUX. From this state, voltage control circuit 400 enters the state where amplifier 430 is sinking no more than the sinking threshold (I)_{TH_N}) And sink the state in which the current is decreasing (lower left ellipse). In this state, the output signals (cmp _ h, cmp _ m, cmp _ l) of the current comparator 440 are 001, and the decoder450 of the output signal etdrv<1:0>Is 01, and the output voltage VSW of the DC-to-DC converter 460 is now VBAT. From this state, voltage control circuit 400 enters the first (leftmost ellipse) state and the process repeats.

By varying the signal V based on the input voltage_inControl voltage V of_tgt/G, the controller 420 can vary the supply voltage Vs for the PA 410 to track the input voltage signal V_inOr output voltage signal V_outOr the supply voltage Vs is varied in any desired manner.

The controller 420 may be able to regulate the positive current threshold I via the threshold control signal th _ set_{TH_P}And a negative current threshold I_{TH_N}Programming is performed. The controller 420 may set a positive current threshold I_{TH_P}And a negative current threshold I_{TH_N}The placement is far apart so that the current generated by the DC-to-DC converter 460 ramps slowly, reducing noise in the supply voltage Vs at the expense of power efficiency. Conversely, the controller 420 may set a positive current threshold I_{TH_P}And a negative current threshold I_{TH_N}Are disposed relatively close to each other such that the current generated by the DC-to-DC converter 460 ramps faster to improve power efficiency when increasing noise in the supply voltage Vs. Therefore, the threshold control signal th _ set can be set to achieve a desired trade-off between power efficiency and noise in the supply voltage Vs.

Fig. 5 illustrates a flow chart of an example method 500 of comparing an input current (e.g., a first current) to a set of current thresholds (e.g., a second current and a third current), according to another aspect of the present disclosure.

The method 500 includes generating a first output signal based on a comparison of a first current and at least a second current (block 510). An example of an apparatus for generating a first output signal based on a comparison of a first current with at least a second current comprises comparator CMP1 of current comparators 200 or 440.

The method 500 further includes generating a second output signal based on a comparison of the first current and at least a third current (block 520). An example of an apparatus for generating a second output signal based on a comparison of a first current and at least a third current comprises comparator CMP3 of current comparators 200 or 440.

The method 500 further includes enabling the comparison of the first current to the at least second current when the comparison of the first current to the at least third current is disabled (block 530). Examples of means for enabling the means for comparing the first current with the at least second current when the means for comparing the first current with the at least third current is disabled include a comparator CMP2, an inverter I, and a transistor M1 configured to turn on and a transistor M2 configured to turn off.

Alternatively, method 500 includes enabling the comparison of the first current to the at least third current when the comparison of the first current to the at least second current is disabled (block 540). Examples of means for enabling the means for comparing the first current with the at least third current when the means for comparing the first current with the at least second current is disabled include a comparator CMP2, an inverter I, and a transistor M1 configured to turn off and a transistor M2 configured to turn on.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.