阅读说明：本技术 数据处理方法、数据处理装置和计算装置 (Data processing method, data processing device and computing device ) 是由 武杨 于 2020-12-07 设计创作，主要内容包括：一种数据处理方法、数据处理装置和计算装置。该数据处理方法包括：接收将对象缓存行替换出缓冲存储器的替换指令,对象缓存行包括对象数据；基于对象缓存行生成数据包,数据包包括对象数据以及第一标注位；至少基于第一标注位的值,执行将对象数据写入并列缓冲存储器中的操作以及将对象数据写入非易失性主存储器中的操作的至少一项。该数据处理方法可以在提升数据安全性的情况下优化性能。(A data processing method, a data processing device and a computing device are provided. The data processing method comprises the following steps: receiving a replacement instruction to replace an object cache line out of the buffer memory, the object cache line including object data; generating a data packet based on the object cache line, wherein the data packet comprises object data and a first marking bit; at least one of an operation of writing the object data into the parallel buffer memory and an operation of writing the object data into the nonvolatile main memory is performed based on at least the value of the first flag. The data processing method can optimize performance under the condition of improving data security.)

1. A method of data processing, comprising:

receiving a replacement instruction to replace an object cache line out of a buffer memory, wherein the object cache line comprises object data;

generating a data packet based on the object cache line, wherein the data packet comprises the object data and a first marking bit; and

at least one of writing the object data into a parallel buffer memory and writing the object data into a non-volatile main memory is performed based on at least a value of the first flag.

2. The data processing method of claim 1, wherein the value of the first tagging bit is a first value or a second value different from the first value; and

the performing at least one of the operation of writing the object data into a parallel buffer memory and the operation of writing the object data into a non-volatile main memory based on at least the value of the first flag bit includes:

in response to the value of the first flag bit being the first value, performing an operation of writing the object data into the parallel buffer memory, and

in response to the value of the first flag bit being the second value, an operation of writing the object data into the parallel buffer memory is not performed.

3. The data processing method of claim 2, wherein the data packet further comprises a second flag bit;

the value of the second flag bit is selected from the first value and the second value; and

the performing at least one of the operation of writing the object data into a parallel buffer memory and the operation of writing the object data into a non-volatile main memory based on at least the value of the first flag bit further comprises:

in response to the value of the second flag bit being the first value, performing an operation to write the object data into the non-volatile main memory, and

in response to the value of the second flag bit being the second value, an operation of writing the object data into the nonvolatile main memory is not performed.

4. A data processing method as claimed in claim 3, wherein the value of the first flag bit and the value of the second flag bit are not equal to the second value at the same time.

5. The data processing method of claim 3 or 4, wherein the object cache line further comprises a third flag bit and a fourth flag bit;

the third flag bit is configured to identify whether it is desired to write the data in the object cache line into the parallel buffer memory when the object cache line is replaced out of the buffer memory;

the fourth flag bit is configured to identify whether it is desired to write the data in the object cache line into the non-volatile main memory when the object cache line is replaced out of the cache memory; and

the data processing method further comprises:

receiving a tag instruction for the object cache line, an

Setting a value of the third flag bit and a value of the fourth flag bit based on the tag instruction in response to the object cache line loading data.

6. The data processing method of claim 5, wherein said setting the value of the third flag bit and the value of the fourth flag bit based on the marker instruction comprises:

causing the value of the third flag bit and the value of the fourth flag bit to be selected from the first value and the second value, and causing the value of the third flag bit and the value of the fourth flag bit to not be equal to the second value at the same time.

7. The data processing method of claim 5, wherein the generating a data packet based on the object cache line comprises:

generating the data packet based on the object data, the value of the third flag bit and the value of the fourth flag bit, and matching the value of the first flag bit and the value of the second flag bit with the value of the third flag bit and the value of the fourth flag bit, respectively.

8. The data processing method of claim 7, wherein said causing the value of the first flag bit and the value of the second flag bit to match the value of the third flag bit and the value of the fourth flag bit, respectively, comprises: and enabling the value of the first marking bit to be equal to the value of the third flag bit, and enabling the value of the second marking bit to be equal to the value of the fourth flag bit.

9. The data processing method of claim 2, wherein the performing at least one of the writing of the object data to a parallel buffer memory and the writing of the object data to a non-volatile main memory based at least on the value of the first flag bit further comprises:

in response to the value of the first flag bit being the first value, performing no operation to write the object data into the non-volatile main memory;

in response to the value of the first flag bit being the second value, an operation of writing the object data into the parallel buffer memory is performed.

10. A data processing apparatus comprising: a controller, a buffer memory, a parallel buffer memory, and an interface coupled to the non-volatile main memory,

wherein the controller is configured to:

receiving a replacement instruction to replace an object cache line out of a buffer memory, wherein the object cache line comprises object data;

generating a data packet based on the object cache line, wherein the data packet comprises the object data and a first marking bit; and

performing at least one of an operation of writing the object data into the parallel buffer memory and an operation of transferring the object data to the interface based on at least a value of the first flag bit, wherein the performing of the operation of transferring the object data to the interface allows the object data to be written into the non-volatile main memory via the interface.

11. The data processing apparatus according to claim 10, wherein the value of the first tagging bit is a first value or a second value different from the first value; and

the performing at least one of an operation of writing the object data into the parallel buffer memory and an operation of transferring the object data to the interface based on at least the value of the first flag bit includes:

in response to the value of the first flag bit being the first value, performing an operation of writing the object data into the parallel buffer memory, and

in response to the value of the first flag bit being the second value, an operation of writing the object data into the parallel buffer memory is not performed.

12. The data processing apparatus of claim 11, wherein the data packet further comprises a second flag bit;

the value of the second flag bit is selected from the first value and the second value; and

the performing at least one of an operation of writing the object data into a parallel buffer memory and an operation of transferring the object data to the interface based on at least a value of the first flag bit, further includes:

responsive to the value of the second flag bit being the first value, performing an operation to pass the object data to the interface, an

In response to the value of the second flag bit being the second value, no operation is performed to transfer the object data to the interface.

13. The data processing apparatus according to claim 12, wherein the value of the first flag bit and the value of the second flag bit are not equal to the second value at the same time.

14. The data processing apparatus according to claim 12 or 13, wherein the object cache line further comprises a third flag bit and a fourth flag bit;

the third flag bit is configured to identify whether it is desired to write the data in the object cache line into the parallel buffer memory when the object cache line is replaced out of the buffer memory;

the fourth flag bit is configured to identify whether it is desired to transfer data in the object cache line to the interface when the object cache line is replaced out of the cache memory; and

the controller is further configured to: receiving a tag instruction for the object cache line, and setting a value of the third flag bit and a value of the fourth flag bit based on the tag instruction in response to the object cache line loading data.

15. The data processing apparatus of claim 14, wherein said setting the value of the third flag bit and the value of the fourth flag bit based on the marker instruction comprises:

causing the value of the third flag bit and the value of the fourth flag bit to be selected from the first value and the second value, and causing the value of the third flag bit and the value of the fourth flag bit to not be equal to the second value at the same time.

16. A computing device comprising the data processing apparatus according to any of claims 10-15 and the non-volatile main memory, wherein the non-volatile main memory is coupled to the data processing apparatus via the interface.

Technical Field

Embodiments of the present disclosure relate to a data processing method, a data processing apparatus, and a computing apparatus.

Background

Because the operating frequency of the CPU core is much higher than that of the main memory, it is necessary to wait for tens of clock cycles or even hundreds of clock cycles to directly obtain data from the main memory, which often causes the CPU core to idle due to the fact that the CPU core cannot continue to operate related instructions, and thus causes performance loss of the CPU core.

To reduce the performance loss of the CPU core, a multi-level cache architecture may be employed. For example, a buffer memory (Cache, having a plurality of Cache lines) having a high access speed buffer may be provided between the CPU core and the main memory, and the buffer memory is used to hold a portion of data that has been recently accessed or recycled. If the CPU needs to use the part of data, the part of data can be directly acquired from the buffer memory, so that the waiting time of the CPU is reduced, and the efficiency of the CPU is improved.

When the CPU core reads data, if the target data of an access request output by the CPU core is not in the cache memory (e.g., the first-level cache memory), that is, a cache miss occurs in the cache memory, it is necessary to acquire the target data of the access request from the memory device of the next level (e.g., the second-level cache memory) and write the acquired target data of the access request into the cache memory in which the cache miss occurs.

However, in the case that the cache memory has no available space, before writing the target data of the access request to the cache memory in which the cache miss occurs, a cache line in the cache memory in which the cache miss occurs needs to be moved out of the cache memory in which the cache miss occurs, and the moved cache line is called an innocent person (victim); the above process of removing a cache line from the cache memory to make room for new data is referred to as cache replacement.

Disclosure of Invention

At least one embodiment of the present disclosure provides a data processing method, including: receiving a replacement instruction to replace an object cache line out of a buffer memory, wherein the object cache line comprises object data; generating a data packet based on the object cache line, wherein the data packet comprises the object data and a first marking bit; and performing at least one of an operation of writing the object data into a parallel buffer memory and an operation of writing the object data into a nonvolatile main memory based on at least a value of the first flag.

For example, in at least one example of the data processing method, the value of the first tagging bit is a first value or a second value different from the first value. The performing at least one of the operation of writing the object data into a parallel buffer memory and the operation of writing the object data into a non-volatile main memory based on at least the value of the first flag bit includes: in response to the value of the first flag bit being the first value, performing an operation of writing the object data into the parallel buffer memory, and in response to the value of the first flag bit being the second value, not performing an operation of writing the object data into the parallel buffer memory.

For example, in at least one example of the data processing method, the data packet further includes a second flag bit; the value of the second flag bit is selected from the first value and the second value. The performing at least one of the operation of writing the object data into a parallel buffer memory and the operation of writing the object data into a non-volatile main memory based on at least the value of the first flag bit further comprises: performing an operation of writing the object data into the non-volatile main memory in response to the value of the second flag bit being the first value, and not performing the operation of writing the object data into the non-volatile main memory in response to the value of the second flag bit being the second value.

For example, in at least one example of the data processing method, the value of the first flag bit and the value of the second flag bit are not equal to the second value at the same time.

For example, in at least one example of the data processing method, the object cache line further includes a third flag bit and a fourth flag bit. The third flag bit is configured to identify whether it is desired to write the data in the object cache line into the parallel buffer memory when the object cache line is replaced out of the buffer memory; the fourth flag bit is configured to identify whether it is desired to write the data in the object cache line into the non-volatile main memory when the object cache line is replaced out of the cache memory; and the data processing method further comprises: receiving a tag instruction for the object cache line, and setting a value of the third flag bit and a value of the fourth flag bit based on the tag instruction in response to the object cache line loading data.

For example, in at least one example of the data processing method, the setting the value of the third flag bit and the value of the fourth flag bit based on the flag instruction includes: causing the value of the third flag bit and the value of the fourth flag bit to be selected from the first value and the second value, and causing the value of the third flag bit and the value of the fourth flag bit to not be equal to the second value at the same time.

For example, in at least one example of the data processing method, the generating a data packet based on the object cache line includes: generating the data packet based on the object data, the value of the third flag bit and the value of the fourth flag bit, and matching the value of the first flag bit and the value of the second flag bit with the value of the third flag bit and the value of the fourth flag bit, respectively.

For example, in at least one example of the data processing method, the causing the value of the first flag bit and the value of the second flag bit to match the value of the third flag bit and the value of the fourth flag bit, respectively, includes: and enabling the value of the first marking bit to be equal to the value of the third flag bit, and enabling the value of the second marking bit to be equal to the value of the fourth flag bit.

For example, in at least one example of the data processing method, the performing at least one of the operation of writing the object data into a parallel buffer memory and the operation of writing the object data into a nonvolatile main memory based on at least the value of the first flag bit further includes: in response to the value of the first flag bit being the first value, performing no operation to write the object data into the non-volatile main memory; in response to the value of the first flag bit being the second value, an operation of writing the object data into the parallel buffer memory is performed.

At least one embodiment of the present disclosure also provides a data processing apparatus including: a controller, a buffer memory, a parallel buffer memory, and an interface coupled to the non-volatile main memory. The controller is configured to: receiving a replacement instruction to replace an object cache line out of a buffer memory, wherein the object cache line comprises object data; generating a data packet based on the object cache line, wherein the data packet comprises the object data and a first marking bit; and performing at least one of an operation of writing the object data into the parallel buffer memory and an operation of transferring the object data to the interface based on at least a value of the first flag bit, wherein the performing of the operation of transferring the object data to the interface allows the object data to be written into the non-volatile main memory via the interface.

For example, in at least one example of the data processing apparatus, the value of the first tagging bit is a first value or a second value different from the first value. The performing at least one of an operation of writing the object data into the parallel buffer memory and an operation of transferring the object data to the interface based on at least the value of the first flag bit includes: in response to the value of the first flag bit being the first value, performing an operation of writing the object data into the parallel buffer memory, and in response to the value of the first flag bit being the second value, not performing an operation of writing the object data into the parallel buffer memory.

For example, in at least one example of the data processing apparatus, the data packet further includes a second flag bit; the value of the second flag bit is selected from the first value and the second value. The performing at least one of an operation of writing the object data into a parallel buffer memory and an operation of transferring the object data to the interface based on at least a value of the first flag bit, further includes: performing an operation of transferring the object data to the interface in response to the value of the second flag bit being the first value, and not performing the operation of transferring the object data to the interface in response to the value of the second flag bit being the second value.

For example, in at least one example of the data processing apparatus, the value of the first flag bit and the value of the second flag bit are not equal to the second value at the same time.

For example, in at least one example of the data processing apparatus, the object cache line further comprises a third flag bit and a fourth flag bit; the third flag bit is configured to identify whether it is desired to write the data in the object cache line into the parallel buffer memory when the object cache line is replaced out of the buffer memory; the fourth flag bit is configured to identify whether it is desired to transfer data in the object cache line to the interface when the object cache line is replaced out of the cache memory; and the controller is further configured to: receiving a tag instruction for the object cache line, and setting a value of the third flag bit and a value of the fourth flag bit based on the tag instruction in response to the object cache line loading data.

For example, in at least one example of the data processing apparatus, the setting the value of the third flag bit and the value of the fourth flag bit based on the flag instruction includes: causing the value of the third flag bit and the value of the fourth flag bit to be selected from the first value and the second value, and causing the value of the third flag bit and the value of the fourth flag bit to not be equal to the second value at the same time.

At least one embodiment of the present disclosure also provides a computing device comprising at least one data processing device of the present disclosure and the non-volatile main memory. The non-volatile main memory is coupled to the data processing apparatus through the interface.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

Fig. 1 is an exemplary flow chart of a data processing method provided by at least one embodiment of the present disclosure;

fig. 2 is an exemplary block diagram of an example of a computing device suitable for employing the data processing method provided by at least one embodiment of the present disclosure of fig. 1;

FIG. 3 is a schematic diagram of a first processing manner of object data replaced out of a buffer memory according to at least one embodiment of the disclosure;

FIG. 4 is a diagram illustrating a second manner of processing object data that is replaced out of a buffer memory according to at least one embodiment of the present disclosure;

FIG. 5 is a diagram illustrating a third manner of processing object data that is replaced out of a buffer memory according to at least one embodiment of the present disclosure;

fig. 6 is an exemplary block diagram of a data processing apparatus provided by at least one embodiment of the present disclosure;

FIG. 7 is another schematic diagram of the data processing apparatus shown in FIG. 6; and

fig. 8 is an exemplary block diagram of a computing device provided by at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

At least one embodiment of the present disclosure provides a data processing method, a data processing apparatus, and a computing apparatus. The data processing method comprises the following steps: receiving a replacement instruction to replace an object cache line out of the buffer memory, the object cache line including object data; generating a data packet based on the object cache line, wherein the data packet comprises object data and a first marking bit; at least one of an operation of writing the object data into the parallel buffer memory and an operation of writing the object data into the nonvolatile main memory is performed based on at least the value of the first flag.

For example, the data processing method may write data of a cache line that is replaced out of the buffer memory in the cache replacement into at least one of the parallel buffer memory and the nonvolatile main memory according to a requirement of the software layer, whereby performance may be optimized while data security is improved.

In the following, a data processing method provided according to at least one embodiment of the present disclosure is described in a non-limiting manner by several examples and embodiments, and as described below, different features in these specific examples and embodiments may be combined with each other without mutual conflict, so as to obtain new examples and embodiments, which also belong to the protection scope of the present disclosure.

Fig. 1 is an exemplary flowchart of a data processing method provided by at least one embodiment of the present disclosure. As shown in fig. 1, the data processing method includes the following steps S110 to S130.

Step S110: a replacement instruction is received to replace the object cache line out of the buffer memory. The object cache line includes object data.

Step S120: a data packet is generated based on the object cache line. The data packet includes object data and a first flag.

Step S130: at least one of an operation of writing the object data into the parallel buffer memory and an operation of writing the object data into the nonvolatile main memory is performed based on at least the value of the first flag.

For example, steps S110 to S130 are sequentially performed in the order of step S110, step S120, and step S130.

For example, in the first example, in step S130, at least one of an operation of writing the object data into the parallel buffer memory and an operation of writing the object data into the nonvolatile main memory is performed, including the following three cases.

(1) An operation of writing the object data into the parallel buffer memory is performed, and an operation of writing the object data into the nonvolatile main memory is performed.

(2) An operation of writing the object data into the parallel buffer memory is performed, but an operation of writing the object data into the nonvolatile main memory is not performed.

(3) An operation of writing the object data into the parallel buffer memory is not performed, but an operation of writing the object data into the nonvolatile main memory is performed.

For example, the buffer memory is a private buffer memory dedicated to the CPU core provided between the CPU core and the nonvolatile main memory; the parallel buffer memory is a shared buffer memory in parallel with the buffer memory. This is illustrated in connection with fig. 2. Fig. 2 is an exemplary block diagram of an example of a computing device suitable for employing the data processing method provided by at least one embodiment of the present disclosure in fig. 1.

For example, as shown in fig. 2, a computing device may include a plurality of CPU cores, each of the plurality of CPU cores corresponding to a group of buffer memories, each group of buffer memories being accessible only by the CPU core corresponding to the group of buffer memories. For example, each set of buffer memories includes a primary buffer memory and a secondary buffer memory, and for clarity, FIG. 2 shows only one buffer memory of a set of buffer memories; each buffer memory in fig. 2 is a private buffer memory of the CPU core corresponding to the buffer memory.

For example, as shown in FIG. 2, the computing device may also include a parallel buffer memory. For example, as shown in fig. 2, the parallel buffer memory may be accessed by a first number of CPU cores of the plurality of CPU cores, for example, the first number is an integer greater than 1 and less than or equal to the number of the plurality of CPU cores, that is, the parallel buffer memory shown in fig. 2 is a shared buffer memory.

It should be noted that the data processing method provided by at least one embodiment of the present disclosure is not limited to be applied to the computing device shown in fig. 2, and may also be applied to other suitable computing devices. For example, although fig. 2 illustrates a computing device having multiple CPU cores and a parallel buffer memory as a shared buffer memory for the multiple CPU cores, at least one embodiment of the disclosure is not so limited. In some examples, the parallel buffer memory may also be a private buffer memory that is parallel to a buffer memory provided between the CPU core and the nonvolatile main memory; for example, a computing device has multiple CPU cores, each of which corresponds to one of the parallel buffer memories; for another example, the computing device may be a single CPU core, with the parallel buffer memory being a private buffer memory for only the single CPU core.

For example, data exchange between the buffer memory and the CPU core is in units of "words"; data exchange between the buffer memory and the non-volatile main memory is in units of "blocks" or "rows"; a "block" for example comprises a plurality of words of fixed length.

For example, the buffer memory may be a level one buffer memory, but at least one embodiment of the present disclosure is not limited thereto. The buffer memory may also be a second level buffer memory or a last level buffer memory, for example. For example, the buffer memory includes a plurality of object cache lines, the size of which is, for example, 64 bytes.

For example, a parallel buffer memory may be used to temporarily store object data that is replaced out of the buffer memory. For example, when the CPU core reads target data, it is checked whether the target data is not only in the buffer memory but also in the parallel buffer memory.

For example, nonvolatile main memory is non-volatile memory that does not involve I/O devices. For example, implementing a main Memory using a non-volatile Memory allows a computing device including the non-volatile main Memory to have the potential to increase data security compared to implementing the main Memory using a Dynamic Random Access Memory (DRAM), because, for a non-volatile main Memory, data stored in the non-volatile main Memory does not disappear when current is turned off (e.g., an unexpected power outage).

For example, the Non-Volatile main Memory may be a Non-Volatile Dual-Inline-Memory-Modules (NVDIMMs), although at least one embodiment of the present disclosure is not so limited. For example, the non-volatile main memory may also be implemented as a phase change memory, a spin-torque transfer memory, a resistive memory, or other suitable memory.

For example, by performing an operation of writing object data into the parallel buffer memory, the object data replaced out of the buffer memory can be temporarily stored in the parallel buffer memory, and in this case, not only can resources consumed for writing the object data back to the nonvolatile main memory be avoided, but also the object data can be acquired more quickly when the CPU core reads the object data, whereby the performance of subsequent operations related to the object data can be improved.

For example, by executing the operation of writing the object data into the nonvolatile main memory, the object data replaced out of the buffer memory can be written back into the nonvolatile main memory, so that the nonvolatile main memory can be ensured to be updated, the data security is improved, the space of the parallel buffer memory occupied by the data which may not be used in a short period can be avoided, that is, the parallel buffer memory can store more data which may be accessed in a short period.

For example, the inventors of the present disclosure noted in their research that in the case where the data packet does not include the first flag, after the object data is replaced out of the buffer memory, the object data will be uniformly written into the parallel buffer memory or uniformly written back to the nonvolatile main memory; for the example in which the object data is to be uniformly written into the parallel buffer memory, not only the data security is low, but also there is a problem that the data that is not used in a short period occupies the space of the parallel buffer memory; for the example in which the object data is to be uniformly written back to the nonvolatile main memory, more resources may be consumed in writing the object data back to the nonvolatile main memory, and the speed of acquiring the object data is reduced.

For example, in a data processing method provided by at least one embodiment of the present disclosure, by performing at least one of an operation of writing object data into a parallel buffer memory and an operation of writing object data into a non-volatile main memory based on at least a value of a first flag, it is possible to write the object data into at least one of the parallel buffer memory and the non-volatile main memory according to requirements of a software layer (e.g., an application program) on the object data in terms of access speed and data security after the object data is replaced out of the buffer memory, whereby it is possible to optimize performance while improving overall data security.

For example, when the data security of the object data has a large impact (for example, the object data needs to be updated through a long-time operation), the software layer (for example, an application program) wants to perform an operation of writing the object data into the nonvolatile main memory, so that the data security can be improved, and the adverse impact caused by the object data loss can be avoided (for example, the time-consuming calculation again caused by unexpected power failure is reduced).

For example, for object data that may be used in a short period of time (e.g., object data used at a high frequency), a software layer (e.g., an application) may wish to perform an operation of writing the object data into a parallel buffer memory, thereby shortening the time for acquiring the object data and improving performance.

For example, for object data that may be used in a short period of time and may cause a large adverse effect after being lost (for object data that is obtained only by a long-time arithmetic operation and is used with a high frequency after being obtained), a software layer (for example, an application program) desires to perform an operation of writing the object data into a parallel buffer memory and an operation of writing the object data into a nonvolatile main memory, whereby it is possible to improve performance with improved data security.

For example, in a first example, the data packet further includes a second flag bit. For example, in step S130, performing at least one of an operation of writing the object data into the parallel buffer memory and an operation of writing the object data into the nonvolatile main memory based on at least the value of the first flag includes: at least one of an operation of writing the object data into the parallel buffer memory and an operation of writing the object data into the nonvolatile main memory is performed based on the value of the first flag bit and the value of the second flag bit.

For example, the value of the first tagging bit is a first value or a second value different from the first value. For example, the value of the first marker bit is related to the requirement of the software layer (e.g., application) on the object data in terms of access speed. For example, for object data that may be used for a short period of time (e.g., object data used with high frequency), the value of the first flag bit is at a first value; the first flag bit has a value equal to the second value for object data that may not be used for a short period of time.

For example, the value of the second flag bit is selected from the first value and the second value. For example, the value of the second marker bit is related to the requirement of the software layer (e.g., application) on the object data in terms of data security (data integrity). For example, when the data security of the object data has a large impact (for example, the object data needs to be updated through a long-time operation), the value of the second flag bit may be the first value; the value of the second flag may be a second value when the data security of the object data is less affected (e.g., object data that is easily obtained again).

For example, the value of the first flag bit and the value of the second flag bit are not equal to the second value at the same time, so that the corresponding data of the nonvolatile main memory can be updated when the target data is replaced out of the buffer memory and is not written into the parallel buffer memory.

For example, in the first example, at least one of the operation of writing the object data into the parallel buffer memory and the operation of writing the object data into the nonvolatile main memory is performed based on the value of the first flag and the value of the second flag, including the following three cases.

(1) In response to both the value of the first flag bit and the value of the second flag bit being the first value, an operation of writing the object data into the parallel buffer memory and an operation of writing the object data into the nonvolatile main memory are performed.

(2) In response to the value of the first flag bit and the value of the second flag bit being the first value and the second value, respectively, an operation of writing the object data into the parallel buffer memory is performed, but an operation of writing the object data into the nonvolatile main memory is not performed.

(3) In response to the value of the first flag bit and the value of the second flag bit being the second value and the first value, respectively, the operation of writing the object data into the parallel buffer memory is not performed, but the operation of writing the object data into the nonvolatile main memory is performed.

FIG. 3 is a schematic diagram of a first processing manner of object data replaced out of a buffer memory according to at least one embodiment of the disclosure; FIG. 4 is a diagram illustrating a second manner of processing object data that is replaced out of a buffer memory according to at least one embodiment of the present disclosure; fig. 5 is a schematic diagram of a third processing manner of object data replaced out of the buffer memory according to at least one embodiment of the present disclosure.

For example, as shown in fig. 3 to 5, the data processing method further includes: after step S120 is performed (i.e., after the packet is generated based on the object cache line), the packet is provided to a home node (home node) before step S130 is performed; correspondingly, step S130 includes: the master node performs at least one of an operation of writing the object data into the parallel buffer memory and an operation of writing the object data into the nonvolatile main memory based on the value of the first flag and the value of the second flag.

For example, as shown in fig. 3, when both the value of the first flag bit and the value of the second flag bit are the first value, the master node writes the object data into the parallel buffer memory in response to the value of the first flag bit being the first value; in response to the value of the second flag bit being the first value, the master node writes the object data into the non-volatile main memory.

For example, as shown in fig. 4, in a case where the value of the first flag bit and the value of the second flag bit are a first value and a second value, respectively, the master node writes the object data into the parallel buffer memory in response to the value of the first flag bit being the first value; in response to the value of the second flag bit being the second value, the master node does not write the object data into the non-volatile main memory.

For example, as shown in fig. 5, when the value of the first flag bit and the value of the second flag bit are the second value and the first value, respectively, the master node does not write the target data into the parallel buffer memory in response to the value of the first flag bit being the second value; in response to the value of the second flag bit being the first value, the master node writes the object data into the non-volatile main memory.

For example, the master node includes a logic control unit. For example, the logic control unit is configured to determine whether to write the object data into the parallel buffer memory according to a value of the first flag, and determine whether to write the object data into the nonvolatile main memory according to a value of the second flag. For example, the master node may be implemented as a unit circuit.

For example, the object cache line further includes a third flag bit and a fourth flag bit; the third flag bit is configured to identify whether it is desired to write data in the object cache line into the parallel cache memory when the object cache line is replaced out of the cache memory; the fourth flag bit is configured to identify whether it is desired to write data in the object cache line to the non-volatile main memory when the object cache line is replaced out of the cache memory. For example, the third flag bit and the fourth flag bit are located in the flag bit extension flag bit of the object cache line.

For example, the data processing method includes the following steps S140 and S150.

Step S140: a tag instruction for an object cache line is received.

Step S150: in response to the object cache line loading data, the values of the third flag bit and the fourth flag bit are set based on the tag instruction.

For example, step S140 and step S150 are sequentially executed in the order of step S140 and step S150, and are executed in executing step S110 to step S130.

For example, in step S150, "loading data in response to the object cache line" means at the time of or subsequent to the data loading of the object cache line.

For example, in step S150, setting the value of the third flag bit and the value of the fourth flag bit based on the flag instruction includes: such that the value of the third flag bit and the value of the fourth flag bit are selected from the first value and the second value, and such that the value of the third flag bit and the value of the fourth flag bit are not equal to the second value at the same time.

For example, in step S150, the value of the third flag bit of the cache line where the target data is located may be set according to the requirement of the application program for the target data in terms of access speed, and the value of the fourth flag bit of the cache line where the target data is located may be set according to the requirement of the application program for the target data in terms of data security.

For example, in step S150, setting the value of the third flag bit and the value of the fourth flag bit based on the flag instruction includes: when the object cache line is replaced out of the cache memory, if the data in the object cache line is expected to be written into the parallel cache memory and the nonvolatile main memory, setting the value of the third flag bit and the value of the fourth flag bit to be the first value; setting the value of the third flag bit and the value of the fourth flag bit to a first value and a second value, respectively, if it is desired to write the data in the object buffer line to the parallel buffer memory but not to the non-volatile main memory; if it is desired to write the data in the object buffer line to the non-volatile main memory but not to the parallel buffer memory, the values of the third flag bit and the fourth flag bit are set to the second value and the first value, respectively.

For example, the above-mentioned marker instruction is one of a plurality of instructions included in the instruction set. For example, the marker instruction may be an assembler instruction. For example, the developer of the application program may directly call a function of the piece of markup instruction (assembly instruction) and determine a processing policy for the object data replaced out of the buffer memory according to application requirements (for example, requirements of the application program on the object data in terms of data security and data access speed) (that is, the application program may use the instruction to perform an explicit markup operation); in this case, when or after the object data required for the application program to run is loaded into the object cache line, the value of the third flag bit and the value of the fourth flag bit are set by the tag instruction (assembler instruction), whereby it is possible to tag whether or not it is desired to write the object data into the parallel buffer memory and whether or not it is desired to write the object data into the nonvolatile main memory in the case where the object cache line in which the object data is located is replaced out of the buffer memory.

For example, in step S120, generating a packet (including a packet replaced out of the buffer memory) based on the object cache line includes: in response to the object data being dirty (dirty) data, a data packet is generated based on the object cache line. For example, "the object data is dirty data" means that the object data is updated data, but the updated data is not written back to the nonvolatile main memory. For example, the address at which the target data is written into the nonvolatile main memory is the address of the data before update corresponding to the target data in the nonvolatile main memory.

For example, in step S120, generating a data packet based on the object cache line includes: and generating a data packet based on the object data, the value of the third label bit and the value of the fourth label bit, and respectively matching the value of the first label bit and the value of the second flag bit with the value of the third label bit and the value of the fourth label bit.

For example, generating a data packet based on the object data, the value of the third marker bit, and the value of the fourth marker bit includes: so that the data packet includes object data, the value of the third flag bit is set based on the value of the first flag bit, and the value of the fourth flag bit is set based on the value of the second flag bit.

For example, matching the value of the first flag bit and the value of the second flag bit with the value of the third flag bit and the value of the fourth flag bit, respectively, includes: the value of the first flag bit is made equal to the value of the third flag bit and the value of the second flag bit is made equal to the value of the fourth flag bit.

For example, the determination logic may be simplified by making the value of the first flag bit, the value of the second flag bit, the value of the third flag bit, and the value of the fourth flag bit all selected from the first value and the second value, and making the value of the first flag bit equal to the value of the third flag bit and the value of the second flag bit equal to the value of the fourth flag bit, but at least one embodiment of the present disclosure is not limited thereto.

In some examples, the value of the third flag bit and the value of the fourth flag bit are each selected from a third value and a fourth value; "the value of the third flag bit is a third value" indicates that it is desired to write the target data into the parallel buffer memory when the target cache line is replaced out of the buffer memory; "the value of the third flag bit is a fourth value" indicates that it is not desirable to write the target data into the parallel buffer memory when the target cache line is replaced out of the buffer memory; "the value of the fourth flag bit is the third value" indicates that it is desired to write the object data into the nonvolatile main memory in the case where the object cache line is replaced out of the buffer memory; the "value of the fourth flag bit is a fourth value" indicates that it is not desirable to write the object data into the nonvolatile main memory when the object cache line is replaced out of the buffer memory. For example, the third value and the fourth value are equal to the second value and the first value, respectively; in this case, setting the value of the third flag bit based on the value of the first flag bit includes: such that the value of the first flag is selected from among the third value and the fourth value that are not equal to the value of the third flag (e.g., such that the value of the first flag is the fourth value if the value of the third flag is the third value); setting a value of a fourth flag bit based on the value of the second flag bit, including: such that the value of the second flag bit is selected from the third value and the fourth value that are not equal to the value of the fourth flag bit.

It should be noted that, although the above example illustrates an object cache line and a data packet having two tag bits, at least one embodiment of the disclosure is not limited thereto. For example, the object cache line and the data packet may have a flag, and in this case, the data of the cache line that is replaced out of the cache memory in the cache replacement may be written into one of the parallel cache memory and the nonvolatile main memory according to a requirement of the software layer, so that the performance may also be optimized under the condition of improving the data security, which is described below with reference to the second example.

For example, in the second example, in step S130, an operation of writing the object data into the parallel buffer memory or an operation of writing the object data into the nonvolatile main memory is performed, including the following two cases.

(1) An operation of writing the object data into the parallel buffer memory is performed, but an operation of writing the object data into the nonvolatile main memory is not performed.

(2) An operation of writing the object data into the parallel buffer memory is not performed, but an operation of writing the object data into the nonvolatile main memory is performed.

For example, in the second example, in step S130, at least one of the operation of writing the object data into the parallel buffer memory and the operation of writing the object data into the nonvolatile main memory is performed based on at least the value of the first flag, including: based on the value of the first flag bit, an operation of writing the object data into the parallel buffer memory or an operation of writing the object data into the nonvolatile main memory is performed.

For example, in the second example, in step S130, in response to the value of the first flag being the first value, the operation of writing the object data into the parallel buffer memory is performed, but the operation of writing the object data into the nonvolatile main memory is not performed; in response to the value of the first flag being the second value, the operation of writing the object data into the parallel buffer memory is not performed, but the operation of writing the object data into the nonvolatile main memory is performed.

For example, in a second example, the object cache line further includes a third flag bit; the third flag bit is configured to identify whether the data in the object buffer line is desired to be written to the parallel buffer memory and whether the data in the object buffer line is desired to be written to the non-volatile main memory when the object buffer line is replaced out of the cache memory.

For example, in a second example, the data processing method includes: receiving a tag instruction for an object cache line; the value of the third flag bit is set based on the tag instruction in response to the object cache line loading data. For example, the value of the third flag bit of the cache line in which the object data is located may be set according to the requirement of the application program on the object data in terms of access speed and data security.

For example, in a second example, setting a value of a third flag bit based on the marker instruction includes: when the object cache line is replaced out of the cache memory, if the data in the object cache line is expected to be written into the parallel cache memory but not the nonvolatile main memory, setting the value of the third flag bit to be the first value; if it is desired to write the data in the object buffer line to the non-volatile main memory but not to the parallel buffer memory, the value of the third flag bit is set to the second value.

For example, in the second example, in step S120, generating a data packet based on the object cache line includes: in response to the object data being dirty (dirty) data, a data packet is generated based on the object data and the value of the third marker bit, and the value of the first marker bit is matched to the value of the third marker bit.

For example, the specific implementation of the example where the object cache line and the data packet both have one tag bit is similar to the example where the object cache line and the data packet both have two tag bits, and therefore, only differences between the two are explained herein, and the same or similar parts are not repeated.

The individual operations of the methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and/or software components and/or modules including, but not limited to, a hardware circuit, an Application Specific Integrated Circuit (ASIC), or a processor.

The various illustrative logical blocks, modules, and circuits described may be implemented or performed with a general purpose processor, a Digital Signal Processor (DSP), an ASIC, a field programmable gate array signal (FPGA) or other Programmable Logic Device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may reside in any form of tangible storage medium. Some examples of storage media that may be used include Random Access Memory (RAM), Read Only Memory (ROM), flash memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, and the like. A storage medium may be coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. A software module may be a single instruction, or many instructions, and may be distributed over several different code segments, among different programs, and across multiple storage media.

The functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more instructions on a tangible computer-readable medium. A storage media may be any available tangible media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other tangible medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.

At least one embodiment of the present disclosure also provides a data processing apparatus. Fig. 6 is an exemplary block diagram of a data processing apparatus provided by at least one embodiment of the present disclosure; fig. 7 is another schematic diagram of the data processing apparatus shown in fig. 6. For example, as shown in fig. 6 and 7, the data processing apparatus includes a controller, a buffer memory, a parallel buffer memory, and an interface 101 coupled to a non-volatile main memory.

For example, the controller is configured to: receiving a replacement instruction to replace an object cache line out of the buffer memory, the object cache line including object data; generating a data packet based on the object cache line, wherein the data packet comprises object data and a first marking bit; at least one of an operation of writing the object data into the parallel buffer memory and an operation of transferring the object data to the interface 101 is performed based on at least the value of the first flag, the operation of transferring the object data to the interface 101 allowing the object data to be written into the nonvolatile main memory via the interface 101. For example, the aforementioned home node may be part of the controller.

For example, the first tagging bit of the packet has a first value or a second value different from the first value.

In a first example, the data packet further comprises a second flag bit; performing at least one of an operation of writing the object data into the parallel buffer memory and an operation of transferring the object data to the interface 101 based on at least the value of the first flag bit, including: at least one of an operation of writing the object data into the parallel buffer memory and an operation of transferring the object data to the interface 101 is performed based on at least the value of the first flag and the value of the second flag.

For example, in a first example, the value of the second flag bit is one of a first value and a second value; the value of the first marking bit and the value of the second marking bit are not equal to the second value at the same time.

For example, in the first example, at least one of the operation of writing the object data into the parallel buffer memory and the operation of transferring the object data to the interface 101 is performed based on at least the value of the first flag, including the following three cases.

(1) In response to both the value of the first flag bit and the value of the second flag bit being the first value, an operation of writing the object data into the parallel buffer memory and an operation of writing the object data into the parallel buffer memory are performed (see fig. 7).

(2) In response to the value of the first flag bit and the value of the second flag bit being the first value and the second value, respectively, an operation of writing the object data into the parallel buffer memory is performed, but an operation of writing the object data into the parallel buffer memory is not performed.

(3) In response to the value of the first flag bit and the value of the second flag bit being the second value and the first value, respectively, the operation of writing the object data into the parallel buffer memory is not performed, but the operation of writing the object data into the parallel buffer memory is performed.

For example, the object cache line further includes a third flag bit and a fourth flag bit; the third flag bit is configured to identify whether it is desired to write data in the object cache line into the parallel cache memory when the object cache line is replaced out of the cache memory; the fourth flag bit is configured to identify whether it is desired to transfer data in the object cache line to the interface 101 when the object cache line is replaced out of the cache memory; the controller is further configured to: a tag instruction for the subject cache line is received, and a value of the third flag bit and a value of the fourth flag bit are set based on the tag instruction in response to the subject cache line loading data.

For example, setting the value of the third flag bit and the value of the fourth flag bit based on the marker instruction includes: such that the value of the third flag bit and the value of the fourth flag bit are selected from the first value and the second value, and such that the value of the third flag bit and the value of the fourth flag bit are not equal to the second value at the same time.

In a second example, performing at least one of an operation of writing object data into the parallel buffer memory and an operation of transferring the object data to the interface 101 based on at least a value of the first flag bit includes: based on the value of the first flag, an operation of writing the object data into the parallel buffer memory or an operation of transferring the object data to the interface 101 is performed.

For example, in the second example, performing at least one of the operation of writing the object data into the parallel buffer memory and the operation of transferring the object data to the interface 101 based on at least the value of the first flag bit includes: in response to the value of the first flag being the first value, an operation of writing the object data into the parallel buffer memory is performed, but an operation of transferring the object data to the interface 101 is not performed; in response to the value of the first flag being the second value, the operation of writing the object data into the parallel buffer memory is not performed, but the operation of transferring the object data to the interface 101 is performed.

For example, specific implementations of the controller and the data processing apparatus may refer to a data processing method provided in at least one embodiment of the present disclosure, and are not described herein again. For example, the data processing apparatus may optimize performance with improved data security.

At least one embodiment of the present disclosure also provides a computing device 10. Fig. 8 is an exemplary block diagram of a computing device provided by at least one embodiment of the present disclosure; as shown in fig. 8, the computing device includes at least one data processing device of the present disclosure and a non-volatile main memory. The non-volatile main memory is coupled to the data processing apparatus via an interface 101. For example, the computing device 10 may optimize performance while promoting data security.

Although the present disclosure has been described in detail hereinabove with respect to general illustrations and specific embodiments, it will be apparent to those skilled in the art that modifications or improvements may be made thereto based on the embodiments of the disclosure. Accordingly, such modifications and improvements are intended to be within the scope of this disclosure, as claimed.

The above description is intended to be exemplary of the present disclosure, and not to limit the scope of the present disclosure, which is defined by the claims appended hereto.