阅读说明：本技术 具有耐压机制的输出电路 (Output circuit with voltage withstand mechanism ) 是由 曹太和 蔡宗谚 于 2020-08-14 设计创作，主要内容包括：本发明包含一种具有耐压机制的输出电路,包含：P型晶体管、N型晶体管、耐压辅助N型晶体管及耐压辅助电路。P型晶体管包含电性耦接于电压源及输出端的第一源极以及第一漏极,及接收第一输入信号的第一栅极。N型晶体管包含电性耦接于接地端及连接端的第二源极以及第二漏极,及接收第二输入信号的第二栅极。耐压辅助N型晶体管包含电性耦接于输出端及连接端的第三漏极以及第三源极。耐压辅助电路电性耦接于电压源以及耐压辅助N型晶体管的第三栅极间,配置以：在输出端操作于逻辑高准位与逻辑低准位时分别提供电流导通机制与阻性机制。(The present invention includes an output circuit with a voltage withstanding mechanism, comprising: a P-type transistor, an N-type transistor, a voltage-withstanding auxiliary N-type transistor and a voltage-withstanding auxiliary circuit. The P-type transistor comprises a first source electrode and a first drain electrode which are electrically coupled with the voltage source and the output end, and a first grid electrode for receiving a first input signal. The N-type transistor comprises a second source electrode, a second drain electrode and a second grid electrode, wherein the second source electrode and the second drain electrode are electrically coupled to the grounding end and the connecting end, and the second grid electrode is used for receiving a second input signal. The voltage-resistant auxiliary N-type transistor comprises a third drain electrode and a third source electrode which are electrically coupled to the output end and the connecting end. The voltage-withstanding auxiliary circuit is electrically coupled between the voltage source and the third gate of the voltage-withstanding auxiliary N-type transistor, and is configured to: when the output end is operated at a logic high level and a logic low level, a current conduction mechanism and a resistance mechanism are respectively provided.)

1. An output circuit having a withstand voltage mechanism, comprising:

a P-type transistor including a first source and a first drain electrically coupled to a voltage source and an output terminal, respectively, and a first gate configured to receive a first input signal;

an N-type transistor including a second source and a second drain electrically coupled to a ground terminal and a connection terminal, respectively, and a second gate configured to receive a second input signal;

a voltage-withstanding auxiliary N-type transistor including a third drain and a third source electrically coupled to the output terminal and the connection terminal, respectively; and

a voltage-withstanding auxiliary circuit electrically coupled between the voltage source and a third gate of the voltage-withstanding auxiliary N-type transistor, such that the voltage-withstanding auxiliary N-type transistor is electrically coupled to the voltage source through the voltage-withstanding auxiliary circuit to maintain conduction, and configured to:

providing a current conducting mechanism when the output terminal is operated at a logic high level, so that the third gate electrode leads a current to the voltage source; and

providing a resistive mechanism when the output terminal is operated at a logic low level, so that the third gate generates a voltage drop along with the output terminal.

2. The output circuit of claim 1, wherein the voltage-tolerant auxiliary circuit comprises:

a resistor electrically coupled between the voltage source and the third gate; and

a diode including a cathode electrically coupled to the voltage source and an anode electrically coupled to the voltage-assisted N-type transistor.

3. The output circuit of claim 1, wherein the voltage-tolerant auxiliary circuit is a voltage-tolerant auxiliary P-type transistor that is turned on and configured to provide the resistive mechanism, and a parasitic diode of the voltage-tolerant auxiliary P-type transistor is configured to provide the current-conducting mechanism.

4. The output circuit of claim 1, wherein the first input signal and the second input signal are respectively at the logic low level in a first operating state to make the output terminal at the logic high level, and the first input signal and the second input signal are respectively at the logic high level in a second operating state to make the output terminal at the logic low level.

5. The output circuit of claim 4, wherein the first input signal and the second input signal are the logic high level and the logic low level respectively in a third operating state between the first operating state and the second operating state.

6. The output circuit of claim 5, wherein in the third operating state, the voltage at the output terminal is less than the logic low level.

7. The output circuit of claim 4, further comprising an output driver circuit configured to generate the first input signal and the second input signal.

8. The output circuit of claim 7, further comprising a determining circuit configured to determine whether the voltage of the voltage source is greater than a predetermined voltage to generate a determination result;

the output driving circuit is further configured to make the first input signal be the logic high level and the second input signal be the logic low level when the judgment result shows that the voltage of the voltage source is greater than the preset voltage, so that the P-type transistor and the N-type transistor are turned off.

9. The output circuit of claim 1, wherein a parasitic capacitance coupling effect exists between the third gate of the voltage-withstanding auxiliary N-type transistor and the output terminal, so that the third gate varies with the voltage of the output terminal.

10. The output circuit of claim 1, wherein the output terminal is electrically coupled to an external circuit through an inductor.

Technical Field

The present invention relates to circuit technologies, and in particular, to an output circuit with a voltage withstanding mechanism.

Background

In the design of integrated circuits, the circuit module is often provided with an output circuit at the last stage to output the signal processed by the circuit module to an external circuit module. In response to the voltage source, the output circuit is capable of operating in a tolerable range without damage, and the devices, such as P-type transistors or N-type transistors, included in the output circuit must have sufficient voltage endurance.

However, in some operating environments, the voltage source may have an unstable condition, resulting in an excessively high voltage. In such a situation, if there is no proper circuit design to improve the voltage endurance capability of the internal components of the output circuit, the components are easily damaged and cannot operate.

Disclosure of Invention

In view of the problems of the prior art, an object of the present invention is to provide an output circuit with a voltage withstanding mechanism, so as to improve the prior art.

An objective of the present invention is to provide an output circuit with a voltage withstanding mechanism, so as to improve the withstand voltage tolerance of the output circuit and further improve the reliability of the output circuit.

The present invention includes an output circuit with a voltage withstanding mechanism, one embodiment of which includes: a P-type transistor, an N-type transistor, a withstand voltage auxiliary N-type transistor, and a withstand voltage auxiliary circuit. The P-type transistor includes a first source and a first drain electrically coupled to the voltage source and the output terminal, respectively, and a first gate configured to receive a first input signal. The N-type transistor comprises a second source electrode, a second drain electrode and a second grid electrode, wherein the second source electrode and the second drain electrode are electrically coupled to the grounding end and the connecting end respectively, and the second grid electrode is configured to receive a second input signal. The voltage-resistant auxiliary N-type transistor comprises a third drain electrode and a third source electrode which are electrically coupled to the output end and the connecting end respectively. The voltage-withstanding auxiliary circuit is electrically coupled between the voltage source and a third gate of the voltage-withstanding auxiliary N-type transistor, so that the voltage-withstanding auxiliary N-type transistor is electrically coupled to the voltage source through the voltage-withstanding auxiliary circuit to maintain conduction, and is configured to: providing a current conduction mechanism when the output end is operated at a logic high level so that the third grid electrode leads out current to the voltage source; and providing a resistive mechanism when the output terminal is operated at a logic low level, so that the third gate generates a voltage drop along with the output terminal.

The features, implementations, and technical advantages of the present invention are described in detail below with reference to the accompanying drawings.

Drawings

FIG. 1 is a circuit diagram of an output circuit with a voltage withstanding mechanism according to an embodiment of the present invention; and

FIG. 2 is a circuit diagram of an output circuit with a voltage withstanding mechanism according to another embodiment of the present invention.

Description of the symbols

100. 200 output circuit

110. 210 withstand voltage auxiliary circuit

120 output driving circuit

130 judging circuit

CR comparison results

D1 first drain electrode

D2 second drain electrode

D3 third drain electrode

D4 fourth drain electrode

DI diode

DIC parasitic diode

G1 first grid

G2 second grid

G3 third grid

G4 fourth grid

GND ground terminal

HVD voltage source

IN1 first input signal

IN2 second input signal

L-shaped inductor

MN 1N-type transistor

MN2 voltage-resistant auxiliary N-type transistor

MP 1P-type transistor

MP2 voltage-resistant auxiliary P-type transistor

NC connecting end

O output terminal

R resistance

S1 first source electrode

S2 second source electrode

S3 third source

S4 fourth source electrode

VC control voltage

VP preset voltage

Detailed Description

An objective of the present invention is to provide an output circuit with a voltage withstanding mechanism, so as to improve the withstand voltage tolerance of the output circuit and further improve the reliability of the output circuit.

Please refer to fig. 1. Fig. 1 is a circuit diagram of an output circuit 100 with a voltage withstanding mechanism according to an embodiment of the present invention. The output circuit 100 includes: a P-type transistor MP1, an N-type transistor MN1, a withstand voltage auxiliary N-type transistor MN2, and a withstand voltage auxiliary circuit 110.

The P-type transistor MP1 includes a first source S1, a first drain D1 electrically coupled to the voltage source HVD and the output terminal O, respectively, and a first gate G1 configured to receive a first input signal IN 1. The N-type transistor MN1 includes a second drain D2 and a second source S2 electrically coupled to the connection node NC and the ground GND, respectively, and a second gate G2 configured to receive a second input signal IN 2.

The voltage-withstanding auxiliary N-type transistor MN2 is configured to provide a resistance-like function, providing a voltage-withstanding mechanism for the N-type transistor MN1, and preventing the N-type transistor MN1 from being damaged due to voltage variation during operation. In more detail, the voltage-withstanding auxiliary N-type transistor MN2 includes a third drain D3 and a third source S3 electrically coupled to the output terminal O and the connection terminal NC, respectively. In one embodiment, the third gate G3 of the auxiliary voltage-withstanding N-type transistor MN2 is electrically coupled to the voltage source HVD through the auxiliary voltage-withstanding circuit 110, so as to continuously receive the voltage from the voltage source HVD through the auxiliary voltage-withstanding circuit 110 and maintain the voltage at a conducting state.

The voltage-withstanding auxiliary circuit 110 can provide a voltage-withstanding mechanism for the voltage-withstanding auxiliary N-type transistor MN2, so as to prevent the voltage-withstanding auxiliary N-type transistor MN2 from being damaged due to voltage variation during operation. In one embodiment, the voltage-withstanding auxiliary circuit 110 includes a diode DI and a resistor R as shown in fig. 1. The diode DI includes a cathode electrically coupled to the voltage source HVD and an anode electrically coupled to the third gate G3 of the voltage-withstanding auxiliary N-type transistor MN 2. The resistor R is electrically coupled between the voltage source HVD and the third gate G3 of the voltage-withstanding auxiliary N-type transistor MN 2.

The operation of the output circuit 100 and the mechanism of withstand voltage will be described below.

According to the above structure, the output circuit 100 can be divided into an upper half-bridge including the P-type transistor MP1 and a lower half-bridge including the N-type transistor MN1 and the voltage-withstanding auxiliary N-type transistor MN2 by taking the output terminal O as a boundary. The output terminal O may be electrically coupled to an external circuit (not shown) through, for example, but not limited to, an inductor L included in the output circuit 100, so as to output the voltage of the output terminal O.

IN one embodiment, the output circuit 100 further includes an output driving circuit 120 electrically coupled to the first gate G1 and the second gate G2 of the P-type transistor MP1 and the N-type transistor MN1, and configured to generate the first input signal IN1 and the second input signal IN2 to the first gate G1 and the second gate G2.

IN the first operating state, the output driving circuit 120 generates the first input signal IN1 and the second input signal IN2 that are logic low. Therefore, the P-type transistor MP1 will be turned on because the first gate G1 is controlled by the first input signal IN1 with a logic low level, and inject a current into the output terminal O according to the voltage source HVD. On the other hand, the N-type transistor MN1 will be turned off because the second gate G2 is controlled by the second input signal IN2 of logic low level.

Therefore, in the first operating state, the voltage at the output terminal O will rise to the logic high level due to the turn-off of the lower half-bridge and the turn-on of the upper half-bridge.

IN the second operating state, the output driving circuit 120 generates the first input signal IN1 and the second input signal IN2 with logic high levels respectively. Therefore, the P-type transistor MP1 is turned off because the first gate G1 is controlled by the first input signal IN1 with a logic high level. On the other hand, the N-type transistor MN1 is turned on by the second gate G2 being controlled by the second input signal IN2 with a logic high level, and draws current to the output terminal O according to the ground terminal GND.

Therefore, in the second operating state, the voltage at the output terminal O will drop to the logic low level due to the turn-on of the lower half-bridge and the turn-off of the upper half-bridge.

In some technologies, the output circuit 100 does not include the voltage-withstanding auxiliary N-type transistor MN2, and the second drain D2 and the second source S2 of the N-type transistor MN1 are directly electrically coupled to the output terminal O and the ground terminal GND. Under such a situation, due to the coupling effect of the parasitic capacitance between the second drain D2 and the second gate G2 of the N-type transistor MN1, when the output terminal O is operated at the logic high level, the voltage of the second gate G2 is increased accordingly, and the breakdown voltage (breakdown down voltage) of the N-type transistor MN1 is decreased.

When the output circuit 100 operates in an environment that is not good enough to cause the voltage source HVD to be higher than the rated operating voltage, the logic high level of the output terminal O will have a higher voltage. The voltage at the second gate G2 of the N-type transistor MN1 will further increase, causing the breakdown voltage to drop again, resulting in the damage of the N-type transistor MN 1.

By the arrangement of the voltage-withstanding auxiliary N-type transistor MN2, a resistance effect can be provided, so that the second drain D2 of the N-type transistor MN1 receives the voltage drop of the voltage source HVD. Therefore, the voltage-withstanding auxiliary N-type transistor MN2 can prevent the N-type transistor MN1 from receiving too high voltage, and reduce the probability of damage to the N-type transistor MN 1.

However, the same problem of withstand voltage exists for the withstand voltage assistant N-type transistor MN 2. Due to the coupling effect of the parasitic capacitance between the third drain D3 of the voltage-withstanding auxiliary N-type transistor MN2 and the third gate G3 of the voltage-withstanding auxiliary N-type transistor MN2, when the output terminal O is at the logic high level, the voltage of the third gate G3 is increased accordingly, and the breakdown voltage of the voltage-withstanding auxiliary N-type transistor MN2 is decreased.

When the output circuit 100 operates in an environment that is not good and the voltage source HVD is higher than the rated operating voltage, the logic high level of the output terminal O has a higher voltage. The voltage of the third gate G3 of the voltage-withstanding auxiliary N-type transistor MN2 will be further raised, causing the breakdown voltage to drop again, resulting in the damage of the N-type transistor MN 1.

The resistor R of the auxiliary voltage withstanding circuit 110 can cause the third gate G3 of the auxiliary voltage withstanding N-type transistor MN2 to conduct current to the voltage source HVD when the output terminal O is operated at a logic high level, but the speed is slow. Therefore, the diode DI of the voltage-withstanding auxiliary circuit 110 can provide a fast current conduction mechanism when the output terminal O is operated at a logic high level. When the output circuit 100 operates in an environment where the logic high level of the output terminal O has a higher voltage to raise the voltage of the third gate G3, the third gate G3 of the voltage-withstanding auxiliary N-type transistor MN2 will conduct current to the voltage source HVD through the diode DI.

On the other hand, IN one embodiment, between the first operating state and the second operating state, for example, when the first operating state is transited to the second operating state or the second operating state is transited to the first operating state, IN order to avoid the occurrence of the short circuit, a third operating state may exist to generate the first input signal IN1 with a logic high level and the second input signal IN2 with a logic low level by the output driving circuit 120. Therefore, the P-type transistor MP1 is turned off by the first input signal IN1 with a logic high level. On the other hand, the N-type transistor MN1 is controlled by the second input signal IN2 with a logic low level and is turned off.

In this situation, due to the current continuity of the inductor L, the parasitic diode of the base of the voltage-withstanding auxiliary N-type transistor MN2 generates a current flowing from the connection terminal NC to the output terminal O, forcing the output terminal O to generate a voltage lower than the normal logic low level, resulting in a large voltage difference between the third gate G3 and the third drain D3 of the voltage-withstanding auxiliary N-type transistor MN 2.

Therefore, the resistor R of the voltage withstanding auxiliary circuit 110 will provide a resistive mechanism, so that the third gate G3 will not directly receive the input of the voltage source HVD. Due to the coupling effect of the parasitic capacitance between the third drain D3 and the third gate G3, the third gate G3 can drop with the voltage drop of the output terminal O, so as to prevent the voltage difference between the third gate G3 and the third drain D3 of the voltage-tolerant auxiliary N-type transistor MN2 from being too large and damaged.

In an embodiment, the output circuit 100 of fig. 1 may further optionally include a determining circuit 130 configured to determine whether the voltage of the voltage source HVD is greater than the predetermined voltage VP and generate the comparison result CR. The output driving circuit 120 sets the first input signal IN1 to be at the logic high level and the second input signal IN2 to be at the logic low level when the voltage of the voltage source HVD is greater than the predetermined voltage VP according to the comparison result CR. Therefore, the P-type transistor MP1 is turned off because the first gate G1 is controlled by the first input signal IN1 with a logic high level. On the other hand, the N-type transistor MN1 will be turned off because the second gate G2 is controlled by the second input signal IN2 of logic low level.

Therefore, by the determination mechanism of the determination circuit 130 and the operation of the output driving circuit 120 according to the comparison result CR, the output circuit 100 can stop operating when the voltage of the voltage source HVD is too high, providing a protection mechanism to avoid the internal device damage.

Please refer to fig. 2. Fig. 2 is a circuit diagram of an output circuit 200 with a voltage withstanding mechanism according to another embodiment of the present invention.

Much different from the output circuit 100 shown in fig. 1, the output circuit 200 includes: the P-type transistor MP1, the N-type transistor MN1, and the auxiliary N-type transistor MN2 have the same structure and operation as those of the device shown in fig. 1, and therefore are not described herein again.

Unlike the output circuit 100 shown in fig. 1, in the present embodiment, the voltage-withstanding auxiliary circuit 210 included in the output circuit 200 is implemented by a voltage-withstanding auxiliary P-type transistor MP 2.

The two fourth source/drains SD41 and SD42 of the voltage-withstanding auxiliary P-type transistor MP2 are electrically coupled to the voltage source HVD and the third gate G3 of the voltage-withstanding auxiliary N-type transistor MN2, respectively, and the fourth gate G4 of the voltage-withstanding auxiliary P-type transistor MP2 is turned on according to the control voltage VC to provide the resistive mechanism.

Further, the voltage-withstanding auxiliary P-type transistor MP2 has a parasitic diode DIC between the fourth source S4 and the fourth drain D4, configured to provide the aforementioned current conduction mechanism.

Therefore, the voltage-withstanding auxiliary circuit 210 in this embodiment can be implemented by the voltage-withstanding auxiliary P-type transistor MP2, so that the voltage-withstanding auxiliary N-type transistor MN2 has a preferable voltage-withstanding degree.

In summary, the output circuit of the present invention can make the N-type transistor and the voltage-withstanding auxiliary N-type transistor have better voltage-withstanding capability through the arrangement of the voltage-withstanding auxiliary N-type transistor and the voltage-withstanding auxiliary circuit, respectively, so as to improve the reliability of the operation of the output circuit.

Although the embodiments of the present invention have been described above, the embodiments are not intended to limit the present invention, and those skilled in the art can make variations on the technical features of the present invention according to the explicit or implicit contents of the present invention, and all such variations may fall within the scope of the patent protection sought by the present invention.