阅读说明：本技术 一种超低功耗cmos温度感应电路 (Ultra-low power consumption CMOS temperature sensing circuit ) 是由 梅年松 于 2020-12-02 设计创作，主要内容包括：本发明公开了一种超低功耗CMOS温度感应电路,包括：电流产生电路,用于产生温度感应电路所需的参考偏置电流；温度感应电路,用于在所述参考偏置电流作用下产生与温度成线性关系的温感输出电压；反馈环路,连接所述电流产生电路及温度感应电路,以避免所述电流产生电路与温度感应电路的失配。(The invention discloses an ultra-low power consumption CMOS temperature sensing circuit, comprising: the current generating circuit is used for generating a reference bias current required by the temperature sensing circuit; the temperature sensing circuit is used for generating temperature sensing output voltage which is in linear relation with temperature under the action of the reference bias current; and the feedback loop is connected with the current generation circuit and the temperature sensing circuit so as to avoid the mismatch of the current generation circuit and the temperature sensing circuit.)

1. An ultra-low power CMOS temperature sensing circuit comprising:

the current generating circuit is used for generating a reference bias current required by the temperature sensing circuit;

the temperature sensing circuit is used for generating temperature sensing output voltage which is in linear relation with temperature under the action of the reference bias current;

and the feedback loop is connected with the current generation circuit and the temperature sensing circuit so as to avoid the mismatch of the current generation circuit and the temperature sensing circuit.

2. The ultra-low power CMOS temperature sensing circuit of claim 1, wherein: the current generating circuit comprises a first diode and a first PMOS bias tube, wherein the source electrode of the first PMOS bias tube is connected with a power supply VDD, the grid electrode and the drain electrode are connected to the temperature sensing circuit after being in short circuit, the grid electrode and the drain electrode are connected with the cathode of the first diode and one input end of the feedback loop, and the anode of the first diode is grounded.

3. The ultra-low power CMOS temperature sensing circuit of claim 2, wherein: the temperature sensing circuit comprises a second diode and a second PMOS (P-channel metal oxide semiconductor) tube, wherein the source electrode of the second PMOS tube is connected with a power supply VDD, the grid electrode of the second PMOS tube is connected to the grid drain electrode in short circuit with the first PMOS biasing tube, the drain electrode of the second PMOS tube is connected with the other input end of the feedback loop, the anode of the second diode is connected with the output end of the feedback loop to form the temperature sensing output voltage node, and the cathode of the second diode is grounded.

4. The ultra-low power CMOS temperature sensing circuit of claim 3, wherein: the feedback loop comprises an operational amplifier and a third PMOS tube, one input end of the operational amplifier is connected with a short-circuited gate drain electrode of a first PMOS bias tube of the current generating circuit, the other input end of the operational amplifier is connected with a drain electrode of the second PMOS tube and is connected with a source electrode of the third PMOS tube, an output end of the operational amplifier is connected with a gate electrode of the third PMOS tube, and the drain electrode of the third PMOS tube is connected with an anode of a second diode to form the temperature-sensitive output voltage node.

5. The ultra-low power CMOS temperature sensing circuit of claim 4, wherein: the non-inverting input end of the operational amplifier is connected with the short-circuited grid drain electrode of the first PMOS bias tube of the current generating circuit, and the inverting input end of the operational amplifier is connected with the drain electrode of the second PMOS bias tube and the source electrode of the third PMOS bias tube.

6. The ultra-low power CMOS temperature sensing circuit of claim 5, wherein: and regulating the voltage between the source electrode and the drain electrode of the third PMOS transistor to ensure that the voltages of the non-inverting input end and the inverting input end of the operational amplifier are the same, thereby avoiding the current mismatch caused by the difference of the voltages of the drain electrodes of the first PMOS bias tube and the second PMOS bias tube.

Technical Field

The present invention relates to a temperature sensing circuit, and more particularly to an ultra-low power consumption CMOS temperature sensing circuit.

Background

The temperature is a basic physical phenomenon, is the most common and important technological parameter applied in the production process, and can not be measured in industrial and agricultural production, scientific research and national defense modernization, so that the temperature sensor is the most widely applied one of various sensors. The integrated temperature sensor is developed on the basis of PN junction temperature sensor, and has the characteristics of miniaturization, convenient use and low cost. Temperature sensor integration is becoming an important trend.

Currently, the main implementations of integrated temperature sensors include: a temperature sensor based on a MOS tube and a CMOS temperature sensor based on a parasitic bipolar transistor in a CMOS process. The common method for realizing the temperature sensor based on the temperature characteristic of the MOS transistor includes two methods: the first method is as follows: when the gate-source voltage is lower than the threshold voltage of the MOS tube, the drain-source current of the MOS tube in the sub-threshold state has the characteristic of being directly Proportional To Absolute Temperature (PTAT) to realize temperature sensing, however, the leakage current of the MOS tube is very obvious under the condition of high temperature, so that the PTAT characteristic of the drain-source current of the MOS tube in the sub-threshold state at high temperature is seriously influenced, and the temperature measuring range of the temperature sensor realized by the method of the PTAT characteristic of the sub-threshold current of the MOS tube cannot be too wide, otherwise, the temperature measuring precision of the temperature sensor can be seriously influenced; the second method is as follows: the temperature sensor is realized by utilizing the temperature characteristic that the carrier mobility and the threshold voltage in the MOS tube are seriously dependent on the temperature under the strong inversion state, and the method has the advantages of good temperature precision, special process and great influence by process fluctuation.

The CMOS temperature sensor utilizes parasitic bipolar transistors in a CMOS process to generate a voltage proportional to temperature to realize temperature conversion. The CMOS process is gradually popularized due to the ease of integration of digital and analog circuits, and is dominant in integrated circuit design. Compared with an MOS temperature sensor, the CMOS temperature sensor has the advantages of simple design, accurate measurement, high integration, low price and the like, and is widely applied to the fields of computers, industrial control, telecommunication, medicine and the like. However, reducing power consumption and improving linearity are constantly sought after in CMOS temperature sensing circuits.

Disclosure of Invention

In order to overcome the defects of the prior art, the invention aims to provide an ultra-low power consumption CMOS temperature sensing circuit to achieve the purposes of reducing power consumption and improving linearity of a CMOS temperature sensor.

To achieve the above and other objects, the present invention provides an ultra-low power consumption CMOS temperature sensing circuit, comprising:

the current generating circuit is used for generating a reference bias current required by the temperature sensing circuit;

the temperature sensing circuit is used for generating temperature sensing output voltage which is in linear relation with temperature under the action of the reference bias current;

and the feedback loop is connected with the current generation circuit and the temperature sensing circuit so as to avoid the mismatch of the current generation circuit and the temperature sensing circuit.

Preferably, the current generating circuit includes a first diode and a first PMOS bias transistor, a source of the first PMOS bias transistor is connected to a power supply VDD, a gate and a drain of the first PMOS bias transistor are connected to the temperature sensing circuit after being shorted, and the first PMOS bias transistor is connected to a cathode of the first diode and an input end of the feedback loop, and an anode of the first diode is grounded.

Preferably, the temperature sensing circuit comprises a second diode and a second PMOS transistor, wherein the source of the second PMOS transistor is connected with a power supply VDD, the gate of the second PMOS transistor is connected to the gate-drain electrode of the first PMOS bias transistor in short circuit, the drain of the second PMOS bias transistor is connected with the other input end of the feedback loop, the anode of the second diode is connected with the output end of the feedback loop to form the temperature-sensing output voltage node, and the cathode of the second diode is grounded.

Preferably, the feedback loop comprises an operational amplifier and a third PMOS transistor, one input end of the operational amplifier is connected to the short-circuited gate drain of the first PMOS bias transistor of the current generating circuit, the other input end of the operational amplifier is connected to the drain of the second PMOS transistor and to the source of the third PMOS transistor, the output end of the operational amplifier is connected to the gate of the third PMOS transistor, and the drain of the third PMOS transistor is connected to the anode of the second diode to form the temperature-sensitive output voltage node.

Preferably, the non-inverting input terminal of the operational amplifier is connected to the shorted gate drain of the first PMOS bias transistor of the current generating circuit, and the inverting input terminal is connected to the drain of the second PMOS transistor and the source of the third PMOS transistor.

Preferably, the voltage between the source and the drain of the third PMOS transistor is adjusted to ensure that the voltages of the non-inverting input terminal and the inverting input terminal of the operational amplifier are the same, so as to avoid current mismatch caused by the difference between the voltages of the drains of the first PMOS bias transistor and the second PMOS bias transistor.

Compared with the prior art, the ultra-low power consumption CMOS temperature sensing circuit provided by the invention has the advantages that the voltage between the source electrode and the drain electrode of the third PMOS pipe PM3 of the temperature sensing circuit is adjusted by utilizing the feedback loop, so that the voltage of the drain electrode of the first PMOS bias pipe PM1 is ensured to be the same as that of the drain electrode of the second PMOS pipe PM2, the current mismatch caused by the difference of the voltage of the drain electrodes of the first PMOS bias pipe PM1 and the second PMOS pipe PM2 is avoided, and the purposes of reducing the power consumption and improving the linearity of the CMOS temperature sensor are realized.

Drawings

FIG. 1 is a circuit diagram of an ultra-low power CMOS temperature sensing circuit according to a preferred embodiment of the present invention.

Detailed Description

Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.

FIG. 1 is a circuit diagram of an ultra-low power CMOS temperature sensing circuit according to a preferred embodiment of the present invention. As shown in fig. 1, in a preferred embodiment of the present invention, an ultra-low power CMOS temperature sensing circuit includes: including a current generating circuit 10, a temperature sensing circuit 20, and a feedback loop 30.

The current generating circuit 10 is composed of a first diode D1 and a first PMOS bias transistor PM1, and is configured to generate a reference bias current required by the temperature sensing circuit 20; the temperature sensing circuit 20 is composed of a second diode D2 and a second PMOS transistor PM2, and is configured to generate a temperature-sensitive output voltage Vout proportional to the temperature under the action of the reference bias current; the feedback loop 30 is composed of an operational amplifier OPA and a third PMOS transistor PM3, and is configured to adjust a voltage between a source and a drain of the third PMOS transistor PM3, so as to ensure that an IN + voltage, i.e., a drain voltage of the first PMOS bias transistor PM1, is the same as an IN voltage, i.e., a drain voltage of the second PMOS transistor PM2, thereby avoiding current mismatch caused by the difference between the drain voltages of the first PMOS bias transistor PM1 and the second PMOS bias transistor PM 2.

Specifically, the power supply VDD is connected to the source of the first PMOS bias transistor PM1 and the source of the second PMOS transistor PM2, the gate and the drain of the first PMOS bias transistor PM1 are shorted and then connected to the gate of the second PMOS transistor PM2, the cathode of the first diode D1 and the non-inverting input terminal IN + of the operational amplifier OPA, the drain of the second PMOS transistor PM2 is connected to the inverting input terminal IN-of the operational amplifier OPA and the source of the third PMOS transistor PM3, the output Out of the operational amplifier OPA is connected to the gate of the third PMOS transistor PM3, the drain of the third PMOS transistor PM3 is connected to the anode of the second diode D2 to form a temperature output Vout node, and the cathode of the second diode D2 and the anode of the first diode D1 are grounded.

The working principle of the invention is as follows:

in fig. 1, a current generating circuit 10 is composed of a first diode D1 and a first PMOS bias transistor PM 1; the second diode D2 and the second PMOS transistor PM2 form a temperature sensing circuit 20, and the temperature output Vout is:

where VT is the transistor hot voltage,k IS a Boltzmann constant, q IS an electronic charge, T IS an absolute temperature, A D2 IS a diode cross-sectional area, IS IS a reverse saturation current, and a current I2 flowing through the second PMOS tube PM2 IS

In the above equation (2), V is the reverse bias voltage of the diode D1, and when V < -3VT, the above equation can be approximated as:

I₂≈N*A_D1*I_S (3)

substituting the above equation (3) into equation (1), equation (1) becomes:

this results in an output voltage that is completely linear with temperature.

The operational amplifier OPA and the third PMOS transistor PM3 form a negative feedback loop 30, and the voltage between the source and the drain of the third PMOS transistor PM3 is adjusted to ensure that the voltage of the non-inverting input terminal IN + is the same as the voltage of the inverting input terminal IN-, thereby avoiding current mismatch caused by the difference between the voltages of the drain terminals of the first PMOS bias transistor PM1 and the second PMOS bias transistor PM 2.

In summary, in the ultra-low power consumption CMOS temperature sensing circuit of the present invention, the voltage between the source and the drain of the third PMOS transistor PM3 of the temperature sensing circuit is adjusted by using the feedback loop, so as to ensure that the voltage of the drain of the first PMOS bias transistor PM1 is the same as the voltage of the drain of the second PMOS transistor PM2, thereby avoiding the current mismatch caused by the difference between the voltages of the drains of the first PMOS bias transistor PM1 and the second PMOS transistor PM2, and achieving the purposes of reducing power consumption and improving linearity of the CMOS temperature sensor.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.