阅读说明：本技术 掩膜版、半导体器件的制造方法 (Mask and method for manufacturing semiconductor device ) 是由 李寒骁 陈金星 马霏霏 于 2021-06-26 设计创作，主要内容包括：本发明提供一种掩膜版、半导体器件的制造方法。掩膜版用于半导体器件的光刻,半导体器件包括依次层叠的衬底、堆叠结构及光阻层,衬底包括器件区及位于器件区外围的切割道区。掩膜版设有多个第一图案,第一图案用于在器件区的光阻层内形成开口,掩膜版还设有多个第二图案,第二图案用于在切割道区的光阻层内形成开口。其中,每一第一图案和每一第二图案的形状、大小相同,多个第一图案的排布密度大于多个第二图案的排布密度。当以光刻后的光阻层为掩膜对半导体器件的堆叠结构进行刻蚀时,通过监测第二图案对应的开口是否缩小至小于预设阈值,即可实现对刻蚀副产物的监控,有利于提高半导体器件的生产良率。(The invention provides a mask and a method for manufacturing a semiconductor device. The mask is used for photoetching of a semiconductor device, the semiconductor device comprises a substrate, a stacking structure and a photoresist layer which are sequentially stacked, and the substrate comprises a device area and a cutting path area which is positioned on the periphery of the device area. The mask plate is provided with a plurality of first patterns, the first patterns are used for forming openings in the light resistance layer of the device area, the mask plate is also provided with a plurality of second patterns, and the second patterns are used for forming openings in the light resistance layer of the cutting path area. The shape and the size of each first pattern and each second pattern are the same, and the arrangement density of the first patterns is larger than that of the second patterns. When the photoetching photoresist layer is used as a mask to etch the stacked structure of the semiconductor device, monitoring whether the opening corresponding to the second pattern is reduced to be smaller than a preset threshold value can be carried out, so that the etching by-products can be monitored, and the production yield of the semiconductor device can be improved.)

1. A mask is used for photoetching of a semiconductor device, and the semiconductor device comprises a substrate, a stacked structure and a photoresist layer which are sequentially stacked, wherein the substrate comprises a device area and a cutting path area positioned on the periphery of the device area;

the mask is provided with a plurality of first patterns, the first patterns are used for forming openings in the light resistance layer of the device area, the mask is also provided with a plurality of second patterns, and the second patterns are used for forming openings in the light resistance layer of the cutting path area;

the first patterns and the second patterns are the same in shape and size, and the arrangement density of the first patterns is larger than that of the second patterns.

2. The reticle of claim 1, wherein the substrate includes a plurality of the device regions distributed in an array, the scribe lane regions include a plurality of first scribe lane regions and a plurality of second scribe lane regions distributed in an intersection, the first scribe lane regions extend along a first direction, and the second scribe lane regions extend along a second direction;

the mask is provided with at least one pattern array area corresponding to at least one part of the first cutting path area and/or at least one part of the second cutting path area, and each pattern array area is provided with a plurality of second patterns.

3. The mask according to claim 2, wherein the portion of the mask corresponding to each of the device regions is adjacently disposed with one of the pattern array regions; or

The substrate is circular, the mask is provided with a plurality of pattern array areas, orthographic projections of the pattern array areas on the substrate have different distances from the circle center of the substrate respectively, and the orthographic projections of the pattern array areas are distributed along the same radial direction of the substrate or distributed along different radial directions of the substrate.

4. The reticle of any one of claims 1-3, wherein the plurality of first patterns and the plurality of second patterns are arranged in a plurality of rows and columns array, the row direction and the column direction of the first patterns are the same as the row direction and the column direction of the second patterns, respectively, and wherein a pitch between two adjacent first patterns is smaller than a pitch between two adjacent second patterns.

5. A method of manufacturing a semiconductor device, comprising:

providing a substrate, and sequentially forming a stacking structure and a light resistance layer above the substrate, wherein the substrate comprises a device area and a cutting path area positioned at the periphery of the device area;

arranging a mask on one side of the photoresist layer far away from the stacked structure, wherein a part of the mask, corresponding to the device region, is provided with a plurality of first patterns, and a part of the mask, corresponding to the dicing channel region, is provided with a plurality of second patterns, wherein the shape and the size of each first pattern are the same as those of each second pattern, and the arrangement density of the first patterns is greater than that of the second patterns;

etching by taking the mask plate as a mask to form a plurality of openings which correspond to the first patterns and the second patterns one to one in the photoresist layer;

etching the stacked structure through the plurality of openings of the photoresist layer by taking the photoresist layer after photoetching as a mask so as to form a channel hole extending in a direction vertical to the stacked structure in the stacked structure; and

and when the size of the opening corresponding to at least one second pattern is monitored to be reduced to be smaller than a preset threshold value, judging that a byproduct generated by the stacked structure etching is abnormal, and stopping etching the stacked structure.

6. The method of manufacturing the semiconductor device according to claim 5, wherein the channel hole does not penetrate through the stacked structure when the by-product is abnormal.

7. The method according to claim 6, wherein the number of the openings narrowed to less than the predetermined threshold is proportional to an abnormal amount of the by-product.

8. The method of manufacturing a semiconductor device according to claim 6, wherein the substrate includes a plurality of the device regions distributed in an array, the scribe lane region includes a plurality of first scribe lane regions extending in a first direction and spaced apart in a second direction, and a plurality of second scribe lane regions extending in the second direction and spaced apart in the first direction, the plurality of first scribe lane regions and the plurality of second scribe lane regions are distributed to intersect;

the part of the mask corresponding to at least one first cutting path area and/or the part corresponding to at least one second cutting path area comprises at least one pattern array area, and each pattern array area is provided with a plurality of second patterns.

9. The method for manufacturing a semiconductor device according to claim 8, wherein a portion of the mask corresponding to each of the device regions is provided adjacent to one of the pattern array regions.

10. The method of manufacturing a semiconductor device according to claim 8, wherein the mask plate is provided with a plurality of the pattern array regions, and the plurality of pattern array regions are located at different positions of the mask plate in a radial direction with respect to the substrate.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a mask and a manufacturing method of a semiconductor device.

Background

In the production and manufacture of semiconductor devices, an etching process is essential, but byproducts are generated during the etching process. When the number of byproducts is large (i.e., the byproducts are abnormal), the further etching of the semiconductor device is blocked, and the bridging defect of the pattern formed by etching is easily caused, so that the electrical performance of the semiconductor device is affected, and the production yield of the semiconductor device is reduced. Therefore, it is necessary to strictly monitor whether the amount of by-products generated is abnormal during the etching process. However, there is no method for directly monitoring the amount of by-products generated during the etching process, and the yield of semiconductor devices is affected when the amount of by-products is found to be abnormal.

Disclosure of Invention

In view of this, the present invention provides a mask and a method for manufacturing a semiconductor device, which can monitor the amount of etching byproducts, so as to find the problem of byproduct abnormality before the yield of the semiconductor device is affected, and thus, the yield of the semiconductor device is improved.

In order to achieve the above object, an aspect of the present invention provides a mask for photolithography of a semiconductor device, where the semiconductor device includes a substrate, a stack structure, and a photoresist layer, which are sequentially stacked, and the substrate includes a device region and a scribe line region located at the periphery of the device region;

the mask is provided with a plurality of first patterns, the first patterns are used for forming openings in the light resistance layer of the device area, the mask is also provided with a plurality of second patterns, and the second patterns are used for forming openings in the light resistance layer of the cutting path area;

the first patterns and the second patterns are the same in shape and size, and the arrangement density of the first patterns is larger than that of the second patterns.

Another aspect of the present invention provides a method for manufacturing a semiconductor device, including the steps of:

providing a substrate, and sequentially forming a stacking structure and a light resistance layer above the substrate, wherein the substrate comprises a device area and a cutting path area positioned at the periphery of the device area;

arranging a mask on one side of the photoresist layer far away from the stacked structure, wherein a part of the mask, corresponding to the device region, is provided with a plurality of first patterns, and a part of the mask, corresponding to the dicing channel region, is provided with a plurality of second patterns, wherein the shape and the size of each first pattern are the same as those of each second pattern, and the arrangement density of the first patterns is greater than that of the second patterns;

etching by taking the mask plate as a mask to form a plurality of openings which correspond to the first patterns and the second patterns one to one in the photoresist layer;

etching the stacked structure through the plurality of openings of the photoresist layer by taking the photoresist layer after photoetching as a mask so as to form a channel hole extending in a direction vertical to the stacked structure in the stacked structure; and

and when the size of the opening corresponding to at least one second pattern is monitored to be reduced to be smaller than a preset threshold value, judging that a byproduct generated by the stacked structure etching is abnormal, and stopping etching the stacked structure.

Compared with the prior art, the invention has the beneficial effects that: the mask is provided with a plurality of first patterns and a plurality of second patterns respectively corresponding to different areas of the semiconductor device, the first patterns and the second patterns are configured to be the same in shape and size, and the arrangement density of the first patterns is greater than that of the second patterns, so that after photoetching is carried out on a photoresist layer of the semiconductor device through the mask, the photoresist layer can correspondingly form a plurality of openings with different arrangement densities in different areas, and in the process of etching the semiconductor device through the openings, monitoring whether the size of the opening corresponding to the second pattern is reduced to be smaller than a preset threshold value can be carried out, so that the problem of by-product abnormity can be found in time before the production yield of the semiconductor device is influenced, the production yield of the semiconductor device is improved.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

FIG. 1 is a cross-sectional view of a mask and a semiconductor device when the mask provided by the invention is used for photoetching of the semiconductor device.

FIG. 2 is a schematic top view of a portion of the reticle shown in FIG. 1 in one embodiment.

Fig. 3 is a schematic view of a photoresist layer of the semiconductor device shown in fig. 1 having a plurality of openings formed by photolithography.

Fig. 4 is a schematic view of a stacked structure of the semiconductor device shown in fig. 3 in which a plurality of channel holes are formed by etching.

Fig. 5 is a schematic top view of the semiconductor device shown in fig. 4 in one embodiment.

Fig. 6 is a schematic flow chart of a method for manufacturing a semiconductor device according to the present invention.

Description of the main element symbols:

mask 1

First mask region 11

Second mask region 12

First pattern 111

Second pattern 121

Semiconductor device 2

Substrate 21

Stacking structure 22

Photoresist layer 23

Device region 211

Cutting street region 212

Channel hole 221

Opening 231

First scribe line region 2121

Second scribe line region 2122

The following detailed description will further illustrate the invention in conjunction with the above-described figures.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.

In the description of the present invention, it should be noted that the terms "upper", "lower", "inside", "outside", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

Referring to fig. 1, the present invention provides a mask 1 for photolithography of a semiconductor device 2. The mask 1 includes a first mask region 11 and a second mask region 12, the semiconductor device 2 includes a substrate 21, a stack structure 22 and a photoresist layer 23 stacked in sequence, and the substrate 21 includes a device region 211 and a scribe line region 212 located at the periphery of the device region 211. When the mask 1 is used for photolithography of the semiconductor device 2, the mask 1 is disposed on a side of the photoresist layer 23 away from the stack structure 22, the first mask region 11 corresponds to the device region 211, and the second mask region 12 corresponds to the scribe line region 212. It is understood that the device region 211 and the scribe line region 212 are the device region and the scribe line region of the semiconductor device 2.

Specifically, as shown in fig. 1, the first mask region 11 is provided with a plurality of first patterns 111, and the first patterns 111 are used to form openings in the photoresist layer 23 of the device region 211; the second mask region 12 is provided with a plurality of second patterns 121, and the second patterns 121 are used to form openings in the photoresist layer 23 of the scribe lane region 212. The first pattern 111 and the second pattern 121 have the same shape and size, and the arrangement density of the first patterns 111 is greater than that of the second patterns 121. It should be noted that, in the embodiment of the present invention, the arrangement density of the first patterns 111 is greater than the arrangement density of the second patterns 121, which means that: the number of the first patterns 111 per unit area is greater than the number of the second patterns 121.

Referring to fig. 2, in an embodiment, the first mask region 11 is provided with a plurality of first patterns 111 arranged in a multi-row and multi-column array, and the second mask region 12 is provided with a plurality of second patterns 121 arranged in a multi-row and multi-column array, wherein a row direction and a column direction of the first patterns 111 are respectively the same as a row direction and a column direction of the second patterns 121, a distance between any two adjacent first patterns 111 is the same, a distance between any two adjacent second patterns 121 is the same, and the first patterns 111 and the second patterns 121 are both circular. In this embodiment, the number of the first patterns 111 per unit area is greater than the number of the second patterns 121, and a distance between any two adjacent first patterns 111 is smaller than a distance between any two adjacent second patterns 121.

In other embodiments, the plurality of first patterns 111 and the plurality of second patterns 121 may not be arranged in an array, and a distance between any two adjacent first patterns 111 and a distance between any two adjacent second patterns 121 are not limited as long as the number of first patterns 111 per unit area is greater than the number of second patterns 121.

Referring to fig. 3, the first patterns 111 and the second patterns 121 are used to lithographically form openings 231 in the photoresist layer 23. Specifically, in an embodiment, the photoresist layer 23 is a forward photoresist layer, the first pattern 111 and the second pattern 121 are used for passing through an exposure light source, and the portion of the mask plate 1 except the portion provided with the first pattern 111 and the second pattern 121 is used for shielding the exposure light source, so that after development, the photoresist layer 23 and the portions corresponding to the plurality of first patterns 111 and the plurality of second patterns 121 are dissolved in a developing solution, thereby forming a plurality of openings 231 corresponding to the plurality of first patterns 111 and the plurality of second patterns 121 one by photolithography.

In other embodiments, the photoresist layer 23 may also be a negative photoresist layer, the first pattern 111 and the second pattern 121 are used for shielding an exposure light source, and the portion of the reticle 1 other than the portion provided with the first pattern 111 and the second pattern 121 is used for passing the exposure light source, so that after development, the photoresist layer 23 and the portions corresponding to the first patterns 111 and the second patterns 121 may also be dissolved in a developing solution, so as to lithographically form a plurality of openings 231 corresponding to the first patterns 111 and the second patterns 121. It should be noted that the photolithography process of the photoresist layer 23 includes, but is not limited to, exposure, development and the like, and the specific steps thereof are the same as those of the conventional photolithography process, which is not described in detail herein.

In an embodiment, the mask 1 may be composed of a transparent substrate and a light shielding layer disposed on the substrate, where a portion of the substrate on which the light shielding layer is disposed is used for shielding an exposure light source, and a portion of the substrate on which the light shielding layer is not disposed is used for passing through the exposure light source.

In other embodiments, the mask 1 may also be formed by an opaque substrate, and the mask 1 may be hollowed out through a portion of the exposure light source.

It is understood that the plurality of openings 231 correspond to the plurality of first patterns 111 and the plurality of second patterns 121 one to one, and therefore, the arrangement density of the plurality of openings 231 corresponding to the plurality of first patterns 111 is greater than the arrangement density of the plurality of openings 231 corresponding to the plurality of second patterns 121. In other words, the portion of the photoresist layer 23 corresponding to the scribe lane region 212 includes a smaller number of openings 231 per unit area than the portion of the photoresist layer 23 corresponding to the device region 211 includes. In addition, since the thicknesses of the portions of the photoresist layer 23 are generally the same, but the number of the openings 231 per unit area is different in the portions of the photoresist layer 23 corresponding to different regions of the substrate 21, the volume per unit area of the portions of the photoresist layer 23 corresponding to different regions of the substrate 21 is different, specifically, the volume per unit area of the portions of the photoresist layer 23 corresponding to the device region 211 is smaller, and the volume per unit area of the portions of the photoresist layer 23 corresponding to the scribe line region 212 is larger.

Referring to fig. 4, the stacked structure 22 is etched through the plurality of openings 231 by using the photoresist layer 23 after the photolithography as a mask, so that a plurality of channel holes 221 extending in a direction perpendicular to the stacked structure 22 are formed in the stacked structure 22, and the plurality of openings 231 correspond to the plurality of channel holes 221 one by one. It should be noted that the stacked structure 22 corresponds to a portion of the device region 211 of the substrate 21, and the channel hole 221 included in the stacked structure is used for forming a channel structure of the semiconductor device 2, where the channel structure is a storage structure of the semiconductor device 2; the stacked structure 22 corresponds to a portion of the dicing channel region 212 of the substrate 21, and the channel hole 221 included therein may form a channel structure to support the semiconductor device 2 and is removed after the semiconductor device 2 is manufactured, or the channel structure may not be formed.

As is well known, byproducts are generated during the etching process, the byproducts include a first type of byproducts generated by the reaction of the exposed portion of the stack structure 22 through the opening 231 with the etchant, and a second type of byproducts generated by the reaction of the photoresist layer 23 with the etchant, and the photoresist layer 23 is a consumable during the etching process. Wherein the first type of byproducts are generally deposited on the sidewalls of the channel hole 221 and/or the sidewalls of the opening 231, and the second type of byproducts are generally deposited on the surface of the photoresist layer 23, the sidewalls of the opening 231, and/or the sidewalls of the channel hole 221. When the amount of the byproducts is large, on one hand, the byproducts may fill the sidewalls of the channel hole 221 and/or the opening 231, thereby affecting the further progress of the etching, which may result in insufficient etching depth of the channel hole 221, and thus may not pass through the stacked structure 22 to the substrate 21; on the other hand, the byproducts may also be deposited on the surface of the photoresist layer 23, the sidewalls of the openings 231, and the sidewalls of the channel holes 221 at the same time, so that the byproducts in the adjacent openings 231 and the corresponding channel holes 221 are adhered together, and the channel structures formed in the adjacent channel holes 221 are bridged, which may cause a problem in the electrical performance of the semiconductor device 2.

In the embodiment of the present invention, the first pattern 111 and the second pattern 121 have the same shape and size, so that the shape and size of each opening 231 are the same, and the area of the portion of the stacked structure 22 exposed through each opening 231 is the same. It is understood that the areas of the portions of the stacked structure 22 exposed through each of the openings 231 are the same, and the average amount of the first type byproducts deposited in each of the openings 231 and the corresponding channel holes 221 is the same in the same etching process.

Further, as mentioned above, in the embodiment of the present invention, the volume of the portion of the photoresist layer 23 corresponding to the device region 211 in a unit area is small, and the volume of the portion of the photoresist layer 23 corresponding to the scribe line region 212 in a unit area is large, so that in the same etching process, the total amount of the second type of by-products generated by etching the portion of the photoresist layer 23 corresponding to the device region 211 is small, and the total amount of the second type of by-products generated by etching the portion of the photoresist layer 23 corresponding to the scribe line region 212 is large. In addition, as mentioned above, the photoresist layer 23 has a large number of the openings 231 per unit area corresponding to the device region 211, and the photoresist layer 23 has a small number of the openings 231 per unit area corresponding to the scribe lane region 212, so that the following can be clearly found in combination with the total amount of the second type of by-products and the number of the openings 231: the average amount of the second type of byproducts deposited in each of the openings 231 and the corresponding channel holes 221 included in the portion of the photoresist layer 23 corresponding to the device region 211 is smaller than the average amount of the second type of byproducts deposited in each of the openings 231 and the corresponding channel holes 221 included in the portion of the photoresist layer 23 corresponding to the scribe line region 212.

Therefore, in the embodiment of the present invention, when the semiconductor device 2 is etched, an average amount of the byproducts (including the first type byproducts and the second type byproducts) deposited in each of the openings 231 and the corresponding trench holes 221 included in the portion of the photoresist layer 23 corresponding to the device region 211 is smaller than an average amount of the byproducts deposited in each of the openings 231 and the corresponding trench holes 221 included in the portion of the photoresist layer 23 corresponding to the scribe line region 212. Based on this, it can be inferred that: when the by-products generated by the etching are abnormal (i.e., the total amount is large), compared to the opening 231 and the corresponding channel hole 221 included in the portion of the photoresist layer 23 corresponding to the scribe line region 212, the opening 231 and the corresponding channel hole 221 included in the portion of the photoresist layer 23 corresponding to the scribe line region 212 are more easily filled with the deposited by-products and are shrunk. That is, the opening 231 corresponding to the second pattern 121 is more likely to shrink when the by-product is abnormal than the opening 231 corresponding to the first pattern 111. It should be noted that, in the prior art, when the size of the opening 231 is smaller than a predetermined threshold, the channel hole 221 formed by etching the stacked structure 22 through the opening 231 has a defect of insufficient etching depth, that is, the channel hole 221 does not pass through the stacked structure 22 to the substrate 21. When the trench hole 221 penetrating through the stacked structure 22 is formed by etching any one of the openings 231, the opening 231 has a minimum diameter value, and the minimum diameter value is the predetermined threshold value. It is understood that for stacked structures 22 with different thicknesses, the predetermined threshold corresponding to the opening 231 is different in order to form the trench hole 221 penetrating through the stacked structure 22. Specifically, the larger the thickness of the stacked structure 22 is, the larger the preset threshold corresponding to the opening 231 for forming the channel hole 221 penetrating through the stacked structure 22 is, and the corresponding relationship between the preset threshold and the stacked structure 22 may be obtained through experiments, which is not described in detail herein.

As can be seen from the above, in the etching process of the semiconductor device 2, compared with monitoring whether the opening 231 corresponding to the first pattern 111 is reduced to be smaller than the preset threshold, by monitoring whether the opening 231 corresponding to the second pattern 121 is reduced to be smaller than the preset threshold, the problem of the by-product abnormality can be found earlier, that is, the defect of insufficient depth of the trench hole 221 generated by etching can be found. Further, according to the experiment of the inventors, it is shown that, during the etching, the number of the openings 231 reduced to be smaller than the preset threshold is proportional to the abnormal amount of the by-product generated by the etching, i.e., the more the by-product is generated by the etching, the more the number of the openings 231 reduced to be smaller than the preset threshold is.

In summary, in the mask 1 provided by the present invention, by disposing the plurality of first patterns 111 at the portion corresponding to the device region 211 of the semiconductor device 2 and disposing the plurality of second patterns 121 at the portion corresponding to the scribe lane region 212 of the semiconductor device 2, the plurality of first patterns 111 and the plurality of second patterns 121 are configured to have the same shape and size, and the arrangement density of the plurality of first patterns 111 is greater than the arrangement density of the second patterns 121, after the photoresist layer 23 of the semiconductor device 2 is subjected to photolithography by the mask 1, the photoresist layer 23 can correspondingly form the plurality of openings 231 having different arrangement densities in different regions, so that in the process of etching the semiconductor device 2 by using the photoresist layer 23 as a mask, by monitoring whether the openings 231 corresponding to the second patterns 121 are reduced to be smaller than a preset threshold value, the monitoring of the etching by-products can be realized, so that the problem of by-product abnormity can be found in time before the production yield of the semiconductor device 2 is influenced, and the production yield of the semiconductor device 2 can be improved.

It can be understood that, in the etching process, the byproducts are gradually increased, so that the opening 231 corresponding to the second pattern 121 is gradually decreased, and by comparing the size value of the opening 231 with the preset threshold, it is possible to avoid misjudgment of the byproduct abnormality when the reduction degree of the opening 231 corresponding to the second pattern 121 is small and the final etching effect is not affected, thereby ensuring normal etching of the semiconductor device 2, and being beneficial to further improving the production yield of the semiconductor device 2.

Referring to fig. 5, in an embodiment, the substrate 21 includes a plurality of device regions 211 distributed in a plurality of rows and columns array, and the scribe lane region 212 includes a plurality of first scribe lane regions 2121 extending along a first direction and spaced along a second direction, and a plurality of second scribe lane regions 2122 extending along the second direction and spaced along the first direction. Specifically, as shown in fig. 5, the first direction is a transverse direction shown in fig. 5, the second direction is a longitudinal direction shown in fig. 5, and the first direction is perpendicular to the second direction; the plurality of first scribe line regions 2121 and the plurality of second scribe line regions 2122 are vertically and crosswise distributed, each of the device regions 211 is rectangular, and adjacent device regions 211 are spaced apart by one first scribe line region 2121 or one second scribe line region 2122. Obviously, in other embodiments, the first direction may form an angle with the second direction but not perpendicular to the first direction, the plurality of first scribe line regions 2121 and the plurality of second scribe line regions 2122 are distributed in an oblique crossing manner, and each of the device regions 211 is in a parallelogram shape.

Wherein the substrate 21 is generally circular, and therefore, the number of the device regions 211 arranged in each row or each column may be different; in addition, when the substrate 21 has different sizes, the total number of the device regions 211 may also be different, and is not limited thereto. It should be noted that each of the device regions 211 is used for disposing a device structure (including, but not limited to, the stacked structure 22) to fabricate a memory chip in each of the device regions 211; the scribe line region 212 is used to divide the adjacent device regions 211 so as to separate the adjacent memory chips from each other. The specific method for manufacturing the memory chip in the device region 211 may adopt a method for manufacturing a memory chip known in the art, which is not described in detail herein; the scribe line region 212 may be formed by cutting, mechanically cutting, etching, or the like, which is commonly used in the art, to separate the adjacent device regions 211, which is not described in detail herein.

Of course, in other embodiments, the substrate 21 may also be provided with one device region 211 according to actual needs, and the device region 211 has a larger area, so that a memory chip with a larger volume can be manufactured in the device region 211.

It is understood that, when the device region 211 is plural, the first mask region 11 is also plural, and the number of the first mask region and the second mask region is equal to each other. In the embodiment of the present invention, since each of the device regions 211 is used for manufacturing a memory chip, each of the chips is provided with the channel structure, a portion of the mask 1 corresponding to each of the device regions 211 (i.e. each of the first mask regions 11) is provided with a plurality of the first patterns 111 for forming a plurality of the openings 231 by photolithography at a portion of the photoresist layer 23 corresponding to each of the device regions 211, and further forming a plurality of the channel holes 221 by etching at a portion of the stacked structure 22 corresponding to each of the device regions 211, so as to form a channel structure of each of the memory chips in a subsequent process.

As mentioned above, the portion of the mask 1 corresponding to the scribe line region 212 (i.e., the aforementioned second mask region 12) is provided with a plurality of the second patterns 121. Specifically, in an embodiment, a portion of the mask 1 corresponding to each of the first scribe line regions 2121 is provided with at least one pattern array region, a plurality of pattern array regions are distributed at different positions of the mask 1, and each of the pattern array regions is provided with a plurality of second patterns 121. Preferably, in this embodiment, orthographic projections of the pattern array regions on the substrate 21 have different distances from a center of the substrate 21, respectively, wherein the orthographic projections of the pattern array regions may be distributed along a same radial direction of the substrate 21, or may be distributed along different radial directions of the substrate 21. Of course, in other embodiments, the mask 1 may be provided with a pattern array region adjacent to each of the device regions 211. It can be understood that, when the mask 1 is provided with a plurality of pattern array regions corresponding to different positions of the substrate 21, each first mask region 11 corresponds to a pattern array region that is most adjacent to the first mask region, whether the by-product generated during the etching process by the portion of the semiconductor device 2 corresponding to the first mask region 11 that is adjacent to the pattern array region is abnormal is determined by monitoring whether the opening 231 corresponding to the second pattern 121 in the most adjacent pattern array region is reduced to be less than a preset threshold, and the reliability of the determination result is higher.

Obviously, in other embodiments, a plurality of pattern array regions may also be distributed on the portion of the mask 1 corresponding to the second scribe line region 2122, and distributed on different positions of the mask 1 along the radial direction of the substrate 21.

In other embodiments, the pattern array regions may also be simultaneously distributed on the portions of the mask 1 corresponding to the first scribe line region 2121 and the second scribe line region 2122, and distributed at different positions of the mask 1 along the radial direction of the substrate 21.

In other embodiments, the number of the pattern array regions may be one, and the pattern array regions are distributed in a portion of the mask 1 corresponding to the same first scribe lane region 2121 or a portion corresponding to the same second scribe lane region 2122.

Referring to fig. 6, the present invention further provides a method for manufacturing a semiconductor device, which includes the following steps.

S1, as shown in fig. 3, providing a substrate 21, and sequentially forming a stacked structure 22 and a photoresist layer 23 above the substrate 21, where the substrate 21 includes a device region 211 and a scribe line region 212 located at the periphery of the device region 211.

Wherein the substrate 21 may be made of a semiconductor material including but not limited to silicon, germanium, silicon germanium, gallium arsenide, silicon on insulator or germanium on insulator, or a non-conductive material including but not limited to glass, plastic or sapphire, preferably a semiconductor silicon substrate. The stacked structure 22 includes isolation layers (not shown) and sacrificial layers (not shown) alternately stacked in a direction away from the substrate 21, the isolation layers include, but are not limited to, silicon oxide or silicon carbide, the sacrificial layers include, but are not limited to, silicon nitride or silicon oxynitride, and the isolation layers and the sacrificial layers may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, and other methods commonly used in the art, which are not described in detail herein.

S2, as shown in fig. 3, a mask 1 is disposed on a side of the photoresist layer 23 away from the stack structure 22, a portion of the mask 1 corresponding to the device region 211 is provided with a plurality of first patterns 111, a portion of the mask 1 corresponding to the scribe lane region 212 is provided with a plurality of second patterns 121, wherein each of the first patterns 111 and each of the second patterns 121 have the same shape and size, and the arrangement density of the plurality of first patterns 111 is greater than the arrangement density of the plurality of second patterns 121.

It should be noted that, in the embodiment of the present invention, the arrangement density of the first patterns 111 is greater than the arrangement density of the second patterns 121, which means that: the number of the first patterns 111 per unit area is greater than the number of the second patterns 121.

Specifically, referring to fig. 1 and fig. 2 together, in an embodiment, the first mask region 11 is provided with a plurality of first patterns 111 arranged in an array of rows and columns, and the second mask region 12 is provided with a plurality of second patterns 121 arranged in an array of rows and columns, wherein a row direction and a column direction of the first patterns 111 are respectively the same as a row direction and a column direction of the second patterns 121, a distance between any two adjacent first patterns 111 is the same, a distance between any two adjacent second patterns 121 is the same, and the first patterns 111 and the second patterns 121 are both circular. In this embodiment, the number of the first patterns 111 per unit area is greater than the number of the second patterns 121, and a distance between any two adjacent first patterns 111 is smaller than a distance between any two adjacent second patterns 121.

In other embodiments, the plurality of first patterns 111 and the plurality of second patterns 121 may not be arranged in an array, and a distance between any two adjacent first patterns 111 and a distance between any two adjacent second patterns 121 are not limited as long as the number of first patterns 111 per unit area is greater than the number of second patterns 121.

S3, as shown in fig. 3, the mask 1 is used as a mask to perform etching, so as to form a plurality of openings 231 in the photoresist layer 23, which correspond to the plurality of first patterns 111 and the plurality of second patterns 121 one to one.

Specifically, in an embodiment, the photoresist layer 23 is a forward photoresist layer, the first pattern 111 and the second pattern 121 are used for passing through an exposure light source, and the portion of the mask plate 1 except the portion provided with the first pattern 111 and the second pattern 121 is used for shielding the exposure light source, so that after development, the photoresist layer 23 and the portions corresponding to the plurality of first patterns 111 and the plurality of second patterns 121 are dissolved in a developing solution, thereby forming a plurality of openings 231 corresponding to the plurality of first patterns 111 and the plurality of second patterns 121 one by photolithography. Obviously, in other embodiments, the photoresist layer 23 may also be a negative photoresist layer, the first pattern 111 and the second pattern 121 are used for shielding an exposure light source, and the portion of the mask plate 1 other than the portion provided with the first pattern 111 and the second pattern 121 is used for passing the exposure light source, so that after development, the photoresist layer 23 and the portions corresponding to the first patterns 111 and the second patterns 121 may also be dissolved in a developing solution, so as to lithographically form a plurality of openings 231 corresponding to the first patterns 111 and the second patterns 121. It should be noted that the photolithography process of the photoresist layer 23 includes, but is not limited to, exposure, development and the like, and the specific steps thereof are the same as those of the conventional photolithography process, which is not described in detail herein.

In an embodiment, the mask 1 may be composed of a transparent substrate and a light shielding layer disposed on the substrate, where a portion of the substrate on which the light shielding layer is disposed is used for shielding an exposure light source, and a portion of the substrate on which the light shielding layer is not disposed is used for passing through the exposure light source. Obviously, in other embodiments, the mask 1 may also be formed by an opaque substrate, and the part of the mask 1 that needs to pass through the exposure light source may be hollowed out.

It is understood that the plurality of openings 231 correspond to the plurality of first patterns 111 and the plurality of second patterns 121 one to one, and therefore, the arrangement density of the plurality of openings 231 corresponding to the plurality of first patterns 111 is greater than the arrangement density of the plurality of openings 231 corresponding to the plurality of second patterns 121. In other words, the portion of the photoresist layer 23 corresponding to the scribe lane region 212 includes a smaller number of openings 231 per unit area than the portion of the photoresist layer 23 corresponding to the device region 211 includes. In addition, since the thicknesses of the portions of the photoresist layer 23 are generally the same, but the number of the openings 231 per unit area is different in the portions of the photoresist layer 23 corresponding to different regions of the substrate 21, the volume per unit area of the portions of the photoresist layer 23 corresponding to different regions of the substrate 21 is different, specifically, the volume per unit area of the portions of the photoresist layer 23 corresponding to the device region 211 is smaller, and the volume per unit area of the portions of the photoresist layer 23 corresponding to the scribe line region 212 is larger.

S4, using the photo-etched photoresist layer 23 as a mask, etching the stacked structure 22 through the plurality of openings 231 of the photoresist layer 23, so as to form a trench hole 221 in the stacked structure 22, the trench hole extending in a direction perpendicular to the stacked structure 22.

It should be noted that the stacked structure 22 corresponds to a portion of the device region 211 of the substrate 21, and the channel hole 221 included in the stacked structure is used for forming a channel structure of the semiconductor device 2, where the channel structure is a storage structure of the semiconductor device 2; the stacked structure 22 corresponds to a portion of the dicing channel region 212 of the substrate 21, and the channel hole 221 included therein may form a channel structure to support the semiconductor device 2 and is removed after the semiconductor device 2 is manufactured, or the channel structure may not be formed.

S5, when it is detected that the size of the opening 231 corresponding to at least one of the second patterns 121 is reduced to be smaller than a predetermined threshold, determining that a byproduct generated by etching the stacked structure 22 is abnormal, and stopping etching the stacked structure 22.

It is understood that, when the stacked structure 22 is etched, an average amount of the byproducts deposited in each of the openings 231 and the corresponding channel holes 221 included in the portion of the photoresist layer 23 corresponding to the device region 211 is smaller than an average amount of the byproducts deposited in each of the openings 231 and the corresponding channel holes 221 included in the portion of the photoresist layer 23 corresponding to the scribe line region 212. Based on this, it can be inferred that: when the by-products generated by the etching are abnormal (i.e., the total amount is larger), compared to the opening 231 and the corresponding channel hole 221 included in the portion of the photoresist layer 23 corresponding to the scribe line region 212, the opening 231 and the corresponding channel hole 221 included in the portion of the photoresist layer 23 corresponding to the scribe line region 212 are more easily filled with the deposited by-products and are further reduced to be smaller than the predetermined threshold. That is, the opening 231 corresponding to the second pattern 121 is more likely to shrink when the by-product is abnormal than the opening 231 corresponding to the first pattern 111. From this, it can be deduced in reverse that: in the etching process of the semiconductor device 2, compared with monitoring whether the opening 231 corresponding to the first pattern 111 is shrunk, by monitoring whether the opening 231 corresponding to the second pattern 121 is shrunk to be smaller than the preset threshold, the problem of the by-product abnormality can be found earlier, and therefore, monitoring whether the opening 231 corresponding to the second pattern 121 is shrunk to be smaller than the preset threshold can be used for monitoring the etching by-product. For more detailed inference, please refer to the related description of the mask 1, which is not repeated herein.

Further, according to the experiments of the inventor, the number of the openings 231 reduced to be smaller than the preset threshold during the etching process of the stack structure 22 is proportional to the abnormal amount of the by-products generated by the etching, i.e., the more the by-products generated by the etching are, the more the number of the openings 231 is reduced.

In summary, in the manufacturing method of the semiconductor device provided by the present invention, by providing the plurality of first patterns 111 at the portion of the mask 1 corresponding to the device region 211 of the semiconductor device 2 and providing the plurality of second patterns 121 at the portion corresponding to the scribe lane region 212 of the semiconductor device 2, the plurality of first patterns 111 and the plurality of second patterns 121 are configured to have the same shape and size, and the arrangement density of the plurality of first patterns 111 is greater than the arrangement density of the second patterns 121, so that after the photoresist layer 23 of the semiconductor device 2 is subjected to photolithography by the mask 1, the photoresist layer 23 can correspondingly form the plurality of openings 231 having different arrangement densities in different regions, and further, in the process of etching the semiconductor device 2 by using the photoresist layer 23 as a mask, by monitoring whether the openings 231 corresponding to the second patterns 121 are reduced to be smaller than a preset threshold value, the monitoring of the etching by-products can be realized, so that the problem of more by-products can be found in time before the production yield of the semiconductor device 2 is influenced, and the production yield of the semiconductor device 2 can be improved.

When the trench hole 221 penetrating through the stacked structure 22 is formed by etching any one of the openings 231, the opening 231 has a minimum diameter value, and the minimum diameter value is the predetermined threshold value. It is understood that for stacked structures 22 with different thicknesses, the predetermined threshold corresponding to the opening 231 is different in order to form the trench hole 221 penetrating through the stacked structure 22. Specifically, the larger the thickness of the stacked structure 22 is, the larger the preset threshold corresponding to the opening 231 for forming the channel hole 221 penetrating through the stacked structure 22 is, and the corresponding relationship between the preset threshold and the stacked structure 22 may be obtained through experiments, which is not described in detail herein.

It can be understood that, in the etching process, the byproducts are gradually increased, so that the opening 231 corresponding to the second pattern 121 is gradually decreased, and by comparing the size value of the opening 231 with the preset threshold, it is possible to avoid misjudgment of the byproduct abnormality when the reduction degree of the opening 231 corresponding to the second pattern 121 is small and the final etching effect is not affected, thereby ensuring normal etching of the semiconductor device 2, and being beneficial to further improving the production yield of the semiconductor device 2.

It should be noted that the semiconductor device manufactured by the above manufacturing method also has other functions and features similar to those of the semiconductor device 2, and for a more detailed description, reference may be made to the related contents of the semiconductor device 2, and no further description is provided here.

Further, the present invention also provides a semiconductor device, which is manufactured by using the manufacturing method of the semiconductor device, and the semiconductor device has all functions and features of the semiconductor device 2, and for the specific description, reference may be made to the related content of the semiconductor device 2, and details are not repeated here.

While embodiments of the invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.