阅读说明：本技术 芯片、三维芯片、电子设备及三维芯片的制造方法 (Chip, three-dimensional chip, electronic device, and method for manufacturing three-dimensional chip ) 是由 王嵩 谈杰 刘成 于 2020-12-01 设计创作，主要内容包括：本发明公开了一种芯片、三维芯片、电子设备及三维芯片的制造方法,其中,所述芯片用作三维芯片的子芯片,所述芯片包括：内部接口和内部电路,内部电路用于实现所述芯片的收发功能,内部接口用于连接三维芯片中的其他子芯片,其中,内部电路通过静电释放电路连接到所述内部接口,静电释放电路用于将从所述内部接口灌入的静电荷进行释放。本申请针对构成三维芯片的内部的子芯片,在其内部电路和内部接口之间接入静电释放电路,该静电释放电路使得子芯片在组装的过程中发生ESD(Electro-Static discharge,静电释放)事件时,能够将从内部接口灌入的静电荷进行释放,从而能够避免子芯片被损坏,解决了现有技术中的三维芯片的可靠性较差的技术问题。(The invention discloses a chip, a three-dimensional chip, an electronic device and a manufacturing method of the three-dimensional chip, wherein the chip is used as a sub-chip of the three-dimensional chip and comprises: the chip comprises an internal interface and an internal circuit, wherein the internal circuit is used for realizing the transceiving function of the chip, the internal interface is used for connecting other sub-chips in the three-dimensional chip, the internal circuit is connected to the internal interface through a static electricity releasing circuit, and the static electricity releasing circuit is used for releasing static electricity filled from the internal interface. According to the Static electricity discharge circuit, the Static electricity discharge circuit is connected between the internal circuit and the internal interface of the internal sub-chip which forms the three-dimensional chip, and when an ESD (Electro-Static discharge) event occurs in the assembling process of the sub-chip, the Static electricity charged from the internal interface can be discharged, so that the sub-chip can be prevented from being damaged, and the technical problem that the reliability of the three-dimensional chip in the prior art is poor is solved.)

1. A chip, wherein the chip is used as a sub-chip of a three-dimensional chip, the chip comprising:

an internal interface and an internal circuit, wherein the internal circuit is used for realizing the transceiving function of the chip, the internal interface is used for connecting other sub-chips in the three-dimensional chip, and the three-dimensional chip comprises a chip body,

the internal circuit is connected to the internal interface through a static electricity discharge circuit, and the static electricity discharge circuit is used for discharging static electricity charged from the internal interface.

2. The chip of claim 1, wherein the number of the internal circuits is one or more, a single internal circuit includes any one of a transceiver circuit, a transmission circuit, a reception circuit, wherein,

the receiving and transmitting circuit is used for realizing the receiving function and the transmitting function of the chip;

the receiving circuit is used for realizing the receiving function of the chip;

the transmitting circuit is used for realizing the transmitting function of the chip.

3. The chip of claim 2, wherein each of the internal circuits corresponds to one of the internal interfaces and one of the electrostatic discharge circuits.

4. The chip of claim 1, wherein the internal interface connects the other sub-chips by way of hybrid bonding.

5. The chip of claim 1, wherein the chip is a memory chip or a logic chip.

6. A three-dimensional chip comprising two chips according to any one of claims 1 to 5, wherein the two chips are connected to each other via the respective internal interfaces.

7. The three-dimensional chip of claim 6, wherein each of said internal circuits corresponds to a respective one of said internal interfaces;

the two chips are a first chip and a second chip, respectively, wherein,

when the internal circuit of the first chip comprises a transceiver circuit, the internal circuit of the second chip comprises the transceiver circuit, an internal interface corresponding to the transceiver circuit of the first chip is correspondingly connected with an internal interface corresponding to the transceiver circuit of the second chip, and the transceiver circuit is used for realizing the receiving function and the sending function of the chip;

when the internal circuit of the first chip comprises a receiving circuit, the internal circuit of the second chip comprises a sending circuit, an internal interface corresponding to the receiving circuit of the first chip is correspondingly connected with an internal interface corresponding to the sending circuit of the second chip, the receiving circuit is used for realizing the receiving function of the chip, and the sending circuit is used for realizing the sending function of the chip;

when the internal circuit of the first chip comprises the sending circuit, the internal circuit of the second chip comprises the receiving circuit, and the internal interface corresponding to the sending circuit of the first chip is correspondingly connected with the internal interface corresponding to the receiving circuit of the second chip.

8. The three-dimensional chip of claim 6, wherein the internal interface of the first chip is connected to the internal interface of the second chip by hybrid bonding.

9. An electronic device, comprising: the chip of any one of claims 1-8.

10. A method of fabricating a three-dimensional chip, comprising:

providing two chips, wherein each chip comprises an internal interface and an internal circuit, the internal circuit is used for realizing the transceiving function of the chip, the internal interface of a first chip of the two chips is used for connecting the internal interface of a second chip of the two chips, the internal circuit is connected to the internal interface through an electrostatic discharge circuit, and the electrostatic discharge circuit is used for discharging electrostatic charges injected from the internal interface;

and connecting the two chips through the respective internal interfaces.

11. The method of fabricating a three-dimensional chip as recited in claim 10, wherein said connecting said two chips through respective said internal interfaces comprises:

growing a first bonding pillar on the internal interface of the first chip;

growing a second bonding pillar on the internal interface of the second chip;

and performing hybrid bonding on the first chip and the second chip through the first bonding pillar and the second bonding pillar.

Technical Field

The present invention relates to the field of integrated circuit technologies, and in particular, to a chip, a three-dimensional chip, an electronic device, and a method for manufacturing a three-dimensional chip.

Background

With the increasingly fine chip technology, the technology reaches 3 nanometers, the Moore's law meets the development bottleneck, the physical size almost reaches the limit, but the market requirement on the performance of the chip is not reduced. Under the circumstances, it is becoming more and more difficult to continue to reduce the critical dimension in various chip technologies to achieve performance enhancement, area reduction and cost reduction, and the integration of different chips or different regions of the same chip by using wafer three-dimensional integration is one of the main directions of the development of integrated circuit technologies, and the reliability of three-dimensional chips is receiving unprecedented attention.

However, the reliability of the three-dimensional chip in the prior art is poor.

Disclosure of Invention

The embodiment of the application provides a chip, a three-dimensional chip, an electronic device and a manufacturing method of the three-dimensional chip, and solves the technical problem that the reliability of the three-dimensional chip in the prior art is poor.

In a first aspect, the present application provides the following technical solutions through an embodiment of the present application:

a chip for use as a sub-chip of a three-dimensional chip, the chip comprising: the chip comprises an internal interface and an internal circuit, wherein the internal circuit is used for realizing the transceiving function of the chip, the internal interface is used for connecting other sub-chips in the three-dimensional chip, the internal circuit is connected to the internal interface through an electrostatic discharge circuit, and the electrostatic discharge circuit is used for discharging electrostatic charges poured from the internal interface.

In one embodiment, the number of the internal circuits is one or more, and a single internal circuit includes any one of a transceiver circuit, a receiving circuit and a transmitting circuit, wherein the transceiver circuit is used for realizing the receiving function and the transmitting function of the chip; the receiving circuit is used for realizing the receiving function of the chip; the transmitting circuit is used for realizing the transmitting function of the chip.

In one embodiment, each of the internal circuits corresponds to one of the internal interfaces and one of the electrostatic discharge circuits.

In one embodiment, the internal interface connects the other sub-chips by hybrid bonding.

In one embodiment, the chip is a memory chip or a logic chip.

In a second aspect, the present application provides the following technical solutions through an embodiment of the present application:

a three-dimensional chip comprising two chips according to any one of the first aspect, wherein the two chips are connected to each other through the respective internal interfaces.

In one embodiment, each of the internal circuits corresponds to one of the internal interfaces; the two chips are respectively a first chip and a second chip, wherein when an internal circuit of the first chip comprises a transceiver circuit, the internal circuit of the second chip comprises the transceiver circuit, an internal interface corresponding to the transceiver circuit of the first chip is correspondingly connected with an internal interface corresponding to the transceiver circuit of the second chip, and the transceiver circuit is used for realizing the receiving function and the sending function of the chips; when the internal circuit of the first chip comprises a receiving circuit, the internal circuit of the second chip comprises a sending circuit, an internal interface corresponding to the receiving circuit of the first chip is correspondingly connected with an internal interface corresponding to the sending circuit of the second chip, the receiving circuit is used for realizing the receiving function of the chip, and the sending circuit is used for realizing the sending function of the chip; when the internal circuit of the first chip comprises the sending circuit, the internal circuit of the second chip comprises the receiving circuit, and the internal interface corresponding to the sending circuit of the first chip is correspondingly connected with the internal interface corresponding to the receiving circuit of the second chip.

In one embodiment, the internal interface of the first chip is connected with the internal interface of the second chip by means of hybrid bonding.

In a third aspect, the present application provides the following technical solutions through an embodiment of the present application:

an electronic device comprising a chip as defined in any one of the first aspect.

In a fourth aspect, the present application provides the following technical solutions through an embodiment of the present application:

a method of manufacturing a three-dimensional chip, comprising: providing two chips, wherein each chip comprises an internal interface and an internal circuit, the internal circuit is used for realizing the transceiving function of the chip, the internal interface of a first chip of the two chips is used for connecting the internal interface of a second chip of the two chips, the internal circuit is connected to the internal interface through an electrostatic discharge circuit, and the electrostatic discharge circuit is used for discharging electrostatic charges injected from the internal interface; and connecting the two chips through the respective internal interfaces.

In one embodiment, the connecting the two chips through the respective internal interfaces includes: growing a first bonding pillar on the internal interface of the first chip; growing a second bonding pillar on the internal interface of the second chip; and performing hybrid bonding on the first chip and the second chip through the first bonding pillar and the second bonding pillar.

One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

the applicant finds that, in the process of assembling the three-dimensional chip by connecting the internal interface of the sub-chip with the internal interfaces of other sub-chips, the sub-chip is in direct contact with an external assembly device, and in the contact process, an ESD (Electro-Static discharge) event is easily generated on the internal interface of the sub-chip, and the ESD event generates a large instantaneous voltage and a large current, so as to damage an internal functional circuit, and cause the function failure of the sub-chip. Based on the discovery, the electrostatic discharge circuit is connected between the internal circuit and the internal interface of the internal sub-chip which forms the three-dimensional chip, and when the sub-chip generates an ESD event in the assembling process, the electrostatic discharge circuit can discharge the electrostatic charge injected from the internal interface, so that the sub-chip can be prevented from being damaged, the technical problems that the three-dimensional chip in the prior art is not perfect in electrostatic protection and the reliability of the three-dimensional chip is poor are solved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a chip according to an embodiment of the present disclosure;

FIG. 2 is a diagram of the internal connections of the chip provided in FIG. 1;

FIG. 3 is a schematic diagram of the internal structure of the chip provided in FIG. 2;

FIG. 4 is a schematic diagram of the internal structure of the chip provided in FIG. 2;

FIG. 5 is a schematic diagram of the internal structure of the chip provided in FIG. 2;

fig. 6 is a schematic structural diagram of a three-dimensional chip according to a second embodiment of the present disclosure;

FIG. 7 is a diagram of the interconnections of the three-dimensional chip provided in FIG. 6;

fig. 8 is an architecture diagram of an electronic device according to a third embodiment;

fig. 9 is a flowchart of a method for manufacturing a three-dimensional chip according to a fourth embodiment of the present disclosure;

fig. 10-12 are process flow diagrams of three-dimensional chips according to a second embodiment of the present disclosure.

Detailed Description

The embodiment of the application provides a chip, a three-dimensional chip, an electronic device and a manufacturing method of the three-dimensional chip, and solves the technical problem that the reliability of the three-dimensional chip in the prior art is poor.

In order to solve the technical problems, the general idea of the embodiment of the application is as follows:

the applicant finds that, in the process of assembling the three-dimensional chip by connecting the internal interface of the sub-chip with the internal interfaces of other sub-chips, the sub-chip is in direct contact with an external assembly device, during the contact process, an ESD (Electro-Static discharge) event is easily generated on the internal interface of the sub-chip, and the ESD event generates a transient large voltage and a large current to damage an internal functional circuit, so that the function of the sub-chip is disabled. Based on the discovery, the electrostatic discharge circuit is connected between the internal circuit and the internal interface of the internal sub-chip which forms the three-dimensional chip, and when the sub-chip generates an ESD event in the assembling process, the electrostatic discharge circuit can discharge the electrostatic charge injected from the internal interface, so that the sub-chip can be prevented from being damaged, and the technical problem that the reliability of the three-dimensional chip in the prior art is poor in the aspect of electrostatic protection is solved.

In order to better understand the technical solution, the technical solution will be described in detail with reference to the drawings and the specific embodiments.

First, it is stated that the term "and/or" appearing herein is merely one type of associative relationship that describes an associated object, meaning that three types of relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

Example one

As shown in fig. 1, the present embodiment provides a chip that serves as a sub-chip of a three-dimensional chip. It should be noted that the three-dimensional chip further includes other sub-chips, each sub-chip of the three-dimensional chip is connected through an internal interface I to implement transmission of internal data of the three-dimensional chip, and each sub-chip further provides an external interface corresponding to the internal interface I of the sub-chip, which is used as an interface for communication between the three-dimensional chip and an external device, and is hereinafter referred to as an external interface, and the chip that is used as the sub-chip of the three-dimensional chip is described in detail below.

The chip comprises an internal interface I and an internal circuit 1, wherein,

the internal circuit 1 is used for realizing the transceiving function of the chip, and the internal interface I is an interface externally provided by the internal circuit 1 and used for connecting other sub-chips in the three-dimensional chip so as to realize the communication between the internal circuit 1 of the chip and the other sub-chips.

In this embodiment, the internal circuit 1 is connected to the internal interface I through an electrostatic discharge circuit (hereinafter referred to as an ESD circuit 2), and the ESD circuit 2 is configured to discharge electrostatic charges injected from the internal interface I.

It should be noted that, when the three-dimensional chip leaves the factory and interacts with the customer, there are often damage situations, and when a damage event occurs to the three-dimensional chip, a person skilled in the art usually pays attention to whether there is a problem in the chip itself and whether an ESD event occurs to an external interface, but does not pay attention to whether an internal interface I of a sub-chip constituting the inside of the three-dimensional chip is damaged due to the occurrence of the ESD event, so that there are damage situations to the three-dimensional chip assembled at a later stage, and there are several obstacles that the person skilled in the art cannot pay attention to this point:

after an ESD event occurs, the external interface of the first three-dimensional chip and the internal interface I provided by the sub-chip in the three-dimensional chip are damaged, and no difference exists.

Secondly, as seen by those skilled in the art, there is a possibility that an ESD event may occur at an external interface of a three-dimensional chip, and an internal interface I is packaged inside and is not in contact with the outside, so that the ESD event does not occur.

Based on this, applicants' findings: the internal interface I of the sub-chip is connected with the internal interfaces I of other sub-chips, so that the sub-chip is in direct contact with external assembly equipment in the process of assembling the three-dimensional chip, an ESD (Electro-Static discharge) event can be easily generated on the internal interface I of the sub-chip in the contact process, the ESD event can generate instantaneous large voltage and large current to damage an internal function circuit, and the function failure of the sub-chip is caused. Based on the discovery, the ESD circuit 2 is connected between the internal circuit 1 and the internal interface I of the three-dimensional chip, and when the ESD circuit 2 enables the sub-chip to generate an ESD event in the assembling process, the static charge injected from the internal interface I can be released, so that the internal circuit connected with the internal interface in the sub-chip can be prevented from being damaged, the technical problem that the three-dimensional chip in the prior art is not perfect in the aspect of electrostatic protection and the reliability of the three-dimensional chip is poor is solved.

Further, during the process of cascading the sub-chips for assembling the three-dimensional chip by using the external device, the following three interfaces may be involved: input-output interfaces for both input and output signals, for example: i1 interface in fig. 2, output interface only for output signals, for example: the I2 interface in fig. 2, and an input interface for input signals only, such as: the I3 interfaces in fig. 2 are all prone to introduce static electricity, which causes chip damage, and therefore, the ESD circuit 2 may be provided for electrostatic protection between these internal interfaces I and the corresponding internal circuits 1.

Therefore, alternatively, the number of the internal circuits 1 may be one or more, and a single internal circuit 1 may include any one of the transceiver circuit 11, the transmission circuit 12, and the reception circuit 13. Each internal circuit 1 corresponds to one internal interface I and one ESD circuit 2, and for convenience of description, the internal interface I corresponding to the transceiver circuit 11 is hereinafter referred to as an input/output interface I1; the internal interface I corresponding to the receiving circuit 13 is hereinafter referred to as an input interface I3; the internal interface I corresponding to the transmission circuit 12 is hereinafter collectively referred to as an output interface I2. The ESD circuits 2 corresponding to the transceiver circuit 11 are hereinafter collectively referred to as a first protection circuit 21; the ESD circuit 2 corresponding to the transmission circuit 12 is hereinafter collectively referred to as a second protection circuit 22; the ESD circuit 2 corresponding to the reception circuit 13 is hereinafter collectively referred to as a third protection circuit 23.

It should be noted that, the transceiver circuit 11 herein refers to a circuit for implementing both the receiving function and the transmitting function of the chip, and as an example, the transceiver circuit 11 includes a receiver RX and a transmitter TX, and an input terminal of the receiver RX is connected to an output terminal of the transmitter TX to implement the receiving and transmitting functions of the chip. Here, the receiving circuit 13 refers to a circuit for realizing a receiving function of a chip, and as an example, the receiving circuit 13 may include a receiver RX. The transmission circuit 12 herein refers to a circuit for realizing a transmission function of a chip, and as an example, the transmission circuit 12 may include a transmitter TX.

When the internal circuit 1 includes the transceiver circuit 11, the transceiver circuit 11 is connected to the input/output interface I1 through the first protection circuit 21, and/or

When the internal circuit 1 comprises the transmission circuit 12, the transmission circuit 12 is connected to the output interface I2 via the second protection circuit 22, and/or

When the internal circuit 1 includes the receiving circuit 13, the receiving circuit 13 is connected to the input interface I3 through the third protection circuit 23.

More specifically, the first protection circuit 21, the second protection circuit 22, and the third protection circuit 23 may be any one of the ESD circuits 2 in the following three examples, and for convenience of description, connection points of the internal circuit 1 and the corresponding internal interface I are collectively referred to as protection points.

As shown in fig. 3, the ESD circuit 2 includes, as a first example: a first diode (such as diode D0, diode D2, and diode D4 in fig. 3), a second diode (such as diode D1, diode D3, and diode D5 in fig. 3), and a bidirectional ESD circuit (not shown in the figure, the circuit is already a very conventional circuit and is not described here), wherein a cathode of the first diode is connected to vdd, the second diode is connected to vss, the bidirectional ESD circuit is disposed between vdd and vss, and an anode of the first diode and an anode of the second diode are connected to a protection point.

And (3) electrostatic discharge process: taking the example of a chip interconnected with other sub-chips, an ESD event is generated at the I1 interface. When a forward ESD voltage is generated between the I1 interface and vdd, that is, the I1 interface voltage is higher than vdd, the diode D0 is turned on, so as to drain the current between the I1 interface and vdd, and reduce the voltage between the I1 interface and vdd, thereby protecting the internal circuit 1. When a negative ESD voltage is generated between the I1 interface and vdd, that is, the voltage of the I1 interface is lower than vdd, because there is no voltage on vss (vss is floating), the diode D1 is turned on and the bidirectional ESD circuit between vss and vdd is turned on, so as to drain the current between the I1 interface and vdd, reduce the voltage between the I1 interface and vdd, and thus protect the internal circuit 1. When a forward ESD voltage is generated between the I1 interface and the vss, namely the I1 interface voltage is higher than the vss, because there is no voltage on vdd (vdd is floating), the diode D0 is conducted, and the bidirectional ESD circuit between vdd and vss is conducted, so that the current between the I1 interface and the vss is discharged, and the voltage between the I1 interface and the vss is reduced; when a negative ESD voltage is generated between the I1 interface and the vss, namely the voltage of the I1 interface is lower than the vss, the diode D1 conducts to discharge the current between the I1 interface and the vss and reduce the voltage between the I1 interface and the vss. ESD events generated on other interfaces will also have corresponding bleed paths.

As shown in fig. 4, a second example, the ESD circuit 2 includes: the protection circuit comprises NPN triodes (such as a triode T0, a triode T2 and a triode T4 in fig. 4), PNP triodes (such as a triode T1, a triode T3 and a triode T5 in fig. 4), and a bidirectional ESD circuit (not shown in the figure, the circuit is a very conventional circuit and is not described herein again), wherein a base of the NPN triode is connected to vss, a collector of the NPN triode is connected to vdd, a base of the PNP triode is connected to vdd, a collector of the NPN triode is connected to vss, the bidirectional ESD circuit is arranged between vdd and vss, and an emitter of the NPN triode and an emitter of the PNP triode are both connected to a protection point.

And (3) electrostatic discharge process: taking the example of a chip interconnected with other sub-chips, an ESD event is generated at the I1 interface. When a forward ESD voltage is generated between the I1 interface and vdd, that is, the I1 interface voltage is higher than vdd, the transistor T0 is turned on, so as to drain the current between the I1 interface and vdd, and reduce the voltage between the I1 interface and vdd, thereby protecting the internal circuit 1. When a negative ESD voltage is generated between the I1 interface and vdd, that is, the voltage of the I1 interface is lower than vdd, because there is no voltage (vss floating) on vss, the transistor T1 is turned on and the bidirectional ESD circuit between vss and vdd is turned on, so as to drain the current between the I1 interface and vdd, and reduce the voltage between the I1 interface and vdd, thereby protecting the internal circuit 1. When a forward ESD voltage is generated between the I1 interface and the vss, namely the I1 interface voltage is higher than the vss, because there is no voltage on vdd (vdd is floating), the transistor T0 is turned on, and the bidirectional ESD circuit between vdd and vss is turned on, so that the current between the I1 interface and the vss is discharged, and the voltage between the I1 interface and the vss is reduced; when a negative ESD voltage is generated between the I1 interface and the vss, namely the I1 interface voltage is lower than the vss, the transistor T1 is conducted to discharge the current between the I1 interface and the vss and reduce the voltage between the I1 interface and the vss. ESD events generated on other interfaces will also have corresponding bleed paths.

As shown in fig. 5, a third example, the ESD circuit 2 includes: a first NMOS transistor (e.g., the transistor M0, the transistor M2, and the transistor M4 in fig. 5), a second NMOS transistor (e.g., the transistor M1, the transistor M3, and the transistor M5 in fig. 5), and a bidirectional ESD circuit (not shown in the drawings, the circuit is already very conventional and will not be described here), wherein the gate and the drain of the first NMOS transistor are all wired to vdd, the gate and the source of the second NMOS transistor are all wired to vss, the source of the first NMOS transistor and the drain of the second NMOS transistor are both wired to a protection point, and the bidirectional ESD circuit is disposed between vdd and vss.

And (3) electrostatic discharge process: taking the example of a chip interconnected with other sub-chips, an ESD event is generated at the I1 interface. When a forward ESD voltage is generated between the I1 interface and vdd, that is, the I1 interface voltage is higher than vdd, the transistor M0 is turned on, so as to drain the current between the I1 interface and vdd, and reduce the voltage between the I1 interface and vdd, thereby protecting the internal circuit 1. When a negative ESD voltage is generated between the I1 interface and vdd, that is, the voltage at the I1 interface is lower than vdd, because there is no voltage (vss floating) on vss, the transistor M1 is turned on and the bidirectional ESD circuit between vss and vdd is turned on, so as to drain the current between the I1 interface and vdd, and reduce the voltage between the I1 interface and vdd, thereby protecting the internal circuit 1. When a forward ESD voltage is generated between the I1 interface and the vss, namely the I1 interface voltage is higher than the vss, because there is no voltage on vdd (vdd is floating), the transistor M0 is turned on, and the bidirectional ESD circuit between vdd and vss is turned on, so that the current between the I1 interface and the vss is discharged, and the voltage between the I1 interface and the vss is reduced; when a negative ESD voltage is generated between the I1 interface and vss, i.e. the voltage of the I1 interface is lower than vss, the transistor M1 is turned on to drain the current between the I1 interface and vss, and lower the voltage between the I1 interface and vss, and there will be corresponding drain paths for ESD events generated on other interfaces.

The first protection circuit 21, the second protection circuit 22, and the third protection circuit 23 may be any one of the ESD circuits 2 in the above three examples, and may be the same or different, and in addition, the bidirectional ESD circuits provided between vdd and vss in the above three examples may be shared.

As an alternative embodiment, the internal interface I is connected to other sub-chips by Hybrid Bonding (HB), which generally requires that the chip is completely penetrated Through and only a few pillars are connected between the chips, compared to the Through Silicon Via (TSV) technology in the prior art, and is not very thick.

It should be noted that the internal interface I may also be connected to other sub-chips through other connection manners, which is not limited herein as long as the metal layer of the chip and the metal layer of the other sub-chips can be directly connected.

As an alternative embodiment, the chip is a memory chip or a logic chip.

The technical scheme in the embodiment of the application at least has the following technical effects or advantages:

the applicant finds that, in the process of assembling the three-dimensional chip by connecting the internal interface I of the sub-chip with the internal interface I of another sub-chip, the sub-chip is in direct contact with an external assembly device, and in the contact process, an ESD (Electro-Static discharge) event is easily generated on the internal interface I of the sub-chip, and the ESD event generates a transient large voltage and a large current, so as to damage an internal functional circuit, thereby causing the functional failure of the sub-chip. Based on the above discovery, the ESD circuit 2 is connected between the internal circuit 1 and the internal interface I of the internal sub-chip forming the three-dimensional chip, and the ESD circuit 2 can release the static charge injected from the internal interface I when the sub-chip generates an ESD event in the assembling process, so that the sub-chip can be prevented from being damaged, and the technical problem that the reliability of the three-dimensional chip in the prior art is poor in the aspect of electrostatic protection is solved.

Example two

As shown in fig. 6, the present embodiment provides a three-dimensional chip, including two chips according to any one of the first embodiment, and for convenience of illustration, the two chips are respectively a first chip S01 and a second chip S02, and the internal interface I of the first chip S01 and the second chip S02 are connected to each other through the respective internal interfaces I, it should be understood that, even though the two chips are distinguished in name, the first chip S01 and the second chip S02 both have the structure and function of the chip provided in the first embodiment.

In practical implementation, the first chip S01 and the second chip S02 may be memory chips or logic chips.

The applicant found that: in the process of assembling the three-dimensional chip by connecting the internal interface I of the first chip S01 and the internal interface I of the second chip S02, the internal interface I of the first chip S01, the internal interface I of the second chip S02 and an external assembly device are in direct contact, during the contact process, an ESD (Electro-Static discharge) event is easily generated on the internal interface I, and the ESD event generates instantaneous large voltage and large current to damage an internal functional circuit, so that the functional failure of the sub-chip is caused. Based on the discovery, the ESD circuit 2 is connected between the internal circuit 1 and the internal interface I of the first chip S01 and the second chip S02 which form the inside of the three-dimensional chip, and when the ESD event occurs in the assembly process of the sub-chip, the ESD circuit 2 can release the electrostatic charge injected from the internal interface I, so that the sub-chip can be prevented from being damaged, and the technical problem that the three-dimensional chip in the prior art is not perfect in electrostatic protection and poor in reliability is solved.

As an alternative embodiment, as shown in fig. 7, each internal circuit 1 of the first chip S01 has an internal interface I, and each internal circuit 1 of the second chip S02 has an internal interface I, wherein,

when the internal circuit 1 of the first chip S01 includes the transceiver circuit 11, the internal circuit 1 of the second chip S02 includes the transceiver circuit 11, and the internal interface I corresponding to the transceiver circuit 11 of the first chip S01 is correspondingly connected to the internal interface I corresponding to the transceiver circuit 11 of the second chip S02;

when the internal circuit 1 of the first chip S01 includes the receiving circuit 13, the internal circuit 1 of the second chip S02 includes the transmitting circuit 12, and the internal interface I corresponding to the receiving circuit 13 of the first chip S01 corresponds to the internal interface I corresponding to the transmitting circuit 12 connected to the second chip S02;

when the internal circuit 1 of the first chip S01 includes the transmitting circuit 12, the internal circuit 1 of the second chip S02 includes the receiving circuit 13, and the internal interface I corresponding to the transmitting circuit 12 of the first chip S01 is correspondingly connected to the internal interface I corresponding to the receiving circuit 13 of the second chip S02.

As an alternative embodiment, as shown in fig. 7, the internal interface I of the first chip S01 is connected to the internal interface I of the second chip S02 by Hybrid Bonding (HB), which generally requires the chips to be completely penetrated Through and only a few pillars to be connected between the chips, and is very thick, compared to the Through Silicon Via (TSV) technology in the prior art, the hybrid bonding technology in this embodiment does not require the chips to be penetrated Through and can generate a very large number of connection pillars.

It should be noted that the internal interface I of the first chip S01 may also be connected to the internal interface I of the second chip S02 by other connection methods, as long as the metal layer of the first chip S01 is directly connected to the metal layer of the second chip S02.

The technical scheme in the embodiment of the application at least has the following technical effects or advantages:

the applicant finds that, in the process of assembling the three-dimensional chip by connecting the internal interface I of the sub-chip with the internal interface I of another sub-chip, the sub-chip is in direct contact with an external assembly device, and in the contact process, an ESD (Electro-Static discharge) event is easily generated on the internal interface I of the sub-chip, and the ESD event generates a transient large voltage and a large current, so as to damage an internal functional circuit, thereby causing the functional failure of the sub-chip. Based on the discovery, the electrostatic discharge circuit is connected between the internal circuit 1 and the internal interface I of the internal sub-chip forming the three-dimensional chip, the electrostatic discharge circuit enables the sub-chip to generate an ESD event in the process of assembling the three-dimensional chip, and the electrostatic charge injected from the internal interface I can be released, so that the sub-chip can be prevented from being damaged, and the technical problem that the reliability of the three-dimensional chip in the prior art is poor in the aspect of electrostatic protection is solved.

EXAMPLE III

As shown in fig. 8, the present embodiment provides an electronic device, which includes a chip, where the chip is used as a sub-chip of a three-dimensional chip, the chip includes an internal interface I and an internal circuit 1, the internal circuit 1 is used to implement a transceiving function of the chip, the internal interface 3 is used to connect other sub-chips in the three-dimensional chip, where the internal circuit 1 is connected to the internal interface I through an ESD circuit 2, and the ESD circuit 2 is used to discharge static charges injected from the internal interface I.

In a specific implementation process, the electronic device may further include the chip described in any one of the first embodiment.

Example four

As shown in fig. 9, the present embodiment provides a method for manufacturing a three-dimensional chip, including:

step 301: providing two chips, wherein each chip comprises an internal interface and an internal circuit, the internal circuit is used for realizing the transceiving function of the chip, the internal interface of a first chip in the two chips is used for connecting the internal interface of a second chip in the two chips, the internal circuit is connected to the internal interface through an electrostatic discharge circuit, and the electrostatic discharge circuit is used for discharging electrostatic charges injected from the internal interface;

step 302: the two chips are connected through respective internal interfaces.

As an alternative embodiment, as shown in fig. 10-12, step 302 includes:

growing a first bonding pillar A on the internal interface I (i.e. the metal layer TM1 in FIG. 10) of the first chip;

growing a second bonding pillar B on the internal interface I (i.e., the metal layer TM2 in FIG. 11) of the second chip;

the first chip and the second chip are mixed and bonded through the first bonding posts a and the second bonding posts B to form a three-dimensional chip as shown in fig. 12.

In this embodiment, the electrostatic discharge circuit is connected between the internal circuit and the internal interface of the sub-chip for assembling the three-dimensional chip, and the electrostatic discharge circuit enables an ESD event to occur in the process of assembling the three-dimensional chip, and can discharge electrostatic charges injected from the internal interface, thereby preventing the sub-chip from being damaged, and solving the technical problem that the reliability of the three-dimensional chip in the prior art is poor in the aspect of electrostatic protection.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.