阅读说明：本技术 驱动窄脉冲的抑制方法、装置、设备和存储介质 (Method, device, equipment and storage medium for suppressing driving narrow pulse ) 是由 娄丽丽 索红亮 张洪涛 何永超 于 2020-11-24 设计创作，主要内容包括：本发明提供了一种驱动窄脉冲的抑制方法、装置、设备和存储介质,适用于电力电子技术领域,该方法包括：获取目标IGBT主管的驱动脉冲信号；当检测到驱动脉冲信号的跳变沿时,统计驱动脉冲信号从跳变沿开始保持电平不变的信号持续时长；在跳变沿为上升沿的情况下,若信号持续时长大于死区时长并且小于死区时长与抑制时长之和,则复位目标IGBT主管的封脉信号,否则使能目标IGBT主管的封脉信号；当检测到逐波限流故障时,若目标IGBT主管的封脉信号使能,则封锁目标IGBT主管并在经过死区时长后封锁目标IGBT辅管,否则不响应逐波限流故障。采用本发明可以提高IGBT运行的可靠性。(The invention provides a method, a device, equipment and a storage medium for suppressing a driving narrow pulse, which are suitable for the technical field of power electronics, and the method comprises the following steps: acquiring a driving pulse signal of a target IGBT main pipe; when the jump edge of the driving pulse signal is detected, counting the signal duration of the driving pulse signal, wherein the level of the driving pulse signal is kept unchanged from the jump edge; under the condition that the jumping edge is a rising edge, if the signal duration is longer than the dead zone time and shorter than the sum of the dead zone time and the inhibition time, resetting the pulse sealing signal of the target IGBT main pipe, otherwise enabling the pulse sealing signal of the target IGBT main pipe; when the wave-by-wave current limiting fault is detected, if the pulse sealing signal of the target IGBT main pipe is enabled, the target IGBT main pipe is blocked, the target IGBT auxiliary pipe is blocked after the dead zone time length, and otherwise, the wave-by-wave current limiting fault is not responded. The invention can improve the reliability of the IGBT operation.)

1. A method of suppressing drive narrow pulses, the method being applied to an inverter comprising at least one main IGBT pipe and at least one auxiliary IGBT pipe complementary to the main IGBT pipe, the method comprising:

acquiring a driving pulse signal of a target IGBT main pipe;

when the jump edge of the driving pulse signal is detected, counting the signal duration of the driving pulse signal, wherein the level of the driving pulse signal is kept unchanged from the jump edge;

under the condition that the jumping edge is a rising edge, if the signal duration is longer than the dead zone time and shorter than the sum of the dead zone time and the inhibition time, resetting the pulse sealing signal of the target IGBT main pipe, otherwise enabling the pulse sealing signal of the target IGBT main pipe;

under the condition that the jumping edge is a falling edge, if the signal duration is less than the inhibition duration, resetting the pulse sealing signal of the target IGBT main pipe, otherwise enabling the pulse sealing signal of the target IGBT main pipe;

when the wave-by-wave current limiting fault is detected, if the pulse sealing signal of the target IGBT main pipe is enabled, the target IGBT main pipe is blocked, the target IGBT auxiliary pipe is blocked after the dead zone time length, and otherwise, the wave-by-wave current limiting fault is not responded.

2. The method of suppressing driving a narrow pulse according to claim 1, further comprising:

outputting the driving pulse signal according to the comparison result of the modulation wave and the triangular carrier wave; and the carrier frequency of the triangular carrier corresponds to the switching frequency of the target IGBT main pipe and the switching frequency of the target IGBT auxiliary pipe.

3. The method of suppressing driving narrow pulses according to claim 2, wherein said inverter is a diode midpoint clamped three-level inverter;

the outputting the driving pulse signal according to the comparison result of the modulation wave and the triangular carrier wave includes:

under the condition that the target IGBT main pipe is an IGBT main pipe corresponding to the forward triangular carrier wave, when the modulation wave is larger than the forward triangular carrier wave, a high-level driving pulse signal is output; when the modulation wave is less than or equal to the forward triangular carrier wave, outputting a low-level driving pulse signal;

under the condition that the target IGBT main pipe is an IGBT main pipe corresponding to the negative triangular carrier wave, when the modulation wave is smaller than the negative triangular carrier wave, outputting a high-level driving pulse signal; and when the modulation wave is greater than or equal to the negative triangular carrier, outputting a low-level driving pulse signal.

4. A method of suppressing driving a narrow pulse according to claim 3, said method further comprising:

and when the wave-by-wave current-limiting fault is eliminated, loading a reset signal of the wave-by-wave current-limiting fault at the wave peak value of a preset triangular carrier, wherein the preset triangular carrier is the positive triangular carrier or the negative triangular carrier.

5. A suppression device for driving narrow pulses, said device being applied to an inverter comprising at least one main IGBT pipe and at least one auxiliary IGBT pipe complementary to said main IGBT pipe, said device comprising:

the acquisition module is used for acquiring a driving pulse signal of the target IGBT main pipe;

the counting module is used for counting the signal duration of the driving pulse signal, the level of which is kept unchanged from the jumping edge, when the jumping edge of the driving pulse signal is detected;

the first control module is used for resetting the pulse sealing signal of the target IGBT main pipe if the signal duration is longer than the dead zone time and shorter than the sum of the dead zone time and the inhibition time under the condition that the jumping edge is a rising edge, and otherwise enabling the pulse sealing signal of the target IGBT main pipe;

the second control module is used for resetting the pulse sealing signal of the target IGBT main pipe if the signal duration is shorter than the inhibition duration under the condition that the jumping edge is a falling edge, and otherwise enabling the pulse sealing signal of the target IGBT main pipe;

and the third control module is used for blocking the target IGBT main pipe and blocking the target IGBT auxiliary pipe after the dead zone time length passes if the pulse blocking signal of the target IGBT main pipe is enabled when the wave-by-wave current limiting fault is detected, or else, not responding to the wave-by-wave current limiting fault.

6. The apparatus for suppressing driving of narrow pulses according to claim 5, wherein said apparatus further comprises an output module for:

outputting the driving pulse signal according to the comparison result of the modulation wave and the triangular carrier wave; and the carrier frequency of the triangular carrier corresponds to the switching frequency of the target IGBT main pipe and the switching frequency of the target IGBT auxiliary pipe.

7. The apparatus for suppressing driving of a narrow pulse according to claim 6, wherein said inverter is a diode midpoint clamped three-level inverter;

the output module is further configured to:

under the condition that the target IGBT main pipe is an IGBT main pipe corresponding to the forward triangular carrier wave, when the modulation wave is larger than the forward triangular carrier wave, a high-level driving pulse signal is output; when the modulation wave is less than or equal to the forward triangular carrier wave, outputting a low-level driving pulse signal;

under the condition that the target IGBT main pipe is an IGBT main pipe corresponding to the negative triangular carrier wave, when the modulation wave is smaller than the negative triangular carrier wave, outputting a high-level driving pulse signal; and when the modulation wave is greater than or equal to the negative triangular carrier, outputting a low-level driving pulse signal.

8. The apparatus for suppressing driving of a narrow pulse according to claim 7, wherein said apparatus further comprises a loading module for:

and when the wave-by-wave current-limiting fault is eliminated, loading a reset signal of the wave-by-wave current-limiting fault at the wave peak value of a preset triangular carrier, wherein the preset triangular carrier is the positive triangular carrier or the negative triangular carrier.

9. An apparatus, comprising: a processor and a memory storing computer program instructions;

the processor, when executing the computer program instructions, performs the steps of the method according to any of claims 1-4.

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 4.

Technical Field

The invention belongs to the technical field of power electronics, and particularly relates to a method, a device, equipment and a storage medium for suppressing a driving narrow pulse.

Background

An Insulated Gate Bipolar Transistor (IGBT) is used as a core device of the inverter, and the safety and reliability of the working performance of the IGBT are directly related to the stability and reliability of the operation of the whole inverter. In the operation process of the inverter, a wave-by-wave current limiting technology is usually adopted, once a wave-by-wave current limiting fault occurs, the inverter can block the drive pulse (which can be called as pulse sealing) of the IGBT but does not report the fault and stop the machine, and after the wave-by-wave current limiting fault disappears, the drive pulse (which can be called as pulse opening) of the IGBT is opened, so that the inverter is protected, and the customer experience is not influenced. However, at the pulse sealing moment of the wave-by-wave current limiting fault, a driving narrow pulse occurs, and the reliable operation of the IGBT is affected. In order to reduce the influence of the driving narrow pulse on the reliable operation of the IGBT, the driving narrow pulse needs to be detected and processed.

At present, a hardware circuit is usually adopted to detect the driving narrow pulse, however, the hardware circuit has device errors, so that the driving narrow pulse cannot be accurately detected, and further, the driving narrow pulse is difficult to inhibit, and the reliability of the operation of the IGBT is reduced.

Disclosure of Invention

In view of this, embodiments of the present invention provide a method, an apparatus, a device, and a storage medium for suppressing a driving narrow pulse, so as to solve the problem of low reliability of the operation of the IGBT in the prior art. In order to achieve the purpose, the invention adopts the technical scheme that:

a first aspect of embodiments of the present invention provides a method for suppressing a driving narrow pulse, where the method is applied to an inverter, the inverter includes at least one main IGBT transistor and at least one auxiliary IGBT transistor complementary to the main IGBT transistor, and the method for suppressing a driving narrow pulse includes:

acquiring a driving pulse signal of a target IGBT main pipe;

when the jump edge of the driving pulse signal is detected, counting the signal duration of the driving pulse signal, wherein the level of the driving pulse signal is kept unchanged from the jump edge;

under the condition that the jumping edge is a rising edge, if the signal duration is longer than the dead zone time and shorter than the sum of the dead zone time and the inhibition time, resetting the pulse sealing signal of the target IGBT main pipe, otherwise enabling the pulse sealing signal of the target IGBT main pipe;

under the condition that the jumping edge is a falling edge, if the signal duration is less than the inhibition duration, resetting the pulse sealing signal of the target IGBT main pipe, otherwise enabling the pulse sealing signal of the target IGBT main pipe;

when the wave-by-wave current limiting fault is detected, if the pulse sealing signal of the target IGBT main pipe is enabled, the target IGBT main pipe is blocked, the target IGBT auxiliary pipe is blocked after the dead zone time length, and otherwise, the wave-by-wave current limiting fault is not responded.

Optionally, the method for suppressing the driving narrow pulse further includes:

outputting a driving pulse signal according to a comparison result of the modulation wave and the triangular carrier wave; the carrier frequency of the triangular carrier corresponds to the switching frequency of the target IGBT main pipe and the target IGBT auxiliary pipe.

Optionally, the inverter is a diode midpoint clamping type three-level inverter;

outputting a driving pulse signal according to a comparison result of the modulation wave and the triangular carrier, comprising:

under the condition that the target IGBT main pipe is an IGBT main pipe corresponding to the forward triangular carrier wave, when the modulation wave is larger than the forward triangular carrier wave, a high-level driving pulse signal is output; when the modulation wave is less than or equal to the forward triangular carrier wave, outputting a low-level driving pulse signal;

under the condition that the target IGBT main pipe is the IGBT main pipe corresponding to the negative triangular carrier wave, when the modulation wave is smaller than the negative triangular carrier wave, a high-level driving pulse signal is output; and when the modulation wave is greater than or equal to the negative triangular carrier, outputting a low-level driving pulse signal.

Optionally, the method for suppressing the driving narrow pulse further includes:

when the wave-by-wave current-limiting fault is eliminated, a reset signal of the wave-by-wave current-limiting fault is loaded at the wave peak value of a preset triangular carrier, and the preset triangular carrier is a positive triangular carrier or a negative triangular carrier.

A second aspect of embodiments of the present invention provides a suppression device for driving a narrow pulse, the suppression device for driving a narrow pulse being applied to an inverter, the inverter including at least one main IGBT pipe and at least one auxiliary IGBT pipe complementary to the main IGBT pipe, the suppression device for driving a narrow pulse including:

the acquisition module is used for acquiring a driving pulse signal of the target IGBT main pipe;

the counting module is used for counting the signal duration of the driving pulse signal, the level of which is kept unchanged from the jumping edge, when the jumping edge of the driving pulse signal is detected;

the first control module is used for resetting the pulse sealing signal of the target IGBT main pipe if the signal duration is longer than the dead zone time and shorter than the sum of the dead zone time and the inhibition time under the condition that the jumping edge is a rising edge, and otherwise enabling the pulse sealing signal of the target IGBT main pipe;

the second control module is used for resetting the pulse sealing signal of the target IGBT main pipe if the signal duration is less than the inhibition duration under the condition that the jumping edge is a falling edge, and otherwise enabling the pulse sealing signal of the target IGBT main pipe;

and the third control module is used for blocking the target IGBT main pipe and blocking the target IGBT auxiliary pipe after the dead zone time length passes if the pulse blocking signal of the target IGBT main pipe is enabled when the wave-by-wave current limiting fault is detected, or else, not responding to the wave-by-wave current limiting fault.

Optionally, the apparatus for suppressing driving of a narrow pulse further comprises an output module, configured to:

outputting a driving pulse signal according to a comparison result of the modulation wave and the triangular carrier wave; the carrier frequency of the triangular carrier corresponds to the switching frequency of the target IGBT main pipe and the target IGBT auxiliary pipe.

Optionally, the inverter is a diode midpoint clamping type three-level inverter;

an output module further configured to:

under the condition that the target IGBT main pipe is an IGBT main pipe corresponding to the forward triangular carrier wave, when the modulation wave is larger than the forward triangular carrier wave, a high-level driving pulse signal is output; when the modulation wave is less than or equal to the forward triangular carrier wave, outputting a low-level driving pulse signal;

under the condition that the target IGBT main pipe is the IGBT main pipe corresponding to the negative triangular carrier wave, when the modulation wave is smaller than the negative triangular carrier wave, a high-level driving pulse signal is output; and when the modulation wave is greater than or equal to the negative triangular carrier, outputting a low-level driving pulse signal.

Optionally, the apparatus for suppressing the driving of the narrow pulse further includes a loading module, configured to:

when the wave-by-wave current-limiting fault is eliminated, a reset signal of the wave-by-wave current-limiting fault is loaded at the wave peak value of a preset triangular carrier, and the preset triangular carrier is a positive triangular carrier or a negative triangular carrier.

A third aspect of an embodiment of the present invention provides an apparatus, including: a processor and a memory storing computer program instructions; the processor, when executing the computer program instructions, performs the steps of the method according to the first aspect.

A fourth aspect of embodiments of the present invention provides a computer-readable storage medium storing a computer program which, when executed by a processor, performs the steps of the method according to the first aspect.

Compared with the prior art, the embodiment of the invention has the following beneficial effects:

compared with the prior art, the embodiment of the invention can obtain the driving pulse signal of the target IGBT main pipe, and then when the jump edge of the driving pulse signal is detected, the signal duration of the driving pulse signal, which keeps the level unchanged from the jump edge, is counted. Then, under the condition that the jumping edge is a rising edge, if the signal duration is longer than the dead zone time and shorter than the sum of the dead zone time and the inhibition time, resetting the pulse sealing signal of the target IGBT main pipe, and otherwise enabling the pulse sealing signal of the target IGBT main pipe; and under the condition that the jumping edge is a falling edge, if the signal duration is less than the inhibition duration, resetting the pulse sealing signal of the target IGBT main pipe, otherwise enabling the pulse sealing signal of the target IGBT main pipe. Therefore, when the wave-by-wave current limiting fault is detected, if the pulse sealing signal of the target IGBT main pipe is enabled, the target IGBT main pipe is blocked, the target IGBT auxiliary pipe is blocked after the dead zone time length, and otherwise, the wave-by-wave current limiting fault is not responded. Therefore, the relation between the signal duration of the driving pulse signal keeping the level unchanged from the jumping edge and the dead zone time length and the restraining time length can be counted, the driving narrow pulse signal can be accurately detected, the driving narrow pulse can be restrained, and the operation reliability of the IGBT is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

FIG. 1 is a flowchart illustrating steps of a method for suppressing narrow pulses according to an embodiment of the present invention;

FIG. 2 is a schematic circuit topology diagram of a single-phase diode-clamped three-level inverter according to an embodiment of the present invention;

fig. 3 is a flowchart of detecting a wave-by-wave current limiting fault according to an embodiment of the present invention;

FIG. 4 is a flowchart of an embodiment of the present invention for obtaining the driving pulse signals of Q1 and Q4 in FIG. 1;

FIG. 5 is a flow chart of suppressing the driving narrow pulse according to an embodiment of the present invention;

FIG. 6 is a flow chart of another method for suppressing narrow driving pulses according to an embodiment of the present invention;

fig. 7 is a flowchart of a decision logic for wave-by-wave current limiting faults according to an embodiment of the present invention;

FIG. 8 is a flow chart of Q2 drive pulse enable logic according to an embodiment of the present invention;

FIG. 9 is a logic flow diagram of a Q3 drive pulse enable provided by an embodiment of the present invention;

FIG. 10 is a flow chart of logic for generating a driving pulse signal according to an embodiment of the present invention;

FIG. 11 is a flow chart of logic for generating a driving pulse signal according to an embodiment of the present invention;

FIG. 12 is a schematic diagram of a suppression apparatus for driving narrow pulses according to an embodiment of the present invention;

fig. 13 is a schematic diagram of an apparatus according to an embodiment of the present invention.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

In order to explain the technical means of the present invention, the following description will be given by way of specific examples.

As described in the background art, a hardware circuit has device errors, which results in that a driving narrow pulse cannot be accurately detected, and thus the driving narrow pulse is difficult to be suppressed, and the reliability of the operation of the IGBT is reduced.

In order to solve the problems in the prior art, embodiments of the present invention provide a method, an apparatus, a device, and a storage medium for suppressing a driving narrow pulse. First, a method for suppressing the driving narrow pulse according to an embodiment of the present invention will be described.

The suppression method for driving the narrow pulses may be applied to an inverter, which may comprise at least one main IGBT pipe and at least one auxiliary IGBT pipe complementary to the main IGBT pipe. The inverter may be a single-level inverter, or may be a multilevel inverter such as a two-level inverter or a three-level inverter.

As shown in fig. 1, the method for suppressing the driving narrow pulse according to the embodiment of the present invention includes the following steps:

and S110, acquiring a driving pulse signal of the main pipe of the target IGBT.

In some embodiments, the target IGBT main may be any IGBT main in the inverter.

Alternatively, the driving pulse signal may be obtained by: and outputting a driving pulse signal according to the comparison result of the modulation wave and the triangular carrier wave.

In some embodiments, the carrier frequency of the triangular carrier corresponds to the switching frequency of the target main IGBT and the target auxiliary IGBT.

Alternatively, in the case where the inverter is a diode midpoint clamped three-level inverter, the process of outputting the driving pulse signal according to the comparison result between the modulation wave and the triangular carrier may be as follows:

under the condition that the target IGBT main pipe is an IGBT main pipe corresponding to the forward triangular carrier wave, when the modulation wave is larger than the forward triangular carrier wave, a high-level driving pulse signal is output; when the modulation wave is less than or equal to the forward triangular carrier wave, outputting a low-level driving pulse signal;

under the condition that the target IGBT main pipe is the IGBT main pipe corresponding to the negative triangular carrier wave, when the modulation wave is smaller than the negative triangular carrier wave, a high-level driving pulse signal is output; and when the modulation wave is greater than or equal to the negative triangular carrier, outputting a low-level driving pulse signal.

In some embodiments, the positive and negative peak values of the triangular carrier may be set to ± 1999, and when the positive triangular carrier value reaches the positive peak value and the negative triangular carrier value reaches the negative peak value, the positive and negative peak values of the modulated wave may be set to ± 1900, respectively.

And S120, when the jump edge of the driving pulse signal is detected, counting the signal duration of the driving pulse signal, wherein the level of the driving pulse signal is kept unchanged from the jump edge.

In some embodiments, the transition edge may be divided into a rising edge and a falling edge. In this way, as long as the rising edge or the falling edge of the driving pulse signal is detected, the signal duration of the driving pulse signal keeping the level unchanged from the transition edge starts to be counted.

Specifically, when a rising edge of the driving pulse signal is detected, the driving pulse signal changes from a low level to a high level, and accordingly, the duration of the driving pulse signal from the rising edge to the signal with the level unchanged is the duration of the signal with the level unchanged.

When the falling edge of the driving pulse signal is detected, the driving pulse signal changes from high level to low level, and accordingly, the duration of the driving pulse signal, which is the duration of the signal keeping the level unchanged from the falling edge, is the duration of the signal keeping the low level unchanged.

S130, under the condition that the jumping edge is the rising edge, if the signal duration is longer than the dead zone time and shorter than the sum of the dead zone time and the inhibition time, resetting the pulse sealing signal of the target IGBT main pipe, and otherwise enabling the pulse sealing signal of the target IGBT main pipe.

In some embodiments, the dead time period is the duration of the drive pulse between the main IGBT tube and the auxiliary IGBT tube, for example, 2.5 microseconds. The suppression duration is a duration for suppressing the driving of the narrow pulse, for example, 1 μ sec.

In some embodiments, the signal duration of the driving narrow pulse is very short, and the driving narrow pulse can be detected by the relationship between the signal duration and the dead zone duration and the suppression duration.

In some embodiments, if the transition edge is a rising edge and the signal duration for which the drive pulse signal is held at a constant level from the transition edge is greater than the dead time period and less than the sum of the dead time period and the suppression time period, the drive pulse signal corresponding to the signal duration is a drive narrow pulse. In this case, in order to ensure the reliability of the main IGBT pipe, it is necessary to suppress the driving narrow pulse, that is, to reset the pulse blocking signal of the main IGBT pipe of the target.

Specifically, the purpose of resetting the pulse sealing signal of the main pipe of the target IGBT means that the pulse sealing signal is not responded, that is, the pulse sealing is not performed on the main pipe of the target IGBT. The purpose of enabling the pulse sealing signal of the main pipe of the target IGBT is to respond to the pulse sealing signal, namely, to seal the pulse of the main pipe of the target IGBT.

And S140, under the condition that the jumping edge is the falling edge, if the signal duration is less than the inhibition duration, resetting the pulse sealing signal of the target IGBT main pipe, otherwise enabling the pulse sealing signal of the target IGBT main pipe.

In some embodiments, if the transition edge is a falling edge and the duration of the signal during which the driving pulse signal is kept level-unchanged from the transition edge is less than the suppression duration, the driving pulse signal corresponding to the signal duration is a driving narrow pulse. In this case, in order to ensure the reliability of the main IGBT pipe, it is necessary to suppress the driving narrow pulse, that is, to reset the pulse blocking signal of the main IGBT pipe of the target.

S150, when the wave-by-wave current limiting fault is detected, if the pulse sealing signal of the target IGBT main pipe is enabled, the target IGBT main pipe is blocked, the target IGBT auxiliary pipe is blocked after the dead zone time length, and otherwise, the wave-by-wave current limiting fault is not responded.

In some embodiments, when a wave-by-wave current limiting fault is detected, corresponding processing needs to be executed according to the enabling condition of the pulse sealing signal of the main pipe of the IGBT.

Specifically, if the pulse sealing signal of the target IGBT main pipe is enabled, it indicates that no narrow pulse is driven at this time, and the target IGBT main pipe can be blocked in response to the wave-by-wave current limiting fault, and the target IGBT auxiliary pipe is blocked after the dead time period. If the pulse sealing signal of the target IGBT main pipe is reset, the driving narrow pulse is indicated to exist at the moment, in order to ensure the reliability of the IGBT main pipe, the wave-by-wave current limiting fault is not responded firstly, and after the driving narrow pulse passes, namely the pulse sealing signal of the target IGBT main pipe is changed from reset to enable, the wave-by-wave current limiting fault is responded.

Optionally, after the wave-by-wave current limiting fault is eliminated, the following processing may be performed:

when the wave-by-wave current-limiting fault is eliminated, a reset signal of the wave-by-wave current-limiting fault is loaded at the wave peak value of a preset triangular carrier, and the preset triangular carrier is a positive triangular carrier or a negative triangular carrier.

In some embodiments, when the wave-by-wave current-limiting fault is eliminated, the modulation wave may be smaller than the positive triangular carrier peak value and larger than the negative triangular carrier peak value by loading the reset signal of the wave-by-wave current-limiting fault at the wave peak value of the preset triangular carrier, so that it may be ensured that the driving pulse signal is not the driving narrow pulse when the IGBT pulse-opening logic is to open the inner tube first and open the outer tube with a delay.

In the embodiment of the invention, the driving pulse signal of the target IGBT main pipe can be acquired, and then when the jump edge of the driving pulse signal is detected, the signal duration of the driving pulse signal, which keeps the level unchanged from the jump edge, is counted. Then, under the condition that the jumping edge is a rising edge, if the signal duration is longer than the dead zone time and shorter than the sum of the dead zone time and the inhibition time, resetting the pulse sealing signal of the target IGBT main pipe, and otherwise enabling the pulse sealing signal of the target IGBT main pipe; and under the condition that the jumping edge is a falling edge, if the signal duration is less than the inhibition duration, resetting the pulse sealing signal of the target IGBT main pipe, otherwise enabling the pulse sealing signal of the target IGBT main pipe. Therefore, when the wave-by-wave current limiting fault is detected, if the pulse sealing signal of the target IGBT main pipe is enabled, the target IGBT main pipe is blocked, the target IGBT auxiliary pipe is blocked after the dead zone time length, and otherwise, the wave-by-wave current limiting fault is not responded. Therefore, the relation between the signal duration of the driving pulse signal keeping the level unchanged from the jumping edge and the dead zone time length and the restraining time length can be counted, the driving narrow pulse signal can be accurately detected, the driving narrow pulse can be restrained, and the operation reliability of the IGBT is improved.

In order to better understand the method for suppressing the driving narrow pulse, the method for suppressing the driving narrow pulse is described below by taking a single-phase diode midpoint clamping type three-level inverter as an example.

In some embodiments, the suppression method for driving the narrow pulse can be realized by means of FPGA software programming.

As shown in fig. 2, fig. 2 shows an IGBT power tube of a single-phase diode-clamped three-level inverter circuit topology, where C1 and C2 are capacitors, L1 is an inductor, D1 and D2 are diodes, N is a neutral point, Q1 and Q4 are main tubes (hereinafter, simply referred to as outer tubes) of the IGBT, Q3 is an auxiliary tube (hereinafter, simply referred to as inner tube) of the IGBT complementary to Q1, and Q4 is an inner tube complementary to Q2.

As shown in fig. 3, a process for determining enabling and resetting of the ripple-by-ripple current-limiting fault according to the CBCin input signal of the ripple-by-ripple current-limiting fault is provided.

Specifically, the delay filtering may be performed by detecting a skip edge of the wave-by-wave current-limiting input signal. The delay filtering time Cnt may be selected to be 1 μ s, after the input signal level is delayed for 1 μ s, if CBCin is 0, the hardware ripple current limiting fault enable CBCerr is 0, otherwise, when the forward triangular carrier value is greater than 1950, the hardware ripple current limiting fault reset CBCerr is 1, and CBCin is started to be loaded.

In some embodiments, the peak value of the forward triangular carrier may be 1999, when the forward triangular carrier value reaches the positive peak value and the negative triangular carrier value reaches the negative peak value, the peak value of the modulation wave is limited to ± 1900 at most, when the forward triangular carrier value is determined to be greater than 1950, the loading is started to determine that CBCin is 1, and the hardware wave-by-wave current-limiting fault reset CBCerr is 1, so as to ensure that the IGBT driving pulse is not a narrow pulse in the case that the IGBT pulse-opening logic opens the inner tube first and opens the outer tube with a delay.

As shown in fig. 4, a flow for obtaining the driving pulses of the outer tubes Q1 and Q4 of the diode midpoint clamping type three-level inverter IGBT is provided, wherein, a logic level 1 represents the IGBT on-state, and a logic level 0 represents the IGBT off-state.

In some embodiments, the driving pulse of the outer tube Q1 may be output according to the comparison between the modulated wave a and the forward triangular carrier B, that is, when the modulated wave is greater than the forward triangular carrier B, a logic level 1 is output, and when the modulated wave is less than or equal to the forward triangular carrier B, a logic level 0 is output, so as to obtain the driving pulse PWMQ 1of the outer tube Q1; and comparing the modulation wave with a negative triangular carrier C to output the driving pulse of the outer tube Q4, namely, outputting a logic level 1 when the negative triangular carrier C is larger than the modulation wave, and outputting a logic level 0 when the negative triangular carrier C is smaller than or equal to the modulation wave to obtain the driving pulse PWMQ 4of the outer tube Q4.

As shown in fig. 5, a flow of a method for suppressing the driving narrow pulse is provided, and by detecting the edge jump of the driving pulse PWMQ 1of the outer tube Q1, the fixed high-level driving pulse PWMQ1u and the fixed low-level driving pulse PWMQ1d for suppressing the driving narrow pulse signal can be obtained, and the specific steps are as follows:

(1) and detecting the rising edge of the drive pulse PWMQ1 in real time, starting timing PWMQ1 drive pulse action time T1, and comparing and judging with the extended and widened drive narrow pulse action time Tset which is Tdead + Tmin, wherein the complementary tube dead time (namely the dead time duration) is Tdead, and the IGBT sets the action time of restraining the narrow pulse to be Tmin at the minimum. In some embodiments, Tset may be selected to be 3.5 microseconds, Tdead to be 2.5 microseconds, and Tmin to be 1 microsecond.

If T1< Tdead, the constant high level driving pulse PWMQ1u is 1, and at this time, the outer tube Q1 driving pulse is filtered by dead time, the driving pulse actually applied to the IGBT has no level inversion, there is no narrow pulse to be able to seal the tube currently, and the tube sealing flag enable T1off can be set to 1.

If T1> Tdead and T1< Tset, the fixed high-level driving pulse PWMQ1u is 1, and the high-level driving narrow pulse exists after the dead time Tdead filtering, and the blocking is required to be delayed, so the tube-blocking flag is set to reset T1off to 0. If T1> Tset, the fixed high drive pulse PWMQ1u is 0, the action time Tset to suppress the high drive narrow pulse has been reached, and after filtering by the dead time Tdead, the high drive pulse Tmin remains not a narrow pulse, so the pinch flag enable T1off is set to 1.

(2) And detecting the falling edge of the driving pulse PWMQ1 in real time, starting to time the driving pulse action time T2 when the falling edge is detected, and comparing with Tset which is Tmin to judge, wherein the minimum Tmin is the IGBT setting narrow pulse inhibition action time.

If T2< Tset, the fixed low level driving pulse PWMQ1d is 0, and the pinch low level driving does not require dead time filtering, and there is a low level narrow pulse to be blocked by time delay, so the set pinch flag reset T1off is 0.

If T2> Tset, the fixed low-level drive pulse PWMQ1d is 1, the action time Tmin to suppress the low-level narrow pulse has been reached, Tmin is 1 microsecond, so the pinch flag enable T1off is set to 1; the logic of the drive pulse PWMQ1t for obtaining the outer tube Q1 to suppress the drive narrow pulse is: PWMQ1 and PWMQ1u firstly carry out OR logic operation, and then the result and PWMQ1d carry out AND logic operation; if the generated wave-by-wave current-limiting enable CBCerr is equal to 0, if the blocking mark T1off is equal to 1, the driving pulse enable PWM1en can be immediately blocked to 0, if the driving pulse reset PWM1en is not blocked to 1, and if the wave-by-wave current-limiting reset CBCerr is equal to 1, the driving pulse reset PWM1en can be immediately blocked to 1;

as shown in fig. 6, a flow of suppressing the driving narrow pulse is provided, and the fixed high-level driving pulse PWMQ4u and the fixed low-level driving pulse PWMQ4d of the suppressing narrow pulse signal are obtained by detecting the edge jump of the driving pulse PWMQ 4of the outer tube Q4, and the specific steps are as follows:

(1) and detecting the rising edge of the driving pulse PWMQ4 in real time, starting timing PWMQ4 driving pulse action time T3, and comparing and judging with the action time Tset + Tmin of the set extended and widened driving narrow pulse, wherein the action time Tdead is complemented, and the action time Tmin of the IGBT set and restrained narrow pulse is minimum Tmin. In some embodiments, Tset may be selected to be 3.5 microseconds, Tdead to be 2.5 microseconds, and Tmin to be 1 microsecond.

If T3< Tdead, the constant high level driving pulse PWMQ4u is 1, and at this time, the outer tube Q4 driving pulse is filtered by dead time, the driving pulse actually applied to the IGBT has no level inversion, there is no narrow pulse to be able to seal the tube currently, and the tube sealing flag enable T1off can be set to 1.

If T3> Tdead and T3< Tset, the fixed high-level driving pulse PWMQ4u is equal to 1, at this time, there is a high-level narrow pulse after dead-zone filtering Tdead, which needs to be blocked with time delay, Tdead is equal to 2.5 microseconds, so the set lock flag reset T4off is equal to 0, if T3> Tset, the fixed high-level driving pulse PWMQ4u is equal to 0, the action time Tset for suppressing the high-level driving narrow pulse has been reached, after dead-zone filtering Tdead, the high-level driving pulse of Tmin is not a narrow pulse, Tdead is equal to 2.5 microseconds, Tset is equal to 3.5 microseconds, Tmin is equal to 1 microsecond, so the set lock flag enable T4off is equal to 1.

(2) And detecting the falling edge of the driving pulse PWMQ4 in real time, starting to time the driving pulse action time T4 when the falling edge is detected, and comparing with Tset which is Tmin to judge, wherein the minimum Tmin is the IGBT setting narrow pulse inhibition action time.

If T4< Tset, the fixed low level driving pulse PWMQ4d is 0, and the pinch low level driving does not require dead time filtering, and there is a low level narrow pulse to be blocked by time delay, so the set pinch flag reset T4off is 0.

If T4> Tset, the fixed low-level drive pulse PWMQ4d is 1, the action time Tmin to suppress the low-level narrow pulse has been reached, Tmin is 1 microsecond, so the pinch flag enable T4off is set to 1; the logic of the drive pulse PWMQ4t for obtaining the outer tube Q4 to suppress the drive narrow pulse is: PWMQ4 performs OR logic operation with PWMQ4u, and the result performs AND logic operation with PWMQ4 d; if the wave-by-wave current-limiting enable CBCerr is determined to be 0, if the blocking flag T4off is 1, the tube-sealing-capable logic PWM2en can be immediately set to 0, and the tube-sealing-resetting logic PWM2en can be immediately set to 1, and if the wave-by-wave current-limiting reset CBCerr is determined to be 1, the tube-sealing logic PWM2en can be immediately reset to 1.

As shown in fig. 7, a tube opening logic flow of the ripple current limiting protection tube sealing logic and the ripple current limiting protection reset is provided, according to the pulse sealing driving pulse enable PWM1en of the outer tube Q1 and the pulse sealing driving pulse enable PWM2en of the outer tube Q4, performing or logic operation PWMen ═ PWM1en + PWM2en, if PWMen ═ 0 is enabled, enabling the outer tube to immediately block PWMenup ═ 0, then delaying T5 to enable the inner tube blocking pulse PWMendn ═ 0, and T5 ═ 2 microseconds; if PWMen is reset to 1, the outer tube is enabled to immediately block PWMendn to 1, and the time delay T6 enables the outer tube blocking pulse PWMenup to 1, and T6 to 3 microseconds.

As shown in fig. 8, an output inner tube Q2 driving pulse enable logic flow diagram of wave-by-wave current-limiting protection is provided, an inner tube Q2 driving pulse needs to detect the driving pulse state of a complementary outer tube Q4 and the wave-by-wave current-limiting enable to make a judgment, a falling edge of a driving pulse of an outer tube Q4 is detected in real time to start timing T7, when it is judged that a blocking driving pulse action time T7 is less than a dead time Tdead, Tdead is 2.5 microseconds, if a wave-by-wave current-limiting signal is judged to be enabled, an inner tube Q2 driving pulse enable low level is set to immediately seal the tube, that is, PWMQ2en is 0, and if the inner tube Q2 driving pulse is reset, a high level normal output driving pulse, that is, PWMQ2en is; if the judgment timing T7 is greater than or equal to the dead time Tdead, the inner tube Q2 driving pulse is set to reset the high level normal output driving pulse, namely PWMQ2en is equal to 1.

As shown in fig. 9, a logic flow diagram of enabling drive pulses of an inner tube Q3 output by a three-level inverter IGBT with wave-by-wave current limiting protection is provided, a drive pulse of the inner tube Q3 needs to detect a drive pulse state of a complementary outer tube Q1 and a wave-by-wave current limiting enable to perform judgment, a falling edge of a drive pulse of an outer tube Q1 starts timing T8 in real time, when it is judged that a blocking drive pulse action time T8 is less than a dead zone time Tdead, Tdead is 2.5 microseconds, if a wave-by-wave current limiting signal is enabled, an inner tube Q3 drive pulse enable low level is set to immediately seal a tube, that is, PWMQ3en is 0, and if reset, an inner tube Q3 drive pulse is set to reset a high level normal output drive pulse, that is, PWMQ2en is 1; if the judgment timing T8 is greater than or equal to the dead time Tdead, the inner tube Q3 driving pulse is set to reset the high level normal output driving pulse, namely PWMQ2en is equal to 1.

As shown in fig. 10 and 11, a flow of IGBT driving pulse signal generation logic is provided, in accordance with the outer tube Q4 driving pulse PWMQ4t and the outer tube Q1 driving pulse PWMQ1t, the driving logic of the three-level inverter IGBT is complied with, the driving pulses of the outer tube Q1 and the inner tube Q3 are complementarily conducted, the driving pulses of the inner tube Q2 and the outer tube Q4 are complementarily conducted, in order to prevent the complementary IGBT from generating the through short circuit, the dead time Tdead is added to the driving pulse acting time of the outer tube Q1 and the inner tube Q3, the dead time Tdead is 2.5 microseconds, the dead time Tdead is added to the driving pulse acting time of the inner tube Q2 and the outer tube Q4, the dead time Tdead is 2.5 microseconds, and the output driving pulse signals of the 4-way IGBTs of Q1, Q2, Q3 and Q4 are finally output according to the driving pulse.

Based on the method for suppressing the driving narrow pulse provided by the above embodiment, correspondingly, the invention also provides a specific implementation manner of a device for suppressing the driving narrow pulse, which is applied to the method for suppressing the driving narrow pulse. Please see the examples below.

As shown in fig. 12, there is provided a suppression device for driving a narrow pulse, the suppression device for driving a narrow pulse being applied to an inverter, the inverter including at least one main IGBT pipe of an insulated gate bipolar transistor and at least one auxiliary IGBT pipe complementary to the main IGBT pipe, the suppression device for driving a narrow pulse including:

the obtaining module 1210 is used for obtaining a driving pulse signal of a target IGBT main pipe;

the counting module 1220 is configured to count a signal duration of the driving pulse signal, in which a level of the driving pulse signal is kept unchanged from a transition edge, when the transition edge of the driving pulse signal is detected;

the first control module 1230 is configured to, when the jump edge is a rising edge, reset the pulse sealing signal of the target IGBT main pipe if the signal duration is longer than the dead zone time and shorter than the sum of the dead zone time and the suppression time, and otherwise enable the pulse sealing signal of the target IGBT main pipe;

the second control module 1240 is configured to, if the hopping edge is a falling edge, reset the pulse sealing signal of the target IGBT main pipe if the signal duration is shorter than the suppression duration, and otherwise enable the pulse sealing signal of the target IGBT main pipe;

and a third control module 1250, configured to block the target IGBT main pipe and block the target IGBT auxiliary pipe after a dead zone time length if a pulse blocking signal of the target IGBT main pipe is enabled when the wave-by-wave current limiting fault is detected, or else, not respond to the wave-by-wave current limiting fault.

Optionally, the apparatus for suppressing driving of a narrow pulse further comprises an output module, configured to:

outputting a driving pulse signal according to a comparison result of the modulation wave and the triangular carrier wave; the carrier frequency of the triangular carrier corresponds to the switching frequency of the target IGBT main pipe and the target IGBT auxiliary pipe.

Optionally, the inverter is a diode midpoint clamping type three-level inverter;

an output module further configured to:

under the condition that the target IGBT main pipe is an IGBT main pipe corresponding to the forward triangular carrier wave, when the modulation wave is larger than the forward triangular carrier wave, a high-level driving pulse signal is output; when the modulation wave is less than or equal to the forward triangular carrier wave, outputting a low-level driving pulse signal;

under the condition that the target IGBT main pipe is the IGBT main pipe corresponding to the negative triangular carrier wave, when the modulation wave is smaller than the negative triangular carrier wave, a high-level driving pulse signal is output; and when the modulation wave is greater than or equal to the negative triangular carrier, outputting a low-level driving pulse signal.

Optionally, the apparatus for suppressing the driving of the narrow pulse further includes a loading module, configured to:

when the wave-by-wave current-limiting fault is eliminated, a reset signal of the wave-by-wave current-limiting fault is loaded at the wave peak value of a preset triangular carrier, and the preset triangular carrier is a positive triangular carrier or a negative triangular carrier.

In the embodiment of the invention, the driving pulse signal of the target IGBT main pipe can be acquired, and then when the jump edge of the driving pulse signal is detected, the signal duration of the driving pulse signal, which keeps the level unchanged from the jump edge, is counted. Then, under the condition that the jumping edge is a rising edge, if the signal duration is longer than the dead zone time and shorter than the sum of the dead zone time and the inhibition time, resetting the pulse sealing signal of the target IGBT main pipe, and otherwise enabling the pulse sealing signal of the target IGBT main pipe; and under the condition that the jumping edge is a falling edge, if the signal duration is less than the inhibition duration, resetting the pulse sealing signal of the target IGBT main pipe, otherwise enabling the pulse sealing signal of the target IGBT main pipe. Therefore, when the wave-by-wave current limiting fault is detected, if the pulse sealing signal of the target IGBT main pipe is enabled, the target IGBT main pipe is blocked, the target IGBT auxiliary pipe is blocked after the dead zone time length, and otherwise, the wave-by-wave current limiting fault is not responded. Therefore, the relation between the signal duration of the driving pulse signal keeping the level unchanged from the jumping edge and the dead zone time length and the restraining time length can be counted, the driving narrow pulse signal can be accurately detected, the driving narrow pulse can be restrained, and the operation reliability of the IGBT is improved.

Fig. 13 is a hardware structure diagram of a device implementing various embodiments of the present invention.

The device may include a processor 1301 as well as a memory 1302 storing computer program instructions.

In particular, the processor 1301 may include a Central Processing Unit (CPU), or an Application Specific Integrated Circuit (ASIC), or may be configured as one or more Integrated circuits implementing embodiments of the present invention.

Memory 1302 may include mass storage for data or instructions. By way of example, and not limitation, memory 1302 may include a Hard Disk Drive (HDD), a floppy Disk Drive, flash memory, an optical Disk, a magneto-optical Disk, tape, or a Universal Serial Bus (USB) Drive or a combination of two or more of these. Memory 1302 may include removable or non-removable (or fixed) media, where appropriate. Memory 1302 may be internal or external to the integrated gateway disaster recovery device, where appropriate. In a particular embodiment, the memory 1302 is non-volatile solid-state memory. In a particular embodiment, memory 1302 includes Read Only Memory (ROM). Where appropriate, the ROM may be mask-programmed ROM, Programmable ROM (PROM), Erasable PROM (EPROM), Electrically Erasable PROM (EEPROM), electrically rewritable ROM (EAROM), or flash memory or a combination of two or more of these.

The processor 1301 realizes any one of the above embodiments of the suppression method of driving narrow pulses by reading and executing computer program instructions stored in the memory 1302.

In one example, the device can also include a communication interface 13013 and a bus 1310. As shown in fig. 13, the processor 1301, the memory 1302, and the communication interface 13013 are connected via a bus 1310 to complete communication therebetween.

The communication interface 13013 is mainly used for implementing communication between modules, apparatuses, units and/or devices in the embodiments of the present invention.

The bus 1310 includes hardware, software, or both to couple the devices' components to one another. By way of example, and not limitation, a bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hypertransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an infiniband interconnect, a Low Pin Count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a video electronics standards association local (VLB) bus, or other suitable bus or a combination of two or more of these. Bus 1310 may include one or more buses, where appropriate. Although specific buses have been described and shown in the embodiments of the invention, any suitable buses or interconnects are contemplated by the invention.

An embodiment of the present invention further provides a computer-readable storage medium, where the computer storage medium has computer program instructions stored thereon; the computer program instructions, when executed by the processor, implement the processes of the above-described method for suppressing driving narrow pulses, and achieve the same technical effects, and are not described herein again to avoid repetition.

It is to be understood that the invention is not limited to the specific arrangements and instrumentality described above and shown in the drawings. A detailed description of known methods is omitted herein for the sake of brevity. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present invention are not limited to the specific steps described and illustrated, and those skilled in the art can make various changes, modifications and additions or change the order between the steps after comprehending the spirit of the present invention.

The functional blocks shown in the above-described structural block diagrams may be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it may be, for example, an electronic circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, plug-in, function card, or the like. When implemented in software, the elements of the invention are the programs or code segments used to perform the required tasks. The program or code segments may be stored in a machine-readable medium or transmitted by a data signal carried in a carrier wave over a transmission medium or a communication link. A "machine-readable medium" may include any medium that can store or transfer information. Examples of a machine-readable medium include electronic circuits, semiconductor memory devices, ROM, flash memory, Erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, Radio Frequency (RF) links, and so forth. The code segments may be downloaded via computer networks such as the internet, intranet, etc.

It should also be noted that the exemplary embodiments mentioned in this patent describe some methods or systems based on a series of steps or devices. However, the present invention is not limited to the order of the above-described steps, that is, the steps may be performed in the order mentioned in the embodiments, may be performed in an order different from the order in the embodiments, or may be performed simultaneously.

As described above, only the specific embodiments of the present invention are provided, and it can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the system, the module and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again. It should be understood that the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present invention, and these modifications or substitutions should be covered within the scope of the present invention.