阅读说明：本技术 一种三相三电平双输出逆变器 (Three-phase three-level double-output inverter ) 是由 王汝田 袁帅 刘国钦 刘闯 蔡国伟 郭东波 于 2020-11-30 设计创作，主要内容包括：本发明是一种三相三电平双输出逆变器,其特点是,包括：直流侧接入的两个电容,18个开关模块,逆变级1和逆变级2分别带两组三相负载；通过对开关模块施加合理的驱动信号,三相三电平双输出逆变器可实现将单个直流输入电压变换为两组频率、幅值皆可调的三相交流电压。其有益的效果是：体积小、成本低、结构合理,同时可满足高压大容量双输出逆变场合的需求,如风力发电系统、电动汽车和轨道牵引等。(The invention relates to a three-phase three-level double-output inverter, which is characterized by comprising the following components: two capacitors and 18 switch modules are connected to the direct current side, and an inverter stage 1 and an inverter stage 2 are respectively provided with two groups of three-phase loads; by applying reasonable driving signals to the switch module, the three-phase three-level dual-output inverter can convert a single direct-current input voltage into two groups of three-phase alternating-current voltages with adjustable frequency and amplitude. The beneficial effects are as follows: the high-voltage high-capacity double-output inverter has the advantages of small volume, low cost and reasonable structure, and can meet the requirements of high-voltage high-capacity double-output inversion occasions, such as a wind power generation system, an electric automobile, track traction and the like.)

1. A three-phase three-level dual-output inverter is characterized in that: it includes a capacitor C connected to the DC side₁～C₂Switch modules A1-A4, switch modules B1-B4, switch modules C1-C4 and switch modules O1-O6; two groups of outputs of the inverter are respectively defined as an inverter stage 1 and an inverter stage 2, and the three-phase load carried by the inverter stage 1 is Z_A1、Z_B1、Z_C1The three-phase load of the inverter stage 2 is Z_A2、Z_B2、Z_C2；

The switch modules A1-A4, the switch modules B1-B4, the switch modules C1-C4 and the switch modules O1-O6 have the same structure, and each switch module consists of an insulated gate bipolar transistor and an anti-parallel diode; the anode of a diode of one switch module is connected with the emitter of the insulated gate bipolar transistor, and the cathode of the diode is connected with the collector of the insulated gate bipolar transistor; defining the emitter of the insulated gate bipolar transistor of a switch module as the emitter of the switch module, the collector of the insulated gate bipolar transistor as the collector of the switch module, the switch module being denoted by the symbol Xn, the insulated gate bipolar transistor in the switch module being denoted by the symbol S_XnDenotes, symbol S_XnThe subscript symbol Xn indicates the switch module in which it is located, and the diode in the switch module is denoted by the symbol D_XnDenotes the symbol D_XnThe subscript symbol Xn indicates the switch module in which it is located; wherein, when X belongs to { A, B, C }, n belongs to {1, 2, 3, 4 }; when X belongs to { O }, n belongs to {1, 2, 3, 4, 5, 6 };

two capacitors are connected to the DC side, and are respectively called as a capacitor C₁And a capacitor C₂Capacitor C₁Positive pole of the DC bus and the positive pole end P of the DC bus_busConnected, capacitor C₁Negative electrode of (1) and capacitor C₂Is connected with the positive electrode of the capacitor C₂Negative pole of (2) and negative pole end N of direct current bus_busAre connected and connect the capacitor C₁Negative electrode of (1) and capacitor C₂Positive electrode of (2)The point of connection is defined as the DC neutral point O_bus(ii) a Positive terminal P_busAnd the negative terminal N_busVoltage between is U_dNeutral point O_busPotential 0, positive terminal P_busTo neutral point O_busA voltage ofNeutral point O_busAnd the negative terminal N_busA voltage of

Collector of switch module A1 and positive terminal P of DC bus_busThe emitter of switch module A1 is connected to the collector of switch module A2, the emitter of switch module A2 is connected to the collector of switch module A3, the emitter of switch module A3 is connected to the collector of switch module A4, and the emitter of switch module A4 is connected to the negative terminal N of the DC bus_busConnecting;

collector of switch module B1 and positive terminal P of DC bus_busThe emitter of switch module B1 is connected to the collector of switch module B2, the emitter of switch module B2 is connected to the collector of switch module B3, the emitter of switch module B3 is connected to the collector of switch module B4, and the emitter of switch module B4 is connected to the negative terminal N of the dc bus_busConnecting;

collector of switch module C1 and positive terminal P of DC bus_busThe emitter of the switch module C1 is connected to the collector of the switch module C2, the emitter of the switch module C2 is connected to the collector of the switch module C3, the emitter of the switch module C3 is connected to the collector of the switch module C4, and the emitter of the switch module C4 is connected to the negative terminal N of the dc bus_busConnecting;

collector and DC neutral O of switch module O1_busThe emitter of the switch module O1 is connected to the emitter of the switch module O2, and the collector of the switch module O2 is connected to the emitter of the switch module a 2;

collector and DC neutral O of switch module O3_busThe emitter of the switch module O3 is connected to the emitter of the switch module O4, and the collector of the switch module O4 is connected to the emitter of the switch module B2;

collector and DC neutral O of switch module O5_busThe emitter of the switch module O5 is connected with the emitter of the switch module O6, and the collector of the switch module O6 is connected with the emitter of the switch module C2;

three-phase load Z_A1、Z_B1、Z_C1Are connected to the connection point of the switch modules a1 and a2, the connection point of the switch modules B1 and B2, and the connection point of the switch modules C1 and C2, respectively, and the other ends thereof are connected together;

three-phase load Z_A2、Z_B2、Z_C2Are connected to the connection point of the switch modules A3 and a4, the connection point of the switch modules B3 and B4, and the connection point of the switch modules C3 and C4, respectively, and the other ends thereof are connected together.

Technical Field

The invention relates to the technical field of power electronic conversion devices, in particular to a three-phase three-level double-output inverter.

Background

In recent years, the double-alternating-current output system is applied to the fields of electric automobiles, rail traction, wind power generation and the like. The core of the double alternating current output system is a double-output inverter. At present, the research on the two-level dual-output inverter is mature, but the two-level dual-output inverter cannot meet the requirement of the high-voltage high-capacity dual-output inverter in the current power industry. Meanwhile, the three-level technology can adopt low-voltage devices to realize high-voltage large-capacity output. Therefore, in order to realize the advantages of the three-level technology while realizing dual output, no literature report and practical application of the three-phase three-level dual-output inverter related to the invention are found so far.

Disclosure of Invention

The purpose of the invention is: the three-phase three-level double-output inverter solves the problem of a high-voltage large-capacity inverter required in the field of double alternating current output, and is small in size, low in cost, reasonable in structure and wide in application.

The technical scheme adopted for realizing the purpose of the invention is that the three-phase three-level double-output inverter is characterized in that: it includes a capacitor C connected to the DC side₁And a capacitor C₂Switch modules A1-A4, switch modules B1-B4, switch modules C1-C4 and switch modules O1-O6; two groups of outputs of the inverter are respectively defined as an inverter stage 1 and an inverter stage 2, and the three-phase load carried by the inverter stage 1 is Z_A1、Z_B1、Z_C1The three-phase load of the inverter stage 2 is Z_A2、Z_B2、Z_C2。

The switch modules A1-A4, the switch modules B1-B4, the switch modules C1-C4 and the switch modules O1-O6 have the same structure, and each switch module consists of an insulated gate bipolar transistor and an anti-parallel diode; the anode of a diode of one switch module is connected with the emitter of the insulated gate bipolar transistor, and the cathode of the diode is connected with the collector of the insulated gate bipolar transistor; defining the emitter of the insulated gate bipolar transistor of a switch module as the emitter of the switch module, the collector of the insulated gate bipolar transistor as the collector of the switch module, the switch module being denoted by the symbol Xn, the insulated gate bipolar transistor in the switch module being denoted by the symbol S_XnDenotes, symbol S_XnThe subscript symbol Xn indicates the switch module in which it is located, and the diode in the switch module is denoted by the symbol D_XnDenotes the symbol D_XnThe subscript symbol Xn indicates the switch module in which it is located; wherein, when X belongs to { A, B, C }, n belongs to {1, 2, 3, 4 }; when X is larger than O, n is larger than 1, 2, 3, 4, 5, 6.

Two capacitors are connected to the DC side, and are respectively called as a capacitor C₁And a capacitor C₂Capacitor C₁Positive pole of the DC bus and the positive pole end P of the DC bus_busConnected, capacitor C₁Negative electrode of (1) and capacitor C₂Is connected with the positive electrode of the capacitor C₂Negative pole of (2) and negative pole end N of direct current bus_busAre connected and connect the capacitor C₁Negative electrode of (1) and capacitor C₂The point at which the positive electrodes of (b) are connected is defined as a direct current neutral point O_bus(ii) a Positive terminal P_busAnd the negative terminal N_busVoltage between is U_dNeutral point O_busPotential 0, positive terminal P_busTo neutral point O_busA voltage ofNeutral point O_busAnd the negative terminal N_busA voltage of

Collector of switch module A1 and positive terminal P of DC bus_busThe emitter of switch module A1 is connected to the collector of switch module A2, the emitter of switch module A2 is connected to the collector of switch module A3, the emitter of switch module A3 is connected to the collector of switch module A4, and the emitter of switch module A4 is connected to the negative terminal N of the DC bus_busAre connected.

Collector of switch module B1 and positive terminal P of DC bus_busThe emitter of switch module B1 is connected to the collector of switch module B2, the emitter of switch module B2 is connected to the collector of switch module B3, the emitter of switch module B3 is connected to the collector of switch module B4, and the emitter of switch module B4 is connected to the negative terminal N of the dc bus_busAre connected.

Collector of switch module C1 and positive terminal P of DC bus_busThe connection is carried out in a connecting way,the emitter of switch module C1 is connected to the collector of switch module C2, the emitter of switch module C2 is connected to the collector of switch module C3, the emitter of switch module C3 is connected to the collector of switch module C4, and the emitter of switch module C4 is connected to the negative terminal N of the dc bus_busAre connected.

Collector and DC neutral O of switch module O1_busTo the emitter of switch block O1 is connected to the emitter of switch block O2 and the collector of switch block O2 is connected to the emitter of switch block a 2.

Collector and DC neutral O of switch module O3_busTo the emitter of switch block O3 is connected to the emitter of switch block O4 and the collector of switch block O4 is connected to the emitter of switch block B2.

Collector and DC neutral O of switch module O5_busTo the emitter of switch block O5 is connected to the emitter of switch block O6 and the collector of switch block O6 is connected to the emitter of switch block C2.

Three-phase load Z_A1、Z_B1、Z_C1Are connected to the connection point of the switch modules a1 and a2, the connection point of the switch modules B1 and B2, and the connection point of the switch modules C1 and C2, respectively, and the other ends thereof are connected together.

Three-phase load Z_A2、Z_B2、Z_C2Are connected to the connection point of the switch modules A3 and a4, the connection point of the switch modules B3 and B4, and the connection point of the switch modules C3 and C4, respectively, and the other ends thereof are connected together.

The invention relates to a three-phase three-level double-output inverter, which adopts a direct current side to access a capacitor C₁～C₂The two groups of outputs of the inverter are respectively defined as an inverter stage 1 and an inverter stage 2, the three-phase load carried by the inverter stage 1 is Z, the switch modules A1-A4, the switch modules B1-B4, the switch modules C1-C4 and the switch modules O1-O6 are arranged in sequence, and the three-phase load carried by the inverter stage 1 is Z_A1、Z_B1、Z_C1The three-phase load of the inverter stage 2 is Z_A2、Z_B2、Z_C2The structure of (1) can convert a single direct current input voltage into three groups of adjustable frequencies and amplitudesAn alternating voltage. The beneficial effects are as follows: the high-voltage high-capacity double-output inverter has the advantages of small volume, low cost and reasonable structure, and can meet the requirements of high-voltage high-capacity double-output inversion occasions, such as a wind power generation system, an electric automobile, track traction and the like.

Drawings

FIG. 1 is a three-phase three-level dual-output inverter according to the present invention;

FIG. 2 is a schematic diagram of operating condition 1 in mode 1;

FIG. 3 is a schematic diagram of operating condition 2 in mode 1;

FIG. 4 is a schematic diagram of operating state 3 in mode 1;

FIG. 5 is a schematic diagram of operating condition 1 in mode 2;

FIG. 6 is a schematic diagram of operating condition 2 in mode 2;

FIG. 7 is a schematic diagram of operating condition 3 in mode 2;

FIG. 8 is a schematic diagram of a modulation strategy for carrier PWM;

FIG. 9 is a waveform of the three-phase output current of inverter stage 1 under a first set of simulation parameters;

FIG. 10 is a waveform of the three-phase output current of inverter stage 2 under a first set of simulation parameters;

FIG. 11 shows the output line voltage u of the inverter stage 1 under a first set of simulation parameters_AB1A waveform diagram;

FIG. 12 shows the output line voltage u of the inverter stage 2 under a first set of simulation parameters_AB2A waveform diagram;

FIG. 13 is a waveform of the three-phase output current of inverter stage 1 under a second set of simulation parameters;

FIG. 14 is a three-phase output current waveform of inverter stage 2 under a second set of simulation parameters;

FIG. 15 shows the output line voltage u of the inverter stage 1 under a second set of simulation parameters_AB1A waveform diagram;

FIG. 16 shows the output line voltage u of the inverter stage 2 under a second set of simulation parameters_AB2And (4) waveform diagrams.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

As shown in fig. 1, the three-phase three-level dual-output inverter is formed by connecting two capacitors, 18 switch modules and two groups of three-phase loads, and by applying reasonable driving signals to the switch modules, the three-phase three-level dual-output inverter can convert a single direct-current input voltage into two groups of three-phase alternating-current voltages with adjustable frequencies and amplitudes. The two capacitors are respectively: capacitor C₁～C₂(ii) a The 18 switch modules are respectively: switch modules A1-A4, switch modules B1-B4, switch modules C1-C4 and switch modules O1-O6; two groups of outputs of the inverter are respectively defined as an inverter stage 1 and an inverter stage 2, and the three-phase load carried by the inverter stage 1 is Z_A1、Z_B1、Z_C1The three-phase load of the inverter stage 2 is Z_A2、Z_B2、Z_C2。

The three-phase three-level dual-output inverter has two working modes, wherein the mode 1 is that the inverter stage 1 works in an effective working state, and the mode 2 is that the inverter stage 2 works in an effective working state. When the inverter stage 1 is in an effective working state, the switch module X4(X is equal to { A, B, C }) of each phase is conducted; when the inverter stage 2 is in active operation, the switch module X1(X ∈ { a, B, C }) of each phase is turned on. When the three-phase three-level dual-output inverter works in the mode 1, the three-phase three-level dual-output inverter comprises three working states, namely: operating state 1, operating state 2 and operating state 3, as shown in fig. 2, 3 and 4, respectively; when the three-phase three-level dual-output inverter works in the mode 2, the three-phase three-level dual-output inverter also comprises three working states, namely: operating state 1, operating state 2 and operating state 3 are shown in fig. 5, 6 and 7, respectively. The principle of each operating state will be described below by taking phase a as an example, and B, C has the same principle.

Operating state 1 of mode 1: a drive signal is applied to switch module a1 such that when current flows from the inverter to the load, the current flows through the path S of switch module a1_A1And a load Z_A1As indicated by the dotted line in fig. 2. At this time, the load Z_A1Is connected to the positive terminal P of the direct current bus_busAt a potential ofWhen the current flows from the load to the inverter, the path through which the current flows is the load Z_A1And D of switch module A1_A1As indicated by the long dashed line in fig. 2, when the load Z is present_A1Is still at a potential of

Operating state 2 of mode 1: the driving signals are applied to the switching modules a2, O1 and O2, and when a current flows from the inverter to the load, the current flows through the path S of the switching module O1_O1D of switch module O2_O2D of switch module A2_A2And a load Z_A1As shown in dotted lines in fig. 3. At this time, the load Z_A1To a dc neutral point O_busThe potential is 0; when the current flows from the load to the inverter, the path through which the current flows is the load Z_A1S of switch module A2_A2S of switch module O2_O2And D of switch module O1_O1As indicated by the long dashed line in fig. 3, when the load Z is present_A1The potential of (a) is still 0.

Operating state 3 of mode 1: the driving signals are applied to the switch modules a2, A3 and a4, and when a current flows from the inverter to the load, the current flows through the path D of the switch module a4_A4D of switch module A3_A3D of switch module A2_A2And a load Z_A1As shown in dotted lines in fig. 4. At this time, the load Z_A1Is connected to the negative electrode end N of the direct current bus_busAt a potential ofWhen the current flows from the load to the inverter, the path through which the current flows is the load Z_A1S of switch module A2_A2S of switch module A3_A3And S of switch module A4_A4As indicated by the long dashed line in fig. 4, when the load Z is present_A1Is still at a potential of

Operating state 1 of mode 2: to switch modules A1, A2 and A3The driving signal is added, when the current flows from the inverter to the load, the current flows through the path S of the switch module A1_A1S of switch module A2_A2S of switch module A3_A3And a load Z_A2As shown in dotted lines in fig. 5. At this time, the load Z_A2Is connected to the positive terminal P of the direct current bus_busAt a potential ofWhen the current flows from the load to the inverter, the path through which the current flows is the load Z_A2D of switch module A3_A3D of switch module A2_A2And D of switch module A1_A1As indicated by the long dashed line in fig. 5, when the load Z is present_A2Is still at a potential of

Operating state 2 of mode 2: the driving signals are applied to the switching modules a3, O1 and O2, and when a current flows from the inverter to the load, the current flows through the path S of the switching module O1_O1D of switch module O2_O2S of switch module A3_A3And a load Z_A2As shown in dotted lines in fig. 6. At this time, the load Z_A2To a dc neutral point O_busThe potential is 0; when the current flows from the load to the inverter, the path through which the current flows is the load Z_A2D of switch module A3_A3S of switch module O2_O2And D of switch module O1_O1As indicated by the long dashed line in fig. 6, when the load Z is present_A2The potential of (a) is still 0.

Operating state 3 of mode 2: a drive signal is applied to switch module a4 such that when current flows from the inverter to the load, the current flows through switch module a4 at D_A4And a load Z_A2As shown by the dotted line in fig. 7. At this time, the load Z_A2Is connected to the negative electrode end N of the direct current bus_busAt a potential ofPath through which current flows when flowing from the load to the inverterIs a load Z_A2And S of switch module A4_A4As indicated by the long dashed line in fig. 7, when the load Z is present_A2Is still at a potential ofTable 1 lists the conclusions of the above analysis, indicating that: "ON" indicates that the switch module is in an ON state, "OFF" indicates that the switch module is in an OFF state, and "-" indicates an operating state not allowed by the switch module; "P" indicates an output of"O" represents an operating state with an output of 0, and "N" represents an operating state with an output of 0The operating state of (c).

The insulated gate bipolar transistors of the 18 switch modules of the three-phase three-level dual-output inverter can also adopt other fully-controlled power semiconductor power devices. The components related to the invention are all commercial products.

TABLE 1 relationship between switch module states and output levels in three-phase three-level dual-output inverter (take phase A as an example)

The three-phase three-level double-output inverter adopts a modulation strategy of carrier PWM. The modulation strategy of the carrier PWM is explained below. As shown in FIG. 8, two sets of triangular waves having the same frequency and phase and an amplitude of 1 are stacked one above the other, and the upper and lower triangular carriers are each represented by v_car1And v_car2Represents; v for three-phase modulated wave of inverter stage 1_a1 ^*、v_b1 ^*、v_c1 ^*V for three-phase modulated wave of inverter stage 2_a2 ^*、v_b2 ^*、v_c2 ^*Expressed by the formulas (1) and (2), respectively:

wherein m is₁And m₂The modulation degrees of the inverter stage 1 and the inverter stage 2 respectively; omega₁And ω₂The angular frequencies of the output voltages of inverter stage 1 and inverter stage 2, respectively.

V in FIG. 8_a1 ^*And v_a2 ^*The modulation strategy of carrier PWM is illustrated (in fig. 8 the triangular carrier frequency is about 6 times the frequency of the sinusoidal modulation wave, which is large in practical modulation). When v is_a1 ^*≥v_car1The A-phase of inverter stage 1 outputs the P-state, i.e. output, in timeAn electric potential; when v is_car2≤v_a1 ^*<v_car1In time, the A phase of the inverter stage 1 outputs an O state, namely 0 potential is output; when v is_a1 ^*<v_car2The A-phase of inverter stage 1 outputs N-states, i.e. outputsAnd (4) electric potential. When v is_a2 ^*≥v_car1The A-phase of inverter stage 2 outputs the P-state, i.e. output, in timeAn electric potential; when v is_car2≤v_a2 ^*<v_car1In time, the A phase of the inverter stage 2 outputs an O state, namely 0 potential is output; when v is_a2 ^*<v_car2The A-phase of inverter stage 2 outputs N-states, i.e. outputsAnd (4) electric potential. Further developments can be made from the above analysis in combination with Table 1Drive signals of the switch modules A1-A4, the switch module O1 and the switch module O2. B. The same applies to phase C.

It should be noted that, due to the limitation of the three-phase three-level dual-output inverter structure, in order to avoid generating the invalid working state in table 1 and causing the distortion of the output waveform, the relationship that the modulation waves of the inverter stage 1 and the inverter stage 2 should satisfy is as shown in formula (3).

In order to verify the feasibility of the three-phase three-level dual-output inverter and the effectiveness of a modulation strategy of carrier PWM, simulation verification is carried out through MATLAB/Simulink. The first set of simulation parameters is as follows: the carrier frequency is 10 kHz; the voltage of the direct current side is 300V; the modulation degree of the inverter stage 1 is 0.8, and the frequency is 50 Hz; the modulation degree of the inverter stage 2 is 0.8, and the frequency is 50 Hz; the three-phase load resistance of the inverter stage 1 is 10 omega, and the inductance is 5 mH; the three-phase load resistance of the inverter stage 2 is 10 Ω, and the inductance is 5 mH. The second set of simulation parameters is as follows: the carrier frequency is 10 kHz; the voltage of the direct current side is 300V; the modulation degree of the inverter stage 1 is 0.5, and the frequency is 50 Hz; the modulation degree of the inverter stage 2 is 0.5, and the frequency is 60 Hz; the three-phase load resistance of the inverter stage 1 is 10 omega, and the inductance is 5 mH; the three-phase load resistance of the inverter stage 2 is 10 Ω, and the inductance is 5 mH. Under the first set of simulation parameters, fig. 9 is a three-phase output current waveform diagram of the inverter stage 1, fig. 10 is a three-phase output current waveform diagram of the inverter stage 2, and fig. 11 is an output line voltage u of the inverter stage 1_AB1Waveform diagram, fig. 12 is the output line voltage u of the inverter stage 2_AB2A waveform diagram; under the second set of simulation parameters, fig. 13 is a three-phase output current waveform diagram of the inverter stage 1, fig. 14 is a three-phase output current waveform diagram of the inverter stage 2, and fig. 15 is an output line voltage u of the inverter stage 1_AB1Waveform diagram, FIG. 16 is the output line voltage u of the inverter stage 2_AB2And (4) waveform diagrams.

Although the present invention has been described in connection with the accompanying drawings, the present invention is not limited to the above-described embodiments, which are illustrative rather than restrictive, and those skilled in the art can make other forms without departing from the spirit of the present invention, which fall within the scope of the present invention.