阅读说明：本技术 一种基于多相注入振荡器的晶体振荡器电路 (Crystal oscillator circuit based on multiphase injection oscillator ) 是由 张文京 王耀晨 王子轩 廉政 蔡志匡 谢祖帅 于 2021-02-04 设计创作，主要内容包括：一种基于多相注入振荡器的晶体振荡器电路,采用具有多相激励信号输出的新型驰张振荡器,利用开关矩阵对这些信号进行统一切换,将其输出到晶体进行能量注入,使晶体在短时间内快速起振,在保证低功耗的前提下,启动时间接近最小理论值,并且具有较大的稳态输出摆幅,解决了传统注入技术注入频率不准的问题。(The utility model provides a crystal oscillator circuit based on heterogeneous injection oscillator, adopts the novel relaxation oscillator that has heterogeneous excitation signal output, utilizes switch matrix to unify these signals and switches over, carries out the energy injection with it output to the crystal, makes the crystal start shaking fast in the short time, under the prerequisite of guaranteeing low-power consumption, the start-up time is close minimum theoretical value to have great steady state output swing, solved the inaccurate problem of traditional injection technique injection frequency.)

1. A crystal oscillator circuit based on a multiphase injection oscillator, characterized by: the crystal oscillator circuit comprises a multiphase injection oscillator, a switch matrix, an amplifier and a crystal;

wherein the multi-phase excitation signal output terminal of the multi-phase injection oscillatorV ₁、V ₂……V _n-1、V _nAnd the polyphase excitation signal inputs of the switch matrixV ₁、V ₂……V _n-1、V _nConnecting; one input end of the switch matrix is externally connected with a control signal CTRL; one end of the crystalX _IN Differential oscillation signal input with input terminal of amplifier and switch matrixOut endV _P Connecting; one end of the crystalX _OUT Differential oscillation signal output end of amplifier and switch matrixV _nAre connected.

2. A multiphase injection oscillator based crystal oscillator circuit according to claim 1, wherein: the multiphase injection oscillator adopts a quadrature relaxation oscillator and comprises two relaxation oscillatorsRXO _I AndRXO _Q coupled to form a circuit comprising: a first AND gate AND, a second AND gate AND, a third AND gate AND, a fourth AND gate AND, a first SR flip-flop SR, a second SR flip-flop SR, a first comparator CMP, a second comparator CMP, a third comparator CMP, a fourth comparator CMP, a first amplifier AMP, a second amplifier AMP, a first capacitor C, a second capacitor C, a third capacitor C, a fourth capacitor C, a first resistor R, a second resistor R, a third resistor R, a fourth resistor R, a first not gate INV, a second not gate INV, a third not gate INV, a fourth not gate INV, a first switch SW, a second switch SW, a third switch SW, a fourth switch SW, a fifth switch SW, a sixth switch SW, a seventh switch SW, an eighth switch SW, a ninth switch SW, a tenth switch SW, an eleventh switch SW, a twelfth switch SW, a capacitor C _I Capacitor C _Q Resistance R _I Resistance R _Q Resistance R _a Resistance R _b Resistance R _c Resistance R _d Wherein:

the input terminal R of the first SR flip-flop SR1 is connected to the output terminal of the first comparator CMP 1; an inverting input terminal of the first comparator CMP1 is connected to one terminal of the first capacitor C1, one terminal of the first resistor R1, an input terminal of the second switch SW2, and an output terminal of the third switch SW 3; the other end of the first capacitor C1 is connected to ground GND; the input end of the first switch SW1 is connected with the other end of the first resistor R1, and the output end of the first switch SW1 is connected with the power supply VDD; the output terminal of the second switch SW2 is connected to ground GND; the input S of the first SR flip-flop SR1 is connected to the output of the second comparator CMP2Connecting; an inverting input terminal of the second comparator CMP2 is connected to one terminal of the second capacitor C2, one terminal of the second resistor R2, an input terminal of the fifth switch SW5, and an output terminal of the sixth switch SW 6; the other end of the second capacitor C2 is connected to ground GND; the input end of the fourth switch SW4 is connected with the other end of the second resistor R2, and the output end of the fourth switch SW4 is connected with the power supply VDD; the output terminal of the fifth switch SW5 is connected to ground GND; the output terminal of the first amplifier AMP1 and the capacitor C _I Is connected to the non-inverting input of the first comparator CMP1 and the non-inverting input of the second comparator CMP 2; an inverting input terminal of the first amplifier AMP1 and the resistor R _I One terminal of (1), a capacitor C _I The other ends of the two are connected; resistance R _I The other end of the first switch is connected with the input end of the third switch SW3 and the input end of the sixth switch SW 6; the non-inverting input terminal of the first amplifier AMP1 and the resistor R _a One terminal of (1), resistance R _b One end of the two ends are connected; resistance R _a The other end of the resistor is connected with a power supply VDD and a resistor R _b The other end of the first switch is connected with the ground GND;

the input terminal R of the second SR flip-flop SR2 is connected to the output terminal of the third comparator CMP 3; an inverting input terminal of the third comparator CMP3 is connected to one terminal of the third capacitor C3, one terminal of the third resistor R3, an input terminal of the eighth switch SW8, and an output terminal of the ninth switch SW 9; the other end of the third capacitor C3 is connected to ground GND; an input end of the seventh switch SW7 is connected with the other end of the third resistor R3, and an output end of the seventh switch SW7 is connected with the power supply VDD; the output terminal of the eighth switch SW8 is connected to ground GND; the input S of the second SR flip-flop SR2 is connected to the output of the fourth comparator CMP 4; an inverting input terminal of the fourth comparator CMP4 is connected to one terminal of the fourth capacitor C4, one terminal of the fourth resistor R4, an input terminal of the eleventh switch SW11, and an output terminal of the twelfth switch SW 12; the other end of the fourth capacitor C4 is connected to ground GND; an input terminal of the tenth switch SW10 is connected to the other terminal of the fourth resistor R4, and an output terminal of the tenth switch SW10 is connected to the power supply VDD; an output terminal of the eleventh switch SW11 is connected to ground GND; the output terminal of the second amplifier AMP2 and the capacitor C _Q ToThe terminal, the non-inverting input terminal of the third comparator CMP3, and the non-inverting input terminal of the fourth comparator CMP4 are connected; an inverting input terminal of the second amplifier AMP2 and the resistor R _Q One terminal of (1), a capacitor C _Q The other ends of the two are connected; resistance R _Q And the other end of the first switch is connected with the input end of a ninth switch SW9 and the input end of a twelfth switch SW 12; the non-inverting input terminal of the second amplifier AMP2 and the resistor R _c One terminal of (1), resistance R _d One end of the two ends are connected; resistance R _c The other end of the resistor is connected with a power supply VDD and a resistor R _d The other end of the first switch is connected with the ground GND;

output terminal of the first SR flip-flop SR1Is connected with one input end of the first AND gate AND1 AND one input end of the third AND gate AND 3; the output terminal Q of the first SR flip-flop SR1 is connected to one input terminal of the second AND gate AND2 AND one input terminal of the fourth AND gate AND 4; output terminal of the second SR flip-flop SR2Is connected with the other input end of the second AND gate AND2 AND the other input end of the third AND gate AND 3; the output terminal Q of the second SR flip-flop SR2 is connected to the other input terminal of the first AND gate AND1 AND the other input terminal of the fourth AND gate AND 4; the input end of the first not gate INV1 is connected to the output end of the fourth AND gate AND 4; the input end of the second not gate INV2 is connected to the output end of the third AND gate AND 3; the input end of the third not gate INV3 is connected to the output end of the first AND gate AND 1; an input end of the fourth not gate INV4 is connected to the output end of the second AND gate AND 2.

3. A multiphase injection oscillator based crystal oscillator circuit according to claim 2, wherein: the signal output by the output end Q of the first SR flip-flop SR1Q ₁Controls the closing and opening of the third switch SW 3; output terminal of the first SR flip-flop SR1Output signalQ _1nControls the closing and opening of the sixth switch SW 6; the signal output by the output terminal Q of the second SR flip-flop SR2Q ₂Controls the opening and closing of the ninth switch SW 9; output terminal of the second SR flip-flop SR2Output signalQ _2nControls the opening and closing of the twelfth switch SW 12; signal output from the first AND gate AND1Controls the opening and closing of the eighth switch SW 8; signal output from the second AND gate AND2Controls the closing and opening of the eleventh eighth switch SW 11; signal output from the third AND gate AND3Controls the closing and opening of the fifth switch SW 5; signal output from fourth AND gate AND4Controls the closing and opening of the second switch SW 2; the signal output by the first not gate INV1 controls the closing and opening of the first switch SW 1; the signal output by the second not gate INV2 controls the fourth switch SW4 to be closed or opened; the signal output by the third not gate INV3 controls the opening and closing of the seventh switch SW 7; the signal output by the fourth not gate INV4 controls the closing and opening of the tenth switch SW 10.

Technical Field

The invention relates to a crystal oscillator circuit based on a multiphase injection oscillator, and belongs to the technical field of integrated circuits.

Background

Emerging fields, such as: human body lans for healthcare applications and large-scale wireless sensing technologies for internet of things require ultra-low power electronic devices to extend battery life. One common method of reducing power consumption and extending battery life is to periodically power up the entire system and operate it in an intermittent manner. The wireless sensor nodes mainly constitute transceivers for communication, analog-to-digital converters for data conversion, and back-end processing modules, all of which require low power consumption. Reference frequency synthesis, digital clock timing and carrier frequency generation in these modules are typically implemented using a crystal oscillator (XO). The start-up time of the XO (several milliseconds for megahertz (MHz) crystals) becomes a bottleneck limiting the efficiency and performance of the power cycling scheme, thereby increasing system latency and standby power consumption. In summary, it is important to reduce the start-up time of the crystal oscillator (XO).

In recent years, there has been much research into fast start-up crystal oscillators. Increasing the load capacitance to increase the negative resistance of the active circuit may reduce the attack time of the crystal oscillator, but at the same time increase the gain of the amplifier, which may increase the power consumption for start-up, and if a high gain multi-stage circuit is used, the inverting amplifier may introduce a significant phase shift that may vary with PVT variations, compromising the stability and accuracy of the XO frequency. Accelerating the crystal oscillator by injecting energy into the ring oscillator requires that the frequency of the ring oscillator must be consistent with the frequency of the crystal oscillator, but the oscillation frequency of the ring oscillator is very susceptible to PVT. The DI (thermal-Injection) and CI (chip-Injection) methods improve the defect that the Injection oscillator needs to be trimmed, but cause a large amount of energy waste in the DI and CI stages.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a crystal oscillator circuit with rapid oscillation starting, which has the advantages of short starting time, low starting power consumption, good frequency stability and larger steady-state output swing amplitude.

A crystal oscillator circuit based on a multiphase injection oscillator comprises the multiphase injection oscillator, a switch matrix, an amplifier and a crystal;

wherein the multi-phase excitation signal output terminal of the multi-phase injection oscillatorV ₁、V ₂……V _n-1、V _nAnd the polyphase excitation signal inputs of the switch matrixV ₁、V ₂……V _n-1、V _nConnecting; one input end of the switch matrix is externally connected with a control signal CTRL; one end of the crystalX _IN Differential oscillation signal output end of amplifier and switch matrixV _P Connecting; one end of the crystalX _OUT Differential oscillation signal output end of amplifier and switch matrixV _nAre connected.

Furthermore, the multiphase injection oscillator adopts a quadrature relaxation oscillator and consists of two relaxation oscillatorsRXO _I AndRXO _Q coupled to form a circuit comprising: a first AND gate AND, a second AND gate AND, a third AND gate AND, a fourth AND gate AND, a first SR flip-flop SR, a second SR flip-flop SR, a first comparator CMP, a second comparator CMP, a third comparator CMP, a fourth comparator CMP, a first amplifier AMP, a second amplifier AMP, a first capacitor C, a second capacitor C, a third capacitor C, a fourth capacitor C, a first resistor R, a second resistor R, a third resistor R, a fourth resistor R, a first not gate INV, a second not gate INV, a third not gate INV, a fourth not gate INV, a first switch SW, a second switch SW, a third switch SW, a fourth switch SW, a fifth switch SW, a sixth switch SW, a seventh switch SW, an eighth switch SW, a ninth switch SW, a tenth switch SW, an eleventh switch SW, a twelfth switch SW, a capacitor C _I Capacitor C _Q Resistance R _I Resistance R _Q Resistance R _a Resistance R _b Resistance R _c Resistance R _d Wherein:

the input terminal R of the first SR flip-flop SR1 is connected to the output terminal of the first comparator CMP 1; an inverting input terminal of the first comparator CMP1 is connected to one terminal of the first capacitor C1, one terminal of the first resistor R1, an input terminal of the second switch SW2, and an output terminal of the third switch SW 3; the other end of the first capacitor C1 is connected to ground GND; first of allThe input end of the switch SW1 is connected with the other end of the first resistor R1, and the output end of the first switch SW1 is connected with the power supply VDD; the output terminal of the second switch SW2 is connected to ground GND; the input S of the first SR flip-flop SR1 is connected to the output of the second comparator CMP 2; an inverting input terminal of the second comparator CMP2 is connected to one terminal of the second capacitor C2, one terminal of the second resistor R2, an input terminal of the fifth switch SW5, and an output terminal of the sixth switch SW 6; the other end of the second capacitor C2 is connected to ground GND; the input end of the fourth switch SW4 is connected with the other end of the second resistor R2, and the output end of the fourth switch SW4 is connected with the power supply VDD; the output terminal of the fifth switch SW5 is connected to ground GND; the output terminal of the first amplifier AMP1 and the capacitor C _I Is connected to the non-inverting input of the first comparator CMP1 and the non-inverting input of the second comparator CMP 2; an inverting input terminal of the first amplifier AMP1 and the resistor R _I One terminal of (1), a capacitor C _I The other ends of the two are connected; resistance R _I The other end of the first switch is connected with the input end of the third switch SW3 and the input end of the sixth switch SW 6; the non-inverting input terminal of the first amplifier AMP1 and the resistor R _a One terminal of (1), resistance R _b One end of the two ends are connected; resistance R _a The other end of the resistor is connected with a power supply VDD and a resistor R _b The other end of the first switch is connected with the ground GND;

the input terminal R of the second SR flip-flop SR2 is connected to the output terminal of the third comparator CMP 3; an inverting input terminal of the third comparator CMP3 is connected to one terminal of the third capacitor C3, one terminal of the third resistor R3, an input terminal of the eighth switch SW8, and an output terminal of the ninth switch SW 9; the other end of the third capacitor C3 is connected to ground GND; an input end of the seventh switch SW7 is connected with the other end of the third resistor R3, and an output end of the seventh switch SW7 is connected with the power supply VDD; the output terminal of the eighth switch SW8 is connected to ground GND; the input S of the second SR flip-flop SR2 is connected to the output of the fourth comparator CMP 4; an inverting input terminal of the fourth comparator CMP4 is connected to one terminal of the fourth capacitor C4, one terminal of the fourth resistor R4, an input terminal of the eleventh switch SW11, and an output terminal of the twelfth switch SW 12; the other end of the fourth capacitor C4 is connected to ground GND; tenth opening (K)An input end of the switch SW10 is connected with the other end of the fourth resistor R4, and an output end of the tenth switch SW10 is connected with the power supply VDD; an output terminal of the eleventh switch SW11 is connected to ground GND; the output terminal of the second amplifier AMP2 and the capacitor C _Q Is connected to the non-inverting input of the third comparator CMP3 and the non-inverting input of the fourth comparator CMP 4; an inverting input terminal of the second amplifier AMP2 and the resistor R _Q One terminal of (1), a capacitor C _Q The other ends of the two are connected; resistance R _Q And the other end of the first switch is connected with the input end of a ninth switch SW9 and the input end of a twelfth switch SW 12; the non-inverting input terminal of the second amplifier AMP2 and the resistor R _c One terminal of (1), resistance R _d One end of the two ends are connected; resistance R _c The other end of the resistor is connected with a power supply VDD and a resistor R _d The other end of the first switch is connected with the ground GND;

output terminal of the first SR flip-flop SR1Is connected with one input end of the first AND gate AND1 AND one input end of the third AND gate AND 3; the output terminal Q of the first SR flip-flop SR1 is connected to one input terminal of the second AND gate AND2 AND one input terminal of the fourth AND gate AND 4; output terminal of the second SR flip-flop SR2Is connected with the other input end of the second AND gate AND2 AND the other input end of the third AND gate AND 3; the output terminal Q of the second SR flip-flop SR2 is connected to the other input terminal of the first AND gate AND1 AND the other input terminal of the fourth AND gate AND 4; the input end of the first not gate INV1 is connected to the output end of the fourth AND gate AND 4; the input end of the second not gate INV2 is connected to the output end of the third AND gate AND 3; the input end of the third not gate INV3 is connected to the output end of the first AND gate AND 1; an input end of the fourth not gate INV4 is connected to the output end of the second AND gate AND 2.

Further, the signal output by the output end Q of the first SR flip-flop SR1Q ₁Controls the closing and opening of the third switch SW 3;output terminal of the first SR flip-flop SR1Output signalQ _1nControls the closing and opening of the sixth switch SW 6; the signal output by the output terminal Q of the second SR flip-flop SR2Q ₂Controls the opening and closing of the ninth switch SW 9; output terminal of the second SR flip-flop SR2Output signalQ _2nControls the opening and closing of the twelfth switch SW 12; signal output from the first AND gate AND1Controls the opening and closing of the eighth switch SW 8; signal output from the second AND gate AND2Controls the closing and opening of the eleventh eighth switch SW 11; signal output from the third AND gate AND3Controls the closing and opening of the fifth switch SW 5; signal output from fourth AND gate AND4Controls the closing and opening of the second switch SW 2; the signal output by the first not gate INV1 controls the closing and opening of the first switch SW 1; the signal output by the second not gate INV2 controls the fourth switch SW4 to be closed or opened; the signal output by the third not gate INV3 controls the opening and closing of the seventh switch SW 7; the signal output by the fourth not gate INV4 controls the closing and opening of the tenth switch SW 10.

Compared with the prior art, the crystal oscillator circuit based on the multiphase injection oscillator has the following beneficial effects by adopting the technical scheme: the invention designs a crystal oscillator circuit based on a multiphase injection oscillator, adopts a novel relaxation oscillator with multiphase excitation signal output, uniformly switches the signals by using a switch matrix, outputs the signals to a crystal for energy injection, and enables the crystal to quickly start oscillation in a short time.

Drawings

Fig. 1 is a top level circuit block diagram of a crystal oscillator circuit based on a multiphase injection oscillator according to an embodiment of the present invention.

Fig. 2 is a schematic circuit diagram of the multiphase injection oscillator according to the embodiment of the present invention.

Detailed Description

The technical scheme of the invention is further explained in detail by combining the drawings in the specification.

As shown in fig. 1, a crystal oscillator circuit based on a multiphase injection oscillator according to an embodiment of the present invention includes: multiphase injection oscillator, switch matrix, amplifier and crystal, wherein a multiphase excitation signal output of the multiphase injection oscillatorV ₁、V ₂……V _n-1、V _nAnd the polyphase excitation signal inputs of the switch matrixV ₁、V ₂……V _n-1、V _nConnecting; one input end of the switch matrix is externally connected with a control signal CTRL; one end of the crystalX _IN Differential oscillation signal output end of amplifier and switch matrixV _P Connecting; one end of the crystalX _OUT Differential oscillation signal output end of amplifier and switch matrixV _nAre connected.

In the practical application process of the crystal oscillator circuit based on the multiphase injection oscillator designed by the embodiment of the invention, the multiphase injection oscillator circuit is further designed to adopt a coupled relaxation oscillator, and is specifically designed for the coupled relaxation oscillator, as shown in fig. 2, the multiphase injection oscillator adopts a novel orthogonal relaxation oscillator, and two relaxation oscillators are used for relaxation oscillationSwinging deviceRXO _I AndRXO _Q coupled to form a circuit comprising: a first AND gate AND, a second AND gate AND, a third AND gate AND, a fourth AND gate AND, a first SR flip-flop SR, a second SR flip-flop SR, a first comparator CMP, a second comparator CMP, a third comparator CMP, a fourth comparator CMP, a first amplifier AMP, a second amplifier AMP, a first capacitor C, a second capacitor C, a third capacitor C, a fourth capacitor C, a first resistor R, a second resistor R, a third resistor R, a fourth resistor R, a first not gate INV, a second not gate INV, a third not gate INV, a fourth not gate INV, a first switch SW, a second switch SW, a third switch SW, a fourth switch SW, a fifth switch SW, a sixth switch SW, a seventh switch SW, an eighth switch SW, a ninth switch SW, a tenth switch SW, an eleventh switch SW, a twelfth switch SW, a capacitor C _I Capacitor C _Q Resistance R _I Resistance R _Q Resistance R _a Resistance R _b Resistance R _c Resistance R _d Wherein:

the input terminal R of the first SR flip-flop SR1 is connected to the output terminal of the first comparator CMP 1; an inverting input terminal of the first comparator CMP1 is connected to one terminal of the first capacitor C1, one terminal of the first resistor R1, an input terminal of the second switch SW2, and an output terminal of the third switch SW 3; the other end of the first capacitor C1 is connected to ground GND; the input end of the first switch SW1 is connected with the other end of the first resistor R1, and the output end of the first switch SW1 is connected with the power supply VDD; the output terminal of the second switch SW2 is connected to ground GND; the input S of the first SR flip-flop SR1 is connected to the output of the second comparator CMP 2; an inverting input terminal of the second comparator CMP2 is connected to one terminal of the second capacitor C2, one terminal of the second resistor R2, an input terminal of the fifth switch SW5, and an output terminal of the sixth switch SW 6; the other end of the second capacitor C2 is connected to ground GND; the input end of the fourth switch SW4 is connected with the other end of the second resistor R2, and the output end of the fourth switch SW4 is connected with the power supply VDD; the output terminal of the fifth switch SW5 is connected to ground GND; the output terminal of the first amplifier AMP1 and the capacitor C _I One terminal of (1), a first comparatorThe non-inverting input terminal of the CMP1 is connected to the non-inverting input terminal of the second comparator CMP 2; an inverting input terminal of the first amplifier AMP1 and the resistor R _I One terminal of (1), a capacitor C _I The other ends of the two are connected; resistance R _I The other end of the first switch is connected with the input end of the third switch SW3 and the input end of the sixth switch SW 6; the non-inverting input terminal of the first amplifier AMP1 and the resistor R _a One terminal of (1), resistance R _b One end of the two ends are connected; resistance R _a The other end of the resistor is connected with a power supply VDD and a resistor R _b The other end of the first switch is connected with the ground GND;

the input terminal R of the second SR flip-flop SR2 is connected to the output terminal of the third comparator CMP 3; an inverting input terminal of the third comparator CMP3 is connected to one terminal of the third capacitor C3, one terminal of the third resistor R3, an input terminal of the eighth switch SW8, and an output terminal of the ninth switch SW 9; the other end of the third capacitor C3 is connected to ground GND; an input end of the seventh switch SW7 is connected with the other end of the third resistor R3, and an output end of the seventh switch SW7 is connected with the power supply VDD; the output terminal of the eighth switch SW8 is connected to ground GND; the input S of the second SR flip-flop SR2 is connected to the output of the fourth comparator CMP 4; an inverting input terminal of the fourth comparator CMP4 is connected to one terminal of the fourth capacitor C4, one terminal of the fourth resistor R4, an input terminal of the eleventh switch SW11, and an output terminal of the twelfth switch SW 12; the other end of the fourth capacitor C4 is connected to ground GND; an input terminal of the tenth switch SW10 is connected to the other terminal of the fourth resistor R4, and an output terminal of the tenth switch SW10 is connected to the power supply VDD; an output terminal of the eleventh switch SW11 is connected to ground GND; the output terminal of the second amplifier AMP2 and the capacitor C _Q Is connected to the non-inverting input of the third comparator CMP3 and the non-inverting input of the fourth comparator CMP 4; an inverting input terminal of the second amplifier AMP2 and the resistor R _Q One terminal of (1), a capacitor C _Q The other ends of the two are connected; resistance R _Q And the other end of the first switch is connected with the input end of a ninth switch SW9 and the input end of a twelfth switch SW 12; the non-inverting input terminal of the second amplifier AMP2 and the resistor R _c One terminal of (1), resistance R _d One end of the two ends are connected; resistance R _c The other end of the resistor is connected with a power supply VDD and a resistor R _d The other end of the first switch is connected with the ground GND;

output terminal of the first SR flip-flop SR1Is connected with one input end of the first AND gate AND1 AND one input end of the third AND gate AND 3; the output terminal Q of the first SR flip-flop SR1 is connected to one input terminal of the second AND gate AND2 AND one input terminal of the fourth AND gate AND 4; output terminal of the second SR flip-flop SR2Is connected with the other input end of the second AND gate AND2 AND the other input end of the third AND gate AND 3; the output terminal Q of the second SR flip-flop SR2 is connected to the other input terminal of the first AND gate AND1 AND the other input terminal of the fourth AND gate AND 4; the input end of the first not gate INV1 is connected to the output end of the fourth AND gate AND 4; the input end of the second not gate INV2 is connected to the output end of the third AND gate AND 3; the input end of the third not gate INV3 is connected to the output end of the first AND gate AND 1; an input end of the fourth not gate INV4 is connected to an output end of the second AND gate AND 2;

the signal output by the output terminal Q of the first SR flip-flop SR1Q ₁Controls the closing and opening of the third switch SW 3; output terminal of the first SR flip-flop SR1Output signalQ _1nControls the closing and opening of the sixth switch SW 6; the signal output by the output terminal Q of the second SR flip-flop SR2Q ₂Controls the opening and closing of the ninth switch SW 9; output terminal of the second SR flip-flop SR2Output signalQ _2nControls the opening and closing of the twelfth switch SW 12; signal output from the first AND gate AND1Controls the opening and closing of the eighth switch SW 8; signal output from the second AND gate AND2Controls the closing and opening of the eleventh eighth switch SW 11; signal output from the third AND gate AND3Controls the closing and opening of the fifth switch SW 5; signal output from fourth AND gate AND4Controls the closing and opening of the second switch SW 2; the signal output by the first not gate INV1 controls the closing and opening of the first switch SW 1; the signal output by the second not gate INV2 controls the fourth switch SW4 to be closed or opened; the signal output by the third not gate INV3 controls the opening and closing of the seventh switch SW 7; the signal output by the fourth not gate INV4 controls the closing and opening of the tenth switch SW 10.

The above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiment, but equivalent modifications or changes made by those skilled in the art according to the present disclosure should be included in the scope of the present invention as set forth in the appended claims.