阅读说明：本技术 一种内存交织方法及装置 (Memory interleaving method and device ) 是由 信恒超 夏晶 曾红义 陈挚睿 于 2018-07-31 设计创作，主要内容包括：一种内存交织方法及装置,涉及计算机领域,解决了采用两个交织窗口和交织算法对访问进行交织时出现不同的地址空间的访存性能的差异的问题。具体方案为：根据N个配置信息将访问容量划分为P份部分访问容量,P份部分访问容量的大小相同,N个配置信息为N个内存通道的配置信息,一个配置信息对应一个内存通道,配置信息用于指示内存通道映射的容量份数,N个内存通道中至少一个内存通道映射两份容量,N表示内存通道的总数,N为大于或等于2的整数；根据配置映射表将P份部分访问容量映射到N个内存通道,配置映射表用于指示容量与内存通道的映射关系。本方法及装置用于内存交织的过程中。(A memory interleaving method and device relates to the field of computers and solves the problem that memory access performance differences of different address spaces occur when two interleaving windows and an interleaving algorithm are adopted to interleave accesses. The specific scheme is as follows: dividing the access capacity into P parts of access capacity according to N pieces of configuration information, wherein the P parts of access capacity have the same size, the N pieces of configuration information are configuration information of N memory channels, one piece of configuration information corresponds to one memory channel, the configuration information is used for indicating the number of capacity parts mapped by the memory channels, at least one memory channel in the N memory channels maps two capacity parts, N represents the total number of the memory channels, and N is an integer greater than or equal to 2; and mapping the P parts of partial access capacity to the N memory channels according to a configuration mapping table, wherein the configuration mapping table is used for indicating the mapping relation between the capacity and the memory channels. The method and the device are used in the memory interleaving process.)

A memory interleaving method, comprising:

dividing access capacity into P parts of access capacity according to N pieces of configuration information, wherein the P parts of access capacity have the same size, the N pieces of configuration information are configuration information of N memory channels, one piece of configuration information corresponds to one memory channel, the configuration information is used for indicating the capacity number of the memory channel mapping, at least one memory channel in the N memory channels maps two parts of capacity, N represents the total number of the memory channels, and N is an integer greater than or equal to 2;

and mapping the P parts of partial access capacity to N memory channels according to a configuration mapping table, wherein the configuration mapping table is used for indicating the mapping relation between the capacity and the memory channels.

The memory interleaving method according to claim 1, wherein before said dividing the access capacity into P parts of partial access capacity according to the N configuration information, the method further comprises:

generating the N pieces of configuration information and the configuration mapping table, where the N pieces of configuration information include M pieces of first configuration information and N-M pieces of second configuration information, the first configuration information includes a memory channel identifier and a first indication identifier, the first indication identifier is used to indicate two capacities of the memory channel mapping corresponding to the memory channel identifier, the second configuration information includes a memory channel identifier and a second indication identifier, the second indication identifier is used to indicate one capacity of the memory channel mapping corresponding to the memory channel identifier, M is an integer, and M is greater than or equal to 1 and less than N.

The memory interleaving method according to claim 1 or 2, wherein before said mapping said P partial access capacities to N memory channels according to a configuration mapping table, said method further comprises:

and carrying out continuous processing on the address space corresponding to the discontinuous partial access capacity mapped to the same memory channel.

The memory interleaving method according to claim 3, wherein the identification bits of the address space of each partial access capacity are set at lower bits of an address requesting access to the memory.

The memory interleaving method according to claim 4, wherein the method further comprises:

and respectively restoring the address to the original address according to the N pieces of configuration information and the identification bit of the address space of each part of the access capacity.

A communication apparatus comprising a processing unit configured to implement the memory interleaving method according to any one of claims 1 to 5.

A communications apparatus, comprising: at least one processor, a memory, a bus and a transceiver, wherein the memory is for storing a computer program such that the computer program when executed by the at least one processor implements the memory interleaving method of any one of claims 1-5.

A computer readable storage medium comprising computer software instructions which, when run in a computer, cause the computer to perform the memory interleaving method of any one of claims 1 to 5.

A computer program product comprising instructions for causing a computer to perform the memory interleaving method according to any one of claims 1 to 5 when the computer program product is run on the computer.

A chip system, characterized in that the chip system comprises a processor for implementing the memory interleaving method according to any one of claims 1 to 5.