阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 市川裕章 于 2019-12-06 设计创作，主要内容包括：本发明防止热集中。臂部(2)具备：第一电路图案(5a),其在俯视时呈凹形并配置有第一半导体芯片(6,7)的背面；以及第二电路图案(5b),其配置于第一配置区域(5a1),在俯视时至少一部分配置在由第一电路图案(5a)的凹陷形成的第一配置区域(5a1),并在第一配置区域(5a1)中通过所连接的第一布线部件(8b,8c)电连接于第一负极电极(6b,7b)。由此,配置于第一电路图案(5a)的第一半导体芯片(6,7)不集中在层叠基板(3)的中央部,而是位于层叠基板(3)的外周部。因此,能够分散层叠基板(3)中的发热,并提高散热性。(The present invention prevents heat concentration. The arm (2) is provided with: a first circuit pattern (5a) which is concave in a plan view and on which a back surface of the first semiconductor chip (6,7) is arranged; and a second circuit pattern (5b) which is disposed in the first disposition region (5a1), at least a part of which is disposed in a first disposition region (5a1) formed by a recess of the first circuit pattern (5a) in a plan view, and which is electrically connected to the first negative electrode (6b,7b) in the first disposition region (5a1) via a first wiring member (8b,8c) connected thereto. Thus, the first semiconductor chips (6,7) arranged in the first circuit pattern (5a) are not concentrated in the central portion of the laminated substrate (3), but are positioned in the outer peripheral portion of the laminated substrate (3). Therefore, heat generation in the laminated substrate (3) can be dispersed, and heat dissipation can be improved.)

1. A semiconductor device is characterized in that a semiconductor element,

the semiconductor device has a first arm portion having a first arm portion,

the first arm portion includes:

a first semiconductor chip having a first positive electrode on a back surface thereof and a first negative electrode and a first control electrode on a front surface thereof;

a first circuit pattern which is concave in a plan view and on which the first positive electrode is arranged; and

and a second circuit pattern which is at least partially disposed in a first disposition region formed by a recess of the first circuit pattern in a plan view and which is electrically connected to the first negative electrode in the first disposition region via a first wiring member connected thereto.

2. The semiconductor device according to claim 1,

the first semiconductor chips are arranged in the first circuit patterns with the first arrangement regions therebetween.

3. The semiconductor device according to claim 1 or 2,

the first semiconductor chip is an RC-IGBT or a MOSFET.

4. The semiconductor device according to any one of claims 1 to 3,

the semiconductor device further has a second arm portion,

the second arm portion includes:

a second semiconductor chip having a second positive electrode on a back surface thereof and a second negative electrode and a second control electrode on a front surface thereof;

a third circuit pattern which is concave in a plan view, has a recess facing a side of the first circuit pattern on which the recess is disposed, and on which the second positive electrode is disposed; and

and a fourth circuit pattern which is at least partially disposed in a second disposition region formed by the recess of the third circuit pattern in a plan view and which is electrically connected to the second negative electrode in the second disposition region via a second wiring member to which the fourth circuit pattern is connected.

5. The semiconductor device according to claim 4,

the second circuit pattern is L-shaped in plan view and includes a first portion and a second portion, the first portion is disposed in the first disposition region, and the second portion extends in a direction perpendicular to an extending direction of the first disposition region.

6. The semiconductor device according to claim 5,

the fourth circuit pattern is L-shaped in plan view, including a third portion arranged in the second arrangement region and a fourth portion extending in a direction perpendicular to the extending direction of the second arrangement region and opposite to the extending direction of the second portion of the second circuit pattern.

7. The semiconductor device according to claim 4,

the second circuit pattern is T-shaped in plan view and includes a first portion and a second portion, the first portion being disposed in the first disposition region, and the second portion extending in a direction orthogonal to an extending direction of the first disposition region.

8. The semiconductor device according to claim 7,

the fourth circuit pattern is T-shaped in plan view and includes a third portion and a second portion, the third portion is disposed in the second disposition region, and the second portion extends in a direction orthogonal to an extending direction of the second disposition region.

9. The semiconductor device according to any one of claims 1 to 8,

the first arm portion further has a fifth circuit pattern,

the fifth circuit pattern is disposed adjacent to the first circuit pattern with the first disposition region therebetween, and is electrically connected to the first control electrode through a first control wiring member.

10. The semiconductor device according to any one of claims 4 to 8,

the first arm portion further has a fifth circuit pattern,

the fifth circuit pattern is arranged adjacent to the first circuit pattern with the first arrangement region therebetween and electrically connected to the first control electrode through a first control wiring member,

the second arm portion further has a sixth circuit pattern,

the sixth circuit pattern is adjacent to the third circuit pattern with the second arrangement region therebetween, is arranged at a position opposite to the fifth circuit pattern with the first arrangement region and the second arrangement region therebetween, and is electrically connected to the second control electrode through a second control wiring member.

Technical Field

The present invention relates to a semiconductor device.

Background

The Semiconductor device includes Semiconductor elements such as an IGBT (Insulated Gate Bipolar Transistor), a power MOSFET (metal oxide Semiconductor Field Effect Transistor), a FWD (Free Wheeling Diode), and an SBD (Schottky Barrier Diode). Such a semiconductor device includes a plurality of semiconductor units including the semiconductor element and a heat sink on which the plurality of semiconductor units are arranged. Such a semiconductor device can exhibit a desired function (see, for example, patent document 1).

The power conversion device is realized by disposing, for example, an IGBT and an FWD on a substrate (for example, see patent document 2). In this case, in order to effectively utilize the area of the substrate, IGBTs and FWDs having different chip sizes are arranged in the central portion of the substrate, and the IGBTs and FWDs are further arranged alternately in the vertical direction.

Documents of the prior art

Patent document

Patent document 1: specification of U.S. Pat. No. 5527620

Patent document 2: japanese patent laid-open publication No. 2018-125494

Disclosure of Invention

Technical problem

In order to efficiently arrange the IGBTs and FWDs having different chip sizes as described above in a limited region of the substrate, it is necessary to arrange them so as to be concentrated in a part of the region and suppress the ineffective region. In addition, it is necessary to consider the optimal arrangement of the external terminals and the connection wirings with respect to the substrate. Therefore, the IGBT and the FWD are inevitably disposed in the central portion of the substrate. However, the central portion (one portion) of the substrate on which the IGBTs and FWDs are intensively arranged generates heat intensively. Therefore, the rated current of the semiconductor device and the like may be affected, and it is difficult to enhance the characteristics of the semiconductor device.

The present invention has been made in view of such circumstances, and an object thereof is to provide a semiconductor device capable of preventing heat concentration.

Technical scheme

According to an aspect of the present invention, there is provided a semiconductor device including a first arm portion including: a first semiconductor chip having a first positive electrode on a back surface thereof and a first negative electrode and a first control electrode on a front surface thereof; a first circuit pattern which is concave in a plan view and on which the first positive electrode is arranged; and a second circuit pattern which is at least partially disposed in a first disposition region formed by a recess of the first circuit pattern in a plan view and which is electrically connected to the first negative electrode in the first disposition region through a first wiring member connected thereto.

Effects of the invention

According to the disclosed technology, heat concentration can be prevented and the characteristics of the semiconductor device can be improved.

The above and other objects, features and advantages of the present invention will become more apparent from the following description in connection with the accompanying drawings showing preferred embodiments thereof as examples of the present invention.

Drawings

Fig. 1 is a diagram for explaining an arm portion included in the semiconductor device according to the first embodiment.

Fig. 2 is a plan view of the semiconductor device according to the second embodiment.

Fig. 3 is a cross-sectional view of a semiconductor device of a second embodiment.

Fig. 4 is a circuit configuration diagram of the semiconductor device according to the second embodiment.

Fig. 5 is a diagram for explaining the flow of current in the semiconductor device of the second embodiment.

Fig. 6 is a diagram for explaining a semiconductor device for reference and a flow of current in the semiconductor device.

Description of the symbols

1,10 semiconductor device

2 arm part

3 laminated substrate

4 base plate

5a first circuit pattern

5a1 first disposition region

5b second circuit pattern

6,7 first semiconductor chip

6a,7a first control electrode

6b,7b first negative electrode

8 a-8 e wiring member

20 first arm part

21,31 ceramic circuit board

22,32 insulating plate

23 a-23 d,33 a-33 e circuit patterns

23a1 first routing area

33a1 second disposition region

24,34 metal plate

25,26,35,36 semiconductor chip

25a,26a,35a,36a gate electrode

25b,26b,35b,36b emitter electrode

27 a-27 j,37 a-37 i bonding wire

30 second arm part

40 casing

41 frame body

42 storage area

43-45 external terminal part

Detailed Description

[ first embodiment ]

Hereinafter, an arm included in the semiconductor device according to the first embodiment will be described with reference to fig. 1. Fig. 1 is a diagram for explaining an arm portion included in the semiconductor device according to the first embodiment. The semiconductor device 1 of the first embodiment includes the arm portion 2 shown in fig. 1. The arm portion 2 includes a laminated substrate 3 and first semiconductor chips 6 and 7 arranged on the laminated substrate 3. The first semiconductor chips 6 and 7 are provided with first positive electrodes (not shown) on the back surfaces thereof and first negative electrodes 6b and 7b and first control electrodes 6a and 7a on the front surfaces thereof, respectively. Such first semiconductor chips 6,7 can be, for example, power MOSFETs or RC (Reverse-Conducting) -IGBTs. The RC-IGBT is formed by including an IGBT and an FWD in one chip.

The laminated substrate 3 further includes a substrate 4, and a first circuit pattern 5a and a second circuit pattern 5b formed on the front surface of the substrate 4. The first circuit pattern 5a has a concave shape in plan view. The first circuit pattern 5a is provided with a first positive electrode formed on the back surface of the first semiconductor chips 6, 7. That is, the first circuit pattern 5a is U-shaped in plan view. A first arrangement region 5a1, which includes a concave recess and is indicated by a broken line in fig. 1, is provided on the inner side of the first circuit pattern 5 a. The first circuit pattern 5a is concave. Therefore, the first semiconductor chips 6,7 are arranged on the first circuit patterns 5a via the first arrangement regions 5a1, respectively.

At least a part of the second circuit pattern 5b is arranged in the first arrangement region 5a1, and at least a part of the second circuit pattern 5b is sandwiched by the first circuit pattern 5 a. In addition, the second circuit pattern 5b is connected to one end portion of the first wiring members 8b,8c in the first arrangement region 5a 1. The other end portions of the first wiring members 8b,8c are connected to the first negative electrodes 6b,7b of the first semiconductor chips 6, 7. Therefore, the second circuit pattern 5b is electrically connected to the first negative electrodes 6b,7b in the first arrangement region 5a1 through the connected first wiring members 8b,8 c. The first circuit pattern 5a and the second circuit pattern 5b are made of a conductive material. The wiring members 8b and 8c (and the wiring members 8a,8d, and 8e described later) are formed of bonding wires, lead frames, or strip-shaped conductive members.

In the arm portion 2 of the semiconductor device 1, for example, a current flowing from the wiring member 8a is divided in two directions of the first semiconductor chip 6 and the first semiconductor 7 in the first circuit pattern 5 a. Then, the current conducted in the first circuit pattern 5a flows into the first positive electrode on the back surface of the first semiconductor chip 6,7, and the output current is output from the first negative electrode 6b,7b on the front surface of the first semiconductor chip 6, 7. The output current outputted from the first semiconductor chips 6,7 flows into the second circuit pattern 5b via the wiring members 8b,8 c. At this time, a control signal is input to the first control electrodes 6a,7a of the first semiconductor chips 6,7 at a predetermined timing via the wiring member 8 e. Thus, the output current flowing into the second circuit pattern 5b is output to the outside of the arm portion 2 through the wiring member 8 d.

At this time, the first semiconductor chips 6 and 7 that output current generate heat in the arm portion 2 of the semiconductor device 1 as they are driven. However, the first circuit pattern 5a is concave in plan view, and the second circuit pattern 5b is disposed in the recess of the first circuit pattern 5 a. Therefore, the first circuit pattern 5a is disposed in the outer peripheral portion of the laminated substrate 3, and the second circuit pattern 5b is disposed in the central portion of the laminated substrate 3. The first semiconductor chips 6 and 7 arranged in the first circuit pattern 5a are not arranged in the central portion of the laminated substrate 3 but positioned in the outer peripheral portion of the laminated substrate 3. Therefore, the heat generated is prevented from concentrating at one portion of the laminated substrate 3 and dispersed, thereby improving the heat dissipation. Further, the output currents output from the first semiconductor chips 6 and 7 are collected in the second circuit pattern 5b in the central portion of the laminated substrate 3. Therefore, the control voltages to the first control electrodes 6a,7a of the first semiconductor chips 6,7 can be equalized, and the first semiconductor chips 6,7 can be driven in a balanced manner between the first semiconductor chips 6, 7. Therefore, the deterioration of the characteristics of the semiconductor device 1 including the arm portion 2 can be suppressed.

[ second embodiment ]

In a second embodiment, the semiconductor device of the first embodiment will be described in more detail. First, a semiconductor device will be described with reference to fig. 2 and 3. Fig. 2 is a plan view of the semiconductor device of the second embodiment, and fig. 3 is a sectional view of the semiconductor device of the second embodiment. Fig. 3 (a) is a sectional view taken along a one-dot chain line X1-X1 in fig. 2, and fig. 3 (B) is a sectional view taken along a one-dot chain line X2-X2 in fig. 2.

The semiconductor device 10 has a first arm 20 and a second arm 30. The semiconductor device 10 has upper and lower arm portions formed by the first arm portion 20 and the second arm portion 30. The first arm portion 20 and the second arm portion 30 are electrically connected by bonding wires 27a and 27 g. The semiconductor device 10 includes a heat dissipation substrate (not shown) and a case 40. The heat dissipating substrate is provided with a first arm 20 and a second arm 30 by solder (not shown). The case 40 is disposed on the heat dissipating substrate and surrounds the first arm portion 20 and the second arm portion 30. In addition, the case 40 is electrically connected to the first arm portion 20 and the second arm portion 30 by bonding wires 27f,37a,37 h. In this embodiment, only one bonding wire for electrically connecting the respective portions is shown for simplicity. In practice, the connection may be made by not 1 but a plurality of bonding wires. Instead of the bonding wire, a wiring member such as a plate-shaped lead frame or a thin tape-shaped tape (ribbon) may be used.

The first arm portion 20 has a ceramic circuit board 21 and semiconductor chips 25,26 provided on the front surface of the ceramic circuit board 21. The ceramic circuit board 21 is disposed on the heat dissipating substrate by solder, silver solder, or the like (not shown).

The semiconductor chips 25,26 (first semiconductor chips) are made of silicon. Such semiconductor chips 25,26 include switching elements of an RC-IGBT in which an IGBT and an FWD are formed in one chip. The RC-IGBT chip is formed by connecting an IGBT and an FWD in an inverse parallel mode to form a circuit. The semiconductor chips 25 and 26 are made of silicon carbide. Such semiconductor chips 25 and 26 include switching elements each formed of a MOSFET having a body diode equivalently built therein. The semiconductor chips 25 and 26 have collectors (positive electrodes, and drain electrodes in the case of a MOSFET) as main electrodes on the back surfaces thereof, and gate electrodes 25a and 26a (control electrodes) and emitters 25b and 26b (negative electrodes, and source electrodes in the case of a MOSFET) as main electrodes on the front surfaces thereof, for example. In addition, the gate electrodes 25a,26a of the semiconductor chips 25,26 are disposed at the center of the side portions of the front surface, and the emitter electrodes 25b,26b of the semiconductor chips 25,26 are disposed at the center portion. The illustration of the collector electrode on the back surface is omitted. Since the semiconductor device 10 uses a switching element including an RC-IGBT or a MOSFET made of silicon carbide, it is not necessary to connect diode elements in parallel. Therefore, the switching elements including the RC-IGBTs or MOSFETs made of silicon carbide are preferably arranged on the circuit patterns 23a,33a having a concave shape described later.

The ceramic circuit board 21 includes an insulating plate 22 and a metal plate 24 formed on the back surface of the insulating plate 22. The ceramic circuit board 21 has circuit patterns 23a to 23d formed on the front surface of the insulating plate 22. The insulating plate 22 is made of high thermal conductivity ceramics such as alumina, aluminum nitride, and silicon nitride having excellent thermal conductivity. The metal plate 24 is made of a metal having excellent thermal conductivity, such as aluminum, iron, silver, copper, or an alloy containing at least one of these metals. The circuit patterns 23a to 23d are made of metal having excellent conductivity, such as copper or copper alloy. In addition, in order to improve corrosion resistance, a material such as nickel may be formed on the surfaces of the circuit patterns 23a to 23d by plating or the like. Specifically, in addition to nickel, there are nickel-phosphorus alloys, nickel-boron alloys, and the like. The circuit patterns 23a to 23d have a thickness of, for example, 0.1mm to 1 mm. As the ceramic circuit board 21 having such a configuration, for example, a DCB (Direct Copper Bonding) board or an AMB (Active metal soldered) board can be used. The ceramic circuit board 21 can transmit heat generated by the semiconductor chips 25 and 26 to the heat radiation substrate side through the circuit pattern 23a, the insulating plate 22, and the metal plate 24. The ceramic circuit board 21 is an example, and may be a metal board and/or a lead frame formed of a die pad (die pad).

The circuit pattern 23a (first circuit pattern) constitutes a collector pattern of the first arm portion 20. The circuit pattern 23a is bonded with a collector electrode formed on the back surface of the semiconductor chips 25 and 26 by solder. Such a circuit pattern 23a has a concave shape in a plan view. An arrangement region 23a1 (first arrangement region) formed by a concave depression and indicated by a broken line in fig. 2 is provided inside the circuit pattern 23 a. The circuit pattern 23a may have a U-shape in plan view. In the circuit pattern 23a, the semiconductor chips 25 and 26 are separated by the arrangement region 23a1 and are arranged in a line along the arrangement region 23a 1. The semiconductor chips 25 and 26 are arranged such that the gate electrodes 25a and 26a are aligned in a row. The gate electrodes 25a face each other, and the gate electrodes 26a face each other. Note that the number of the semiconductor chips 25 and 26 may be 3 or more.

The circuit pattern 23b (second circuit pattern) constitutes an emitter pattern of the first arm portion 20. The circuit pattern 23b has an arrangement region 23a 1. The placement region 23a1 is connected to the emitter electrodes 25b,26b of the semiconductor chips 25,26 by bonding wires 27b,27c,27d,27 e. Such a circuit pattern 23b is L-shaped in plan view in fig. 2. That is, the circuit pattern 23b has a first portion and a second portion. The first portion is disposed in the disposition region 23a 1. The second portion extends from the end of the first portion outside the disposition region 23a1 in a direction (lower side in fig. 2) at right angles to the extending direction of the disposition region 23a 1. The circuit pattern 23b may be T-shaped in a plan view of fig. 2. That is, the second portion of the circuit pattern 23b may extend from the end of the first portion outside the arrangement region 23a1 in a direction (up and down in fig. 2) orthogonal to the extending direction of the arrangement region 23a 1.

The circuit patterns 23c,23d constitute a sense emitter pattern and a gate pattern of the first arm portion 20, respectively. The circuit patterns 23c,23d (fifth circuit patterns) are arranged adjacent to the circuit pattern 23a with the circuit pattern 23a sandwiched between the circuit pattern 23a and the arrangement region 23a 1. That is, the circuit patterns 23c and 23d are arranged adjacent to the circuit pattern 23a in parallel with the side of the circuit pattern 23a in the direction perpendicular to the concave opening in a plan view. The circuit patterns 23c and 23d are arranged parallel to the two opposing sides of the arrangement region 23a1 and adjacent to the circuit pattern 23 a. In fig. 2, the circuit patterns 23c and 23d are arranged on the lower side of the circuit pattern 23a in fig. 2. The circuit patterns 23c,23d are not limited to this case, and may be arranged on the upper side of the circuit pattern 23a in fig. 2 as needed. In addition, the circuit patterns 23c,23d are configured to extend in a long and narrow manner along the sides of the insulating plate 22 in order to save space. The circuit pattern 23c is connected to the emitter electrode 25b of the semiconductor chip 25 through a bonding wire 27 j. The circuit pattern 23d is connected to the gate electrodes 25a,26a of the semiconductor chips 25,26 via bonding wires 27h,27i, respectively.

The second arm portion 30 includes a ceramic circuit board 31 and semiconductor chips 35 and 36 provided on the front surface of the ceramic circuit board 31. The ceramic circuit board 31 is disposed on a heat dissipating substrate by solder, silver solder, or the like (not shown). The respective configurations of the second arm portion 30 are arranged to be substantially point-symmetrical with respect to the respective configurations of the first arm portion 20 with respect to the center point of the semiconductor device 10 in a plan view.

The semiconductor chips 35,36 (second semiconductor chips) are made of silicon, as are the semiconductor chips 25, 26. The semiconductor chips 35,36 also include switching elements of an RC-IGBT in which an IGBT and an FWD are formed in one chip. The semiconductor chips 35 and 36 are made of silicon carbide. The semiconductor chips 35,36 also include switching elements composed of MOSFETs. Therefore, the semiconductor chips 35 and 36 also have collectors (positive electrodes, and drain electrodes in MOSFETs) as main electrodes on the back surfaces thereof, and gate electrodes 35a and 36a (control electrodes) and emitters 35b and 36b (negative electrodes, and source electrodes in MOSFETs) as main electrodes on the front surfaces thereof. In addition, the gate electrodes 35a,36a of the semiconductor chips 35,36 are disposed at the center of the side portions of the front surface, and the emitter electrodes 35b,36b of the semiconductor chips 35,36 are disposed at the center portion. The illustration of the collector electrode on the back surface is omitted.

The ceramic circuit board 31 includes an insulating plate 32 and a metal plate 34 formed on the back surface of the insulating plate 32. The ceramic circuit board 31 has circuit patterns 33a to 33e formed on the front surface of the insulating plate 32. The insulating plate 32 is made of high thermal conductivity ceramics such as alumina, aluminum nitride, and silicon nitride, which have excellent thermal conductivity. The metal plate 34 is made of a metal having excellent thermal conductivity, such as aluminum, iron, silver, copper, or an alloy containing at least one of these metals. The circuit patterns 33a to 33e are made of metal having excellent conductivity, such as copper or copper alloy. In addition, in order to improve corrosion resistance, a material such as nickel may be formed on the surfaces of the circuit patterns 33a to 33e by plating or the like. Specifically, in addition to nickel, there are nickel-phosphorus alloys, nickel-boron alloys, and the like. The circuit patterns 33a to 33e have a thickness of, for example, 0.1mm to 1 mm. As the ceramic circuit board 31 having such a configuration, for example, a DCB board or an AMB board can be used. The ceramic circuit board 31 can transmit heat generated by the semiconductor chips 35 and 36 to the heat radiation substrate side through the circuit pattern 33a, the insulating plate 32, and the metal plate 34. The ceramic circuit board 31 is an example, and may be a metal base board and/or a lead frame formed of a die pad.

The circuit pattern 33a (third circuit pattern) constitutes a current collecting pattern of the second arm portion 30. The circuit pattern 33a is bonded with a collector electrode formed on the back surface of the semiconductor chips 35 and 36 by solder. Such a circuit pattern 33a has a concave shape in a plan view. An arrangement region 33a1 (second arrangement region) formed by a concave depression and indicated by a broken line in fig. 2 is provided inside the circuit pattern 33 a. The circuit pattern 33a is adjacent to the circuit pattern 23a such that the arrangement region 23a1 side of the circuit pattern 23a faces the arrangement region 33a1 side of the circuit pattern 33 a. That is, the circuit pattern 23a of the first arm portion 20 and the circuit pattern 33a of the second arm portion 30 are adjacent to each other so that the respective recesses face each other. In the circuit pattern 33a, the semiconductor chips 35 and 36 are separated by the arrangement region 33a1 and are arranged in a line. The semiconductor chips 35 and 36 are arranged such that the gate electrodes 35a and 36a are aligned in a row. The gate electrodes 35a face each other, and the gate electrodes 36a face each other. Note that the number of the semiconductor chips 35 and 36 may be 3 or more.

The circuit pattern 33b (fourth circuit pattern) constitutes an emitter pattern of the second arm portion 30. The circuit pattern 33b has an arrangement region 33a 1. The disposition region 33a1 is connected to the emitter electrodes 35b,36b of the semiconductor chips 35,36 by bonding wires 37b,37c,37d,37 e. Such a circuit pattern 33b is L-shaped in a plan view in fig. 2. That is, the circuit pattern 33b includes a region disposed on the entire arrangement region 33a1 and a region perpendicular to the region on the upper side in fig. 2. The circuit pattern 33b is electrically connected to the circuit pattern 23a through the bonding wire 27 a. Such a circuit pattern 33b is L-shaped in a plan view in fig. 2. That is, the circuit pattern 33b has a third portion and a fourth portion. The third portion is disposed in the disposition region 33a 1. The fourth portion extends from the end of the third portion outside the arrangement region 33a1 in a direction at right angles to the extending direction of the arrangement region 33a1, which is the direction at right angles to the extending direction of the arrangement region 33a1, which is the direction of the opposite side of the second portion of the circuit pattern 23b extending along the lower side in fig. 2. The circuit pattern 33b may be T-shaped in a plan view of fig. 2. That is, the fourth portion of the circuit pattern 33b may extend from the end of the third portion outside the arrangement region 33a1 in a direction (up and down in fig. 2) orthogonal to the extending direction of the arrangement region 33a 1.

The circuit patterns 33c,33d constitute the sense emitter pattern and the gate pattern of the second arm portion 30, respectively. The circuit patterns 33c and 33d (sixth circuit pattern) and the arrangement region 33a1 are arranged adjacent to the circuit pattern 33a with the circuit pattern 33a interposed therebetween. The circuit patterns 33c and 33d are arranged at positions point-symmetrical to the circuit patterns 23c and 23d with respect to the center point of the semiconductor device 10. In this case, the circuit patterns 33c and 33d are arranged on the upper side of the circuit pattern 33a in fig. 2. The circuit patterns 33c,33d are not limited to this case, and may be arranged on the lower side in fig. 2 of the circuit pattern 33a in accordance with the positions of the circuit patterns 23c,23 d. In addition, the circuit patterns 33c,33d are configured to extend in a long and narrow manner along the sides of the insulating plate 32 in order to save space. The circuit pattern 33c is connected to the emitter electrode 36b of the semiconductor chip 36 through a bonding wire 37 i. The circuit pattern 33d is connected to the gate electrodes 35a,36a of the semiconductor chips 35,36 via bonding wires 37f,37g, respectively. The circuit pattern 33e is disposed adjacent to the circuit pattern 33a (lower side in fig. 2) on the opposite side of the circuit pattern 33a from the disposition region 33a 1. In addition, the circuit pattern 33e is electrically connected to the circuit pattern 23b through the bonding wire 27 g.

The case 40 is disposed on the heat dissipating substrate as described above, and includes the frame 41 having a rectangular shape in a plan view. The frame 41 of the case 40 has a box shape surrounding the periphery. A housing area 42 for housing the first arm portion 20 and the second arm portion 30 described above is formed in the housing 41. In addition, external terminal portions 43 to 45 are formed at both left and right ends of the housing 41 in fig. 2, respectively. The external terminal portion 43 is electrically connected to the circuit pattern 33a of the second arm portion 30 housed in the housing 41 via the bonding wire 37 a. The external terminal portion 44 is electrically connected to the circuit pattern 23a housed in the first arm portion 20 of the housing 41 via the bonding wire 27 f. The external terminal portion 45 is electrically connected to the circuit pattern 33e housed in the second arm portion 30 of the housing 41 via the bonding wire 37 h. Therefore, a positive electrode is connected to the external terminal portion 43, a negative electrode is connected to the external terminal portion 45, and an output is obtained from the external terminal portion 44. Although not shown, the housing 40 includes control terminals for receiving control signals on both sides of the housing 41 in the longitudinal direction. From which the control terminals are electrically connected to the circuit patterns 23c,33c, respectively. The housing 40 includes, for example, external terminal portions 43 to 45, and is formed by injection molding using a thermoplastic resin. Examples of such resins include polyphenylene sulfide (PPS), polybutylene terephthalate (PBT) resin, polybutylene succinate (PBS) resin, Polyamide (PA) resin, and acrylonitrile-butadiene-styrene (ABS) resin.

The bonding wires 27a to 27j,37a to 37i described above are made of a metal such as aluminum or copper having excellent conductivity, or an alloy containing at least one of these metals. The bonding wires preferably have a diameter of 100 μm or more and 1mm or less. The heat dissipating substrate, not shown, is made of, for example, aluminum, iron, silver, copper, or an alloy containing at least one of these metals, which has excellent thermal conductivity. In addition, in order to improve corrosion resistance, a material such as nickel may be formed on the surface of the heat dissipating substrate by plating or the like. Specifically, in addition to nickel, there are nickel-phosphorus alloys, nickel-boron alloys, and the like. In such a heat dissipating substrate, mounting holes used for mounting to an external device, contact regions for flowing an output current into the first arm portion 20 and the second arm portion 30, and the like are appropriately formed.

A cooler (not shown) may be mounted on the back surface of the heat dissipating substrate of the semiconductor device 10. At this time, the cooler is mounted by heat conductive grease such as silicone mixed with a metal oxide filler. This also improves the heat dissipation of the semiconductor device 10. The cooler in this case is made of, for example, aluminum, iron, silver, copper, or an alloy containing at least one of these metals, which is excellent in thermal conductivity. As the cooler, a radiator having a plurality of fins, a cooling device using water cooling, or the like can be used. In addition, the heat dissipating substrate may be integrally configured with such a cooler. In this case, the heat dissipating substrate is made of aluminum, iron, silver, copper, or an alloy containing at least one of these metals, which has excellent thermal conductivity. In addition, in order to improve corrosion resistance, a material such as nickel may be formed on the surface of the heat dissipating substrate integrated with the cooler by plating or the like. Specifically, in addition to nickel, there are nickel-phosphorus alloys, nickel-boron alloys, and the like.

Next, a circuit configuration realized by the semiconductor device 10 will be described with reference to fig. 4. Fig. 4 is a circuit configuration diagram of the semiconductor device according to the second embodiment. The semiconductor device 10 thus constitutes an inverter circuit shown in fig. 4 by the semiconductor chips 25,26,35,36, the circuit patterns 23a to 23d,33a to 33e, and the bonding wires 27a to 27j,37a to 37 i.

The semiconductor device 10 is provided with a C1 terminal (corresponding to the external terminal portion 43), an E2 terminal (corresponding to the external terminal portion 45), and an E1C2 terminal (corresponding to the external terminal portion 44). A high potential terminal of the external power supply is connected to the C1 terminal as the input P terminal, and a low potential terminal of the external power supply is connected to the E2 terminal as the input N terminal. Then, a load (not shown) is connected to the E1C2 terminal which is the output U terminal of the semiconductor device 10. Thereby, the semiconductor device 10 functions as an inverter (inverter).

In the semiconductor device 10 having such a configuration, for example, external connection terminals (not shown) may be bonded to the external terminal portions 43 to 45, and the first arm portion 20 and the second arm portion 30 of the housing area 42 of the housing 41 may be sealed with a sealing member. In this case, a thermosetting resin such as an epoxy resin, a phenol resin, and a maleimide resin can be used as the sealing member.

Next, a case where a current is input to operate the semiconductor device 10 will be described with reference to fig. 5. Fig. 5 is a diagram for explaining the flow of current in the semiconductor device of the second embodiment. The semiconductor device 10 shown in fig. 5 is the semiconductor device shown in fig. 4. However, in fig. 5, arrows shown by thick lines indicate the flow of current in the semiconductor device 10. The arrows of the broken lines indicate the flow of current in the regions where the circuit patterns 33a and 33b of the semiconductor chips 35 and 36 are arranged.

In the semiconductor device 10, a current inputted from the external terminal portion 43 flows into the circuit pattern 33a via the bonding wire 37 a. The current flowing in the circuit pattern 33a is divided along the shape of the circuit pattern 33a and directed to 2 regions where the semiconductor chips 35 and 36 are arranged, respectively.

In the circuit pattern 33a, currents branched in 2 directions flow into the semiconductor chips 35,36 from the collectors on the back surfaces of the semiconductor chips 35,36, and output currents are output from the emitters 35b,36b on the front surfaces of the semiconductor chips 35,36, respectively. At this time, a gate voltage is applied to the gate electrodes 35a and 36a of the semiconductor chips 35 and 36 at a predetermined timing. The current output from the emitter electrodes 35b,36b of the semiconductor chips 35,36 flows into the circuit pattern 33b via the bonding wires 37b,37c,37d,37 e. The output current thus flowing flows through the circuit pattern 33b and flows into the circuit pattern 23a of the first arm portion 20 via the bonding wire 27.

In the second arm portion 30 through which the current flows in this manner, the semiconductor chips 35 and 36 are arranged at the periphery of the concave circuit pattern 33a in a plan view. Therefore, even if the semiconductor chips 35 and 36 generate heat during driving with energization, the heat is generated in the second arm portion 30 in a distributed manner, and heat concentration does not occur at one location. In particular, since the semiconductor chips 35 and 36 are both RC-IGBTs having the same chip size, the recessed circuit pattern 33a can be realized in a simple shape rather than a complicated shape in a plan view. Since the circuit pattern 33a has such a shape, the semiconductor chips 35 and 36 can be easily arranged while saving space. Further, the output currents output from the emitter electrodes 35b,36b of the semiconductor chips 35,36 are collected in the circuit pattern 33b disposed in the central portion. Therefore, the gate voltage unevenness to the gate electrodes 35a,36a of the semiconductor chips 35,36 can be suppressed. Also, the semiconductor chips 35,36 can be driven evenly between the semiconductor chip 35 and the semiconductor chip 36. In addition, the length of the wiring from the external terminal portion 43 to the semiconductor chip 35 is the same as the length of the wiring from the external terminal portion 43 to the semiconductor chip 36. Therefore, the current unevenness between the semiconductor chips 35 and 36 can be suppressed.

Similarly, the first arm portion 20 causes the current flowing in the circuit pattern 23a to flow from the collectors on the back surfaces of the semiconductor chips 25 and 26 into the semiconductor chips 25 and 26, and outputs the output current from the emitters 25b and 26b on the front surfaces of the semiconductor chips 25 and 26, respectively. At this time, the gate voltage is also applied to the gate electrodes 25a,26a of the semiconductor chips 25,26 at a predetermined timing. The output current output from the emitter electrodes 25b,26b of the semiconductor chips 25,26 flows into the circuit pattern 23b via the bonding wires 27b,27c,27d,27 e. The output current thus flowing flows through the circuit pattern 23b and flows into the circuit pattern 33e of the second arm portion 30 via the bonding wire 27 g. Therefore, the first arm portion 20 also obtains the same effect as the second arm portion 30 described above.

Here, a semiconductor device 10 of this type will be described with reference to fig. 6. Fig. 6 is a diagram for explaining a semiconductor device for reference and a flow of current in the semiconductor device. In the structure of the semiconductor device 10a shown in fig. 6, the same components as those of the semiconductor device 10 are denoted by the same reference numerals. In addition, only the components necessary for the description are denoted by reference numerals.

The semiconductor device 10a has a first arm portion 60 and a second arm portion 70. The semiconductor device 10a includes first arm portions 60 and second arm portions 70 forming upper and lower arm portions. The first arm portion 60 and the second arm portion 70 are electrically connected by a bonding wire 67a or the like. The semiconductor device 10a includes a heat dissipation substrate (not shown) and a case 40. The heat dissipating substrate is provided with a first arm 60 and a second arm 70 by solder (not shown). The case 40 is disposed on the heat dissipating substrate and surrounds the first arm portion 60 and the second arm portion 70. In addition, the housing 40 and the first arm portion 60 and the second arm portion 70 are electrically connected by a bonding wire 77a or the like.

The first arm part 60 has a ceramic circuit board and semiconductor chips 651-653,661-663 provided on the front surface of the ceramic circuit board. Such a ceramic circuit board is disposed on the heat dissipating substrate by solder, silver solder, or the like (not shown). The semiconductor chips 651-653 are FWD or SBD made of silicon or silicon carbide. The semiconductor chips 651 to 653 have, for example, a cathode electrode (negative electrode) as a main electrode on the back surface and an anode electrode (positive electrode) on the front surface. The semiconductor chips 661 to 663 are IGBTs made of silicon. Such semiconductor chips 661 to 663 include a collector electrode (positive electrode) on the back surface, a gate electrode in the center of the side portion of the front surface, and an emitter electrode (negative electrode) in the center portion of the front surface.

The ceramic circuit board includes an insulating plate 62 and a metal plate formed on the back surface of the insulating plate 62. The ceramic circuit board 61 has circuit patterns 63a to 63c formed on the front surface of the insulating plate 62. The circuit patterns 63a to 63c are arranged in the shape shown in fig. 6. The semiconductor chips 651 to 653,661 to 663 are disposed in the center of a circuit pattern 63a, which will be described later.

The second arm section 70 has a ceramic circuit board 71 and semiconductor chips 751 to 753,761 to 763 provided on the front surface of the ceramic circuit board 71. The ceramic circuit board 71 is disposed on the heat dissipating substrate by solder, silver solder, or the like (not shown).

The semiconductor chips 751 to 753,761 to 763 are made of silicon or silicon carbide as with the semiconductor chips 651 to 653,661 to 663. The semiconductor chips 651-653,661-663 are also FWD and IGBT. Therefore, the semiconductor chips 751 to 753 include, for example, a cathode electrode (negative electrode) as a main electrode on the back surface and an anode electrode (positive electrode) on the front surface. The semiconductor chips 761 to 763 each include a collector electrode (positive electrode) on the back surface, a gate electrode at the center of the front surface side portion, and an emitter electrode (negative electrode) at the center of the front surface. The semiconductor chips 751 to 753,761 to 763 are disposed in the center of a circuit pattern 73a, which will be described later.

The ceramic circuit board 71 includes an insulating plate 72 and a metal plate formed on the rear surface of the insulating plate 72. The ceramic circuit board 71 has circuit patterns 73a to 73d formed on the front surface of the insulating plate 72. The circuit patterns 73a to 7d are arranged in the shape shown in fig. 6.

A case where a current is input to operate the semiconductor device 10a having such a configuration will be described. Note that, in fig. 6, the flow of current in the semiconductor device 10a is also indicated by arrows in a thick line. The arrows with broken lines indicate the flow of current in the regions where the circuit patterns 73a and 73b of the semiconductor chips 751 to 753,761 to 763 are arranged.

In the semiconductor device 10a, a current input from the external terminal portion 43 flows into the circuit pattern 73a via the bonding wire 77 a. The current flowing into the circuit pattern 73a is diffused in the circuit pattern 73 a. The current diffused in the circuit pattern 73a flows from the collector electrodes on the back surfaces of the semiconductor chips 761 to 763 into the semiconductor chips 761 to 763, and the output current is output from the emitter electrodes on the front surfaces of the semiconductor chips 761 to 763. In this case, a gate voltage is applied to the gate electrodes of the semiconductor chips 761 to 763 at a predetermined timing.

The output current output from the emitter electrode of the semiconductor chip 761,763 flows into the circuit pattern 73b via the bonding wires 77c,77 h. The output current output from the emitter electrode of the semiconductor chip 762 flows into the circuit pattern 73b via the bonding wire 77d, the semiconductor chip 752, and the bonding wire 77 f. The output current thus flowing flows through the circuit pattern 73b and flows into the circuit pattern 63a of the first arm portion 60 via the bonding wire 67 a.

In the second arm portion 70 through which the current flows, the semiconductor chips 751 to 753,761 to 763 are disposed in the center of the circuit pattern 73 a. In particular, the semiconductor chips 751 to 753,761 to 763 are different in kind and chip size. Therefore, the circuit patterns 73a need to secure a large number of areas in order to secure their arrangement areas. When the semiconductor chips 751 to 753,761 to 763 are disposed in the circuit pattern 73a, the semiconductor chips must be disposed in a staggered grid pattern in the center of the circuit pattern 73 a. Therefore, if the semiconductor chips 761 to 763 generate heat during driving with energization, heat is concentrated in the center of the second arm portion 70. The lengths of the wirings from the circuit patterns 73b, from which the output currents are output from the emitter electrodes of the semiconductor chips 761 to 763, are not uniform. Therefore, gate voltages of the gate electrodes of the semiconductor chips 761 to 763 are unbalanced, and it is difficult to drive the semiconductor chips 761 to 763 uniformly among the semiconductor chips 761 to 763. Although the first arm portion 60 receiving the current from the second arm portion 70 is not specifically described, the current flows in the same manner as in the second arm portion 70, and the same problem as in the second arm portion 70 occurs.

The first arm 20 and the second arm 30 of the semiconductor device 10 include the semiconductor chips 25,26,35,36, the semiconductor chips 25,26,35,36 include collectors on the back surfaces thereof, and emitters 25b,26b,35b,36b and gate electrodes 25a,26a,35a,36a on the front surfaces thereof. The first arm portion 20 and the second arm portion 30 further include circuit patterns 23a,33a, and the circuit patterns 23a,33a are recessed in a plan view so as to surround at least a part of the arrangement regions 23a1,33a1, and the back surfaces of the semiconductor chips 25,26,35,36 are arranged. The first arm portion 20 and the second arm portion 30 include circuit patterns 23b,33b, and the conductive patterns 23b,33b are disposed in the disposition regions 23a1,33a1 so as to surround at least a part of the circuit patterns 23a,33a, and are electrically connected to the emitter electrodes 25b,26b,35b,36b of the semiconductor chips 25,26,35,36 via bonding wires 27b,27c,27d,27e,37b,37c,37d,37 e. Thus, the semiconductor chips 25,26,35,36 arranged in the circuit patterns 23a,33a are not concentrated on the central portion of the ceramic circuit substrates 21,31, but are positioned on the outer peripheral portion side of the ceramic circuit substrates 21, 31. Therefore, heat generation in the ceramic circuit boards 21 and 31 can be dispersed, and heat dissipation can be improved. In addition, the emitter currents output from the semiconductor chips 25,26,35,36 are collected in the circuit patterns 23b,33b in the center portions of the ceramic circuit substrates 21, 31. Therefore, the gate voltages to the gate electrodes 25a,26a,35a,36a of the semiconductor chips 25,26,35,36 become uniform, and the semiconductor chips 25,26,35,36 can be driven evenly among the semiconductor chips 25,26,35, 36. Therefore, the deterioration of the characteristics of the semiconductor device 10 including the first arm portion 20 and the second arm portion 30 can be suppressed.

The foregoing merely illustrates the principles of the invention. Further, it will be apparent to those skilled in the art that numerous modifications and variations can be made, and the present invention is not limited to the precise configurations and applications shown and described above, and all modifications and equivalents corresponding thereto are deemed to be within the scope of the present invention as defined by the appended claims and equivalents thereof.

The claims (modification according to treaty clause 19)

1. A semiconductor device is characterized in that a semiconductor element,

the semiconductor device has a first arm portion having a first arm portion,

the first arm portion includes:

a first circuit pattern having a concave shape when viewed from above;

a second circuit pattern, at least a part of which is arranged in a first arrangement area formed by the recess of the first circuit pattern when viewed from the top; and

and a first semiconductor chip including a first positive electrode on a back surface thereof, a first control electrode on a front surface thereof, and a first negative electrode electrically connected to the second circuit pattern through a first wiring member, wherein each of the first positive electrodes is disposed in the first circuit pattern with the first disposition region therebetween.

2. The semiconductor device according to claim 1,

the first semiconductor chip is an RC-IGBT.

3. The semiconductor device according to claim 1,

the first semiconductor chip is a MOSFET having a body diode built therein.

4. The semiconductor device according to any one of claims 1 to 3,

the first control electrodes of the first semiconductor chips arranged with the first arrangement region therebetween face the opening direction of the recess or the opposite side of the opening direction, and are formed in a row perpendicular to the opening direction.

5. The semiconductor device according to any one of claims 1 to 4,

the semiconductor device further includes a fifth circuit pattern which is disposed adjacent to a single side of a region of the first circuit pattern where the first semiconductor chip is disposed, with the first circuit pattern sandwiched therebetween together with the first arrangement region, and is electrically connected to the first control electrode through a first control wiring member.

6. The semiconductor device according to claim 5,

the first control wiring member is laid perpendicularly to an opening direction of the recess from the first control electrode,

the first wiring part is arranged in the second circuit pattern from the first negative electrode in parallel with the first control wiring part.

7. The semiconductor device according to claim 1,

the semiconductor device further includes:

an input wiring member connected to an input region of the first circuit pattern, the input region facing the second circuit pattern in parallel with an opening direction of the recess; and

and an output wiring member connected to an output region of the second circuit pattern on a side opposite to the input region.

8. The semiconductor device according to any one of claims 1 to 4,

the semiconductor device further has a second arm portion,

the second arm portion includes:

a third circuit pattern which is concave in a plan view and has a recess facing a side of the first circuit pattern on which the recess is disposed;

a fourth circuit pattern, at least a part of which is arranged in a second arrangement region formed by the recess of the third circuit pattern in a plan view; and

and a second semiconductor chip having a second positive electrode on a back surface thereof, a second control electrode on a front surface thereof, and a second negative electrode electrically connected to the second control electrode through a second wiring member, wherein the second positive electrodes are arranged on the third circuit pattern with the second arrangement region therebetween.

9. The semiconductor device according to claim 8,

the second circuit pattern is L-shaped in plan view and includes a first portion and a second portion, the first portion is disposed in the first disposition region, and the second portion extends in a direction perpendicular to an extending direction of the first disposition region.

10. The semiconductor device according to claim 9,

the fourth circuit pattern is L-shaped in plan view, including a third portion arranged in the second arrangement region and a fourth portion extending in a direction perpendicular to the extending direction of the second arrangement region and opposite to the extending direction of the second portion of the second circuit pattern.

11. The semiconductor device according to claim 8,

the second circuit pattern is T-shaped in plan view and includes a first portion and a second portion, the first portion being disposed in the first disposition region, and the second portion extending in a direction orthogonal to an extending direction of the first disposition region.

12. The semiconductor device according to claim 8,

the fourth circuit pattern is T-shaped in plan view and includes a third portion and a fourth portion, the third portion is disposed in the second disposition region, and the fourth portion extends in a direction orthogonal to an extending direction of the second disposition region.

13. The semiconductor device according to any one of claims 8 to 12,

the first arm portion further has a fifth circuit pattern,

the fifth circuit pattern is arranged adjacent to one side of a region of the first circuit pattern where the first semiconductor chip is arranged, with the first arrangement region interposed therebetween, and is electrically connected to the first control electrode through a first control wiring member,

the second arm portion further has a sixth circuit pattern,

the sixth circuit pattern is adjacent to one side of a region of the third circuit pattern where the second semiconductor chip is arranged, with the third circuit pattern sandwiched therebetween, and is arranged at a position opposite to the fifth circuit pattern with the first arrangement region and the second arrangement region therebetween, and is electrically connected to the second control electrode via a second control wiring member.

14. The semiconductor device according to claim 13,

in the first arm portion,

the first control wiring member is laid perpendicularly to an opening direction of the recess from the first control electrode,

the first wiring part is arranged in the second circuit pattern from the first negative electrode in parallel with the first control wiring part,

in the second arm portion, the first arm portion,

the second control wiring member is arranged on the opposite side of the first control wiring member from the second control electrode in a direction perpendicular to the opening direction of the recess,

the second wiring part is arranged in the fourth circuit pattern from the second negative electrode in parallel with the second control wiring part.

15. The semiconductor device according to claim 14,

the first arm portion further has:

a first input wiring member connected to a first input region of the first circuit pattern, the first input region facing the second circuit pattern in parallel to an opening direction of the recess of the first circuit pattern; and

a first output wiring member connected to a first output region on an opposite side of the first input region of the second circuit pattern and the third circuit pattern,

the second arm portion further has:

a second input wiring member connected to a second input region of the third circuit pattern, the second input region facing the fourth circuit pattern in parallel to an opening direction of the recess of the third circuit pattern; and

and a second output wiring member connected to a second output region of the fourth circuit pattern on an opposite side of the second input region.