阅读说明：本技术 一种处理方法、装置及设备 (Processing method, device and equipment ) 是由 黃圳柏 于 2020-12-04 设计创作，主要内容包括：本申请提供一种处理方法,包括：若输入输出内存管理单元配置了寄存器的第一排除内存范围,在输入输出内存管理单元页表中基于第二外围设备的第二排除内存范围,建立所述寄存器的第二排除内存范围和所述第二外围设备的映射关系,所述寄存器的第二排除内存范围的地址和所述第二外围设备的第二排除内存范围的地址一一对应；所述输入输出内存管理单元页表用于响应所述第二外围设备的内存访问请求,以使得所述第二外围设备访问到目标内存地址。同时,本申请还提供一种处理装置和处理设备。(The application provides a processing method, comprising the following steps: if the input/output memory management unit is configured with a first excluded memory range of a register, establishing a mapping relation between the second excluded memory range of the register and a second peripheral device based on a second excluded memory range of the second peripheral device in a page table of the input/output memory management unit, wherein addresses of the second excluded memory range of the register correspond to addresses of the second excluded memory range of the second peripheral device one by one; the input output memory management unit page table is used for responding to a memory access request of the second peripheral device so that the second peripheral device can access a target memory address. Simultaneously, this application still provides a processing apparatus and treatment facility.)

1. A method of processing, comprising:

if the input/output memory management unit is configured with a first excluded memory range of a register, establishing a mapping relation between the second excluded memory range of the register and a second peripheral device based on a second excluded memory range of the second peripheral device in a page table of the input/output memory management unit, wherein addresses of the second excluded memory range of the register correspond to addresses of the second excluded memory range of the second peripheral device one by one;

the input output memory management unit page table is used for responding to a memory access request of the second peripheral device so that the second peripheral device can access a target memory address.

2. The method of claim 1, further comprising:

and if a memory access request sent by the second peripheral equipment is received, searching an input/output memory management unit page table corresponding to the second peripheral equipment based on the equipment identifier carried in the memory access request to obtain a target memory address to be accessed by the second peripheral equipment.

3. The method of claim 1, wherein the address of the first exclusive memory range of the register and the address of the first exclusive memory range of the first peripheral device are in one-to-one correspondence;

the page table of the i/o memory management unit stores only mapping relationships of excluded ranges of the registers and other peripheral devices except for mapping relationships of the first peripheral device and the first excluded memory range of the registers.

4. The method of claim 1, further comprising:

and if the input/output memory management unit does not configure the excluded memory range of the register, configuring the excluded memory range of the register according to a second excluded memory range of the second peripheral device.

5. The method of claim 1, prior to determining whether the input output memory management unit configures the excluded memory range of registers, further comprising:

in the starting process, inquiring the excluded memory range corresponding to each peripheral device in an input/output memory management unit description table of a high-level configuration and power management interface;

and if the search result has the excluded memory range corresponding to the peripheral equipment, configuring the excluded memory range of the register based on the excluded memory range of the first peripheral equipment searched in the search result.

6. The method of claim 1, further comprising:

and in the starting process, acquiring the page table of the input and output memory management unit representing the mapping relation between the excluded memory range and the equipment identifier.

7. A processing apparatus, comprising:

the judging unit is used for judging whether the input and output memory management unit is configured with the excluded memory range of the register or not;

the device comprises an establishing unit, a memory management unit and a memory management unit, wherein the establishing unit is used for establishing a mapping relation between a second excluded memory range of a register and a second peripheral device based on the second excluded memory range of the second peripheral device in a page table of the input and output memory management unit if the input and output memory management unit is configured with the first excluded memory range of the register, and addresses of the second excluded memory range of the register and addresses of the second excluded memory range of the second peripheral device are in one-to-one correspondence; the input output memory management unit page table is used for responding to a memory access request of the second peripheral device so that the second peripheral device can access a target memory address.

8. The apparatus of claim 7, further comprising:

and the searching unit is used for searching an input/output memory management unit page table corresponding to the second peripheral equipment based on the equipment identifier carried in the memory access request to obtain a target memory address to be accessed by the second peripheral equipment if the memory access request sent by the second peripheral equipment is received.

9. The apparatus of claim 7, the first exclusive memory range of addresses of the register and the first exclusive memory range of addresses of the first peripheral device are in one-to-one correspondence;

the page table of the i/o memory management unit stores only mapping relationships of excluded ranges of the registers and other peripheral devices except for mapping relationships of the first peripheral device and the first excluded memory range of the registers.

10. A processing device, comprising: the method comprises the following steps: a processor and a memory for storing a computer program capable of running on the processor,

wherein the processor is adapted to perform the steps of the method of any one of claims 1 to 6 when running the computer program.

Technical Field

The present application relates to a setting technology for excluding a memory range, and in particular, to a processing method, apparatus, and device.

Background

When the hardware of the Input/Output Memory Management Unit (IOMMU) is used for the translation of Direct Memory Access (DMA) or Input/Output (IO) addresses, only one excluded Memory range register can be configured, which means that it only supports one excluded Memory range defined by one peripheral device. When there are multiple excluded memory ranges defined by multiple peripherals under the same IOMMU hardware, a memory access failure problem occurs.

Disclosure of Invention

In view of the above, an aspect of the present application is to provide a processing method, including: if the input/output memory management unit is configured with a first excluded memory range of a register, establishing a mapping relation between the second excluded memory range of the register and a second peripheral device based on a second excluded memory range of the second peripheral device in a page table of the input/output memory management unit, wherein addresses of the second excluded memory range of the register correspond to addresses of the second excluded memory range of the second peripheral device one by one;

the input output memory management unit page table is used for responding to a memory access request of the second peripheral device so that the second peripheral device can access a target memory address.

In the above scheme, the method further comprises:

and if a memory access request sent by the second peripheral equipment is received, searching an input/output memory management unit page table corresponding to the second peripheral equipment based on the equipment identifier carried in the memory access request to obtain a target memory address to be accessed by the second peripheral equipment.

In the above scheme, the address of the first exclusion memory range of the register corresponds to the address of the first exclusion memory range of the first peripheral device one to one;

the page table of the i/o memory management unit stores only mapping relationships of excluded ranges of the registers and other peripheral devices except for mapping relationships of the first peripheral device and the first excluded memory range of the registers.

In the above scheme, the method further comprises:

and if the input/output memory management unit does not configure the excluded memory range of the register, configuring the excluded memory range of the register according to a second excluded memory range of the second peripheral device.

In the foregoing solution, before determining whether the input/output memory management unit configures an excluded memory range of a register, the method further includes:

in the starting process, inquiring the excluded memory range corresponding to each peripheral device in an input/output memory management unit description table of a high-level configuration and power management interface;

and if the search result has the excluded memory range corresponding to the peripheral equipment, configuring the excluded memory range of the register based on the excluded memory range of the first peripheral equipment searched in the search result.

In the above scheme, the method further comprises:

and in the starting process, acquiring the page table of the input and output memory management unit representing the mapping relation between the excluded memory range and the equipment identifier.

According to another aspect of the present application, there is provided a processing apparatus comprising:

the judging unit is used for judging whether the input and output memory management unit is configured with the excluded memory range of the register or not;

the device comprises an establishing unit, a memory management unit and a memory management unit, wherein the establishing unit is used for establishing a mapping relation between a second excluded memory range of a register and a second peripheral device based on the second excluded memory range of the second peripheral device in a page table of the input and output memory management unit if the input and output memory management unit is configured with the first excluded memory range of the register, and addresses of the second excluded memory range of the register and addresses of the second excluded memory range of the second peripheral device are in one-to-one correspondence; the input output memory management unit page table is used for responding to a memory access request of the second peripheral device so that the second peripheral device can access a target memory address.

In the above scheme, the method further comprises:

and the searching unit is used for searching an input/output memory management unit page table corresponding to the second peripheral equipment based on the equipment identifier carried in the memory access request to obtain a target memory address to be accessed by the second peripheral equipment if the memory access request sent by the second peripheral equipment is received.

In the above scheme, the address of the first exclusion memory range of the register corresponds to the address of the first exclusion memory range of the first peripheral device one to one;

the page table of the i/o memory management unit stores only mapping relationships of excluded ranges of the registers and other peripheral devices except for mapping relationships of the first peripheral device and the first excluded memory range of the registers.

According to a third aspect of the present application, there is provided a processing apparatus comprising: the method comprises the following steps: a processor and a memory for storing a computer program capable of running on the processor,

wherein the processor is configured to execute the steps of any one of the above processing methods when running the computer program.

According to the processing method, the processing device and the processing equipment, whether an input/output memory management unit is configured with an excluded memory range of a register or not is judged, and under the condition that the input/output memory management unit is configured with a first excluded memory range of the register, a mapping relation between a second excluded memory range of the register and second peripheral equipment is established in a page table of the input/output memory management unit based on a second excluded memory range of the second peripheral equipment, wherein addresses of the second excluded memory range of the register and addresses of the second excluded memory range of the second peripheral equipment are in one-to-one correspondence; in the subsequent processing process, responding the memory access request of the second peripheral equipment by using the input/output memory management unit page table so as to enable the second peripheral equipment to access the target memory address. Therefore, under the condition that the input/output memory management unit is configured with the excluded memory range of the register, the memory access request of other peripheral equipment is responded by using the mapping table representing the mapping relation between the excluded memory range and the peripheral equipment, and the plurality of excluded memory ranges of the register corresponding to the plurality of peripheral equipment can be supported, so that the memory access of the plurality of peripheral equipment can be simultaneously carried out.

Drawings

FIG. 1 is a first schematic flow chart of the treatment method of the present application;

FIG. 2 is a schematic diagram of the configuration of IOMMU page tables in the present application;

FIG. 3 is a second flow chart of the treatment method of the present application;

FIG. 4 is a schematic structural component diagram of a processing apparatus according to the present application;

fig. 5 is a schematic structural composition diagram of the processing apparatus in the present application.

Detailed Description

The technical solution of the present application is further described in detail with reference to the drawings and specific embodiments of the specification.

Fig. 1 is a schematic flow chart of a processing method in the present application, as shown in fig. 1, the method includes:

step 101, if an input/output memory management unit is configured with a first excluded memory range of a register, establishing a mapping relationship between a second excluded memory range of the register and a second peripheral device based on a second excluded memory range of the second peripheral device in a page table of the input/output memory management unit, wherein addresses of the second excluded memory range of the register correspond to addresses of the second excluded memory range of the second peripheral device one to one; the input output memory management unit page table is used for responding to a memory access request of the second peripheral device so that the second peripheral device can access a target memory address.

In this application, the method is mainly applied to an electronic device with a storage function, where an Input/Output Memory Management Unit (IOMMU) is configured in the electronic device, and the IOMMU has a Memory range register. In the process of starting up the electronic device, an Input/Output memory Management unit description table of an Advanced Configuration and Power Management Interface (ACPI) is generated through a Unified Extensible Firmware Interface (UEFI) or a Basic Input/Output System (BIOS), and in the process of starting up the electronic device, the IOMMU driver can query the excluded memory range corresponding to each peripheral device in the ACPI description table and obtain a search result; if the search result has an excluded memory range corresponding to at least one peripheral device, the IOMMU driver in the electronic device configures the excluded memory range of the memory range register based on the excluded memory range of the first peripheral device that is first found in the search result.

Here, the memory range configuration to the memory range register is primarily dependent on whether there is a defined memory exclusion range in the chip vendor's IOMMU system specification. If the IOMMU system plan does not define the memory exclusion range, the IOMMU driver will not configure the memory exclusion range of the memory range register for the peripheral device, and if the IOMMU system specification defines the memory exclusion range, the IOMMU driver will set the memory exclusion range of the memory range register according to the memory exclusion range defined in the system specification.

In this application, when the IOMMU drives the memory exclusion range of the peripheral device to be searched in the ACPI i/o memory management unit description table, if the search result has the memory exclusion ranges corresponding to the plurality of peripheral devices, the memory exclusion ranges corresponding to the plurality of peripheral devices may exist in a form of a table or a list.

In the present application, the IOMMU hardware is mainly used to map a virtual memory address to a physical memory address, so that the peripheral device can operate in a virtual memory environment. For example, the peripheral devices may be a disk array controller (RAID controller) and a Network card adapter (Network adapter). When the peripheral device performs memory addressing in the virtual memory of the electronic device, the IOMMU hardware may search for a physical memory address corresponding to the peripheral device within a memory exclusion range of a memory range register, and if the memory address to be translated by the peripheral device is within the memory exclusion range of the register, the IOMMU hardware does not perform any address translation. For example, Device 1 accesses memory address 'A', if it is in the memory range of this register, the IOMMU hardware will not perform any address translation while passing through the IOMMU hardware, i.e., the register will read memory with address 'A'. This eliminates the overhead of IOMMU hardware address translation.

In this application, the IOMMU hardware maintains an IOMMU page table that characterizes the mapping of peripheral devices to memory ranges. When the first excluded memory range is configured in the memory range register, if the ACPI description table has memory excluded ranges of other peripheral devices, the IOMMU driver may obtain an IOMMU page table representing a mapping relationship between the excluded memory range and the device identifier during a boot process, and map the memory excluded ranges of the other peripheral devices and the device identifier of the peripheral device into the IOMMU page table to establish a second excluded memory range and a third excluded memory range … … of the memory range register in the IOMMU page table.

Here, each IOMMU page table corresponds to a peripheral device, and a mapping relationship between a device identifier representing the peripheral device and a memory exclusion range of the peripheral device is stored in the IOMMU page table, wherein in the IOMMU page table, a physical address of the memory exclusion range of the memory range register and a virtual address of the memory exclusion range of the peripheral device are in an exclusive one-to-one correspondence relationship. For example, address "A" corresponds to address "A", and the target memory address of the target peripheral device can be conveniently found from the IOMMU table through one-to-one address mapping.

Here, if the excluded memory range of the memory range register configuration corresponds to the first peripheral device, the physical addresses of the first excluded memory range of the memory range register and the virtual addresses of the first excluded memory range of the first peripheral device are in exclusive one-to-one correspondence, while only the mapping relationships of the excluded ranges of the registers and other peripheral devices other than the mapping relationship of the first excluded memory range of the first peripheral device and the memory range register are stored in the IOMMU page table. Therefore, when the peripheral equipment accesses the memory, the equipment system can conveniently know which channel the target memory address is obtained from.

In this application, the IOMMU driver configures the IOMMU page table for each entry based on the excluded memory range of the peripheral device. For example, as shown in fig. 2, taking three levels of input/output (I/O) page tables and 4K physical pages as an example, assuming that the memory range occupies 8K, the index values of the first level page table are found according to the content values of the physical addresses of the clients, and each page directory entry corresponding to each index value is allocated, where the page directory entry points to the address of the next level I/O page table.

Here, there is one IOMMU page table per peripheral. Each IOMMU page table has a system physical address of the multi-level page table therein.

In this application, when a first peripheral device accesses a memory of the electronic device, the electronic device receives a memory access request of the first peripheral device, and if the IOMMU driver of the electronic device queries that an excluded memory range of the first peripheral device is configured in a memory range register of the IOMMU, when the electronic device receives the memory access request of the first peripheral device, an IOMMU hardware in the electronic device searches for a target memory address to be accessed by the first peripheral device based on the excluded memory range of the memory range register.

In this application, when a second peripheral device accesses a memory of the electronic device, the electronic device receives a memory access request of the second peripheral device, if the IOMMU hardware of the electronic device queries that an excluded memory range is configured in a memory range register of the IOMMU, when the electronic device receives the memory access request of the second peripheral device, the IOMMU hardware of the electronic device searches an IOMMU page table corresponding to the second peripheral device based on a device identifier carried in the memory access request, and obtains a target memory address to be accessed corresponding to the second peripheral device based on a mapping relationship between the device identifier and the excluded memory range in the IOMMU page table corresponding to the second peripheral device. In this way, it is ensured that a plurality of peripheral devices can operate normally without any system failure. Such that the range register supports a plurality of excluded memory ranges defined by a plurality of peripheral devices.

In this application, in the boot process of the device, if the memory range register of the IOMMU hardware is found not to be configured with the excluded memory range of the peripheral device, the IOMMU driver may configure the excluded memory range of the memory range register according to the excluded memory range of the peripheral device.

For example, if the IOMMU finds an excluded memory range for which the memory range register is not configured with a peripheral device, and the second peripheral device defines the excluded memory range in the ACPI description table, and the second peripheral device is the first found peripheral device in the ACPI description table, then the IOMMU configures the memory range register based on the excluded memory range of the second peripheral device.

Here, the physical address of the excluded memory range of the configured memory range register and the virtual address of the excluded memory range of the second peripheral device are in an exclusive one-to-one correspondence relationship.

In the present application, the purpose of the exclusion range register is to inform the IOMMU hardware that no address translation is required if address "" A "" is retrieved (i.e., no I/O page table lookup is used to find the corresponding physical address).

Here, the address translation is not performed, and represents an exclusive one-to-one address correspondence (e.g., address A-address A). However, if two PCIe devices define their own excluded memory range, this means that the excluded memory range of one PCIe device is overwritten (i.e., the excluded memory range of the excluded memory register configuration of the IOMMU hardware is overwritten). Therefore, one-to-one I/O page tables must be prepared to cover the excluded memory range to allow the IOMMU hardware to look through the page tables to find the corresponding address. Such as in fig. 2: guest Physical Address is 0x9f459000, System Physical Address is 0x9f 459000.

Fig. 3 is a schematic flow chart of a processing method in the present application, as shown in fig. 3, including:

step 301, search the exclusion memory range of the corresponding peripheral device in the ACPI description table.

That is, during system boot, the IOMMU driver retrieves the excluded memory range of the corresponding external device in the ACPI description table. The ACPI description table is automatically generated by UEFI/BIOS during the system boot process.

Step 302, determine if the corresponding peripheral device defines its own excluded memory range?

Here, this step is also performed during system boot. The specific definition depends on whether the chip vendor's IOMMU system specification has a configuration excluding memory ranges. If the peripheral device defines its excluded memory range, step 303 is performed, and if the peripheral device does not define an excluded memory range, step 305 is performed.

Step 303, determine if the memory range register is configured.

Here, this step is also performed during system boot. When the system specification of the peripheral device in the ACPI description table defines the excluded memory range, the IOMMU driver sets the excluded memory range of the memory range register according to the system specification of the peripheral device found first in the ACPI description table. If the peripheral device does not define the excluded memory range, the IOMMU driver will not set the excluded memory range of the memory range register.

If the memory range registers are configured, step 304 is performed, and if the memory range registers are not configured, step 306 is performed.

At step 304, IOMMU page tables associated with the peripheral are looked up.

Here, this step is also performed during the boot process. The IOMMIU driver will maintain IOMMU page tables.

Step 305, configuring the IOMMU page table for the tag map according to the retrieved excluded memory range.

Here, one IOMMU page table corresponds to one peripheral device, and the IOMMU page table stores a mapping relationship between a peripheral device other than the peripheral device corresponding to the excluded memory range for which the range register has been configured and an excluded memory address of the peripheral device, where the address of the excluded memory range stored in the IOMMU page and the excluded memory address of the peripheral device are in an exclusive one-to-one correspondence. So that the system finds the target memory address of the target peripheral in the IOMMU page table.

Step 306, configuring the memory range register according to the retrieved excluded memory range.

Here, when it is found that the memory range register is not configured, the memory range register is configured by using the excluded memory range of the peripheral device which is first found in the ACPI description table.

According to the scheme of the application, under the condition that the IOMMU is provided with a plurality of peripheral devices, if the memory range register of the IOMMU is configured, the excluded memory range and the device identification of other peripheral devices are mapped in the IOMMU page table, so that the IOMMU page table is utilized to respond to the memory access requests of other peripheral devices, the normal work of the peripheral devices cannot be influenced, and system faults cannot occur.

Fig. 4 is a schematic structural composition diagram of a processing apparatus according to the present application, as shown in fig. 4, including:

a determining unit 401, configured to determine whether the input/output memory management unit is configured with the excluded memory range of the register;

an establishing unit 402, configured to, when the memory management unit configures a first excluded memory range of a register, establish a mapping relationship between a second excluded memory range of the register and a second peripheral device in a page table of the input/output memory management unit based on the second excluded memory range of the second peripheral device, where addresses of the second excluded memory range of the register and addresses of the second excluded memory range of the second peripheral device are in one-to-one correspondence; the input output memory management unit page table is used for responding to a memory access request of the second peripheral device so that the second peripheral device can access a target memory address.

Here, the i/o memory management unit page table represents a mapping relationship between the excluded memory range and the device identifier, and is obtained during the device boot process.

Here, the apparatus further includes: a search unit 403;

the searching unit 403 is configured to, if a memory access request sent by the second peripheral device is received, search an input/output memory management unit page table corresponding to the second peripheral device based on a device identifier carried in the memory access request, so as to obtain a target memory address to be accessed by the second peripheral device.

Here, the address of the first exclusion memory range of the register and the address of the first exclusion memory range of the first peripheral device correspond one to one; the page table of the i/o memory management unit stores only mapping relationships of excluded ranges of the registers and other peripheral devices except for mapping relationships of the first peripheral device and the first excluded memory range of the registers.

Here, the search unit 403 is further configured to query, in the i/o memory management unit description table of the high-level configuration and power management interface, an excluded memory range corresponding to each peripheral device during the device boot process.

Here, the apparatus further includes: a configuration unit 404;

specifically, if the search result has the excluded memory range corresponding to the peripheral device, the configuration unit 404 configures the excluded memory range of the register based on the excluded memory range of the first peripheral device found in the search result.

And configuring the excluded memory range of the register according to a second excluded memory range of the second peripheral device if the input-output memory management unit does not configure the excluded memory range of the register.

At this time, the second peripheral device may refer to a peripheral device defined with an excluded memory range, which is found first in the ACPI description table.

It should be noted that: in the processing device provided in the above embodiment, when performing the information reminding, only the division of the program modules is exemplified, and in practical applications, the processing distribution may be completed by different program modules as needed, that is, the internal structure of the device may be divided into different program modules to complete all or part of the processing described above. In addition, the processing apparatus and the processing method provided by the above embodiments belong to the same concept, and specific implementation processes thereof are described in the method embodiments and are not described herein again.

An embodiment of the present application further provides a processing device, where the processing device includes: a processor and a memory for storing a computer program capable of running on the processor,

wherein the processor is configured to execute, when running the computer program: if the input/output memory management unit is configured with a first excluded memory range of a register, establishing a mapping relation between the second excluded memory range of the register and a second peripheral device based on a second excluded memory range of the second peripheral device in a page table of the input/output memory management unit, wherein addresses of the second excluded memory range of the register correspond to addresses of the second excluded memory range of the second peripheral device one by one;

the input output memory management unit page table is used for responding to a memory access request of the second peripheral device so that the second peripheral device can access a target memory address.

The processor is further configured to, when executing the computer program, perform: and if a memory access request sent by the second peripheral equipment is received, searching an input/output memory management unit page table corresponding to the second peripheral equipment based on the equipment identifier carried in the memory access request to obtain a target memory address to be accessed by the second peripheral equipment.

The address of the first exclusion memory range of the register corresponds to the address of the first exclusion memory range of the first peripheral device one by one;

the page table of the i/o memory management unit stores only mapping relationships of excluded ranges of the registers and other peripheral devices except for mapping relationships of the first peripheral device and the first excluded memory range of the registers.

The processor is further configured to, when executing the computer program, perform: and if the input/output memory management unit does not configure the excluded memory range of the register, configuring the excluded memory range of the register according to a second excluded memory range of the second peripheral device.

The processor is further configured to, when executing the computer program, perform: in the starting process, the page table of the advanced configuration and power management interface is inquired for the excluded memory range corresponding to each peripheral device;

and if the search result has the excluded memory range corresponding to the peripheral equipment, configuring the excluded memory range of the register based on the excluded memory range of the first peripheral equipment searched in the search result.

The processor is further configured to, when executing the computer program, perform: and in the starting process, acquiring the page table of the input and output memory management unit representing the mapping relation between the excluded memory range and the equipment identifier.

Fig. 5 is a schematic structural component diagram of a processing device in the present application, and the processing device 500 may be a mobile phone, a computer, a digital broadcast terminal, an information transceiver device, a game console, a tablet device, a medical device, an exercise device, a personal digital assistant, or the like. The processing apparatus 500 shown in fig. 5 comprises: at least one processor 501, memory 502, at least one network interface 504, and a user interface 503. The various components in the processing device 500 are coupled together by a bus system 505. It is understood that the bus system 505 is used to enable connection communications between these components. The bus system 505 includes a power bus, a control bus, and a status signal bus in addition to a data bus. For clarity of illustration, however, the various buses are labeled as bus system 505 in FIG. 5.

The user interface 503 may include a display, a keyboard, a mouse, a trackball, a click wheel, a key, a button, a touch pad, a touch screen, or the like, among others.

It will be appreciated that the memory 502 can be either volatile memory or nonvolatile memory, and can include both volatile and nonvolatile memory. Among them, the nonvolatile Memory may be a Read Only Memory (ROM), a Programmable Read Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a magnetic random access Memory (FRAM), a Flash Memory (Flash Memory), a magnetic surface Memory, an optical disk, or a Compact Disc Read-Only Memory (CD-ROM); the magnetic surface storage may be disk storage or tape storage. Volatile Memory can be Random Access Memory (RAM), which acts as external cache Memory. By way of illustration and not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), Enhanced Synchronous Dynamic Random Access Memory (Enhanced DRAM), Synchronous Dynamic Random Access Memory (SLDRAM), Direct Memory (DRmb Access), and Random Access Memory (DRAM). The memory 502 described in embodiments herein is intended to comprise, without being limited to, these and any other suitable types of memory.

The memory 502 in the embodiments of the present application is used to store various types of data to support the operation of the processing device 500. Examples of such data include: any computer programs for operating on the processing device 500, such as an operating system 5021 and application programs 5022; contact data; telephone book data; a message; a picture; video, etc. The operating system 5021 includes various system programs, such as a framework layer, a core library layer, a driver layer, and the like, for implementing various basic services and processing hardware-based tasks. The application 7022 may include various applications such as a Media Player (Media Player), a Browser (Browser), and the like, for implementing various application services. A program for implementing the method according to the embodiment of the present application may be included in the application 5022.

The method disclosed in the embodiments of the present application may be applied to the processor 501, or implemented by the processor 501. The processor 501 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 501. The Processor 501 may be a general purpose Processor, a Digital Signal Processor (DSP), or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, etc. The processor 501 may implement or perform the methods, steps, and logic blocks disclosed in the embodiments of the present application. A general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed in the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium located in the memory 502, and the processor 501 reads the information in the memory 502 and performs the steps of the aforementioned methods in conjunction with its hardware.

In an exemplary embodiment, the processing Device 500 may be implemented by one or more Application Specific Integrated Circuits (ASICs), DSPs, Programmable Logic Devices (PLDs), Complex Programmable Logic Devices (CPLDs), Field Programmable Gate Arrays (FPGAs), general purpose processors, controllers, Micro Controllers (MCUs), microprocessors (microprocessors), or other electronic components for performing the aforementioned methods.

In an exemplary embodiment, the present application further provides a computer readable storage medium, such as a memory 502, comprising a computer program, which is executable by a processor 501 of a processing device 500 to perform the steps of the aforementioned method. The computer readable storage medium can be Memory such as FRAM, ROM, PROM, EPROM, EEPROM, Flash Memory, magnetic surface Memory, optical disk, or CD-ROM; or may be a variety of devices including one or any combination of the above memories, such as a mobile phone, computer, tablet device, personal digital assistant, etc.

A computer-readable storage medium, on which a computer program is stored which, when executed by a processor, performs: if the input/output memory management unit is configured with a first excluded memory range of a register, establishing a mapping relation between the second excluded memory range of the register and a second peripheral device based on a second excluded memory range of the second peripheral device in a page table of the input/output memory management unit, wherein addresses of the second excluded memory range of the register correspond to addresses of the second excluded memory range of the second peripheral device one by one;

the input output memory management unit page table is used for responding to a memory access request of the second peripheral device so that the second peripheral device can access a target memory address.

The computer program, when executed by the processor, further performs: and if a memory access request sent by the second peripheral equipment is received, searching an input/output memory management unit page table corresponding to the second peripheral equipment based on the equipment identifier carried in the memory access request to obtain a target memory address to be accessed by the second peripheral equipment.

The address of the first exclusion memory range of the register corresponds to the address of the first exclusion memory range of the first peripheral device one by one;

the page table of the i/o memory management unit stores only mapping relationships of excluded ranges of the registers and other peripheral devices except for mapping relationships of the first peripheral device and the first excluded memory range of the registers.

The computer program, when executed by the processor, further performs: and if the input/output memory management unit does not configure the excluded memory range of the register, configuring the excluded memory range of the register according to a second excluded memory range of the second peripheral device.

The computer program, when executed by the processor, further performs: in the starting process, inquiring the excluded memory range corresponding to each peripheral device in the input and output memory management unit description table of the high-level configuration and power management interface;

and if the search result has the excluded memory range corresponding to the peripheral equipment, configuring the excluded memory range of the register based on the excluded memory range of the first peripheral equipment searched in the search result.

The computer program, when executed by the processor, further performs: and in the starting process, acquiring the page table of the input and output memory management unit representing the mapping relation between the excluded memory range and the equipment identifier.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or other forms.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

The methods disclosed in the several method embodiments provided in the present application may be combined arbitrarily without conflict to obtain new method embodiments.

Features disclosed in several of the product embodiments provided in the present application may be combined in any combination to yield new product embodiments without conflict.

The features disclosed in the several method or apparatus embodiments provided in the present application may be combined arbitrarily, without conflict, to arrive at new method embodiments or apparatus embodiments.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.