阅读说明：本技术 矩形波信号生成电路及开关电源 (Rectangular wave signal generating circuit and switching power supply ) 是由 行川敏正 于 2020-03-05 设计创作，主要内容包括：实施方式关于矩形波信号生成电路及开关电源。有关实施方式的矩形波信号生成电路具备锯齿波生成电路、第1检测器、第2检测器和PWM第1PWM信号输出电路。锯齿波生成电路检测锯齿波信号的电位超过底部电位的第1定时。第2检测器检测锯齿波信号的电位超过第1脉冲宽度指示电压信号的电位的第2定时。PWM第1PWM信号输出电路生成基于第1定时与第2定时之间的时间差的第1PWM信号。(The embodiment relates to a rectangular wave signal generating circuit and a switching power supply. A rectangular wave signal generating circuit according to an embodiment includes a sawtooth wave generating circuit, a 1 st detector, a 2 nd detector, and a PWM 1 st PWM signal output circuit. The sawtooth wave generation circuit detects the 1 st timing when the potential of the sawtooth wave signal exceeds the bottom potential. The 2 nd detector detects the 2 nd timing at which the potential of the sawtooth wave signal exceeds the potential of the 1 st pulse width indication voltage signal. The PWM 1 st PWM signal output circuit generates a 1 st PWM signal based on a time difference between the 1 st timing and the 2 nd timing.)

1. A rectangular wave signal generating circuit, wherein,

the disclosed device is provided with:

a sawtooth wave output circuit which generates and outputs a sawtooth wave signal synchronous with the clock signal;

a 1 st detector for detecting a 1 st timing at which the potential of the sawtooth wave signal exceeds a bottom potential;

a 2 nd detector for detecting a 2 nd timing at which the potential of the sawtooth wave signal exceeds the potential of the 1 st pulse width indication voltage signal; and

and a 1 st PWM signal output circuit for generating and outputting a 1 st PWM signal based on a time difference between the 1 st timing and the 2 nd timing.

2. The rectangular wave signal generating circuit according to claim 1,

the bottom potential is set based on a linear characteristic of the sawtooth wave signal, and a rising speed of a potential of the sawtooth wave signal exceeding the bottom potential is within a predetermined range.

3. The rectangular wave signal generating circuit according to claim 1,

the 1 st detector and the 2 nd detector are circuits having the same signal response time;

the limited minimum pulse width of the PWM signal is based on the signal response time of the 1 st PWM signal output circuit described above.

4. The rectangular wave signal generating circuit according to claim 1,

when the potential of the 1 st pulse width instruction voltage signal is lower than the bottom potential, the 1 st PWM signal output circuit sets the minimum pulse width of the PWM signal to 0.

5. The rectangular wave signal generating circuit according to claim 1,

the sawtooth wave generating circuit includes:

a 1 st sawtooth wave generating circuit for generating a 1 st sawtooth wave signal having a period which is a multiple of the clock signal; and

a 2 nd sawtooth wave generating circuit for generating a 2 nd sawtooth wave signal which is overlapped with the 1 st sawtooth wave signal in a linear range and has a phase difference of 180 degrees;

the 1 st detector detects the 1 st timing based on the 1 st sawtooth wave signal or the 2 nd sawtooth wave signal;

the 2 nd detector detects the 2 nd timing based on the 1 st sawtooth wave signal or the 2 nd sawtooth wave signal at which the 1 st timing is detected.

6. The rectangular wave signal generating circuit according to claim 5,

further comprises a 1 st selector for switching and selecting the 1 st sawtooth wave signal and the 2 nd sawtooth wave signal according to the period of the clock signal,

the 1 st detector detects the 1 st timing based on the sawtooth wave signal selected by the 1 st selector from among the 1 st sawtooth wave signal and the 2 nd sawtooth wave signal.

7. The rectangular wave signal generating circuit according to claim 5,

further comprises a 2 nd selector for switching and selecting the 1 st sawtooth wave signal and the 2 nd sawtooth wave signal according to the period of the clock signal,

the 2 nd detector detects the 2 nd timing based on the sawtooth wave signal selected by the 2 nd selector from among the 1 st sawtooth wave signal and the 2 nd sawtooth wave signal.

8. The rectangular wave signal generating circuit according to claim 5,

the display device further includes a 2 nd selector that switches and selects a linear range of the 1 st sawtooth wave signal and the 2 nd sawtooth wave signal according to a cycle of the clock signal, and outputs the sawtooth wave signal of a high straight line.

9. The rectangular wave signal generating circuit according to claim 8,

the 2 nd selector switches and selects the 1 st sawtooth wave signal and the 2 nd sawtooth wave signal based on the 1 st timing detected by the 1 st detector.

10. The rectangular wave signal generating circuit according to claim 6,

when the potential of the 1 st pulse width instruction voltage signal is larger than the maximum value of the sawtooth wave signal output by the 1 st selector, the 1 st PWM signal output circuit sets the Hi pulse width duty ratio, which is a high potential pulse width duty ratio in the PWM signal, to 100%.

11. The rectangular wave signal generating circuit according to claim 9,

the apparatus further includes a delay circuit for adjusting a time interval between the 1 st timing and the 2 nd timing.

12. The rectangular wave signal generating circuit according to claim 5,

further comprising a 2 nd selector for switching the ranges of the 1 st sawtooth wave signal and the 2 nd sawtooth wave signal according to the cycle of the clock signal and outputting the sawtooth wave signal,

and a 2 nd selector configured to select a range including a minimum value of the 1 st sawtooth wave signal or the 2 nd sawtooth wave signal when a pulse width of the 1 st PWM signal is less than a predetermined value, and select a linear range of the 1 st sawtooth wave signal or the 2 nd sawtooth wave signal when the pulse width of the 1 st PWM signal is greater than or equal to the predetermined value.

13. The rectangular wave signal generating circuit according to claim 5,

further provided with:

a 2 nd selector for switching ranges of the 1 st sawtooth wave signal and the 2 nd sawtooth wave signal according to a cycle of the clock signal and outputting the sawtooth wave signal; and

and an adjusting unit configured to adjust rising speeds of the 1 st sawtooth wave signal and the 2 nd sawtooth wave signal so that a difference between a timing at which the sawtooth wave signal output from the 2 nd selector reaches a predetermined upper potential and a timing at which the sawtooth wave signal reaches a maximum value becomes a constant value.

14. The rectangular wave signal generating circuit according to claim 1,

further provided with:

a 3 rd detector for detecting a 3 rd timing corresponding to a timing when the potential of the sawtooth wave signal and the potential of the 2 nd pulse width indication voltage signal coincide with each other; and

a 2 nd PWM signal output circuit for generating and outputting a 2 nd PWM signal corresponding to a time difference between the 1 st timing and the 3 rd timing,

the sawtooth wave generating circuit includes:

a 1 st sawtooth wave generating circuit for generating a 1 st sawtooth wave signal having a period which is a multiple of the clock signal; and

a 2 nd sawtooth wave generating circuit for generating a 2 nd sawtooth wave signal which is overlapped with the 1 st sawtooth wave signal in a linear range and has a phase difference of 180 degrees,

the 1 st detector detects the 1 st timing based on the 1 st sawtooth wave signal or the 2 nd sawtooth wave signal,

the 2 nd detector detects the 2 nd timing based on the 1 st sawtooth wave signal or the 2 nd sawtooth wave signal at the 1 st timing,

the 3 rd detector detects the 3 rd timing based on the 1 st sawtooth wave signal or the 2 nd sawtooth wave signal at which the 1 st timing is detected.

15. A switching power supply, wherein,

the disclosed device is provided with:

the rectangular wave signal generating circuit according to any one of claims 1 to 13;

a switching circuit unit connected to an input voltage, switching according to the 1 st PWM signal, and outputting a voltage having a pulse waveform;

a smoothing circuit unit that converts the voltage of the pulse waveform into a direct current and outputs an output voltage; and

and an error amplifier circuit for outputting the 1 st pulse width instruction voltage signal based on a potential difference between the output voltage and a reference potential.

16. A switching power supply for performing voltage step-up and step-down, wherein,

the disclosed device is provided with:

the rectangular wave signal generating circuit according to claim 14;

a 1 st switching element connected between an input power supply terminal and one end of the inductor and switched in accordance with the 1 st PWM signal;

a 2 nd switching element connected between the other end of the inductor and a ground potential, and switching according to the 2 nd PWM signal;

a capacitor connected between an output terminal and a ground potential, the other end of the inductor being connected to the output terminal that outputs an output voltage; and

and an error amplifier circuit for outputting the 1 st pulse width instruction voltage signal and the 1 st pulse width instruction voltage signal based on a potential difference between the output voltage and a reference potential.

Technical Field

The embodiment of the invention relates to a rectangular wave signal generating circuit and a switching power supply.

Background

With the increasing speed of computers and the increasing precision of electronically controlled motors, the requirements for the stability of output power supply voltage with respect to a constant voltage stabilizing power supply have become strict. At the same time, the required output current increases, and the demand for high efficiency also increases. For example, in recent computers, a stabilized power supply is required to output power of 1V and a maximum current of 60A from a 24V power supply. In addition, for the application of an electronically controlled motor, a power source is required which converts an input voltage over a wide range of 10 to 40V into, for example, 20V and a maximum current of 3A and stably outputs the converted voltage.

As a power supply for handling such relatively large power, a high-efficiency switching power supply is generally used. However, it is generally difficult to stably operate a switching power supply capable of performing voltage reduction with a high voltage reduction ratio of, for example, 1/10 or less, or a switching power supply capable of performing voltage increase and decrease with a large allowable input power supply voltage range.

Disclosure of Invention

The invention aims to provide a rectangular wave signal generating circuit and a switching power supply which can achieve both response characteristics and stability.

The rectangular wave signal generating circuit according to the present embodiment includes a sawtooth wave generating circuit, a 1 st detector, a 2 nd detector, and a 1 st PWM signal output circuit. The sawtooth wave output circuit generates and outputs a sawtooth wave signal synchronized with the clock signal. The 1 st detector detects the 1 st timing at which the potential of the sawtooth wave signal crosses the bottom potential. The 2 nd detector detects the 2 nd timing at which the potential of the sawtooth wave signal exceeds the potential of the 1 st pulse width indication voltage signal. The 1 st PWM signal output circuit generates a 1 st PWM signal based on a time difference between the 1 st timing and the 2 nd timing.

Drawings

Fig. 1 is a diagram showing a configuration example of a switching power supply according to embodiment 1.

Fig. 2 is an operation waveform diagram of the switching power supply according to embodiment 1.

Fig. 3 is a diagram showing a detailed configuration example of the sawtooth wave output circuit and the PWM circuit.

Fig. 4 is a diagram showing a configuration example of the switching power supply according to embodiment 2.

Fig. 5 is an operation waveform diagram of the switching power supply of embodiment 2.

Fig. 6 is a detailed configuration diagram of the sawtooth wave output circuit and the PWM circuit according to embodiment 2.

Fig. 7 is an operation waveform diagram of the switching power supply according to embodiment 2.

Fig. 8 is a diagram showing a configuration example of the switching power supply according to embodiment 3.

Fig. 9 is an operation waveform diagram of the switching power supply of embodiment 3.

Fig. 10 is a detailed configuration diagram of the sawtooth wave output circuit and the PWM circuit according to embodiment 3.

Fig. 11 is a detailed operation waveform diagram of the switching power supply according to embodiment 3.

Fig. 12 is a detailed configuration diagram of the sawtooth wave output circuit and the PWM circuit according to embodiment 4.

Fig. 13 is an operation waveform diagram of the switching power supply of embodiment 4.

Fig. 14 is a diagram showing a configuration example of the switching power supply according to embodiment 5.

Fig. 15 is an operation waveform diagram of the switching power supply according to embodiment 5.

Fig. 16 is a detailed configuration diagram of the high linearity sawtooth generator, buck PWM, and boost PWM of embodiment 5.

Detailed Description

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings attached to the present specification, the scale, the aspect ratio, and the like are exaggerated as appropriate for ease of illustration and understanding.

Fig. 1 is a diagram showing a configuration example of a switching power supply 100 according to embodiment 1. The switching power supply 100 is a device that controls an input power supply voltage Vin supplied from an input power supply and outputs an output power supply voltage VOUT from an output power supply voltage terminal VOUT. The ratio of the input power supply voltage Vin to the output power supply voltage Vout of the switching power supply 100 has a high step-down ratio of 10 to 1, for example. The switching power supply 100 may be used for a control computer, a steering motor, and the like constituting an automatic driving device of an automobile.

The switching power supply 100 includes a pwm (pulse Width modulation) circuit 1, a switching driver 2, an LC low-pass filter 3, a voltage divider 4, a reference voltage source 5, an error amplifier 6, a PCMP circuit (Phase Compensation circuit)7, a clock oscillator (CLK)8, a sawtooth wave generator 9, and a reference voltage source 10. The sawtooth generator 9 has a voltage detector 90, a reset control circuit 91, and a sawtooth generator 92. Fig. 1 also illustrates a clock signal Clk, a bottom potential Vbtm, a synchronous clock signal Clkx, a sawtooth wave signal Saw, a feedback signal Fb, a reference voltage Vref, an error signal Err, a duty ratio indicating voltage signal Vd, a reset signal Rst, a switching signal Sw, and a PWM signal Pwmp. Here, the sawtooth wave output circuit 9 is a circuit that outputs a sawtooth wave signal sawn having high linearity, and the rectangular wave signal generating circuit 200 according to the present embodiment is composed of the pulse width modulator 1 and the sawtooth wave generator 9 having high linearity.

The PWM circuit 1 receives the duty ratio designation voltage signal Vd, the sawtooth wave signal Saw, and the synchronous clock signal Clkx, and outputs a PWM signal Pwmp synchronized with the synchronous clock signal Clkx. The sawtooth wave signal sawn is a sawtooth wave having a higher potential than the bottom potential Vbtm and having linearity. In other words, the bottom potential Vbtm is set based on the linear characteristic of the sawtooth wave signal sawn having high linearity.

The PWM signal Pwmp is a rectangular wave. That is, the PWM circuit 1 sets the PWM signal Pwmp to Hi at the 1 st timing when the synchronous clock signal Clkx becomes Hi, and resets the PWM signal Pwmp to Low at the 2 nd timing when the potential of the sawtooth wave signal Saw becomes higher than the potential of the duty ratio designation voltage signal Vd. In this embodiment, the high potential is denoted by "Hi" and the Low potential is denoted by "Low".

The switch driver 2 receives the PWM signal Pwmp from the PWM circuit 1, and connects the input power source to the LC low-pass filter 3 with a low resistance when the PWM signal Pwmp is Hi. On the other hand, when the PWM signal Pwmp is Low, the ground power supply is connected to the LC Low-pass filter 3 with a Low resistance. That is, the switching driver 2 outputs the switching signal Sw having a pulse-like waveform to the LC low-pass filter 3 based on the PWM signal Pwmp. In this way, the Hi period of the PWM signal Pwmp corresponds to the on time of the switching operation of the switch driver 2. Thus, the output power supply voltage Vout decreases as the Hi period of the PWM signal Pwmp becomes shorter. The switch driver 2 corresponds to a switch circuit unit.

The LC low-pass filter 3 is constituted by an inductor 31 and a smoothing capacitor 32. The inductor 31 has one terminal connected to the switch driver 2 and the other terminal connected to the output terminal VOUT and one end of the smoothing capacitor 32. The other end of the smoothing capacitor 32 is connected to a ground power supply. Thus, the supplied potential is smoothed by the smoothing capacitor 32 and output as the output power supply voltage Vout. In this way, the LC low-pass filter 3 converts the switching signal Sw into a direct current, and outputs the output power supply voltage Vout. The LC low-pass filter 3 corresponds to a smoothing circuit unit.

The voltage divider 4 divides the output power supply voltage Vout to generate the feedback signal Fb.

The reference voltage source 5 outputs a reference voltage Vref.

The error amplifier 6 has an inverting differential input terminal to which the voltage divider 4 is connected, and a non-inverting differential input terminal to which the reference voltage source 5 is connected. That is, the error amplifier 6 inputs the feedback signal Fb to the inverting differential input terminal, inputs the reference voltage Vref to the non-inverting differential input terminal, amplifies the potential difference between the both, and outputs the error signal Err.

PCMP7 has an input terminal connected to error amplifier 6, and an output terminal connected to PWM circuit 1. Thus, the PCMP7 receives the error signal Err and outputs the duty ratio indicating voltage signal Vd. In addition, the error amplifying circuit is constituted by the voltage divider 4, the error amplifier 6, and the PCMP 7.

CLK8 generates clock signal CLK. The clock signal Clk is a rectangular wave signal of a certain period.

The sawtooth generator 9 generates a sawtooth signal Saw synchronized with the clock signal Clk.

The voltage detector 90 is connected to the sawtooth generator 92 at a non-inverting terminal, and connected to the reference voltage source 10 at an inverting terminal. Thus, the sawtooth signal sawn is input to the voltage detector 90 at the non-inverting terminal, and the bottom potential Vbtm from the reference voltage source 10 is input to the inverting terminal. The voltage detector 90 detects that the potential of the sawtooth wave signal sawn is lower than the bottom potential Vbtm, sets the synchronous clock signal Clkx to Low, and sets the synchronous clock signal Clkx to Hi when the potential of the sawtooth wave signal sawn is equal to or higher than the bottom potential Vbtm. Details of the voltage detector 90 will be described later.

The reset control circuit 91 is, for example, a flip-flop. The clock signal Clk is input to the clock input terminal CK, and the synchronous clock signal Clkx is input to the negative logic reset terminal R. The reset control circuit 91 acquires and stores the state of the input terminal D at the moment when the clock signal Clk becomes Hi, and outputs the state from the output terminal Q as the reset signal Rst. A signal of Hi is always input to the input terminal D. That is, the reset signal Rst output from the output terminal Q becomes Hi at the instant when the clock signal Clk becomes Hi. On the other hand, when the synchronous clock signal Clkx is Low, the reset control circuit 91 resets the internal state to Low, and outputs the state as the reset signal Rst. That is, the reset signal Rst output from the output terminal Q is a short signal having a Hi pulse width of Hi at the instant when the clock signal Clk becomes Hi and Hi pulse width of Low at the instant when the synchronous clock signal Clkx becomes Low.

The reset signal Rst is input to the sawtooth generator 92. The sawtooth generator 92 rapidly lowers the potential of the sawtooth signal Saw toward 0V at the instant when the reset signal Rst transitions to Hi. Then, if the reset signal Rst changes to Low, the sawtooth generator 92 increases the potential of the sawtooth signal Saw at a constant rate. The sawtooth generator 92 outputs the sawtooth signal sawn to the non-inverting input terminal of the voltage detector 90 and the PWM circuit 1. The detailed structure of the sawtooth generator 92 will be described later.

The reference voltage source 10 has a negative terminal connected to the ground power supply and a positive terminal connected to the inverting input terminal of the voltage detector 90. The reference voltage source 10 is represented by an ideal power source in the present embodiment, but any circuit may be used as long as it generates a bottom potential Vbtm of a constant voltage.

Fig. 2 is an operation waveform diagram of switching power supply 100 according to embodiment 1. The vertical axis shows an input power supply voltage Vin, an output power supply voltage Vout, a clock signal Clk, a sawtooth wave signal sawn, a duty ratio indicating voltage signal Vd, a bottom potential Vbtm, a synchronous clock signal Clkx, and a PWM signal Pwmp in this order from the top. The horizontal axis is time.

In other words, in the uppermost stage, the input power supply voltage Vin of the input power supply is indicated by a solid line, and the voltage waveform of the output power supply voltage Vout is indicated by a broken line.

The next stage represents the waveform of the clock signal Clk. The clock signal Clk is a rectangular wave signal having a constant period Hi as described above.

In the next stage, the sawtooth wave signal sawn is indicated by a solid line, the duty ratio indication voltage signal Vd is indicated by a broken line, and the bottom potential Vbtm of the sawtooth wave signal sawn is indicated by a dotted line. The sawtooth wave signal Saw is reset to the ground potential 0V at the instant when the clock signal Clk is switched to Hi, immediately after which the potential rises at a certain speed. The crossing point of the sawtooth wave signal sawn at a potential higher than the bottom potential Vbtm is denoted by "□", and the crossing point of the sawtooth wave signal sawn at a potential higher than the duty ratio designation voltage signal Vd is denoted by "●".

The synchronous clock signal Clkx is represented in the next section. The synchronous clock signal Clkx is a rectangular wave signal that becomes Hi when the potential of the sawtooth wave signal sawn is higher than the bottom potential Vbtm, that is, at the timing of the "□" mark, and becomes Low when the potential of the sawtooth wave signal sawn is lower than the bottom potential Vbtm.

The PWM signal Pwmp is shown in the bottom section. The PWM signal Pwmp becomes Hi at the timing when the synchronous clock signal Clkx is converted to Hi, and becomes Low when the potential of the sawtooth wave signal Saw is higher than the potential of the duty ratio designation voltage signal Vd (timing indicated by "●").

The input power supply voltage Vin of the input power supply changes from a very high state exceeding ten times the voltage of the output power supply voltage Vout to a substantially doubled voltage. On the other hand, the voltage of the output Vout is held at a constant voltage Vout set by the resistance-voltage division ratio of the voltage divider 4 and the reference voltage Vref generated by the reference voltage source 5.

At this time, the Hi pulse width duty ratio D of the PWM signal Pwmp becomes substantially equal to the ratio of the output power supply voltage Vout to the input power supply voltage Vin by the action of the feedback control loop as shown in expression (1).

In the waveform diagram of fig. 2, the Hi pulse width duty ratio D of the PWM signal Pwmp changes from a value lower than 10% to a value of approximately 50%. Here, attention is paid to the left side of the waveform diagram of fig. 2, that is, a case where the input power supply voltage Vin is very high with respect to the output power supply voltage Vout.

The switching frequency of the recent switching power supply 100 tends to increase from several hundred kHz to several MHz. Accordingly, the on state time of the switching operation becomes shorter from several tens of ns to several ns or less. In the switching power supply 100, the value of the output power supply voltage Vout is changed in accordance with the on time of the switching operation of the switching driver 2. Therefore, when the input power supply voltage Vin is extremely high with respect to the output power supply voltage Vout, it is important whether or not the switching operation of the switching driver 2 can be stably performed for an on time of several ns or less.

The linearity immediately after the start of the potential rise of the sawtooth wave signal Saw cannot be said to be good due to the influence of parasitic capacitance and the like. In the sawtooth wave signal sawn of the present embodiment shown in fig. 2, the waveform is blunted in the region below the bottom potential Vbtm, and the voltage rising speed is not constant. However, according to the switching power supply 100 of the present embodiment, the sawtooth wave is not used in this portion, but the sawtooth wave signal sawn is used after the potential becomes higher than the bottom potential Vbtm and the linearity becomes sufficiently good. This enables a stable switching operation with a short on time of several ns or less.

The state of good linearity of the sawtooth wave signal sawn means that the rising timing of the sawtooth wave signal coincides with the Hi conversion timing of the synchronous clock signal Clkx, and the voltage rising speed of the sawtooth wave signal sawn after the synchronous clock signal Clkx is converted to Hi is constant. In the present embodiment, the PWM signal Pwmp is generated using the difference between the Hi transition timing of the synchronous clock signal Clkx and the timing at which the potential of the sawtooth wave signal Saw is higher than the duty ratio designation voltage signal Vd. This allows the range of the sawtooth wave signal having poor linearity to be hidden, and generation control of the PWM signal Pwmp having very high definition can be stably performed.

If the PWM signal Pwmp is generated using a sawtooth wave signal with poor linearity, the output power supply voltage Vout becomes unstable. For example, if the synchronous clock signal Clkx is switched to Hi before the potential of the sawtooth wave signal sawn starts to rise, a problem occurs such that a short-time pulse disappears or the synchronous clock signal Clkx is fixed to the Hi state in one cycle.

When the rising speed of the sawtooth wave signal sawn is not constant, a problem occurs such as the switching pulse width periodically varying.

On the other hand, the voltage accuracy of the bottom potential Vbtm and the accuracy of the rising speed thereof are of little importance. This is because, even if the bottom potential Vbtm of the sawtooth wave signal sawn slightly deviates from an assumed value, the voltage of the error signal Err of the error amplifier 6 is automatically adjusted by the action of the feedback control loop, and the variation with respect to the output power supply voltage Vout is suppressed.

Even if the rising speed of the voltage of the sawtooth wave signal Saw slightly deviates from an assumed value, the response time to the load fluctuation varies in proportion thereto, and the influence on the output power supply voltage Vout is slight.

Fig. 3 is a diagram showing a detailed configuration example of the sawtooth generator 9 and the PWM circuit 1.

The voltage detector 90 of the sawtooth generator 9 has a comparator 98 and a synchronous clock delay circuit (delay) 911. Further, the sawtooth wave generator 92 has a constant current source 94, an adjustment capacitor 95, and a reset N-type MOS transistor 96. Furthermore, the PWM circuit 1 has a comparator 11 and a flip-flop 12. In addition, the flip-flop 12 corresponds to the 1 st PWM signal output circuit, the comparator 98 corresponds to the 1 st detector, and the comparator 11 corresponds to the 2 nd detector.

Also illustrated in fig. 3 are a clock signal Clk, a bottom potential Vbtm, a synchronous clock signal Clkx, a sawtooth wave signal Saw, a constant current Isaw, a current control signal Sisaw, a duty ratio indicating voltage signal Vd, a reset signal Rst, a PWM reset signal Rn. The reference voltage source 10 and the voltage detector 90 may be provided outside the sawtooth wave generator 9.

The constant current source 94 is controlled by a current control signal Sisaw to output a constant current Isaw. A constant current source 94 is connected to one terminal of the adjustment capacitor 95, and a ground power supply is connected to the other terminal.

When the reset signal Rst is Hi, the sawtooth wave signal reset N-type MOS transistor 96 turns on the source terminal and the drain terminal. On the other hand, when the reset signal Rst is Low, the source terminal and the drain terminal are in a non-conductive state.

When the synchronous clock signal Clkx outputted from the synchronous clock delay circuit (delay)911 is Low, the reset signal Rst is Low, and therefore the adjustment capacitor 95 having the capacitance value Csaw is charged by the charging current Isaw flowing through the constant current source 94. Accordingly, the potential Vsaw of the sawtooth signal Saw increases at a constant rate Vsaw/dt as shown in equation (2).

When the reset signal Rst is Hi, the adjustment capacitor 95 is discharged by the sawtooth signal reset N-type MOS transistor 96. Thereby, the potential of the sawtooth wave signal sawn rapidly decreases toward the ground power supply potential 0V.

The bottom potential Vbtm is input to an inverting input terminal of the comparator 98, and the sawtooth wave signal sawn is input to a non-inverting input terminal thereof. The sawtooth wave synchronous clock output signal Clkx is output from the output terminal of the comparator 98 via the synchronous clock delay circuit 911. As described above, the comparator 98 sets the synchronous clock signal Clkx to Low when the potential of the sawtooth wave signal sawn is lower than the bottom potential Vbtm, and sets Hi when the potential is other than Low.

As described above, the reset control circuit 91 receives the synchronous clock signal Clkx and sets the synchronous clock signal Clkx to Low, and sets the reset signal Rst to Low. That is, if the synchronous clock signal Clkx becomes Low, the adjustment capacitor 95 is discharged, and the potential thereof becomes lower than the bottom potential Vbtm, and the potential drop of the sawtooth wave signal sawn automatically stops. However, the potential of the sawtooth wave signal Saw is lowered to substantially 0V, which is the ground potential, by the delay generated in the comparator 98 and the synchronous clock delay circuit 911.

The comparator 11 has a pulse width designation voltage signal Vd input to its non-inverting input terminal and a sawtooth wave signal sawn input to its inverting input terminal. When the potential of the sawtooth wave signal Saw is lower than the potential of the pulse width designation voltage signal Vd, the comparator 11 sets the PWM reset signal Rn output as Hi, and otherwise sets Low. That is, the timing at which the PWM reset signal Rn transitions to Low corresponds to the 2 nd timing.

The synchronous clock signal Clkx is input to the clock input terminal CK of the flip-flop 12, and the PWM reset signal Rn output from the comparator 11 is input to the negative logic reset terminal R thereof. At the moment when the synchronous clock signal Clkx becomes Hi, the flip-flop 12 internally stores the state of the input terminal D and outputs the state to the output terminal Q. The signal Hi is always input to the input terminal D. That is, at the moment when the synchronous clock signal Clkx becomes Hi, the PWM signal Pwmp output from the output terminal Q becomes Hi.

On the other hand, when the PWM reset signal Rn is Low, the flip-flop 12 resets the internal state to Low and outputs the state. That is, the PWM signal Pwmp output from the output terminal Q becomes Low. In this way, the flip-flop 12 generates the PWM signal Pwmp based on the time difference between the 1 st timing corresponding to the timing at which the potential of the sawtooth wave signal sawn detected by the comparator 98 exceeds the potential of the bottom potential Vbtm and the 2 nd timing corresponding to the timing at which the potential of the sawtooth wave signal sawn detected by the comparator 11 exceeds the potential of the 1 st pulse width indication voltage signal Vd.

Further, when the PWM reset signal Rn is Low, the flip-flop 12 resets its internal state to Low. The reset action is asynchronous and takes precedence over the fetch action described above. That is, when the potential of the pulse width control voltage signal Vd is lower than the bottom potential Vbtm, the flip-flop 12 ignores the synchronous clock signal Clkx and keeps the PWM signal Pwmp Low even if it is switched to Hi.

In a general switching power supply, a clock signal and a reset signal are input to an asynchronous RS latch, and a PWM signal Pwmp is generated. At this time, if the timings of the clock signal and the reset signal are shifted slightly, the PWM signal Pwmp is not generated, but rather, a problem occurs in that the clock signal and the reset signal are held at Hi in one cycle.

In a normal switching power supply, a potential of the sawtooth wave signal Saw is compared with the pulse width designation voltage signal Vd by one comparator to generate the PWM signal Pwmp. Therefore, there is a limit to the response speed of the comparator, and it is not possible to respond to an instantaneous operation of several tens of ns or less of the input signal. For example, under the condition that the potential of the sawtooth wave signal Saw is lower than the potential of the pulse width indicating voltage signal Vd only momentarily, the PWM comparator cannot respond, and the PWM reset signal Rn is fixed at Low.

In this way, in a normal switching power supply, the minimum pulse width of the PWM signal Pwmp is limited to the response speed of the comparator, and is several tens of ns. If a PWM signal Pwmp of a pulse width below that is desired, the PWM signal Pwmp is fixed at Low. Thus, it is difficult to output a stable voltage.

In contrast, in the switching power supply 100 according to the present embodiment, 2 comparators, i.e., the comparator 11 and the comparator 98, are used. The comparator 11 detects the timing at which the potential of the sawtooth wave signal sawn exceeds the potential of the pulse width designation voltage signal Vd, and outputs the PWM reset signal Rn. On the other hand, the comparator 98 detects the timing at which the potential of the sawtooth wave signal sawn exceeds the potential of the bottom potential Vbtm, and outputs the synchronous clock signal Clkx. Here, the feature is that the states of the PWM reset signal Rn and the synchronous clock signal Clkx are switched without fail every switching period.

Further, it is assumed that circuits having the same characteristics are used in the comparator 11 and the comparator 98. More specifically, the comparator 11 and the comparator 98 use circuits having the same signal response time. Thus, the delay occurring when the timing at which the potential of the sawtooth wave signal sawn generated by the comparator 98 exceeds the potential of the bottom potential Vbtm is detected is equal to the delay occurring when the timing at which the potential of the sawtooth wave signal sawn generated by the comparator 11 exceeds the potential of the pulse width designation voltage signal Vd. Therefore, by obtaining a time difference of 2 timings, 2 detection delays can be cancelled out. In particular, when the potential of the pulse width indicating voltage signal Vd is substantially equal to the potential of the sawtooth bottom signal Btm, the timing difference between the PWM reset signal Rn and the synchronous clock signal Clkx becomes very small, but even the PWM signal Pwmp having the very small pulse width (even the pulse width of 0.1ns or less) may be generated.

Thus, the limit of the pulse width of the PWM signal Pwmp is limited by the response speed of the flip-flop 12. The signal response time of the flip-flop 12 is less than 1ns, several tens of times faster than that of the comparator. Therefore, the limit of the pulse width of the PWM signal Pwmp is shortened to 1/several tenths of a minute as compared with a normal switching power supply limited by the signal response time of the comparator.

As described above, in the switching power supply 100 according to the present embodiment, the comparator 98 detects the 1 st timing corresponding to the timing when the potential of the sawtooth wave signal Saw exceeds the potential of the bottom potential Vbtm, the comparator 11 detects the 2 nd timing corresponding to the timing when the potential of the sawtooth wave signal Saw exceeds the potential of the pulse width command voltage signal Vd, and the flip-flop 12 generates the PWM signal Pwmp based on the timing difference. This makes it possible to use a range in which the linearity of the sawtooth wave signal Saw is stable, and to stably shorten the Hi pulse width of the PWM signal Pwmp based on the timing difference to a range in which the response speed of the flip-flop 12 is of the order of magnitude. By generating the PWM signal Pwmp of the short pulse width in a stable manner in this way, it is possible to provide the switching power supply for voltage reduction having a high step-down ratio of the output power supply voltage Vout to the input power supply voltage Vin, which is equal to or less than 1/10.

Further, when the potential of the pulse width designation voltage signal Vd is lower than the bottom potential Vbtm, the flip-flop 12 ignores even if the synchronous clock signal Clkx transitions to Hi, and keeps the PWM signal Pwmp Low. Thus, the duty ratio of the PWM signal Pwmp is 0, and the output power supply voltage Vout can be maintained at 0V.

(embodiment 2)

The switching power supply 100 according to embodiment 2 is a step-down switching power supply capable of stably outputting an output power supply voltage Vout having a high voltage substantially equal to an input power supply voltage Vin. The main structure is as follows. The sawtooth wave generating circuit 9 generates a 1 st sawtooth wave signal and a 2 nd sawtooth wave signal which are 180 degrees out of phase with each other and have a double period with respect to the clock signal Clk, the comparator 11 detects a timing when the potential Vd exceeding the pulse width indication voltage signal is detected for one sawtooth wave signal, and the comparator 98 detects a timing when the potential Vbtm exceeding the bottom potential is detected for the other sawtooth wave signal as a timing when the 2 sawtooth wave signals are switched. Thus, the Low pulse width (the difference between the timing of exceeding the potential Vd and the timing of switching 2 sawtooth wave signals) at the time of generating the maximum width of the PWM signal Pwmp is stably reduced to the order of the response speed of the flip-flop 12. Hereinafter, differences from the switching power supply 100 according to embodiment 1 will be described.

Fig. 4 is a diagram showing a configuration example of the switching power supply 100 according to embodiment 2. The switching power supply 100 according to embodiment 2 includes a PWM circuit 1, a switching driver 2, an LC low-pass filter 3, a voltage divider 4, a reference voltage source 5, an error amplifier 6, a PCMP circuit 7, CLK8, and a sawtooth generator 9.

The sawtooth wave generator 9 has a voltage detector 90a, a reset control circuit 91a, a 1 st sawtooth wave generator 92a, a 2 nd sawtooth wave generator 92b, and a selector 912. Fig. 4 also shows a clock signal Clk, a synchronous clock signal Clkx, a 1 st sawtooth wave signal Saw0, a 2 nd sawtooth wave signal Saw1, a 1 st reset signal Rst0, a 2 nd reset signal Rst1, a sawtooth wave signal Saw, a duty indication voltage signal Vd, a phase signal Phip, a selection signal Phipx, a 1 st reset signal Rst0, a 2 nd reset signal Rst1, a switching signal Sw, a PWM signal Pwmp, a reference voltage Vref, and an error signal Err. In addition, the 1 st sawtooth wave generator 92a corresponds to a 1 st sawtooth wave generation circuit, and the 2 nd sawtooth wave generator 92b corresponds to a 2 nd sawtooth wave generation circuit.

The voltage detector 90a outputs a synchronous clock signal Clkx. The synchronous clock signal Clkx is switched to Hi at the instant when the potential of the 1 st sawtooth wave signal Saw0 or the 2 nd sawtooth wave signal Saw1 selected by the phase signal Phip obtained by dividing the clock signal Clk becomes higher than the bottom potential Vbtm, and is switched to Low at the instant when the clock signal Clk is switched to Hi. Further, the voltage detector 90a outputs the selection signal Phipx. The selection signal Phipx is a rectangular wave signal having a period of twice the clock signal Clk and alternately switched to the Hi state and the Low state at the timing of switching the synchronous clock signal Clkx to Hi.

The reset control circuit 91a is connected to CLK8, and generates a phase signal Phip obtained by dividing the clock signal CLK, a 1 st reset signal Rst0, and a 2 nd reset signal Rst1 whose phase is delayed by 180 ° from that of the 1 st reset signal Rst 0.

The 1 st sawtooth wave generator 92a generates a 1 st sawtooth wave signal Saw0 of a period which is a multiple of the clock signal Clk based on the 1 st reset signal Rst 0. The 2 nd sawtooth wave generator 92b generates a 2 nd sawtooth wave signal Saw1 having a phase delayed by 180 with respect to the 1 st sawtooth wave signal Saw0 based on the 2 nd reset signal Rst 1.

The selector 912 selects the 1 st sawtooth wave signal Saw0 when the state of the selection signal Phipx is Low, and conversely selects the 2 nd sawtooth wave signal Saw1 when the state is Hi, and outputs the signal as the sawtooth wave signal Saw. That is, the selector 912 switches and selects the linear ranges of the 1 st sawtooth wave signal Saw0 and the 2 nd sawtooth wave signal Saw1 at the 1 st timing when the potential of the sawtooth wave signal Saw exceeds the bottom potential Vbtm, and outputs the sawtooth wave signal Saw having the same period as the clock signal Clk. In addition, the selector 912 corresponds to the 2 nd selector.

Fig. 5 is an operation waveform diagram of switching power supply 100 according to embodiment 2. The vertical axis shows an input power supply voltage Vin, an output power supply voltage Vout, a clock signal Clk, a top voltage Vtop, a sawtooth wave signal Saw, a duty ratio designation voltage signal Vd, a bottom potential Vbtm, a synchronous clock signal Clkx, and a PWM signal Pwmp in this order from the top. The horizontal axis is time.

In other words, in the uppermost stage, the voltage waveform of the input power supply voltage Vin is indicated by a solid line, and the voltage waveform of the output power supply voltage Vout is indicated by a broken line. The next stage represents the waveform of the clock signal Clk.

In the next stage, the top voltage Vtop is indicated by a dotted line, the sawtooth wave signal sawn is indicated by a solid line, the duty ratio designation voltage signal Vd is indicated by a dotted line, and the bottom potential Vbtm of the sawtooth wave signal sawn is indicated by a dotted line. In the next paragraph, the synchronous clock signal Clkx is represented by a solid line. The PWM signal Pwmp is shown in the bottom section.

The input power supply voltage Vin of the input power supply changes from a voltage multiplied by the output power supply voltage Vout to substantially the same voltage. On the other hand, the output power supply voltage Vout is held at a constant voltage Vout set by the resistance-voltage division ratio of the voltage divider 4 and the reference voltage Vref generated by the reference voltage source 5.

Here, the Hi pulse width duty ratio D of the PWM signal Pwmp becomes substantially equal to the ratio of the output power supply voltage Vout to the input power supply voltage Vin of the input power supply, as shown in expression (1), by the action of the feedback control loop. Thus, the Hi pulse width duty ratio D of the PWM signal Pwmp changes from, for example, 50% to substantially 100%.

The voltage of the sawtooth wave signal sawn is instantaneously reset from the top potential Vtop to the bottom potential Vbtm at the timing when the synchronous clock signal Clkx is converted to Hi, and immediately thereafter, rises at a constant speed.

When the input power supply voltage Vin drops to be substantially equal to the output power supply voltage Vout, the timing at which the sawtooth wave signal Saw is reset needs to be made to coincide with the Hi transition timing of the synchronous clock signal Clkx in order to output a stable output power supply voltage Vout. Further, it is necessary to keep the voltage rising speed of the sawtooth wave signal constant in the vicinity of the top potential Vtop.

As the waveform diagram of fig. 5 becomes closer to the right side, that is, as the input power supply voltage Vin of the input power supply decreases, the duty ratio of the PWM signal Pwmp becomes larger. In a state where the input power supply voltage Vin and the output power supply voltage Vout are substantially equal to each other, the off-state period of the switching operation becomes shorter from several tens of ns to several ns or less, and finally becomes a 100% duty ratio. Here, if the reset timing of the sawtooth wave signal is out of synchronization with the synchronous clock signal Clkx, the pulse disappears (a phenomenon in which the duty ratio becomes 0%) or the pulse width becomes unstable. For example, a phenomenon of irregular fluctuation occurs. In either case, the output power supply voltage Vout becomes unstable, which is a serious problem.

On the other hand, the accuracy of the voltage of the top voltage Vtop in the sawtooth wave signal Saw and the accuracy of the average value of the rising speed in the sawtooth wave signal Saw have little influence on the stability of the output power supply voltage Vout. This is because even if the top voltage Vtop is slightly deviated from an assumed value, the voltage of the error signal Err of the error amplifier 6 is automatically adjusted by the action of the feedback control loop, and the variation with respect to the output power supply voltage Vout is suppressed. Even if the average value of the rising speed of the voltage Vsaw of the sawtooth wave signal sawn slightly deviates from an assumed value, the response time varies to the extent of the load variation, and the influence of the output power supply voltage Vout is slight.

Fig. 6 is a diagram showing a detailed configuration example of the sawtooth generator 9 and the PWM circuit 1 according to embodiment 2.

The sawtooth generator 9 includes a voltage detector 90a, a reset control circuit 91a, a 1 st sawtooth generator 92a, a 2 nd sawtooth generator 92b, and a selector 912. The voltage detector 90a may be provided outside the sawtooth wave generator 9.

The voltage detector 90a includes a comparator 98, a bottom potential detection selector 99, a selection signal flip-flop 910, and a synchronous clock delay circuit 911.

The reset control circuit 91a has an input signal frequency divider 915, a reset signal generator 916, a 1 st reset signal generator 9160, and a 2 nd reset signal generator 9161.

The 1 st sawtooth wave generator 92a has a 1 st constant current source 940, a 1 st adjusting capacitor 950, and a 1 st sawtooth wave signal reset N-type MOS transistor 960.

The 2 nd sawtooth generator 92b has a 2 nd constant current source 941, a 2 nd adjusting capacitor 951, and a 2 nd signal reset N-type MOS transistor 961. Also illustrated in fig. 6 are a constant current Isaw, a current control signal Sisaw, a 1 st reset signal Rst0, a 2 nd reset signal Rst1, a 1 st sawtooth wave signal Saw0, a 2 nd sawtooth wave signal Saw1, a sawtooth wave signal Saw, a duty indicating voltage signal Vd, a PWM reset signal Rn, a phase signal Phip, a selection signal Phipx, a reset signal Rst, a clock signal Clk, a bottom potential Vbtm, a synchronous clock signal Clkx, a constant current Isaw, a current control signal Sisaw, and a PWM reset signal Rn.

First, the details of the reset control circuit 91a will be described.

The input signal divider 915 is, for example, a flip-flop, and the clock signal Clk is input to the clock input terminal CK, and the inverted signal of the phase signal Phip output from the input terminal D is input thereto. The input signal divider 915 takes and holds the inverted state of the phase signal Phip output by itself to the inside at the moment when the clock signal Clk becomes Hi, and changes the phase signal Phip to this state. Thus, the phase signal Phip becomes a square wave of a frequency halving of the clock signal Clk.

The reset signal generator 916 is, for example, a flip-flop, and a clock signal Clk is input to a clock input terminal CK, a synchronous clock signal Clkx output from the synchronous clock delay circuit 911 is input to a negative logic reset terminal R, and a signal of Hi is always input to an input terminal D. The reset signal generator 916 sets its internal state to Hi at the instant when the clock signal Clk becomes Hi, and sets the reset signal Rst to Hi to output. Further, the reset signal generator 916 resets the internal state to Low when the synchronous clock signal Clkx is Low, and sets the reset signal Rst to Low and outputs it.

When the phase signal Phip is Low, the 1 st reset signal generator 9160 outputs the state of the reset signal Rst as the 1 st reset signal Rst 0. Similarly, the 2 nd reset signal generator 9161 outputs the state of the reset signal Rst as the 2 nd reset signal Rst1 when the phase signal Phip is Hi. That is, when the phase signal Phip is Low, the 1 st reset signal Rst0 changes from Low to Hi and then to Low again in accordance with the state of the reset signal Rst. Alternatively, when the phase signal Phip is Hi, the 2 nd reset signal Rst1 changes from Low to Hi and then to Low again in accordance with the state of the reset signal Rst.

Next, the details of the voltage detector 90a will be described. The voltage detector 90a detects the 1 st timing at which the potential of the 1 st sawtooth wave signal Saw0 or the 2 nd sawtooth wave signal Saw1 selected by the phase signal Phip becomes higher than the bottom potential Vbtm, and outputs the synchronous clock signal Clkx and the selection signal Phipx.

The bottom potential detection selector 99 receives the 1 st sawtooth wave signal Saw0 at one input terminal and the 2 nd sawtooth wave signal Saw1 at the other input terminal. When the phase signal Phip is Low, the 1 st sawtooth wave signal Saw0 is selected, and when Hi, the 2 nd sawtooth wave signal Saw1 is selected and output to the non-inverting input terminal of the comparator 98. Here, the phase signal Phip is a divided-by-two signal of the clock signal Clk, and its state transitions at the timing at which the clock signal Clk transitions to Hi. That is, the bottom potential detection selector 99 alternately selects and outputs the 1 st sawtooth wave signal saf 0 or the 2 nd sawtooth wave signal saf 1.

The comparator 98 outputs Hi when the potential of the 1 st sawtooth wave signal Saw0 or the 2 nd sawtooth wave signal Saw1 input to the non-inverting input terminal is higher than the bottom potential Vbtm input to the inverting input terminal, and outputs Low in the other cases. That is, the output signal of the comparator 98 is a timing signal that is converted into Hi when the potential of the 1 st sawtooth wave signal Saw0 or the 2 nd sawtooth wave signal Saw1 exceeds the bottom potential Vbtm. The timing signal is input to the clock input terminal CK of the selection signal flip-flop 910 and the synchronous clock delay circuit 911.

The synchronous clock delay circuit 911 compensates for the delay generated in the selection signal flip-flop 910 and the selector 912 described later, and outputs the synchronous clock signal Clkx. The synchronous clock signal Clkx is input to the clock terminal CK of the flip-flop 12, and becomes the start point of the operation thereof. In other words, the synchronous clock delay circuit 911 adjusts the time interval between the 1 st timing, which is the time point when the high-linearity sawtooth wave signal Saw becomes higher than the bottom potential Vbtm, and the 2 nd timing, which is the time point when the sawtooth wave signal Saw exceeds the potential of the pulse width designation voltage signal Vd, to cancel the difference in the response speed of the circuit path.

The selection signal flip-flop 910 receives the timing signal output from the comparator 98 at its clock input terminal CK. At the moment when the timing signal is converted to Hi, the selection signal flip-flop 910 internally acquires the state of the phase signal Phip input to the data input terminal D, and outputs the state from the data output terminal Q as the selection signal Phipx. Thus, as described above, the selection signal Phipx is a rectangular wave signal divided by two with respect to the clock signal Clk, which changes its state at the timing when the potential of the 1 st sawtooth wave signal Saw0 or the 2 nd sawtooth wave signal Saw1 becomes higher than the bottom potential Vbtm.

Next, details of the 1 st sawtooth generator 92a and the 2 nd sawtooth generator 92b will be described.

The 1 st and 2 nd sawtooth wave generators 92a and 92b receive the 1 st and 2 nd reset signals Rst0 and Rst1, respectively, and output the 1 st and 2 nd sawtooth wave signals Saw0 and Saw1 divided by two with respect to the clock signal Clk and having phases different from each other by 180 °.

The 1 st constant current source 940 is controlled by the current control signal Sisaw to output a constant charging current Isaw. The 1 st constant current source 940 is connected to one terminal of the 1 st adjustment capacitor 950, and the ground power supply is connected to the other terminal.

The 1 st sawtooth wave signal reset N-type MOS transistor 960 has a gate to which a 1 st reset signal Rst0 is input. When the 1 st reset signal Rst0 is Hi, the 1 st sawtooth signal reset N-type MOS transistor 960 is turned on between the source terminal and the drain terminal. On the other hand, when the 1 st reset signal Rst0 is Low, the source terminal and the drain terminal are in a non-conductive state.

When the 1 st reset signal Rst0 is Hi, the 1 st adjustment capacitor 950 is discharged, and the potential of the sawtooth wave signal sawn rapidly decreases toward the ground power supply potential 0V, and is reset to the ground power supply potential 0V. On the other hand, when the 1 st reset signal Rst0 is Low, the 1 st adjustment capacitor 950 is charged by the charging current Isaw flowing through the 1 st constant current source 940. The potential of the 1 st adjustment capacitor 950 is output to the selector 912 as a 1 st sawtooth signal Saw 0. The potential rising speed of the 1 st sawtooth wave signal Saw0 can be set by the values of the charging current Isaw and the capacitance Csaw of the 1 st adjustment capacitor 950.

The 2 nd sawtooth generator 92b has the same configuration as the 1 st sawtooth generator 92 a. The 2 nd constant current source 941 is controlled by the current control signal Sisaw to output the charging current Isaw. A 2 nd constant current source 941 is connected to one terminal of the 2 nd adjustment capacitor 951, and a ground power supply is connected to the other terminal.

The 2 nd signal reset N-type MOS transistor 961 has a gate to which a 2 nd reset signal Rst1 is connected. When the 2 nd reset signal Rst1 is Hi, the 2 nd signal reset N-type MOS transistor 961 is turned on between the source terminal and the drain terminal. On the other hand, when the 2 nd reset signal Rst1 is Low, the source terminal and the drain terminal are in a non-conductive state.

When the 2 nd reset signal Rst1 is Hi, the 2 nd adjustment capacitor 951 is discharged, and the potential of the sawtooth wave signal sawn rapidly decreases toward the ground power supply potential 0V, and is reset to the ground power supply potential 0V. On the other hand, when the 2 nd reset signal Rst1 is Low, the 2 nd adjustment capacitor 951 is charged by the charging current Isaw flowing through the 2 nd constant current source 941. The potential of the 2 nd adjustment capacitor 951 is output to the selector 912 as the 2 nd sawtooth signal Saw 1. The rate of increase in the potential of the 2 nd sawtooth signal Saw1 can be set by the values of the charging current Isaw and the capacitance Csaw of the 2 nd adjustment capacitor 951. In addition, if the 1 st and 2 nd reset signals Rst0 and Rst1 become Low, the 1 st and 2 nd signal reset N-type MOS transistors 960 or 961 end the reset operation. Due to the delay caused by the comparator 98 after the end of the reset operation, the potential of the reset 1 st or 2 nd sawtooth wave signal Saw0 or Saw1 reaches approximately the ground potential 0V.

The selector 912 selects the 1 st sawtooth wave signal Saw0 when the state of the selection signal Phipx is Low, and selects the 2 nd sawtooth wave signal Saw1 when the state is Hi, and outputs the signal as the sawtooth wave signal Saw. That is, the selector 912 alternately changes the selected sawtooth wave signal and outputs the signal at a timing when the potential of the 1 st sawtooth wave signal Saw0 or the 2 nd sawtooth wave signal Saw1 detected by the comparator 98 becomes higher than the bottom potential Vbtm. Thus, the sawtooth wave signal Saw output from the selector 912 has a constant voltage rise rate and high linearity.

Next, details of the PWM circuit 1 will be described.

The PWM circuit 1 receives a sawtooth wave signal Saw, a synchronous clock signal Clkx, and a pulse width indication voltage signal Vd. The PWM circuit 1 outputs a PWM signal Pwmp corresponding to the pulse width indication voltage signal Vd.

The comparator 11 receives the pulse width designation voltage signal Vd at the non-inverting input terminal and receives the sawtooth wave signal sawn at the inverting input terminal. The comparator 11 outputs to the flip-flop 12a PWM reset signal Rn, which is Hi when the potential of the sawtooth wave signal Saw is Low relative to the potential of the pulse width designation voltage signal Vd and Low when the potential is other than the Low. Specifically, the comparator 11 detects the 2 nd timing when the sawtooth wave signal sawn exceeds the potential of the pulse width command voltage signal Vd, and generates the PWM reset signal Rn. In addition, the comparator 11 maintains the PWM reset signal Rn at Hi when the potential of the pulse width direction voltage signal Vd is higher than the potential of the top voltage Vtop.

The flip-flop 12 receives the synchronous clock signal Clkx at its clock input terminal CK, the PWM reset signal Rn output from the comparator 11 at the negative logic reset terminal R, and a signal always in the Hi state at the data terminal D. Flip-flop 12 sets its internal state to Hi at the instant when synchronous clock signal Clkx is converted to Hi, and outputs the state thereof from data output terminal Q as PWM signal Pwmp.

When the PWM reset signal Rn is Low, the flip-flop 12 resets the internal state to Low, and outputs the state to the PWM signal. Thus, the Hi pulse width of the PWM signal Pwmp changes in accordance with the potential of the pulse width designation voltage signal Vd. Here, when the potential of the pulse width designation voltage signal Vd is higher than the potential of the top voltage Vtop, the state of the PWM reset signal Rn is maintained at Hi and is not Low. Thus, the duty ratio of the PWM signal Pwmp becomes 100%.

In the present embodiment, the sawtooth wave signal Saw is generated by the switching operation of the selector 912. The selector 912 may be constituted by a simple MOS transistor-based changeover switch. The operation is faster than the operation of resetting the 1 st and 2 nd adjustment capacitors 950 and 951 by discharging the 1 st and 2 nd adjustment capacitors 960 and 961 by the 1 st and 2 nd signal reset N-type MOS transistors.

The linearity of the sawtooth wave signal sawn generated by the switching operation of the selector 912 is high particularly near Vtop. Therefore, when the potential of the pulse width indicating voltage signal Vd is substantially the same as the top potential Vtop, the comparator 11 can output the PWM reset signal Rn having a very short Low pulse width (for example, a Low pulse width of 1ns or less).

Further, as described above, since the timing at which the synchronous clock signal Clkx is switched to Hi is generated by the comparator 98 having the same electrical characteristics as the comparator 11, the delay caused by both is cancelled, and the deviation of the timing is suppressed. Further, the synchronous clock delay circuit 911 can adjust the timing margin.

Fig. 7 is an operation waveform diagram of switching power supply 100 according to embodiment 2. The clock signal Clk, the phase signal Phip, the 1 st reset signal Rst0, the 2 nd reset signal Rst1, the top voltage Vtop, the 1 st sawtooth wave signal Saw0, the 2 nd sawtooth wave signal Saw1, the bottom potential Vbtm, the synchronous clock signal Clkx, the top voltage Vtop, the sawtooth wave signal Saw, the duty ratio indicating voltage signal Vd, the bottom potential Vbtm, the PWM reset signal Rn, and the PWM signal Pwmp are shown in this order from the top of the vertical axis. The horizontal axis is time.

That is, the clock signal Clk is shown at the uppermost stage. The clock signal Clk is a rectangular wave signal having a constant period, and the following signals operate in synchronization with the Hi transition timing of the clock signal Clk.

The phase signal Phip is shown in the next paragraph. The phase signal Phip is a frequency-divided signal whose state is switched at the instant when the clock signal Clk becomes Hi.

The 1 st reset signal Rst0 is indicated by a solid line and the 2 nd reset signal Rst1 is indicated by a dotted line in the next stage. The 1 st reset signal Rst0 and the 2 nd reset signal Rst1 are pulse signals that are alternately switched to Hi at the Hi switching timing of the clock signal Clk.

In the next stage, the 1 st sawtooth wave signal Saw0 is indicated by a solid line, the 2 nd sawtooth wave signal Saw1 is indicated by a broken line, the sawtooth bottom voltage signal is indicated by a dotted line, the crossing point at which the potential of the 1 st sawtooth wave signal Saw0 or the potential of the 2 nd sawtooth wave signal Saw1 is lower than the bottom potential Vbtm is indicated by an "x" symbol, and the crossing point that is exceeded is indicated by a "□" symbol.

The 1 st sawtooth wave signal Saw0 is reset to the ground power supply potential when the 1 st reset signal Rst0 is Hi. Similarly, the 2 nd sawtooth wave signal Saw1 is reset to the ground power supply potential when the 2 nd reset signal Rst1 is Hi.

The 1 st and 2 nd reset signals Rst0 and Rst1 become Low when the potentials of the 1 st and 2 nd sawtooth wave signals Saw0 and Saw1 are detected to be equal to or less than the potential of the bottom potential Vbtm. At this time, the potential of the sawtooth wave signal becomes substantially 0V, which is the ground power supply potential, due to the delay caused by the comparator 98 and the synchronous clock delay circuit 911. During the period when the 1 st and 2 nd reset signals Rst0 and Rst1 are Low, the potentials of the 1 st and 2 nd sawtooth wave signals Saw0 and Saw1 respectively rise at a constant rate.

The synchronous clock signal Clkx is represented in the next section. When the phase signal Phip is Low, the synchronous clock signal Clkx becomes Hi when the potential of the 1 st sawtooth wave signal Saw0 becomes higher than the bottom potential Vbtm (at the timing of the "□" mark), and becomes Low when the potential of the 1 st sawtooth wave signal Saw0 becomes higher than the sawtooth top voltage Vtop (at the timing of the "x" mark). Similarly, when the phase signal Phip is Hi, the synchronous clock signal Clkx becomes Hi when the potential of the 2 nd sawtooth wave signal Saw1 becomes higher than the bottom potential Vbtm (at the timing indicated by "□"), and becomes Low when the potential of the 2 nd sawtooth wave signal Saw1 becomes higher than the sawtooth top voltage Vtop (at the timing indicated by "x").

The selection signal Phipx is indicated in the next paragraph. The selection signal Phipx is generated by capturing the state of the phase signal Phip inside the selection signal flip-flop 910 at the timing at which the sawtooth wave synchronous clock signal is converted into Hi, holding the state, and outputting the state.

In the next stage, the sawtooth wave signal sawn is indicated by a solid line, the duty ratio designation voltage signal Vd is indicated by a broken line, and an intersection point at which the potential of the sawtooth wave signal sawn becomes higher than the potential of the duty ratio designation voltage signal Vd is indicated by a symbol "●". The sawtooth wave signal Saw is generated by selecting the 1 st sawtooth wave signal Saw0 when the selection signal Phipx is Low, and selecting the 2 nd sawtooth wave signal Saw1 when the selection signal Phipx is Hi.

The next paragraph represents the PWM reset signal Rn. The PWM reset signal Rn is Low when the potential of the sawtooth wave signal sawn is higher than the potential of the duty ratio designation voltage signal Vd, that is, at the timing indicated by "●", and is Hi when the potential of the sawtooth wave signal sawn is other than Low.

The PWM signal Pwmp is shown in the bottom section. The PWM signal Pwmp becomes Hi at the timing when the synchronous clock signal Clkx becomes Hi, and becomes Low when the PWM reset signal Rn becomes Low. Here, as shown at the right end of fig. 7, when the potential of the duty ratio designation voltage signal Vd is higher than the top potential Vtop, the PWM reset signal Rn does not become Low. In this case, the PWM signal Pwmp is held in the Hi state. In this way, in the present embodiment, a PWM signal Pwmp having a wide pulse width close to a 100% duty ratio can be generated. More specifically, the Low pulse width of the PWM signal Pwmp can be thinned to the limit of the trigger response.

As described above, the switching power supply 100 of the present embodiment outputs a stable output power supply even when the input power supply voltage drops to substantially the same level as the output power supply voltage.

(embodiment 3)

In the switching power supply 100 according to embodiment 3, the Hi pulse width duty ratio D ((2)) is changed more stably between 0% and 100% by changing the amplitude range of the high linearity sawtooth wave signal output from the sawtooth generator 9 in accordance with the state of the PWM signal Pwmp. Hereinafter, differences from the switching power supply 100 according to embodiment 2 will be described.

Fig. 8 is a diagram showing a configuration example of the switching power supply 100 according to embodiment 3. As shown in fig. 8, the PWM signal Pwmp output from the pulse modulator 1 is fed back to the voltage detector 90b, unlike the switching power supply 100 according to embodiment 2 shown in fig. 4.

More specifically, voltage detector 90b changes the timing of the state transition of cut-out signal Phipxx in accordance with the state of PWM signal Pwmp. Thereby, the amplitude range of the sawtooth wave signal Saw output from the sawtooth wave generator 9 is changed.

Fig. 9 is an operation waveform diagram of switching power supply 100 according to embodiment 3.

The vertical axis shows an input power supply voltage Vin, an output power supply voltage Vout, a clock signal Clk, a cut-out signal Phipxx, a top voltage Vtop, a 1 st sawtooth wave signal Saw0, a sawtooth wave signal Saw, a duty ratio indicating voltage signal Vd, a bottom potential Vbtm, a synchronous clock signal Clkx, and a PWM signal Pwmp in this order from the top. The horizontal axis is time.

That is, the solid line at the uppermost stage represents the change of the voltage Vin of the input power supply, and the broken line represents the voltage Vout of the output power supply. As described above, the switching power supply 100 according to embodiment 3 can output the stable output power supply Vout even when the input power supply voltage Vin changes from a high state, in which the voltage is more than ten times the output power supply voltage Vout, to a substantially equal state.

The voltage Vin of the input power supply is indicated by a solid line in the next stage, and the state of change in the voltage Vout of the output power supply is indicated by a broken line. In this way, the switching power supply 100 according to embodiment 3 can change the output power supply voltage Vout from 0V to a voltage substantially equal to the input power supply voltage, and output the voltage.

The clock signal Clk is represented in the next section. The clock signal Clk is a rectangular wave signal of a certain period.

The next paragraph represents the cut-out signal phixxx. Cut-out signal Phipxx is a two-division rectangular wave signal whose state changes at the timing when clock signal Clk switches to Hi when the Hi duty ratio of PWM signal Pwmp, which will be described later, is smaller than a predetermined value, and is a two-division rectangular wave signal whose state changes at the timing when sawtooth wave signal Saw is reset when the Hi duty ratio of PWM signal Pwmp is equal to or greater than the predetermined value.

In the next stage, the sawtooth wave signal Saw is indicated by a solid line. The sawtooth wave signal sawn is generated by selectively cutting out two sawtooth wave signals Saw0 and Saw1, which are not shown, by the cut-out signal Phipxx. In this section, the duty ratio indication voltage signal Vd is indicated by a broken line, and a mark "●" is given to an intersection where the sawtooth wave signal Saw becomes high with respect to the duty ratio indication voltage signal Vd, and a mark "□" is given to an intersection with the bottom potential Vbtm or the reset timing thereof.

The synchronous clock signal Clkx is represented in the next section. The synchronous clock signal Clkx is a rectangular wave signal that is converted to Hi at the timing of the aforementioned "□" symbol and is converted to Low at the Hi conversion timing of the clock signal Clk.

The PWM signal Pwmp is shown in the bottom section. The PWM signal Pwmp is switched to Hi at the timing when the synchronous clock signal Clkx is switched to Hi (the timing indicated by "□" in the figure), and is switched to Low at the timing when the potential of the sawtooth wave signal Saw becomes higher than the potential of the duty ratio designation voltage signal Vd (the timing indicated by "●" in the figure). Here, when the potential of the duty ratio designation voltage signal Vd is lower than the bottom potential Vbtm as in the left end state in the drawing, the PWM signal Pwmp is not generated and Low is maintained. Further, if the potential of the duty ratio designation voltage signal Vd is slightly higher than the bottom potential Vbtm, the PWM signal Pwmp becomes a very fine rectangular wave signal of the Hi pulse width.

Conversely, when the potential of the duty ratio designation voltage signal Vd is higher than the top potential Vtop as in the right end state in the figure, the PWM signal Pwmp becomes a rectangular wave signal with a 100% duty ratio, that is, Hi is held. Further, if the potential of the duty ratio designation voltage signal Vd becomes slightly lower than the top potential Vtop, the PWM signal Pwmp becomes a rectangular wave signal having a duty ratio close to 100% and being only once Low.

Fig. 10 is a diagram showing a detailed configuration example of the sawtooth generator 9 and the PWM circuit 1 according to embodiment 3. As shown in fig. 10, the voltage detector 90b is different from the voltage detector 90a according to embodiment 2. That is, the voltage detector 90b is different from the voltage detector 90a in that it further includes a determination delay circuit 917, a wide pulse width determination flip-flop 918, and a switch 919. Fig. 10 is different from fig. 6 in that a wider pulse determination synchronous clock signal Clkxx and a wider pulse width determination signal Widep are also shown.

The determination delay circuit 917 receives the synchronous clock signal Clkx, adds a delay longer than the response time of the comparator 98 and the comparator 11, and outputs a wide pulse determination synchronous clock signal Clkxx.

The wide pulse width determination flip-flop 918 receives the wide pulse determination synchronous clock signal Clkxx at its clock input terminal CK and the PWM signal Pwmp at its data terminal D. The wide pulse width determination flip-flop 918 internally takes the state of the PWM signal Pwmp at the timing at which the wide pulse determination synchronous clock signal Clkxx transitions to Hi, and outputs the state as a wide pulse width determination signal Widep. Thus, when the potential of the duty command voltage signal Vd is higher than the bottom potential Vbtm by a predetermined value or more, the wider pulse width determination signal Widep is set to Hi, and otherwise, Low. That is, when the pulse width of the rectangular wave signal is wide, the wide pulse width determination signal Widep is Hi, and when the pulse width of the rectangular wave signal is narrow, the wide pulse width determination signal Widep is Low.

A wide pulse width determination signal Widep is input to a selection terminal of the switch 919. When the wider pulse width determination signal Widep is Hi, switch 919 selects selection signal Phipx output from selection signal flip-flop 910, and outputs the selected signal Phipx to selector 912 as cut-out signal phixxx. On the other hand, when the wider pulse width determination signal Widep is Low, the phase signal Phip output from the input signal frequency divider 915 is selected and output to the selector 912 as the cut-out signal Phipxx.

Thus, the selector 912 switches the ranges of the 1 st sawtooth wave signal Saw0 and the 2 nd sawtooth wave signal Saw1 according to the cycle of the clock signal Clk, and outputs the signals as the sawtooth wave signal Saw. More specifically, the selector 912 selects the 1 st sawtooth wave signal Saw0 or the 2 nd sawtooth wave signal Saw1 including a signal component in a range of the bottom potential Vbtm or less when the pulse width of the PWM signal Pwmp is less than a predetermined value (the wide pulse width determination signal Widep is Low), and selects the 1 st sawtooth wave signal Saw0 or the 2 nd sawtooth wave signal Saw1 in a range of the bottom potential Vbtm to the bottom potential Vbtm when the pulse width of the PWM signal Pwmp is greater than or equal to the predetermined value (the wide pulse width determination signal Widep is Hi).

Fig. 11 is a detailed operation waveform diagram of switching power supply 100 according to embodiment 3. The clock signal Clk, the phase signal Phip, the 1 st reset signal Rst0, the 2 nd reset signal Rst1, the top voltage Vtop, the 1 st sawtooth wave signal Saw0, the 2 nd sawtooth wave signal Saw1, the bottom potential Vbtm, the synchronous clock signal Clkx, the selection signal Phipx, the cut-out signal phixxx, the top voltage Vtop, the sawtooth wave signal Saw, the duty ratio indication voltage signal Vd, the bottom potential Vbtm, the PWM reset signal Rn, the PWM signal Pwmp, and the pulse width determination signal Widep are shown in this order from the top of the vertical axis. The horizontal axis is time.

That is, the waveforms from the clock signal Clk shown in the uppermost stage to the selection signal Phipx shown in the sixth stage from the top are the same as those in the operation waveform diagram (fig. 7) of embodiment 2, and therefore, the description thereof is omitted.

The next paragraph represents the cut-out signal phixxx. Cut-out signal phixxx is a rectangular wave signal which is converted at the same timing as phase signal Phip when a wider pulse width determination signal Widep described later is Low, and is a rectangular wave signal which is converted at the same timing as selection signal Phipx when wider pulse width determination signal Widep is Hi.

In the next stage, the sawtooth wave signal sawn is indicated by a solid line, and the duty ratio indicating voltage signal Vd is indicated by a dotted line. Further, an intersection where the potential of the sawtooth wave signal sawn is higher than the potential of the duty ratio designation voltage signal Vd is denoted by "●", and an intersection where the potential is lower than the potential of the duty ratio designation voltage signal Vd is denoted by "x". The intersection at which the potential of the sawtooth wave signal Saw is lower than the bottom potential Vbtm is denoted by "□".

The sawtooth wave signal Saw is a waveform cut out by selecting the 1 st sawtooth wave signal Saw0 when the cut-out signal Phipxx is Low, and a waveform cut out by selecting the 2 nd sawtooth wave signal Saw1 when the cut-out signal Phipxx is Hi. Accordingly, when the pulse width of the pulse PWM signal Pwmp is small, that is, when the wide pulse width determination signal Widep is Low, the sawtooth wave signal Saw becomes a sawtooth wave signal whose potential rises from the ground power supply voltage 0V and is reset to the ground power supply voltage 0V again immediately before reaching the top potential Vtop. On the other hand, when the pulse width of the PWM signal PWMp is wide, that is, when the wide pulse width determination signal Widep is Hi, the sawtooth wave signal Saw is a sawtooth wave signal whose potential rises at a constant rate from the bottom potential Vbtm and is reset to the bottom potential Vbtm again when reaching the top potential Vtop. In either case, however, the timing at which the potential of the sawtooth wave signal sawn is higher than the bottom potential Vbtm coincides with the timing at which the synchronous clock signal Clkx is converted to Hi. That is, the period of the "□" mark is constant.

The next paragraph represents the PWM reset signal Rn. The PWM reset signal Rn is Hi at the timing of the "x" mark when the potential of the sawtooth wave signal Saw is lower than the potential of the duty ratio designation voltage signal Vd, and Low at the timing of the "●" mark when the potential is other than Hi. Here, when the wide pulse width determination signal Widep is Low, since the sawtooth wave signal sawn includes a signal component equal to or less than the bottom potential Vbtm, even if the duty ratio designation voltage signal Vd is in the vicinity of or equal to the bottom potential Vbtm, the timing at which the potential of the sawtooth wave signal sawn is higher than the potential of the duty ratio designation voltage signal Vd can be stably detected, and the PWM reset signal Rn is generated without fail. On the other hand, when the wider pulse width determination signal Widep is Hi, the highest potential of the sawtooth wave signal sawn becomes the top potential Vtop. Thus, if the duty ratio indicating voltage signal Vd is slightly lower than the top potential Vtop, the PWM reset signal Rn of a very fine Low pulse is generated, and conversely, if the duty ratio indicating voltage signal Vd is higher than the top potential Vtop, the Low pulse disappears and the PWM reset signal Rn is held at Hi.

The PWM signal Pwmp is represented in the next segment. The PWM signal Pwmp is set to Hi at the timing when the synchronous clock signal Clkx becomes Hi, and is reset to Low when the PWM reset signal Rn is Low. Here, since the period for converting the synchronous clock signal Clkx into Hi is kept constant, the period for converting the PWM signal Pwmp into Hi is also kept constant. On the other hand, the timing at which the PWM reset signal Rn transitions to Low varies according to the potential of the duty ratio designation voltage signal Vd. That is, the pulse width of the PWM signal Pwmp changes according to the potential of the duty ratio designation voltage signal Vd.

As shown at the left end of the operation waveform diagram of fig. 11, if the potential of the duty ratio indicating voltage signal Vd is lower than the bottom potential Vbtm, the timings of the "□" mark and the "●" mark are reversed, and the ● mark appears first. That is, when the PWM reset signal Rn is in a Low state, the synchronous clock signal Clkx is converted to Hi. At this time, the flip-flop 12 takes priority of the input to the reset terminal R by the switching of the clock input terminal CK, and therefore the PWM signal Pwmp is kept Low. However, the duty ratio designation voltage signal Vd is slightly higher in potential than the bottom potential Vbtm, and outputs a PWM signal Pwmp having a very short Hi pulse width corresponding to the period immediately before the mark "□" appears before the mark "●".

In this way, when the wide pulse width determination signal Widep is Low, since the sawtooth wave signal Saw includes a signal component equal to or less than the bottom potential Vbtm, a very thin PWM signal Pwmp can be generated, and the output power supply voltage Vout with a high step-down ratio can be stably output. In addition, when the potential of the pulse width designation voltage signal Vd is equal to or lower than the potential of the bottom potential Vbtm, the PWM signal Pwmp can be kept Low, and the output power supply voltage Vout can be kept 0V.

On the other hand, as shown at the right end of the operation waveform diagram of fig. 11, under the condition that the input power supply voltage Vin and the output power supply voltage Vout are substantially equal to each other, the wide pulse width determination signal Widep is Hi, and the maximum potential of the sawtooth wave signal sawn is the top potential Vtop. Thus, if the potential of the duty ratio designation voltage signal Vd is close to the top potential Vtop, a PWM signal Pwmp whose time to become Low is extremely short is generated.

Further, if the potential of the duty ratio indicating voltage signal Vd is higher than the top potential Vtop, the "●" mark disappears, and the PWM reset signal Rn no longer becomes Low. Therefore, the PWM signal Pwmp is held at Hi, and the duty ratio thereof becomes 100%.

The lower most part shows a wider pulse width determination signal Widep. The wide pulse width determination flip-flop 918 latches the state of the PWM signal Pwmp at the timing marked by "Δ" after the delay added by the determination delay circuit 917 since the synchronous clock signal Clkx is converted to Hi, and generates a wide pulse width determination signal Widep. That is, when the PWM signal Pwmp stays at Hi at the timing of the "Δ", it is determined that the pulse width is wide and the wide pulse width determination signal Widep becomes Hi, whereas when the PWM signal Pwmp is already reset to Low at the timing of the "Δ", it is determined that the pulse width is narrow and the wide pulse width determination signal Widep becomes Low.

As described above, the switching power supply 100 according to the present embodiment switches the amplitude of the sawtooth wave signal sawn in accordance with the width of the PWM signal Pwmp determined by the wide pulse width determining flip-flop 918. Thus, when the wide pulse width determination signal Widep is Low, the sawtooth wave signal Saw has a signal component equal to or lower than the bottom potential Vbtm. Thus, when the pulse width designation voltage signal Vd is at a low potential substantially equal to the potential of the bottom potential Vbtm, the PWM signal Pwmp having a very small pulse width can be stably generated. Further, when the potential of the pulse width command voltage signal Vd is equal to or lower than the potential of the bottom potential Vbtm, the duty ratio of the PWM signal Pwmp is 0%.

On the other hand, when the wide pulse width determination signal Widep is Hi, the range in which the sawtooth wave signal Saw is cut out is changed so that the maximum potential of the sawtooth wave signal Saw becomes the top potential Vtop. Thus, when the potential of the duty ratio designation voltage signal Vd is slightly lower than the top potential Vtop, the PWM reset signal Rn of a very small Low pulse width is generated. The flip-flop 12 responds to the PWM reset signal Rn of the very small Low pulse width, sets the PWM signal Pwmp to Low, and sets the PWM signal Pwmp to Hi again when receiving the next synchronization clock signal Clkx and then converting it to Hi after a short time. Here, the timing at which the clock signal Clkx is converted into Hi and the timing at which the sawtooth wave signal Saw is reset from the top potential Vtop to the sawtooth wave bottom potential btm are adjusted to coincide by the delay circuit 911. Therefore, the PWM signal Pwmp having a wide pulse width close to the 100% duty ratio can be stably generated. Further, if the potential of the duty ratio designation voltage signal Vd is higher than the top potential Vtop, the duty ratio of the PWM signal Pwmp becomes 100%.

Thus, according to the present embodiment, the continuity of the duty ratio of the PWM signal Pwmp from 0% to 100% can be controlled. Therefore, it is possible to provide a step-down switching power supply that stably operates in an input power supply over a wide range from a voltage substantially equal to the output power supply voltage to a high voltage exceeding the output power supply voltage by a factor of 10. Alternatively, a step-down switching power supply can be provided which stably outputs a voltage in a wide range from 0V to a voltage substantially equal to the input power supply voltage.

(embodiment 4)

The switching power supply 100 according to embodiment 4 is different from the switching power supply 100 according to embodiment 3 in that a sawtooth crest voltage adjustment function and an automatic adjustment function for matching the waveform of the 1 st sawtooth wave signal Saw0 with the waveform of the 2 nd sawtooth wave signal Saw1 are added to the voltage detector 90 c. Hereinafter, differences from the switching power supply 100 according to embodiment 3 will be described.

Fig. 12 is a diagram showing a detailed configuration example of the sawtooth generator 9 and the PWM circuit 1 according to embodiment 4.

As shown in fig. 12, the voltage detector 90c is different from the voltage detector 90b according to embodiment 3 shown in fig. 10 in configuration. More specifically, the voltage detector 90c further includes a top potential detection selector 920, a top potential detection comparator 921, a top potential reference voltage source 922, a suppression pulse generator 923, a 1 st suppression pulse generator 9240, and a 2 nd suppression pulse generator 9241. Also illustrated in fig. 10 are a 1 st control signal Sisaw0, a 2 nd control signal Sisaw1, a top potential Vtop, a suppression pulse signal Dch, a 1 st suppression pulse signal Dch0n, a 2 nd suppression pulse signal Dch1 n. In addition, the 1 st sawtooth generator 92a and the 2 nd sawtooth generator 92b correspond to the adjustment portion.

The 1 st sawtooth wave generator 92a further includes a 1 st speed-suppressing P-type MOS transistor 9250, a 1 st speed-increasing N-type MOS transistor 9260, a 1 st changing resistor 9270, and a 1 st holding capacitor 9280.

The 2 nd sawtooth wave generator 92b further includes a 2 nd speed-suppressing P-type MOS transistor 9251, a 2 nd speed-increasing N-type MOS transistor 9261, a 2 nd changing resistor 9271, and a 2 nd holding capacitor 9281.

First, a detailed configuration of the voltage detector 90c is explained.

The phase signal Phip is input to the top potential detection selector 920 at the selection signal terminal. The top potential detection selector 920 selects and outputs the 1 st sawtooth wave signal Saw1 when the phase signal Phip is Hi, and selects and outputs the 2 nd sawtooth wave signal Saw0 when the phase signal Phip is Low.

The top potential detection comparator 921 has a non-inverting input terminal to which the 1 st sawtooth wave signal Saw0 or the 2 nd sawtooth wave signal Saw1 selected by the top potential detection selector 920 is input, and has an inverting input terminal to which the top potential Vtop generated by the top potential reference voltage source 922 is input. The top potential detection comparator 921 outputs the top potential detection signal Tp at Hi when the selected 1 st sawtooth wave signal Saw0 or 2 nd sawtooth wave signal Saw1 is higher than the top potential Vtop, and outputs the top potential detection signal Tp at Low when the top potential detection signal Tp is not high.

The comparator 98 receives the 1 st sawtooth wave signal Saw0 or the 2 nd sawtooth wave signal Saw1 selected by the bottom potential detection selector 99 at its non-inverting input terminal, and receives the bottom potential Vbtm generated by the reference voltage source 97 at its inverting input terminal. The comparator 98 outputs the top potential detection signal Tp as Hi when the selected 1 st sawtooth wave signal Saw0 or 2 nd sawtooth wave signal Saw1 is higher than the bottom potential Vbtm, and outputs the bottom potential detection signal Bp as Low when the top potential detection signal Tp is Hi.

The suppression pulse generator 923 receives the Hi conversion of the top potential detection signal Tp, outputs the suppression pulse signal Dchp as Hi, and receives the Hi conversion of the bottom potential detection signal Bp, outputs the suppression pulse signal Dchp as Low. The suppression pulse generator 923 is composed of two flip-flops 923a and 923 b.

The top potential detection signal Tp is input to the clock input terminal CK of the flip-flop 923a, a signal in the Hi state at all times is input to the signal terminal D, and an output signal of the flip-flop 923b is input to the reset terminal RN. The bottom potential detection signal Bp output from the comparator 98 is input to the clock input terminal CK of one flip-flop 923b, a signal in a Hi state at all times is input to the signal terminal D, and the suppression pulse signal Dchp is input to the reset terminal RN in an inverted manner.

Thus, the suppression pulse generator 923 becomes a high-speed RS latch that operates upon reception of the Hi conversion of the input signal. That is, the suppression pulse generator 923 can generate the suppression pulse signal Dchp having a very small Hi pulse width by detecting a slight timing difference between the Hi transition of the top potential detection signal Tp and the Hi transition of the bottom potential detection signal Bp.

The phase signal Phip and the killer pulse signal Dchp are input to the 1 st killer pulse generator 9240. The 1 st killer pulse generator 9240 inverts the killer pulse signal Dchp when the phase signal Phip is Hi to output the 1 st killer pulse signal Dch0n, and holds the 1 st killer pulse signal Dch0n in Hi when the phase signal Phip is Low.

The 2 nd killer pulse generator 9241 receives the inverted input phase signal Phip and the killer pulse signal Dchp. The 2 nd killer pulse generator 9241 inverts the killer pulse signal Dchp when the phase signal Phip is Low, outputs the 2 nd killer pulse signal Dch1n, and holds the 2 nd killer pulse signal Dch1n at Hi when the phase signal Phip is Hi.

The 1 st speed suppression P-type MOS transistor 9250 is inverted at its gate terminal and receives the 1 st suppression pulse signal Dch0 n. The 1 st speed suppression P-type MOS transistor 9250 is turned on when the 1 st suppression pulse signal Dch0n is Low, and discharges the charge of the 1 st holding capacitor 9280 to the power supply potential connected to the source terminal via the 1 st changing resistor 9270 connected to the drain terminal.

On the other hand, the 1 st speed-increasing N-type MOS transistor 9260 has a 1 st reset signal Rst0 input to its gate terminal. The 1 st speed-increasing N-type MOS transistor 9260 is turned on when the 1 st reset signal Rst0 is Hi, and charges the 1 st holding capacitor 9280 from the ground power supply potential 0V connected to the source terminal via the 1 st changing resistor 9270 connected to the drain terminal.

The Low period of the 1 st suppression pulse signal Dch0n and the Hi period of the 1 st reset signal Rst0 are each configured to be very short. In accordance with the short pulse period, the amount of charge accumulated in the 1 st holding capacitor 9280 is adjusted to control the potential of the 1 st control signal Sisaw 0.

Similarly, the 2 nd speed suppression P-type MOS transistor 9251 has the 2 nd suppression pulse signal Dch1n inverted and input to its gate terminal. The 2 nd speed suppression P-type MOS transistor 9251 is turned on when the 2 nd suppression pulse signal Dch1n is Low, and discharges the charge of the 2 nd holding capacitor 9281 to the power supply potential connected to the source terminal via the 2 nd change resistor 9271 connected to the drain terminal.

On the other hand, the 2 nd speed-increasing N-type MOS transistor 9261 is input with a 2 nd reset signal Rst1 at its gate terminal. When the 2 nd reset signal Rst1 is Hi, it is turned on, and charges in the 2 nd holding capacitor 9281 are charged from the ground power supply potential 0V connected to the source terminal via the 2 nd sawtooth wave changing resistor 9272 connected to the drain terminal.

The Low period of the 2 nd suppression pulse signal Dch1n and the Hi period of the 2 nd reset signal Rst1 are each configured to be very short. In accordance with the short pulse period, the amount of charge accumulated in the 2 nd holding capacitor 9281 is adjusted to control the potential of the 2 nd control signal Sisaw 1.

The 1 st reset signal Rst0 and the 2 nd reset signal Rst1 are pulse signals that alternately become Hi at the timing when the clock signal Clk transitions to Hi. The Hi pulse widths are very short and equal to each other. On the other hand, the 1 st suppression pulse signal Dch0n is an inversion pulse signal that is set to Low when the potential of the 1 st sawtooth wave signal Saw0 becomes higher than the top potential Vtop and is reset to Hi when the potential of the 2 nd sawtooth wave signal Saw1 becomes higher than the bottom potential Vbtm. Similarly, the 2 nd suppression pulse signal Dch1n is an inversion pulse signal that is set to Low when the potential of the 2 nd sawtooth wave signal Saw1 becomes higher than the top potential Vtop, and is reset to Hi when the potential of the 1 st sawtooth wave signal Saw0 becomes higher than the bottom potential Vbtm.

Therefore, the 1 st suppression pulse signal Dch0n and the 2 nd suppression pulse signal Dch1n are pulse signals that alternately become Low at a timing immediately before the synchronous clock signal Clkx transitions to Hi, and the pulse widths thereof independently change in accordance with the highest potential of the 1 st sawtooth wave signal Saw0 and the highest potential of the 2 nd sawtooth wave signal Saw 1.

For example, when the potential of the 1 st sawtooth wave signal Saw0 has a slow rising speed, the potential of the 1 st sawtooth wave signal Saw0 does not reach the top potential Vtop at the timing when the synchronous clock signal Clkx transitions to Hi, the 1 st suppression pulse signal Dch0n is held at Hi, and a Low period does not occur. In contrast, when the potential of the 1 st sawtooth wave signal Saw0 has a high rising speed, and the potential of the 1 st sawtooth wave signal Saw0 has reached the top potential Vtop at the timing when the synchronous clock signal Clkx is converted to Hi, the 1 st suppression pulse signal Dch0n is a pulse signal that is set to Low at the timing when the potential of the 1 st sawtooth wave signal Saw0 reaches the top potential Vtop, and is reset to Hi at the timing when the synchronous clock signal Clkx is converted to Hi.

The potential of the 1 st control signal Sisaw0 and the potential of the 2 nd control signal Sisaw1 are gradually decreased by receiving the 1 st reset signal Rst0 and the 2 nd reset signal Rst1, respectively. Under the control of the voltage regulator, the rising speed of the sawtooth wave potential of the 1 st sawtooth wave signal Saw0 and the rising speed of the sawtooth wave potential of the 2 nd sawtooth wave signal Saw1 are increased in the same proportion to each other.

On the other hand, the potential of the 1 st control signal Sisaw0 and the potential of the 2 nd control signal Sisaw1 gradually rise in response to the 1 st suppression pulse signal Dch0n or the 1 st suppression pulse signal Dch1n, respectively. Under the control, the rising speed of the sawtooth wave potential of the 1 st sawtooth wave signal Saw0 and the rising speed of the sawtooth wave potential of the 2 nd sawtooth wave signal Saw1 decrease, and the respective sawtooth wave rising speeds decrease more and more. By this operation, the 1 st sawtooth wave potential rising speed and the 2 nd sawtooth wave rising speed are automatically adjusted to the same speed. In this way, the 1 st sawtooth wave generator 92a and the 2 nd sawtooth wave generator 92b have a function of adjusting the rising speed of the 1 st sawtooth wave signal Saw0 and the 2 nd sawtooth wave signal Saw1 so that the difference between the timing at which the sawtooth wave signal Saw output from the selector 912 reaches the predetermined top voltage Vtop and the timing at which the sawtooth wave signal sawn reaches the maximum value becomes a constant value.

Fig. 13 is an operation waveform diagram of switching power supply 100 according to embodiment 4. The clock signal Clk, the phase signal Phip, the 1 st reset signal Rst0, the 2 nd reset signal Rst1, the top voltage Vtop, the 2 nd sawtooth wave signal Saw1, the 1 st sawtooth wave signal Saw0, the bottom potential Vbtm, the synchronous clock signal Clkx, the 1 st suppression pulse signal Dch0n, the 2 nd suppression pulse signal Dch1n, the selection signal Phipx, the cut-out signal phixxx, the top voltage Vtop, the duty ratio indication voltage signal Vd, the sawtooth wave signal Saw, the bottom potential Vbtm, the PWM reset signal Rn, and the PWM signal Pwmp are shown in this order from the top of the vertical axis. The horizontal axis is time.

That is, the clock signal Clk is shown at the uppermost stage. The clock signal Clk is a rectangular wave signal having a constant period, and operates in synchronization with the Hi transition timing.

The phase signal Phip is shown in the next paragraph. The phase signal Phip is a frequency-divided signal whose state is switched at the instant when the clock signal Clk becomes Hi.

The 1 st reset signal Rst0 is indicated by a solid line and the 2 nd reset signal Rst1 is indicated by a dotted line in the next stage. The 1 st reset signal Rst0 and the 2 nd reset signal Rst1 alternately transition to Hi at the Hi transition timing of the clock signal Clk.

In the next stage, the 1 st sawtooth wave signal Saw0 is indicated by a solid line, the 2 nd sawtooth wave signal Saw1 is indicated by a dotted line, and the sawtooth bottom voltage signal is indicated by a dotted line. Note that the crossing point at which the potential of the 1 st sawtooth wave signal Saw0 or the potential of the 2 nd sawtooth wave signal Saw1 is lower than the bottom potential Vbtm is indicated by an "x" symbol, and the crossing point higher than the bottom potential Vbtm is indicated by a "□" symbol.

The 1 st sawtooth wave signal Saw0 is reset to the ground power supply potential when the 1 st reset signal Rst0 is Hi. Similarly, the 2 nd sawtooth wave signal Saw1 is reset to the ground power supply potential when the 2 nd reset signal Rst1 is Hi. The 1 st reset signal Rst0 and the 2 nd reset signal Rst1 automatically become Low upon detecting that the potentials of the 1 st sawtooth wave signal Saw0 and the 2 nd sawtooth wave signal Saw1 become equal to or less than the potential of the bottom potential Vbtm, respectively.

At this time, the potential of the sawtooth wave signal becomes substantially 0V, which is the ground power supply potential, due to the delay caused by the comparator 98 and the synchronous clock delay circuit 911. While the 1 st reset signal Rst0 and the 2 nd reset signal Rst1 are Low, the potentials of the 1 st sawtooth wave signal Saw0 and the 2 nd sawtooth wave signal Saw1 increase at a constant rate.

The synchronous clock signal Clkx is represented in the next section. When the phase signal Phip is Low, the potential of the 1 st sawtooth wave signal Saw0 becomes Hi when it becomes higher than the potential of the bottom potential Vbtm (timing indicated by "□"), and becomes Low when it is not (timing indicated by "x"). Similarly, when the phase signal Phip is Hi, the potential of the 2 nd sawtooth wave signal Saw1 becomes Hi when it becomes higher than the potential of the bottom potential Vbtm (timing indicated by "□"), and becomes Low when it is not (timing indicated by "x").

Here, if the left side of fig. 13 is viewed and the initial stage of the operation is viewed, the potential rise rate of the 1 st sawtooth wave signal Saw0 is slower than assumed, and conversely, the potential rise rate of the 2 nd sawtooth wave signal Saw1 is faster than assumed. In the figure, an "o" mark is given to an intersection where the 1 st sawtooth wave signal Saw0 and the 2 nd sawtooth wave signal Saw1 are higher than the top potential Vtop. Then, since the potential rising speed of the 1 st sawtooth wave signal Saw0 is slower than expected, it is reset to the ground potential 0V before reaching the top potential Vtop, and the mark "o" does not appear for a long time. On the other hand, since the potential of the 2 nd sawtooth wave signal Saw1 rises faster than expected, the mark "o" appears earlier than expected, and then the potential of the 2 nd sawtooth wave signal Saw1 also rises and becomes higher than the top potential Vtop.

The 1 st suppression pulse signal Dch0n is shown in the next stage, and the 2 nd suppression pulse signal Dch1n is shown in the further next stage. The 1 st suppression pulse signal Dch0n is set to Low at the timing of the "o" mark where the potential of the 1 st sawtooth wave signal Saw0 becomes higher than the top potential Vtop, and is reset to Hi at the timing of the "□" mark where the potential of the 2 nd sawtooth wave signal Saw1 becomes higher than the bottom potential Vbtm. Similarly, the 2 nd suppression pulse signal Dch1n is set to Low at the timing of the "o" mark where the potential of the 2 nd sawtooth wave signal Saw1 becomes higher than the top potential Vtop, and is reset to Hi at the timing of the "□" mark where the potential of the 1 st sawtooth wave signal Saw0 becomes higher than the bottom potential Vbtm.

Here, at the left side of fig. 13 and in the initial stage of the operation, the 1 st sawtooth wave signal Saw0 has a slow potential rise speed, does not reach the top potential Vtop, or appears later in the timing of the "o" mark than the "□" mark even when it becomes high, and therefore the 1 st suppression pulse signal Dch0n is not generated. On the other hand, the 2 nd sawtooth wave signal Saw0 has a higher potential rising speed and reaches the top potential Vtop earlier than expected, and therefore the 2 nd suppression pulse signal Dch1n having a wider Low pulse width is generated.

Since the 1 st suppression pulse signal Dch0n is not generated, the 1 st reset signal Rst0 alone acts thereon, and the 1 st sawtooth wave potential rising speed rises. This operation is repeated, and finally, the pulse width of the 1 st suppression pulse signal Dch0n becomes the same as the pulse width of the 1 st reset signal Rst0, and the 1 st sawtooth rising speed is stabilized. In contrast, since the action of the wider 2 nd suppression pulse signal Dch1n is higher than that of the 2 nd reset signal Rst1, the 2 nd sawtooth wave potential rising speed falls. This operation is repeated, and finally, the pulse width of the 2 nd suppression pulse signal Dch1n becomes the same as the pulse width of the 2 nd reset signal Rst1, and the 2 nd sawtooth wave rising speed is stabilized. The 1 st sawtooth wave rising speed and the 2 nd sawtooth wave rising speed are alternately adjusted by using a common circuit. Thus, the waveforms of the 1 st sawtooth wave signal Saw0 and the 2 nd sawtooth wave signal Saw1 are automatically adjusted to be completely identical.

The next section shows the selection signal Phipx and the cut-out signal phixxx. The selection signal Phipx is generated by acquiring the state of the phase signal Phip to the inside of the selection signal flip-flop 910 at the timing at which the sawtooth wave synchronous clock signal is converted into Hi, holding the state, and outputting the state. Since cut-out signal phixxx operates at the same timing, the waveform overlaps selection signal Phipx.

In the next stage, the sawtooth wave signal Saw is indicated by a solid line, and the duty ratio indicating voltage signal Vd is indicated by a broken line. An intersection at which the potential of the sawtooth wave signal sawn becomes higher than the potential of the duty ratio designation voltage signal Vd is denoted by an "●" symbol. The sawtooth wave signal Saw is generated by selecting the 1 st sawtooth wave signal Saw0 when the cut-out signal Phipxx is Low and selecting the 2 nd sawtooth wave signal Saw1 when the cut-out signal Phipxx is Hi.

The next paragraph represents the PWM reset signal Rn. The PWM reset signal Rn becomes Low when the potential of the sawtooth wave signal sawn becomes higher than the potential of the duty ratio designation voltage signal Vd, that is, at the timing indicated by "●", and becomes Hi when the potential of the sawtooth wave signal sawn is other than the Low potential, that is, at the timing at which the sawtooth wave signal sawn is reset.

The PWM signal Pwmp is shown in the bottom section. The PWM signal Pwmp becomes Hi at the timing when the synchronous clock signal Clkx becomes Hi, and becomes Low when the PWM reset signal Rn becomes Low. Here, in the initial state on the left side of fig. 13, the potential rising speed of the 1 st sawtooth wave signal Saw0 does not match the potential rising speed of the 2 nd sawtooth wave signal Saw 0. Due to this influence, the following disadvantages occur: the PWM signal Pwmp operates at a frequency of half the clock signal Clk, or alternately appears with a wider pulse width and a thinner pulse width. However, this operation is repeated, and finally, the potential rising speed of the 1 st sawtooth wave signal Saw0 and the potential rising speed of the 2 nd sawtooth wave signal Saw0 are automatically adjusted to completely match each other, and a PWM signal Pwmp having a stable pulse width is generated.

As described above, in the switching power supply 100 according to the present embodiment, the 1 st reset signal Rst0 and the 2 nd reset signal Rst1 respectively decrease the potential of the 1 st control signal Sisaw0 and the potential of the 2 nd control signal Sisaw1 at predetermined ratios, and increase the rate of increase in the sawtooth wave potential of the 1 st sawtooth wave signal Saw0 and the rate of increase in the sawtooth wave potential of the 2 nd sawtooth wave signal Saw1 at the same ratio. On the other hand, when the rising speed of the sawtooth wave potential of the 1 st sawtooth wave signal Saw0 is too fast as compared with the assumed speed, the 1 st suppression pulse signal Dch0n is generated, and the rising speed of the sawtooth wave potential of the 1 st sawtooth wave signal Saw0 is decelerated by increasing the potential of the 1 st control signal Sisaw 0. Similarly, when the rising rate of the sawtooth wave potential of the 2 nd sawtooth wave signal Saw1 is too high compared with the assumed rate, the 2 nd suppression pulse signal Dch1n is generated, the potential of the 2 nd control signal Sisaw1 is increased, and the rising rate of the sawtooth wave potential of the 2 nd sawtooth wave signal Saw1 is decelerated.

By these operations, the 1 st sawtooth wave potential rising speed and the 2 nd sawtooth wave rising speed are automatically adjusted to the same speed. This enables generation of a sawtooth signal having high linearity and an amplitude in a desired voltage range in accordance with the cycle of the clock signal Clk. According to the switching power supply of the present embodiment, for example, a switching power supply which operates more stably than the switching power supply of embodiment 3 can be provided.

(embodiment 5)

The switching power supply 100 according to embodiment 5 is a step-up/step-down switching power supply that can generate an output power supply having a lower voltage than an input power supply voltage and, conversely, can generate an output power supply having a higher voltage. The configuration is different from the switching power supply 100 according to embodiment 4 in that the pulse modulator 1, the selector 912, and the switching driver 2 are provided as two systems for voltage boosting and voltage dropping. Hereinafter, differences from the switching power supply 100 according to embodiment 4 will be described.

Fig. 14 is a diagram showing a configuration example of the switching power supply 100 according to embodiment 5.

The step-down system includes a step-down pwm (pwm)1bk, a step-down switching pre-driver 21, a step-down driver N-type MOS transistor 22, a step-down asynchronous power diode 23, and a selector 912 a.

On the other hand, the boosting system includes a boosting pwm (pwm)1bt, a boosting predriver 24, a boosting driver N-type MOS transistor 25, and a boosting asynchronous power diode 26. Fig. 15 also shows buck PWM signal Pwmbkp, boost PWM signal Pwmbtp, boost gate signal Gbkp, boost gate signal Gbtp, boost duty ratio indication voltage signal Vdbt, boost sawtooth wave signal Sawbt, and buck sawtooth wave signal Sawbk. In addition, the boosting duty ratio indicating voltage signal Vdbt corresponds to the 2 nd pulse width indicating voltage signal, and the boosting PWM signal Pwmbtp corresponds to the 2 nd PWM signal. Further, the step-down driver N-type MOS transistor 22 corresponds to the 1 st switching element, and the step-up driver N-type MOS transistor 25 corresponds to the 2 nd switching element.

In addition, a buck-boost duty ratio indication gap voltage source 10a is newly provided between the buck system and the boost system. The step-down PWM circuit 1bk modulates and outputs the Hi pulse width of the step-down PWM signal Pwmbkp synchronized with the synchronous clock signal Clkx, in accordance with the step-down duty indicating voltage signal Vd.

Similarly, step-down PWM circuit 1bt modulates and outputs Hi pulse width of step-up PWM signal Pwmbtp synchronized with synchronous clock signal Clkx, in accordance with step-up duty indicating voltage signal Vdbt.

The step-up/down duty indication voltage source 10a generates a step-up duty indication voltage signal Vdbt that is a voltage dropped by the step-up/down gap voltage Vgap (not shown) from the step-down duty indication voltage signal Vd. Although the step-up/down duty ratio instruction gap voltage source 10a is illustrated as an ideal voltage source, a circuit having any configuration may be used as long as a potential difference of the step-up/down gap voltage Vgap is generated.

The step-down switch pre-driver 21 receives the step-down PWM signal Pwmbkp and outputs a step-down switch gate signal Gbkp.

A buck switch gate signal Gbkp is input to the gate terminal of the buck driver N-type MOS transistor 22, a buck switch node SWBK is connected to the source terminal, and an input power supply is connected to the drain terminal. The step-down driver N-type MOS transistor 22 is in an on state in which the resistance between the source terminal and the drain terminal is very low when the potential of the gate terminal is higher than the potential of the source terminal, and in an off state in which the resistance between the source terminal and the drain terminal is very high when the potential of the gate terminal is not higher than the potential of the source terminal.

When the step-down PWM signal Pwmbkp is Low, the potential of the step-down switch gate signal Gbkp becomes equal to the potential of the step-down switch node Swbk. On the other hand, when the step-down PWM signal Pwmbkp is Hi, the potential of the step-down switching gate signal Gbkp becomes higher than the potential of the step-down switching node Swbk. That is, the step-down switch node Swbk is electrically connected to the input power supply when the step-down PWM signal Pwmbkp is Hi, and is opened in the other cases.

The boost pre-driver 24 receives a boost PWM signal Pwmbtp and outputs a boost gate signal Gbtp.

Boost driver N-type MOS transistor 25 has a gate terminal to which a boost gate signal Gbtp is input, a source terminal to which a ground power supply is connected, and a drain terminal to which a boost switch node SWBT is connected.

Boost driver N-type MOS transistor the boost driver N-type MOS transistor 25 is in an on state in which the resistance between the source terminal and the drain terminal is very low when the potential of the gate terminal is higher than the potential of the source terminal, and in other cases, is in an off state in which the resistance between the source terminal and the drain terminal is very high.

When the boost PWM signal Pwmbtp is Low, the potential of the boost gate signal Gbkp becomes 0V, and when the boost PWM signal Pwmbtp is Hi, the potential of the boost gate signal Gbtp becomes Hi. That is, boost switch node SWBT is electrically connected to ground power supply 0V when boost PWM signal Pwmbtp is Hi, and is open otherwise. The buck switch node SWBK and the boost switch node SWBT are connected via a current choke inductor 31.

The step-down switch node SWBK is connected to the cathode terminal of the step-down asynchronous power diode 23, and the ground power supply is connected to the anode terminal. The output power supply voltage Vout is connected to the cathode terminal of the step-up asynchronous power diode 26, and the step-up switch node SWBT is connected to the anode terminal thereof.

The current flowing through the current choke inductor 31 is rectified by the on/off operations of the step-down driver N-type MOS transistor 22 and the step-up driver N-type MOS transistor 25, and the output power supply voltage Vout is output from the input power supply.

A smoothing capacitor 32 is connected to the output power supply voltage Vout, and the voltage thereof is held at a predetermined value set by the potential Vref of the reference voltage source 5 by the action of a feedback control loop.

The step-down PWM circuit 1bk receives the sawtooth wave signals Sawbk and Sawbt and a synchronous clock signal Clkx synchronized with the sawtooth wave signals Sawbk and Sawbt. Similarly, the boost PWM circuit 1bt receives the sawtooth wave signals Sawbk and Sawbt and the synchronous clock signal Clkx synchronized with the sawtooth wave signals Sawbk and Sawbt.

Selector 912a receives as input the buck cut-out signal Phibkpxx state (japanese: スタ). Selector 912a cuts out and outputs 1 st sawtooth wave signal Saw0 as buck sawtooth wave signal Sawbk when buck cut-out signal phibbxx is in a Low state, and cuts out and outputs 2 nd sawtooth wave signal Saw1 as buck sawtooth wave signal Sawbk when buck cut-out signal phibbxx is in a Hi state.

Similarly, the boost selector 912b receives the boost cut signal Phibtpxx. When the boost cut-out signal phibtxx is Low, the 1 st sawtooth wave signal Saw0 is cut out and output as the boost sawtooth wave signal Sawbt, and when the boost cut-out signal phibtxx is Hi, the 2 nd sawtooth wave signal Saw1 is cut out and output as the boost sawtooth wave signal Sawbt.

Voltage detector 90d monitors the states of buck PWM signal Pwmbkp and boost PWM signal Pwmbtp and outputs buck cut-out signal phipkpxx and boost cut-out signal Phibtpxx.

Fig. 15 is an operation waveform diagram of switching power supply 100 according to embodiment 5.

The input power supply voltage Vin, the output power supply voltage Vout, the clock signal Clk, the state of the step-down cut-out signal phibbxx, the step-up cut-out signal Phibtpxx, the top voltage Vtop, the step-down sawtooth wave signal Sawbk, the bottom potential Vbtm, the top voltage Vtop, the step-up sawtooth wave signal Sawbt, the bottom potential Vbtm, the synchronous clock signal Clkx, the step-down PWM signal Pwmbkp, and the step-up PWM signal Pwmbtp are shown in this order from the top of the vertical axis. The horizontal axis is time.

That is, the solid line at the uppermost stage represents the change of the input power supply voltage Vin of the input power supply, and the broken line represents the voltage of the output power supply voltage Vout. In this way, the input power supply voltage Vin of the input power supply changes from a high state in which the voltage of the input power supply voltage Vout exceeds ten times to a low state in which the voltage of the input power supply voltage Vin is less than half. Alternatively, as indicated by the solid line in the next stage, the output power supply voltage Vout is changed from 0V to a higher voltage more than twice as high as the input power supply of the constant voltage Vin, and output.

The clock signal Clk is represented in the next section. As indicated by a solid line, the clock signal Clk is a rectangular wave signal of a certain period.

The next section shows the state of the reduced-pressure excision signal phipkpxx. The buck cut-out signal phibbxx state is a two-frequency-division rectangular wave signal whose state changes at the timing when the Hi duty ratio of a buck PWM signal Pwmbkp described later is smaller than a certain value. Further, the buck cut-out signal phibbxx state is a two-frequency-division rectangular wave signal whose state changes at the timing at which the buck sawtooth wave signal Sawbk described later is reset when the Hi duty ratio of the buck PWM signal Pwmbkp is larger than a certain value.

The next section shows the boost cut-out signal phibtxx. Boost cut-out signal Phibtpxx is a two-frequency-divided rectangular wave signal whose state changes at the timing when clock signal Clk transitions to Hi when the Hi duty ratio of boost PWM signal Pwmbtp, which will be described later, is smaller than a certain value. The boost sawtooth wave selection switch-out signal Pwmbtp is a two-frequency-division rectangular wave signal whose state changes at the timing at which the boost sawtooth wave signal Sawbt described later is reset when the Hi duty ratio of the boost PWM signal Pwmbtp is greater than a certain value.

In the next stage, the step-down sawtooth wave signal Sawbk is indicated by a solid line, the step-down duty command voltage signal Vd is indicated by a broken line, the "●" mark is given to the intersection where the step-down sawtooth wave signal Sawbk is at a high potential with respect to the step-down duty command voltage signal Vd, and the "□" mark is given to the intersection with the bottom potential Vbtm or the reset timing thereof. The buck sawtooth wave signal Sawbk is selectively cut out in the state of the buck cut-out signal phipkpxx to generate two sawtooth wave signals Saw0 and Saw1, which are not shown.

In the next stage, the step-down sawtooth wave signal Sawbk is indicated by a solid line, the step-down duty command voltage signal Vd is indicated by a broken line, the "●" mark is given to the intersection where the step-down sawtooth wave signal Sawbk is at a high potential with respect to the step-down duty command voltage signal Vd, and the "□" mark is given to the intersection with the bottom potential Vbtm or the reset timing thereof. The boost sawtooth wave signal Sawbt is selectively cut out by the boost cut-out signal phibtxx to generate two sawtooth wave signals Saw0 and Saw1, which are not shown.

The synchronous clock signal Clkx is represented in the next section. The synchronous clock signal Clkx is a rectangular wave signal that is converted to Hi at the timing of the aforementioned "□" symbol and is converted to Low at the Hi conversion timing of the clock signal Clk.

The next segment represents the buck PWM signal Pwmbkp. The buck PWM signal Pwmbkp is switched to Hi at the timing when the synchronous clock signal Clkx is switched to Hi (the timing indicated by "□" in the figure), and is switched to Low at the timing when the potential of the buck sawtooth wave signal Sawbk becomes higher than the potential of the buck duty ratio instruction voltage signal Vd (the timing indicated by "●" in the figure). Here, as in the state at the left end in the figure, when the potential of the duty ratio designation voltage signal Vd is lower than the bottom potential Vbtm, the step-down PWM signal Pwmbkp is not generated and Low is held. Further, if the potential of the step-down duty ratio designation voltage signal Vd is slightly higher than the bottom potential Vbtm, the step-down PWM signal Pwmbkp becomes a very fine rectangular wave signal of the Hi pulse width.

On the contrary, when the potential of the step-down duty ratio designation voltage signal Vd is higher than the top potential Vtop as in the right-hand side state in the figure, the step-down PWM signal Pwmbkp becomes a rectangular wave signal with a duty ratio of 100%, that is, Hi hold. When the potential of the step-down duty ratio designation voltage signal Vd is slightly lower than the top potential Vtop, the step-down PWM signal Pwmp becomes a rectangular wave signal having a duty ratio close to 100% and becoming Low at one moment.

Similarly, the boost PWM signal Pwmbtp is shown in the bottom stage and the next stage. Boost PWM signal Pwmbtp is switched to Hi at the timing when synchronous clock signal Clkx is switched to Hi (timing indicated by "□" in the figure), and is switched to Low at the timing when the potential of boost sawtooth wave signal Sawbt becomes higher than the potential of boost duty ratio instruction voltage signal Vdbt (timing indicated by "●" in the figure). Here, as in the state at the left end in the figure, when the potential of the boost duty ratio instruction voltage signal Vdbt is lower than the bottom potential Vbtm, the boost PWM signal Pwmbtp is not generated, and Low is held. Further, if the potential of the boost duty ratio instruction voltage signal Vdbt is slightly higher than the bottom potential Vbtm, the boost PWM signal Pwmbtp becomes a very fine rectangular wave signal of the Hi pulse width.

Further, if the potential of boost duty ratio instruction voltage signal Vdbt rises, boost PWM signal Pwmbtp increases to a duty of 100% in accordance therewith.

Fig. 16 is a diagram showing a detailed configuration example of the sawtooth generator 9, the step-down PWM circuit 1bk, and the step-up PWM circuit 1bt according to embodiment 5. In fig. 16, a wider step-down pulse width determination signal Widebkp, a wider step-up pulse width determination signal Widebkt, a step-up duty ratio indicating voltage signal Vdbt, a step-down PWM signal Pwmbkp, and a step-up PWM signal Pwmbtp are also illustrated.

The step-down PWM circuit 1bk is constituted by a step-down comparator 11bk and a step-down flip-flop 12 bk.

Similarly, the boost PWM circuit 1bt is constituted by a boost comparator 11bt and a boost flip-flop 12 bt. The configuration and operation of both are the same as those of the PWM circuit 1 according to embodiment 4, and therefore, the description thereof is omitted. The boost comparator 11bt corresponds to the 3 rd detector, and the boost flip-flop 12bt corresponds to the PWM 2 nd PWM signal output circuit.

The sawtooth wave generator 9 is provided with circuits of two systems, a step-down sawtooth wave generation system and a step-up sawtooth wave generation system. The step-down sawtooth wave generating system is constituted by a step-down wide pulse width determination flip-flop 918bk, a step-down changeover switch 919bk, and a selector 912 a.

Similarly, the step-up sawtooth wave generating system is constituted by a pulse width determination flip-flop 918bt whose step-up is wide, a step-up changeover switch 919bt, and a step-up selector 912 bt. The configurations and operations of both are the same as those of the wide pulse width determination flip-flop 918, the change-over switch 919, and the selector 912 according to embodiment 4, and therefore, the description thereof is omitted.

In the case of a step-up/step-down switching power supply, if the potential relationship of the input/output power supply fluctuates, the step-down switching pulse width and the step-up switching pulse width vary from 0% to 100%. It is important that the change at the time when the pulse disappears or when the pulse becomes full operation is smooth.

When the pulse width changes rapidly, a problem occurs such as a rapid change or a periodic variation in the output power supply voltage. As a countermeasure, there is a method of limiting the amount of change in the pulse width to, for example, 10% to 90%, but when the voltage ratio of the input/output power supply is large, the conversion power efficiency is deteriorated due to unnecessary switching operation.

As described above, according to the present embodiment, the amplitude of the sawtooth wave signal sawn is switched to generate the buck PWM signal Pwmbkp for controlling the buck driver N-type MOS transistor 22 and the boost PWM signal Pwmbtp for controlling the boost driver N-type MOS transistor 25. Thus, the buck PWM signal Pwmbkp and the boost PWM signal Pwmbtp can be controlled continuously and independently with duty ratios in a wide range from 0% to 100%. Therefore, the voltage raising operation, the voltage raising/lowering operation, and the voltage lowering operation can be smoothly switched. Thus, a step-up/step-down switching power supply which has high power conversion efficiency and operates stably even when the potential relationship of the input/output power supply fluctuates can be provided.

Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments may be implemented in other various forms, and various omissions, substitutions, and changes may be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.