阅读说明：本技术 具有增强模式和耗尽模式晶体管二者的单片微波集成电路 (Monolithic microwave integrated circuit with both enhancement mode and depletion mode transistors ) 是由 S·斯瑞拉姆 J·高 J·费舍 S·什帕德 于 2019-05-14 设计创作，主要内容包括：一种基于氮化镓的单片微波集成电路包括基板(110)、基板上的沟道层(130)和沟道层上的阻挡层(140)。在阻挡层的顶表面中提供凹部(412)。在阻挡层上与沟道层相对地提供第一栅电极、第一源电极和漏电极,其中,第一栅电极(210、310)的底表面与阻挡层直接接触。在阻挡层上与沟道层相对地还提供第二栅电极(410)、第二源电极(420)和第二漏电极(430)。在阻挡层中的凹部中提供栅绝缘层(412),并且第二栅电极与阻挡层相对地在栅绝缘层上并延伸到凹部中。第一栅电极、第一源电极和第一漏电极包括耗尽模式晶体管(200、300)的电极,并且第二栅电极、第二源电极和第二漏电极包括增强模式晶体管(400)的电极。(A monolithic gallium nitride-based microwave integrated circuit includes a substrate (110), a channel layer (130) on the substrate, and a barrier layer (140) on the channel layer. A recess (412) is provided in a top surface of the barrier layer. A first gate electrode, a first source electrode and a drain electrode are provided on the barrier layer opposite the channel layer, wherein a bottom surface of the first gate electrode (210, 310) is in direct contact with the barrier layer. A second gate electrode (410), a second source electrode (420), and a second drain electrode (430) are also provided on the barrier layer opposite the channel layer. A gate insulating layer (412) is provided in the recess in the barrier layer, and a second gate electrode is on the gate insulating layer opposite the barrier layer and extends into the recess. The first gate electrode, the first source electrode and the first drain electrode comprise electrodes of a depletion-mode transistor (200, 300), and the second gate electrode, the second source electrode and the second drain electrode comprise electrodes of an enhancement-mode transistor (400).)

1. A monolithic microwave integrated circuit, comprising:

a monolithic substrate;

a gallium nitride-based channel layer on the monolithic substrate;

a gallium nitride-based barrier layer on the gallium nitride-based channel layer opposite the monolithic substrate, the gallium nitride-based barrier layer including a recess in a top surface thereof;

a first source electrode, a first drain electrode, and a first gate electrode on the gallium nitride based barrier layer opposite the gallium nitride based channel layer, the first gate electrode being located between the first source electrode and the first drain electrode, wherein a bottom surface of the first gate electrode is in direct contact with the gallium nitride based barrier layer;

a second source electrode and a second drain electrode on the gallium nitride based barrier layer opposite the gallium nitride based channel layer;

a gate insulating layer in the recess in the gallium nitride based barrier layer; and

a second gate electrode on the gate insulating layer opposite the gallium nitride-based barrier layer, the second gate electrode being between the second source electrode and the second drain electrode and extending into the recess,

wherein the first source electrode, the first drain electrode, and the first gate electrode comprise electrodes of a depletion-mode transistor, and the second source electrode, the second drain electrode, and the second gate electrode comprise electrodes of an enhancement-mode transistor.

2. The monolithic microwave integrated circuit of claim 1, wherein the recess extends completely through the gallium nitride-based barrier layer to expose the gallium nitride-based channel layer.

3. The monolithic microwave integrated circuit of claim 2, wherein the recess further extends into a top surface of the gallium nitride based channel layer.

4. The monolithic microwave integrated circuit of any of claims 1-3, further comprising:

a third source electrode on the gallium nitride-based barrier layer opposite the gallium nitride-based channel layer;

a third drain electrode on the gallium nitride-based barrier layer opposite the gallium nitride-based channel layer;

a third gate electrode on the gallium nitride-based barrier layer opposite the gallium nitride-based channel layer, the third gate electrode extending between the third source electrode and the third drain electrode, wherein a bottom surface of the third gate electrode is in direct contact with the barrier layer,

wherein the depletion mode transistor comprises a first depletion mode transistor, an

Wherein the third source electrode, the third drain electrode, and the third gate electrode comprise electrodes of a second depletion mode transistor.

5. The monolithic microwave integrated circuit of claim 4, wherein a first distance between the second source electrode and the second gate electrode is substantially the same as a second distance of the second drain electrode and the second gate electrode.

6. The monolithic microwave integrated circuit of claim 5, wherein a third distance between the first source electrode and the first gate electrode is less than a fourth distance between the first drain electrode and the first gate electrode.

7. The monolithic microwave integrated circuit of any of claims 1-6, further comprising an insulating layer on the gallium nitride-based barrier layer, the insulating layer including openings for each of the first and second source electrodes, the first and second drain electrodes, and the first and second gate electrodes, wherein the insulating layer and the gate insulating layer are formed of different materials, and wherein the gate insulating layer extends along a top surface of at least a portion of the insulating layer and along sidewalls of the opening in the insulating layer for the second gate electrode.

8. The monolithic microwave integrated circuit of claim 7, wherein the gate insulating layer comprises an oxide layer and the insulating layer comprises a nitride layer.

9. The monolithic microwave integrated circuit of any of claims 1 to 3, wherein the depletion mode transistor comprises a field plate and the enhancement mode transistor does not comprise a field plate.

10. A semiconductor integrated circuit comprising:

a substrate;

a Radio Frequency (RF) power amplifier formed on a first region of the substrate, the RF power amplifier including a plurality of gallium nitride based depletion mode transistors; and

a digital circuit formed on a second region of the substrate, the digital circuit comprising a plurality of gallium nitride based enhancement mode transistors.

11. The semiconductor integrated circuit of claim 10, wherein the digital circuit further comprises a plurality of gallium nitride based depletion mode transistors.

12. The semiconductor integrated circuit according to any one of claims 10 to 11, further comprising:

a gallium nitride-based channel layer on the substrate;

a gallium nitride-based barrier layer on the gallium nitride-based channel layer opposite the substrate, the gallium nitride-based barrier layer including a plurality of recesses in a top surface thereof;

wherein a gate electrode of the gallium nitride based depletion mode transistor in the first region of the substrate directly contacts the gallium nitride based barrier layer, an

Wherein gate electrodes of the gallium nitride based enhancement mode transistors in the second region of the substrate extend into respective recesses in the gallium nitride based barrier layer.

13. The semiconductor integrated circuit of claim 12, further comprising a gate insulating layer in the recess in the gallium nitride based barrier layer between the respective gate electrode of the gallium nitride based enhancement mode transistor and the gallium nitride based barrier layer.

14. The semiconductor integrated circuit as recited in claim 13, wherein the recess extends completely through the gallium nitride-based barrier layer to expose the gallium nitride-based channel layer.

15. The semiconductor integrated circuit as recited in claim 14 wherein the recess further extends into a top surface of the gallium nitride based channel layer.

16. The semiconductor integrated circuit according to claim 15, wherein the gate insulating layer comprises an oxide layer.

17. The semiconductor integrated circuit as recited in any of claims 12 to 16, wherein the recess extends only partially through the gallium nitride-based barrier layer, and wherein a gate electrode of the gallium nitride-based enhancement mode transistor in the second region of the substrate directly contacts a corresponding portion of the gallium nitride-based barrier layer.

18. The semiconductor integrated circuit as recited in any of claims 10 to 17, wherein each gallium nitride based enhancement mode transistor comprises a gate electrode, a source electrode, and a drain electrode, and wherein the gate electrode of each gallium nitride based enhancement mode transistor is equidistant between its corresponding source and drain electrodes.

19. The semiconductor integrated circuit as recited in any of claims 10 to 18, wherein each gallium nitride based depletion mode transistor comprises a gate electrode, a source electrode, and a drain electrode, and wherein the gate electrode of each gallium nitride based depletion mode transistor is closer to its corresponding source electrode than the gate electrode of the transistor is to its corresponding drain electrode.

20. The semiconductor integrated circuit according to claim 10, further comprising:

a gallium nitride-based channel layer on the substrate; and

a gallium nitride-based barrier layer on the gallium nitride-based channel layer opposite the substrate,

wherein each of the gallium nitride-based enhancement mode transistors includes a gate electrode, a source electrode, and a drain electrode, an

Wherein the gallium nitride-based barrier layer is doped with a dopant of a first conductivity type under a source electrode and a drain electrode of each gallium nitride-based enhancement-mode transistor, and the gallium nitride-based barrier layer is doped with a dopant of a second conductivity type under a gate electrode of each gallium nitride-based enhancement-mode transistor, wherein the first conductivity type is opposite the second conductivity type.

21. A semiconductor integrated circuit comprising:

a monolithic substrate;

a first gallium nitride based depletion mode transistor on a first region of the monolithic substrate, the first gallium nitride based depletion mode transistor having a first gate width and a first gate length;

a second gallium nitride based depletion mode transistor on a second region of the monolithic substrate, the second gallium nitride based depletion mode transistor having a second gate width and a second gate length; and

a gallium nitride based enhancement-mode transistor on the second region of the monolithic substrate, the gallium nitride based enhancement-mode transistor having a third gate width and a third gate length.

22. The semiconductor integrated circuit as claimed in claim 21, wherein the first gate width exceeds the second gate width by at least ten times.

23. The semiconductor integrated circuit according to any one of claims 21 to 22, wherein the first gate length is smaller than the second gate length.

24. The semiconductor integrated circuit as claimed in any one of claims 21 to 23, wherein the first gate width exceeds the third gate width by at least ten times.

25. The semiconductor integrated circuit according to any one of claims 21 to 24, wherein the first gate length is smaller than the third gate length.

26. The semiconductor integrated circuit according to any one of claims 21 to 25, wherein the second gate length exceeds the third gate length.

27. The semiconductor integrated circuit according to any one of claims 21 to 26, further comprising:

a gallium nitride-based channel layer on the monolithic substrate;

a gallium nitride-based barrier layer on the gallium nitride-based channel layer opposite the monolithic substrate, a top surface of the gallium nitride-based barrier layer including a recess,

wherein the gate electrode of the first gallium nitride based depletion-mode transistor and the gate electrode of the second gallium nitride based depletion-mode transistor each directly contact the gallium nitride based barrier layer, and the gate electrode of the gallium nitride based enhancement-mode transistor extends into the recess in the gallium nitride based barrier layer.

28. The semiconductor integrated circuit as recited in any one of claims 21 to 27, further comprising a gate insulating layer in the recess in the gallium nitride based barrier layer between a gate electrode of the gallium nitride based enhancement mode transistor and the gallium nitride based barrier layer.

29. The semiconductor integrated circuit as recited in any one of claims 21 to 28, wherein the recess extends completely through the gallium nitride-based barrier layer to expose the gallium nitride-based channel layer.

30. The semiconductor integrated circuit as recited in claim 29 wherein the recess further extends into a top surface of the gallium nitride based channel layer.

31. The semiconductor integrated circuit according to any one of claims 21 to 30, wherein the gate insulating layer comprises an oxide layer.

32. The semiconductor integrated circuit as recited in any one of claims 21 to 31, wherein the recess extends only partially through the gallium nitride-based barrier layer, and wherein a gate electrode of the gallium nitride-based enhancement mode transistor directly contacts sidewalls and a bottom surface of the recess.

33. The semiconductor integrated circuit according to claim 21, further comprising:

a gallium nitride-based channel layer on the monolithic semiconductor substrate; and

a gallium nitride-based barrier layer on the gallium nitride-based channel layer opposite the monolithic semiconductor substrate,

wherein the gallium nitride-based enhancement mode transistor comprises a gate electrode, a source electrode, and a drain electrode, an

Wherein the gallium nitride-based barrier layer is doped with a dopant of a first conductivity type under source and drain electrodes of the gallium nitride-based enhancement-mode transistor, and the gallium nitride-based barrier layer is doped with a dopant of a second conductivity type under a gate electrode of the gallium nitride-based enhancement-mode transistor, wherein the first conductivity type is opposite the second conductivity type.

34. A method of fabricating a monolithic gallium nitride based microwave integrated circuit device, the method comprising:

forming a gallium nitride-based channel layer on a substrate;

forming a gallium nitride-based barrier layer on the gallium nitride-based channel layer opposite the substrate;

forming an insulating layer on the gallium nitride-based barrier layer, the insulating layer including a plurality of first gate electrode openings exposing the gallium nitride-based barrier layer, a plurality of second gate electrode openings exposing the gallium nitride-based barrier layer, and a plurality of source/drain electrode openings exposing the gallium nitride-based barrier layer;

forming recesses in respective portions of the gallium nitride-based barrier layer exposed by the first gate electrode opening;

forming a gate insulating layer in the first gate electrode opening, the gate insulating layer covering sidewalls and a bottom surface of the respective recess;

forming a plurality of first source electrodes, a plurality of second source electrodes, a plurality of first drain electrodes, and a plurality of second drain electrodes in the source/drain electrode openings in the insulating layer, the first source electrodes, the second source electrodes, the first drain electrodes, and the second drain electrodes directly contacting a top surface of the gallium nitride based barrier layer;

forming first gate electrodes in the first gate electrode openings on the gate insulating layer, each first gate electrode extending into a corresponding one of the recesses,

forming a second gate electrode in a second gate electrode opening in the insulating layer, the second gate electrode directly contacting a top surface of the gallium nitride based barrier layer; and

wherein each set of the first source electrode, the first drain electrode and the first gate electrode comprises an electrode of an enhancement mode transistor, and each set of the second source electrode, the second drain electrode and the second gate electrode comprises an electrode of a depletion mode transistor.

35. The method of claim 34, further comprising forming source/drain regions in the gallium nitride-based barrier layer prior to forming the first and second source electrodes and the first and second drain electrodes.

36. The method of any of claims 34 to 35, wherein the recess extends completely through the gallium nitride-based barrier layer.

37. The method of any of claims 34-36, wherein the recess extends into the gallium nitride based channel layer.

38. The method of any of claims 34 to 37, wherein the gate insulating layer comprises an oxide layer.

Technical Field

The inventive concepts described herein relate to integrated circuit devices and, more particularly, to monolithic microwave integrated circuits.

Background

Power semiconductor devices are widely used to carry large currents, support high voltages, and/or operate at high frequencies such as radio frequencies. A wide variety of power semiconductor devices are known in the art, including, for example, power switching devices and power amplifiers. Many power semiconductor devices are implemented using various types of field effect transistors including, for example, High Electron Mobility Transistors (HEMTs) and Metal Oxide Semiconductor Field Effect Transistors (MOSFETs).

Modern power semiconductor devices are typically made of wide bandgap semiconductor materials. For example, power HEMTs may be made from gallium arsenide (GaAs) based material systems, or more recently, gallium nitride (GaN) based material systems formed on silicon carbide (SiC) substrates. The power semiconductor devices may be formed as discrete devices or as a plurality of devices (which may include transistors and other circuit devices such as resistors, inductors, capacitors, transmission lines, etc.) formed on a common substrate to provide a so-called Monolithic Microwave Integrated Circuit (MMIC). MMICs refer to integrated circuits that operate on radio frequency and/or microwave frequency signals, in which all circuitry for a particular function is integrated in a single semiconductor chip. Example MMIC devices are transistor amplifiers that include associated matching circuits, feed networks, and the like, all implemented on a common substrate. The MMIC transistor amplifier typically includes a plurality of unit cell HEMT transistors connected in parallel.

Field effect transistors such as HEMTs and MOSFETs may be classified into a depletion mode type and an enhancement mode type corresponding to whether the transistors are in an ON (ON) state or an OFF (OFF) state when the gate-source voltage is zero. In enhancement mode devices, the device is turned off at zero gate-source voltage, while in depletion mode devices, the device is turned on at zero gate-source voltage. HEMTs are typically implemented as depletion mode devices because they are conductive at zero gate-source bias due to polarization induced charge at the interface of the barrier and channel layers of the device.

Disclosure of Invention

In accordance with an embodiment of the present invention, an MMIC device is provided that includes a monolithic substrate, a gallium nitride based channel layer on the monolithic substrate, and a gallium nitride based barrier layer on the gallium nitride based channel layer opposite the monolithic substrate, the gallium nitride based barrier layer including a recess in a top surface thereof. A first source electrode, a first drain electrode, and a first gate electrode are provided on the gallium nitride-based barrier layer opposite the gallium nitride-based channel layer, the first gate electrode being located between the first source electrode and the first drain electrode, wherein a bottom surface of the first gate electrode is in direct contact with the gallium nitride-based barrier layer. A second source electrode and a second drain electrode are also provided on the gallium nitride-based barrier layer opposite the gallium nitride-based channel layer. A gate insulating layer is in the recess in the gallium nitride based barrier layer, and a second gate electrode is on the gate insulating layer opposite the gallium nitride based barrier layer, the second gate electrode being between the second source electrode and the second drain electrode and extending into the recess. The first source electrode, the first drain electrode, and the first gate electrode comprise electrodes of a depletion mode transistor, and the second source electrode, the second drain electrode, and the second gate electrode comprise electrodes of an enhancement mode transistor.

In some embodiments, the recess extends completely through the gallium nitride-based barrier layer to expose the gallium nitride-based channel layer. The recess may optionally extend further into a top surface of the gallium nitride based channel layer.

In some embodiments, the MMIC device may further include a third source electrode, a third drain electrode, and a third gate electrode on the gallium nitride based barrier layer opposite the gallium nitride based channel layer, the third gate electrode extending between the third source electrode and the third drain electrode, wherein a bottom surface of the third gate electrode is in direct contact with the barrier layer. In such embodiments, the depletion mode transistor may be a first depletion mode transistor, and the third source electrode, the third drain electrode, and the third gate electrode may be electrodes of a second depletion mode transistor.

In some embodiments, a first distance between the second source electrode and the second gate electrode may be substantially the same as a second distance between the second drain electrode and the second gate electrode. In some embodiments, the third distance between the first source electrode and the first gate electrode may be less than the fourth distance between the first drain electrode and the first gate electrode.

In some embodiments, the MMIC device may further comprise an insulating layer on the gallium nitride based barrier layer, the insulating layer having openings for each of the first and second source electrodes, the first and second drain electrodes, and the first and second gate electrodes. In such embodiments, the insulating layer and the gate insulating layer may be formed of different materials, and the gate insulating layer may extend along a top surface of at least a portion of the insulating layer and along sidewalls of the opening in the insulating layer for the second gate electrode.

In some embodiments, the gate insulating layer may be an oxide layer, and the insulating layer may be a nitride layer.

In some embodiments, the depletion mode transistor may include a field plate, and the enhancement mode transistor does not include a field plate.

In accordance with a further embodiment of the present invention, a semiconductor integrated circuit is provided that includes a substrate, a Radio Frequency (RF) power amplifier formed on a first region of the substrate, the RF power amplifier including a plurality of gallium nitride based depletion mode transistors and a digital circuit formed on a second region of the substrate, the digital circuit including a plurality of gallium nitride based enhancement mode transistors.

In some embodiments, the digital circuit may further include a plurality of gallium nitride based depletion mode transistors.

In some embodiments, the semiconductor integrated circuit may further include a gallium nitride-based channel layer on the substrate and a gallium nitride-based barrier layer on the gallium nitride-based channel layer opposite the substrate, the gallium nitride-based barrier layer including a plurality of recesses in a top surface thereof. The gate electrode of the gallium nitride based depletion-mode transistor in the first region of the substrate may directly contact the gallium nitride based barrier layer, and the gate electrode of the gallium nitride based enhancement-mode transistor in the second region of the substrate may extend into a corresponding recess in the gallium nitride based barrier layer.

In some embodiments, the semiconductor integrated circuit may further include a gate insulating layer in a recess in the gallium nitride based barrier layer between the gallium nitride based barrier layer and the respective gate electrode of the gallium nitride based enhancement mode transistor.

In some embodiments, the recess extends completely through the gallium nitride-based barrier layer to expose the gallium nitride-based channel layer.

In some embodiments, the recess further extends into a top surface of the gallium nitride based channel layer.

In some embodiments, the gate insulating layer includes an oxide layer.

In some embodiments, the recess extends only partially through the gallium nitride-based barrier layer, and wherein the gate electrode of the gallium nitride-based enhancement mode transistor in the second region of the substrate directly contacts a corresponding portion of the gallium nitride-based barrier layer.

In some embodiments, each gallium nitride-based enhancement-mode transistor includes a gate electrode, a source electrode, and a drain electrode, and wherein the gate electrode of each gallium nitride-based enhancement-mode transistor is equidistant between its corresponding source electrode and drain electrode.

In some embodiments, each gallium nitride-based depletion mode transistor includes a gate electrode, a source electrode, and a drain electrode, and wherein the gate electrode of each gallium nitride-based depletion mode transistor is closer to its corresponding source electrode than the gate electrode of each gallium nitride-based depletion mode transistor is to its corresponding drain electrode.

In some embodiments, the semiconductor integrated circuit may further include a gallium nitride-based channel layer on the substrate and a gallium nitride-based barrier layer on the gallium nitride-based channel layer opposite the substrate, wherein each gallium nitride-based enhancement mode transistor includes a gate electrode, a source electrode, and a drain electrode, and the gallium nitride-based barrier layer is doped with a dopant of a first conductivity type under the source electrode and the drain electrode of each gallium nitride-based enhancement mode transistor and is doped with a dopant of a second conductivity type under the gate electrode of each gallium nitride-based enhancement mode transistor, wherein the first conductivity type is opposite the second conductivity type.

In accordance with yet a further embodiment of the present invention, a semiconductor integrated circuit is provided that includes a monolithic substrate, a first gallium nitride based depletion-mode transistor on a first region of the monolithic substrate, the first gallium nitride based depletion-mode transistor having a first gate width and a first gate length, a second gallium nitride based depletion-mode transistor on a second region of the monolithic substrate, the second gallium nitride based depletion-mode transistor having a second gate width and a second gate length, and a gallium nitride based enhancement-mode transistor on the second region of the monolithic substrate, the gallium nitride based enhancement-mode transistor having a third gate width and a third gate length.

In some embodiments, the first gate width exceeds the second gate width by at least ten times.

In some embodiments, the first gate length is less than the second gate length.

In some embodiments, the first gate width exceeds the third gate width by at least ten times.

In some embodiments, the first gate length is less than the third gate length.

In some embodiments, the second gate length exceeds the third gate length.

In some embodiments, the semiconductor integrated circuit may further include a gallium nitride-based channel layer on the monolithic substrate and a gallium nitride-based barrier layer on the gallium nitride-based channel layer opposite the monolithic substrate, a top surface of the gallium nitride-based barrier layer including a recess. In such embodiments, the gate electrode of the first gallium nitride based depletion-mode transistor and the gate electrode of the second gallium nitride based depletion-mode transistor may each directly contact the gallium nitride based barrier layer, and the gate electrode of the gallium nitride based enhancement-mode transistor extends into the recess in the gallium nitride based barrier layer.

In some embodiments, the semiconductor integrated circuit may further include a gate insulating layer in a recess in the gallium nitride based barrier layer between the gate electrode of the gallium nitride based enhancement mode transistor and the gallium nitride based barrier layer.

In some embodiments, the recess extends completely through the gallium nitride-based barrier layer to expose the gallium nitride-based channel layer.

In some embodiments, the recess further extends into a top surface of the gallium nitride based channel layer.

In some embodiments, the gate insulating layer includes an oxide layer.

In some embodiments, the recess extends only partially through the gallium nitride-based barrier layer, and wherein a gate electrode of the gallium nitride-based enhancement mode transistor directly contacts sidewalls and a bottom surface of the recess.

In some embodiments, the semiconductor integrated circuit may further include: a gallium nitride-based channel layer on the monolithic semiconductor substrate and a gallium nitride-based barrier layer on the gallium nitride-based channel layer opposite the monolithic semiconductor substrate. In such embodiments, the gallium nitride-based enhancement-mode transistor may include a gate electrode, a source electrode, and a drain electrode, and the gallium nitride-based barrier layer may be doped with a dopant of a first conductivity type under the source electrode and the drain electrode of the gallium nitride-based enhancement-mode transistor, and the gallium nitride-based barrier layer may be doped with a dopant of a second conductivity type under the gate electrode of the gallium nitride-based enhancement-mode transistor, wherein the first conductivity type is opposite the second conductivity type.

In accordance with additional embodiments of the present invention, methods of fabricating a gallium nitride based monolithic microwave integrated circuit device are provided in which a gallium nitride based channel layer is formed on a substrate. A gallium nitride-based barrier layer is formed on the gallium nitride-based channel layer opposite the substrate. An insulating layer is formed over the gallium nitride-based barrier layer, the insulating layer including a plurality of first gate electrode openings exposing the gallium nitride-based barrier layer, a plurality of second gate electrode openings exposing the gallium nitride-based barrier layer, and a plurality of source/drain electrode openings exposing the gallium nitride-based barrier layer. A recess is formed in a corresponding portion of the gallium nitride based barrier layer exposed by the first gate electrode opening. A gate insulating layer is formed in the first gate electrode opening, the gate insulating layer covering sidewalls and a bottom surface of the respective recess. A plurality of first source electrodes, a plurality of second source electrodes, a plurality of first drain electrodes, and a plurality of second drain electrodes are formed in the source/drain electrode openings in the insulating layer, the first source electrodes, the second source electrodes, the first drain electrodes, and the second drain electrodes directly contacting a top surface of the gallium nitride based barrier layer. First gate electrodes are formed in the first gate electrode openings on the gate insulating layer, each of the first gate electrodes extending into a corresponding one of the recesses. A second gate electrode is formed in a second gate electrode opening in the insulating layer, the second gate electrode directly contacting a top surface of the gallium nitride based barrier layer. Each set of the first source electrode, the first drain electrode, and the first gate electrode comprises an electrode of an enhancement mode transistor, and each set of the second source electrode, the second drain electrode, and the second gate electrode comprises an electrode of a depletion mode transistor.

Drawings

Fig. 1 is a schematic plan view of a conventional gallium nitride-based power semiconductor device controlled using a digital control signal supplied from an external control circuit.

Figure 2A is a schematic cross-sectional view of three regions of a gallium nitride based MMIC device including both depletion mode and enhancement mode transistors, according to an embodiment of the present invention.

Fig. 2B to 2D are schematic plan views corresponding to the three sectional areas illustrated in fig. 2A.

Figure 3 is a cross-sectional view of an alternative enhancement-mode transistor design that may be used in gallium nitride based MMIC devices according to embodiments of the present invention.

Figure 4 is a cross-sectional view of another alternative enhancement mode transistor design that may be used in gallium nitride based MMIC devices according to embodiments of the present invention.

Fig. 5A-5C are schematic plan views of gallium nitride based MMIC devices according to various embodiments of the present invention.

Figure 6 is a flow chart depicting a method of fabricating a gallium nitride based MMIC device in accordance with certain embodiments of the present invention.

Detailed Description

Gallium nitride based power semiconductor devices, such as gallium nitride based HEMT devices, are promising candidates for high power RF applications, such as high power amplifiers used in radio communication systems, radar and various other wireless applications. As used herein, the term "gallium nitride-based" refers to those semiconductor compounds that include at least gallium and nitrogen, including gallium nitride as well as ternary and quaternary compounds such as aluminum gallium nitride (AlGaN) and aluminum indium gallium nitride (AlInGaN). Gallium nitride based power semiconductor devices have been developed as both discrete devices coupled with other circuitry such as, for example, impedance matching networks, or as MMIC devices (e.g., multi-stage HEMT amplifiers with built-in impedance matching networks). In many applications, gallium nitride based power semiconductor devices are controlled by a control signal. Typically, commercially available digital circuits are used to generate the control signals supplied to the gallium nitride based power semiconductor devices. These digital circuits may include one or more additional semiconductor chips and are typically silicon-based semiconductor devices.

Fig. 1 is a schematic plan view of a conventional gallium nitride-based power semiconductor device controlled using a digital control signal. As shown in fig. 1, a gallium nitride based integrated circuit chip 10 is provided. The gallium nitride based integrated circuit chip 10 may include a base substrate 12 such as, for example, a silicon carbide semiconductor substrate having a plurality of gallium nitride based epitaxial layers formed thereon. Various input/output pads may be formed on the substrate 12 including, for example, RF input pads 14, RF output pads 16, bias signal pads 18, and control signal pads 20. A control circuit integrated circuit chip 30 may also be provided. The control circuit integrated circuit chip 30 may be implemented on a second semiconductor substrate 32, which second semiconductor substrate 32 may comprise, for example, a silicon substrate. Various input/output pads may be formed on substrate 32 of control circuit integrated circuit chip 30, including, for example, bias signal pads 34, control signal input pads 36, and control signal output pads 38. Although fig. 1 illustrates a single control circuit integrated circuit chip 30, it will be understood that multiple separate control circuit integrated circuit chips 30 may be required to generate the necessary control signals, especially if off-the-shelf digital circuitry is used to form the control circuitry.

In some cases (such as the example of fig. 1), the gallium nitride based integrated circuit chip 10 and the control circuit integrated circuit chip 30 may be mounted in a single package. As shown in fig. 1, in such embodiments, a plurality of bond wires or other interconnects 40 may be provided that connect various output pads 38 included in the control circuit integrated circuit chip 30 to the input pads 20 included in the gallium nitride based integrated circuit chip 10. In other cases, the two integrated circuit chips 10, 30 may be individually packaged and interconnected, for example, via control lines and/or bond wires on a printed circuit board. In either case, interconnecting the two integrated circuit chips 10, 30 tends to add significant additional complexity and expense to the fabrication process, and also reduces the performance of the device.

In accordance with an embodiment of the present invention, there is provided a gallium nitride-based MMIC device in which both an RF circuit and a control circuit for generating digital control signals for controlling the operation of the RF circuit are formed on a single monolithic substrate. Typically, gallium nitride based RF circuits are formed using depletion mode (normally on) transistors. However, digital control circuits formed exclusively using depletion mode transistors are more difficult to design, require significantly more chip area to implement, and use more power than digital control circuits implemented exclusively using enhancement mode transistors in combination with depletion mode transistors or digital control circuits implemented exclusively using enhancement mode transistors. As a result, digital control circuitry has not been integrated into conventional gallium nitride based RF MMIC devices.

Gallium nitride based MMIC devices according to embodiments of the present invention may be smaller, cheaper, and less complex than conventional multi-chip circuits that provide the same functionality. Furthermore, by integrating digital control circuitry into gallium nitride based MMICs, various performance advantages may be realized, including improved high temperature performance and faster operating speeds. Furthermore, currently available tools and fabrication techniques may be used to fabricate gallium nitride based MMIC devices according to embodiments of the present invention.

In some embodiments, gallium nitride-based MMIC devices are provided that include gallium nitride-based epitaxial structures formed on a substrate, such as, for example, a silicon carbide substrate. The gallium nitride-based epitaxial structure may include, for example, a gallium nitride-based channel layer and a gallium nitride-based barrier layer formed on the gallium nitride-based channel layer opposite the substrate. Additional epitaxial layers may be included as part of the gallium nitride based channel layer or the gallium nitride based barrier layer such as, for example, a buffer layer, strain balance layer, transition layer, etc. A plurality of depletion mode transistors may be formed on and in the gallium nitride based epitaxial structure. These depletion mode transistors may include a gate electrode, a source electrode, and a drain electrode. These electrodes may be formed on the gallium nitride-based barrier layer opposite the gallium nitride-based channel layer and may be in direct contact with the gallium nitride-based barrier layer.

Additionally, a plurality of enhancement-mode transistors may be formed on and in the gallium nitride based epitaxial structure. The enhancement mode transistor may likewise include a gate electrode, a source electrode, and a drain electrode. The source and drain electrodes may be formed on and may be in direct contact with the gallium nitride based barrier layer. A portion of the gallium nitride-based barrier layer between the source electrode and the drain electrode may be etched away to form an opening in the barrier layer that exposes the channel layer. Such as, for example, an oxide layer (e.g., SiO) may be formed in the opening₂) And the like, and the gate electrode may be formed on the gate insulating layer opposite the gallium nitride-based channel layer and the gallium nitride-based barrier layer.

In other embodiments, the enhancement-mode transistor may have a different design in which a portion of the gallium nitride based barrier layer between the source electrode and the drain electrode may be only partially etched away such that an opening formed in the gallium nitride based barrier layer does not expose the gallium nitride based channel layer. A gate electrode is formed in the opening in the gallium nitride based barrier layer.

In some embodiments, the depletion-mode transistor may comprise a "RF" depletion-mode transistor configured to operate on a radio frequency ("RF") signal, such as a transistor of a gallium nitride-based HEMT RF amplifier. In some embodiments, the depletion mode transistor may additionally comprise a "digital" depletion mode transistor as part of the digital control circuit. The size and layout of the digital depletion mode transistor and the RF depletion mode transistor may be different. The enhancement mode transistor may be a "digital" enhancement mode transistor that is part of a digital control circuit.

An embodiment of the present invention will now be described in more detail with reference to fig. 2A to 6.

Figure 2A is a schematic cross-sectional view of three regions of a gallium nitride based MMIC device including both depletion mode and enhancement mode transistors, according to an embodiment of the present invention. Fig. 2B to 2D are schematic plan views corresponding to the three cross-sectional areas illustrated in fig. 2A.

Referring to fig. 2A-2D, it can be seen that the gallium nitride based MMIC device 100 includes three different types of transistors, namely, an RF depletion mode transistor 200, a digital depletion mode transistor 300, and a digital enhancement mode transistor 400. Although fig. 2A illustrates only a single instance of each transistor 200, 300, 400 for simplicity of the drawing, it will be understood that in general a gallium nitride based MMIC device 100 will include a plurality of each type of transistor 200, 300, 400. It will also be understood that the digital depletion mode transistor 300 may be omitted in some embodiments.

As shown in fig. 2A, the RF depletion mode transistor 200, the digital depletion mode transistor 300, and the digital enhancement mode transistor 400 may all be formed on a monolithic substrate 110, such as, for example, a silicon carbide semiconductor substrate 110. For example, the substrate 110 may include a 4H-SiC or 6H-SiC substrate. Sapphire (Al) as a very common substrate material for gallium nitride based devices₂O₃) In contrast, silicon carbide has a much closer lattice match to gallium nitride based materials. The closer lattice match of silicon carbide may result in higher quality gallium nitride-based materials than are typically available on sapphire. Silicon carbide also has a very high thermal conductivity, so that the total output power of gallium nitride-based devices on silicon carbide is generally not limited by the thermal dissipation of the substrate, as is the case for the same devices formed on sapphire. Moreover, the availability of semi-insulating silicon carbide substrates may provide device isolation and reduced parasitic capacitance. Although silicon carbide may be used as the substrate material, embodiments of the present invention may utilize any suitable substrate such as sapphire, aluminum nitride, aluminum gallium nitride, silicon, GaAs, LGO, ZnO, LAO, InP, and the like.

As shown in fig. 2A, a gallium nitride-based epitaxial structure 120 is formed on a substrate 110. The gallium nitride based epitaxial structure 120 may include a first set of one or more gallium nitride based layers 130. The first set of gallium nitride based layers 130 may include, for example, Al_xGa_1-xN (where 0 ≦ x<1) Such as a gallium nitride based channel layer. In some embodiments of the present invention, the gallium nitride-based channel layer may have the formula Al_xGa_1-xN, where x ═ 0 indicates that the channel layer is a gallium nitride layer. However, it will be understood that in other embodiments, the gallium nitride based channel layer may also be a different gallium nitride based layer such as InGaN, AlInGaN, or the like. In example embodiments, the gallium nitride-based channel layer may be undoped or unintentionally doped, and may be grown to greater than aboutIs measured. The gallium nitride based channel layer may also be a multi-layer structure such as a superlattice and may include a combination of GaN, AlGaN, and the like. In some embodiments, the first set of gallium nitride-based layers 130 may include a gallium nitride-based channel layer and one or more additional layers such as, for example, buffer layers, nucleation layers, transition layers, and/or strain balance layers. For example, an aluminum nitride buffer layer may be included to provide an appropriate crystal structure transition between the silicon carbide substrate and the rest of the device. Herein, the first set of gallium nitride-based layers 130 will be referred to as gallium nitride-based channel layers 130, whether the first set of gallium nitride-based layers includes only gallium nitride-based channel layers or additional layers.

The gallium nitride based epitaxial structure 120 may also include a second set of one or more gallium nitride based layers 140. The second set of gallium nitride based layers 140 may include gallium nitride based barrier layers and may also include additional layers such as transition layers and/or strain balance layers. The second set of gallium nitride based layers will be referred to herein as gallium nitride based barrier layer 140 whether the second set of gallium nitride based layers includes only gallium nitride based barrier layers or additional layers. The band gap of the lower portion of the gallium nitride-based barrier layer 140 in contact with the upper surface of the gallium nitride-based channel layer 130 may exceed the band gap of the uppermost layer of the gallium nitride-based channel layer 130. Additionally, the gallium nitride-based channel layer 130 may have a greater electron affinity than the gallium nitride-based barrier layer 140. The energy of the conduction band edge of the gallium nitride-based channel layer 130 is less than the energy of the conduction band edge of the gallium nitride-based barrier layer 140 at the interface between the gallium nitride-based channel layer 130 and the gallium nitride-based barrier layer 140.

In certain embodiments, the gallium nitride based barrier layer 140 is AlN, AlInN, AlGaN, or AlInGaN, or a combination of layers thereof, having a thickness between about 0.1nm and about 30 nm. In some embodiments of the present invention, the gallium nitride-based barrier layer 140 is Al_xGa_1-xN, wherein x is more than 0 and less than 1. In a specific embodiment, the aluminum concentration is about 25%. However, in other embodiments of the present invention, the gallium nitride based barrier layer 140 comprises AlGaN having an aluminum concentration between about 5% and about 100%. In a specific embodiment of the invention, the aluminum concentration is greater than about 10%. In some embodiments, the gallium nitride-based barrier layer 140 may be undoped or doped with an n-type dopant to less than about 10¹⁹cm^-3The concentration of (c). The gallium nitride-based barrier layer 140 may be sufficiently thick and have a sufficiently high aluminum concentration to induce a significant carrier concentration at the interface between the gallium nitride-based channel layer 130 and the gallium nitride-based barrier layer 140. In an example embodiment, an uppermost portion of the gallium nitride-based channel layer 130 may include gallium nitride, and a lowermost portion of the gallium nitride-based barrier layer 140 may include aluminum gallium nitride.

As further shown in fig. 2A, the substrate 110 may include a first region 112 and a second region 114. The RF depletion mode transistor 200 may be formed in the first region 112 of the substrate 110, and the digital depletion mode transistor 300 and the digital enhancement mode transistor 400 may be formed in the second region 114 of the substrate 110.

Referring now to fig. 2A and 2B, each RF depletion mode transistor 200 includes a gate electrode 210, a source electrode 220, and a drain electrode 230. The gate electrode 210 may include relatively narrow gate fingers 210 extending in parallel between the source electrode 220 and the drain electrode 230. The "gate width" of a transistor refers to the distance that the gate finger 210 extends between or "overlaps" its associated source and drain electrodes 220, 230. As shown in fig. 2B, the gate width of the RF depletion mode transistor 200 may be relatively large. In the depicted embodiment, the width of the gate finger 210 of the RF depletion mode transistor is about 500 microns.

As further shown in fig. 2A, source/drain regions 142 may be formed in the gallium nitride based barrier layer 140 under the respective source and drain electrodes 220, 230. As shown, the source/drain regions 142 may extend into the gallium nitride based channel layer 130. Source/drain regions 142 may be doped (or more heavily doped) regions of gallium nitride based barrier layer 140. Source/drain regions 142 may be formed, for example, by ion implantation. Source/drain regions 142 may have any suitable doping concentration. In example embodiments, the source/drain regions 142 may have a size of about 1 × 10²⁰To 1X 10²¹cm³The doping concentration of (c). In other embodiments, source/drain regions 142 may extend only partially through, rather than completely through, gallium nitride-based barrier layer 140. In still other embodiments, the source/drain regions 142 may be omitted such that the source electrode 220 and the drain electrode 230 are formed directly on the gallium nitride based barrier layer 140. The digital depletion mode transistor 300 and the digital enhancement mode transistor 400, which will be discussed in more detail below, may have any of the configurations discussed above for the source/drain regions 142, including omitting the source/drain regions 142.

Although not shown in the figures, it will be understood that a plurality of RF depletion mode transistors 200 may be provided in the first region 112 of the substrate 110. These RF depletion mode transistors 200 may include a plurality of unit cell transistors electrically connected in parallel with each other. Each unit cell transistor 200 may share a source electrode 220 and/or a drain electrode 230 with one or more adjacent unit cell transistors 200.

An insulating layer 150 is formed on the top surface of the gallium nitride based barrier layer 140. The insulating layer 150 may include, for example, a nitride layer such as a silicon nitride layer. In some embodiments, the insulating layer 150 may serve as a passivation layer. The insulating layer 150 may additionally (or alternatively) insulate wings 212 extending laterally from an upper portion of the gate electrode 210 from the gallium nitride based barrier layer 140. Openings for the respective gate electrode 210, source electrode 220 and drain electrode 230 are provided in the insulating layer 150. These openings expose the gallium nitride-based barrier layer 140 so that the gate electrode 210, the source electrode 220, and the drain electrode 230 can directly contact the top surface of the gallium nitride-based barrier layer 140.

The depletion mode transistor 200 may include a HEMT transistor. Due to the difference in band gap between the gallium nitride-based barrier layer 140 and the gallium nitride-based channel layer 130 and the piezoelectric effect at the interface between the gallium nitride-based barrier layer 140 and the gallium nitride-based channel layer 130, a two-dimensional electron gas (2DEG) is induced in the gallium nitride-based channel layer 130 at the junction between the gallium nitride-based channel layer 130 and the gallium nitride-based barrier layer 140. The 2DEG serves as a high conductivity layer that allows conduction between the source and drain regions of the depletion mode transistor 200 below the source and drain electrodes 220 and 230, respectively. The source electrode 220 and the drain electrode 230 may directly contact the barrier layer 140. The gate finger 210 may also directly contact the gallium nitride based barrier layer 140 and be located between the source electrode 220 and the drain electrode 230. Although the gate finger 210 and the source and drain electrodes 220, 230 are all shown in fig. 2A as having the same "length" (i.e., the distance the electrodes extend in the X direction), it will be understood that, in practice, the gate finger 210 has a length that is substantially less than the length of the source and drain electrodes 220, 230, as can be seen in fig. 2B. It will also be understood that the source electrode 220 and the drain electrode 230 need not have the same length.

In some embodiments, the gate fingers 210 may comprise metal gate fingers. The particular material(s) used to form the gate fingers 210 may be selected based on, for example, the composition of the gallium nitride-based barrier layer 140. In an example embodiment, the gate fingers 210 may include one or more of Ni, Pt, and Au. The source electrode 220 and the drain electrode 230 may include one or more metals such as Ti, Ni, and Pt. In an example embodiment, the source electrode 220 and the drain electrode 230 may include a Ti/Si/Ni/Pt stack. The source electrode 220 and the drain electrode 230 may form an ohmic contact to the gallium nitride based barrier layer 140. As shown in fig. 2B, the gate electrode 210 may be closer to the source electrode 220 than the gate electrode 210 is to the drain electrode 230.

As further shown in fig. 2A and 2B, a separation layer 240 can be formed on top of the gate electrode 210 and on top portions of the insulating layer 150. A field plate 250 can be formed on top of the spacer layer 240. The field plate 250 can vertically overlap both a portion of the gate electrode 210 and a portion of the semiconductor structure 120 between the gate electrode 210 and the drain electrode 230. The field plate 250 is electrically isolated from both the gate electrode 210 and a portion of the semiconductor structure 120 that vertically overlaps the field plate 250. The field plate 250 may be connected to the source electrode 220 via an electrical connection not shown in the figure. The field plate 250 is a conductive plate that redistributes the electric field on the drain side of the transistor 200 in order to improve the breakdown voltage, gain and maximum operating frequency of the device.

Fig. 2A and 2C illustrate the design of a digital depletion mode transistor 300. The digital depletion mode transistor 300 may have similar layers and regions as the RF depletion mode transistor 200, but the dimensions of the various regions may vary greatly. As shown in fig. 2A and 2C, the digital depletion mode transistor 300 includes a gallium nitride-based channel layer 130 formed on a substrate 110 and a gallium nitride-based barrier layer 140 on the gallium nitride-based channel layer 130 opposite the substrate 110. The gallium nitride based barrier layer 140 may include source/drain regions 142. A gate electrode 310, a source electrode 320, and a drain electrode 330 are formed on the gallium nitride-based barrier layer 140. The gate electrode 310 extends in parallel between the source electrode 320 and the drain electrode 330.

An insulating layer 150 (e.g., a silicon nitride insulating layer) as discussed above is also formed on the top surface of the gallium nitride based barrier layer 140 in the second region 114 of the substrate 110. The gate electrode 310, the source electrode 320, and the drain electrode 330 are formed in respective openings in the insulating layer 150. Like depletion mode transistor 200, depletion mode transistor 300 may comprise a HEMT transistor and may operate in the same manner as depletion mode transistor 200 discussed above.

As shown in fig. 2C, the gate width of the digital depletion mode transistor 300 may be several orders of magnitude smaller than the gate width of the RF depletion mode transistor 200. In the depicted embodiment, the width of the gate electrode 310 of the digital depletion mode transistor is about 3 microns compared to the gate width of about 500 microns for the RF depletion mode transistor 200. In the depicted embodiment, the length of the gate electrode 310 of the digital depletion mode transistor is about 6 to 7 microns compared to a gate length of about 0.1 to 0.5 microns for the RF depletion mode transistor 200. As also shown in fig. 2C, in an example embodiment, the gate width of each of the depletion mode transistors 300 may be about half of its gate length. The gate electrode 310, the source electrode 320, and the drain electrode 330 may be formed of the same material as the corresponding material used to form the gate electrode 210, the source electrode 220, and the drain electrode 230 of the depletion mode transistor 200. The field plate 250 included in the depletion mode transistor 200 may be omitted in the depletion mode transistor 300. Additionally, in the depletion mode transistor 300, the gate electrode 310 may be located substantially equidistant from the source electrode 320 and the drain electrode 330.

Referring next to fig. 2A and 2D, each digital enhancement mode transistor 400 includes a gate electrode 410 between a source electrode 420 and a drain electrode 430. The gate width of the digital enhancement mode transistor 400 may be several orders of magnitude smaller than the gate width of the RF depletion mode transistor 200 and may be about the same as the gate width of the digital depletion mode transistor 300. The gate length of the digital enhancement mode transistor 400 may be an order of magnitude smaller than the gate length of the digital depletion mode transistor 300.

The digital enhancement mode transistor 400 may be similar to the digital depletion mode transistor 300 described above, but may have a different gate electrode design. In particular, referring first to fig. 2A, it can be seen that a recess 412 is formed in the gallium nitride based barrier layer 140 and the gate electrode 410 extends into the recess 412. In some embodiments, the recess 412 may extend completely through the gallium nitride based barrier layer 140 and may extend into the gallium nitride based channel layer 130. For example, in some embodiments, the recess 412 may extend between 1nm and 15nm into the gallium nitride based channel layer 130. A gate insulating layer 414 is formed in the recess 412. The gate insulating layer 414 may cover exposed sidewalls of the gallium nitride-based barrier layer 140 and exposed top surface of the gallium nitride-based channel layer 130 so as to isolate the gate electrode 410 from the gallium nitride-based channel layer 130. The modified gate electrode configuration causes transistor 400 to operate as an enhancement mode device. Advantageously, the enhancement mode transistor 400 may be formed using the same common process steps used to form the depletion mode transistors 200, 300 to allow both the depletion mode transistor and the enhancement mode transistor to be easily formed on the same substrate.

In some embodiments, the digital enhancement mode transistor 400 may have a gate width similar to that of the digital depletion mode transistor 300. For example, the gate width of each digital enhancement mode transistor 400 may be about 2 to 6 microns. The gate length of each digital enhancement mode transistor 400 may be smaller than the gate length of the digital depletion mode transistor. For example, the gate length of each digital enhancement mode transistor 400 may be less than 1 micron.

The RF depletion mode transistor 200 is typically implemented as a "unit cell" transistor, wherein a plurality of individual "unit cell" transistors are formed to be electrically connected in parallel so as to operate as a single transistor. A number of unit cells may be provided to increase the current carrying capability and voltage blocking capability of the device. In contrast, the digital depletion mode transistor 300 and the digital enhancement mode transistor 400 are typically implemented as separate transistors because these transistors pass much smaller current levels.

In some embodiments, the RF depletion mode transistor 200 may include an RF power amplifier, and the digital depletion mode transistor 300 and the digital enhancement mode transistor 400 may be arranged to form a digital control circuit that gates an RF signal input to the RF power amplifier. The digital depletion mode transistor 300 and the digital enhancement mode transistor 400 may be low voltage devices that generate relatively low electric fields.

Gallium nitride based MMIC devices according to embodiments of the present invention may exhibit a number of advantages. For example, the RF transistor and the digital control transistor may be formed on a common substrate, thereby allowing a transmission line connecting the digital control circuit to the RF circuit to be formed on the common substrate. This may avoid the necessity and associated cost of interconnecting multiple chips via wire bonding or other techniques. As such, gallium nitride based MMIC devices according to embodiments of the present invention may be smaller, less expensive, and less complex than conventional multi-chip circuits that provide the same functionality. Also, devices according to embodiments of the present invention may have much shorter control lines and may therefore exhibit improved performance. Additionally, by fabricating the digital transistors 300, 400 as gallium nitride based transistors, the high temperature performance and overall robustness of the circuit may be improved. Also, the digital enhancement mode transistor 400 can be formed using substantially the same process steps used to form the depletion mode transistors 200, 300, allowing the same process equipment to be used to form all three types of transistors on a common substrate. The fabrication of the enhancement mode transistor 400 may require additional steps of forming the recess 412 in the gallium nitride based barrier layer 140 and forming the gate insulation layer 414 in the second region of the substrate 110, but both are standard process steps that may be readily incorporated into the fabrication process.

The gallium nitride based enhancement mode transistors as shown in fig. 2A and 2D have a non-conventional design that may not represent an ideal way to fabricate gallium nitride based enhancement mode transistors. However, this design presents certain advantages when used to form gallium nitride based MMIC devices with integrated control circuitry, since the enhancement mode transistors can be easily fabricated during the process steps used to form the RF transistors.

In accordance with further embodiments of the present invention, gallium nitride based MMIC devices may be provided that include enhancement mode transistors with alternative designs. Fig. 3 and 4 illustrate two alternative enhancement mode transistor designs that may be used for gallium nitride based MMIC devices according to embodiments of the present invention. The enhancement-mode transistor design illustrated in fig. 3 and 4 may be used in place of the enhancement-mode transistor 400 of fig. 2A.

Fig. 3 is a cross-sectional view of an alternative enhancement-mode transistor 500 that may be used in a gallium nitride based MMIC device, according to an embodiment of the present invention. As can be seen by comparing fig. 3 with fig. 2A, the enhancement-mode transistor 500 may be similar to the enhancement-mode transistor 400 described above, but the enhancement-mode transistor 500 includes a recess 512 that does not extend completely through the gallium nitride-based barrier layer 140. The gate electrode 510 is formed in the recess 512 to cover a sidewall of the recess 512 and a bottom surface of the recess 512.

In the enhancement mode transistor 500, a gate insulating layer 414 may optionally be provided, since it may increase the forward gate voltage of the device. However, it will be understood that the gate insulator layer 414 may be omitted in other embodiments, as the remaining portion of the gallium nitride based barrier layer 140 may prevent the gate electrode 510 from forming a short circuit with the gallium nitride based channel layer 130. In embodiments including the gate insulating layer 414, the gate insulating layer 414 may be a high dielectric constant material (i.e., a material having a dielectric constant higher than that of silicon oxide), such as, for example, aluminum oxide, hafnium oxide, zirconium oxide, or any other suitable high dielectric constant material. In some embodiments, the gate electrode 510 may comprise nickel oxide, which may advantageously increase the threshold voltage of the enhancement mode transistor 500.

Fig. 4 is a cross-sectional view of another alternative enhancement-mode transistor 600 that may be used in a gallium nitride based MMIC device according to yet a further embodiment of the present invention. As shown in fig. 6, the enhancement mode transistor 600 has a somewhat different design than the enhancement mode transistor 400 of fig. 2A and 2D. In particular, the enhancement mode transistor 600 does not include a recess in the gallium nitride barrier layer 640, and does not include any gate insulating layer. However, the gallium nitride based barrier layer 640 of the enhancement mode transistor 600 does include a doped region 660 doped with a dopant of the second conductivity type under the gate electrode 610. For example, if the source/drain regions 142 in the gallium nitride based barrier layer 640 are doped with an n-type dopant, the doped regions 660 may be doped with a p-type dopant. The doped regions 660 may be formed, for example, by ion implantation. In an example embodiment, the doped region 660 may be doped with a p-type dopant such as magnesium. For example, it may be at 2 × 10¹³cm^-2To perform an 8keV implant.

Fig. 5A-5C are schematic plan views of gallium nitride based MMIC devices according to various embodiments of the present invention.

Referring first to fig. 5A, an MMIC digital power amplifier 700 is illustrated, the MMIC digital power amplifier 700 including an amplifier stage 710 formed using unit cell RF depletion mode transistors, a digital control block 720 formed using a combination of digital depletion mode transistors and digital enhancement mode transistors, and digital driver circuitry 730 formed using a combination of digital depletion mode transistors and digital enhancement mode transistors. MMIC digital power amplifier 700 may operate as a switching amplifier in which its amplifying transistors spend very little time in the linear region (i.e., the transistors are fully on or fully off), which may allow power amplifier 700 to achieve very high efficiency levels (e.g., greater than 90%).

Fig. 5B is a schematic plan view of an integrated circuit 800 including an RF transistor 810 and control circuitry 820 including both enhancement mode and depletion mode transistors. Control circuitry 820 modulates, limits, or otherwise controls the bias of RF transistor 810 in order to affect the linearity, temperature response, gain response, or other performance parameters of RF transistor 810.

Fig. 5C is a schematic plan view of an MMIC transmit/receive circuit 900 adapted in a time division duplex communication system that transmits and receives signals using the same frequency band. As shown in fig. 5C, the MMIC transmit/receive circuit 900 includes a high power amplifier circuit 910, a low noise amplifier circuit 920, a transmit/receive switch 930, and a digital control block 940. The high power amplifier circuit 910 and the low noise amplifier circuit 920 may each be implemented using a unit cell RF depletion mode transistor. Control block 940 may include bias control circuitry, for example, for high power amplifier 910 and/or for low noise amplifier 920, and may also include digital control circuitry for controlling the operation of transmit/receive switch 930. For example, control block 940 may be implemented using digital depletion mode transistors and digital enhancement mode transistors.

Figure 6 is a flow chart illustrating a method of fabricating a gallium nitride based MMIC device according to some embodiments of the present invention. As shown in fig. 6, operations may begin by forming a gallium nitride-based channel layer on a monolithic substrate (block 1000). The monolithic substrate may comprise, for example, a silicon carbide wafer, and the gallium nitride-based channel layer may comprise a single layer or multiple layers of gallium nitride-based materials. Next, a gallium nitride-based barrier layer may be formed on the gallium nitride-based channel layer opposite the substrate (block 1010). The gallium nitride-based barrier layer may include a single layer or multiple layers, and a lower portion of the gallium nitride-based barrier layer has a bandgap that is greater than a bandgap of an upper portion of the gallium nitride-based channel layer immediately adjacent to the gallium nitride-based barrier layer.

Next, an insulating layer is formed over the gallium nitride based barrier, the insulating layer including a plurality of first, second, and third gate electrode openings and a plurality of source/drain electrode openings exposing the gallium nitride based barrier layer (block 1020). A plurality of recesses are then formed in the gallium nitride based barrier in the first gate electrode opening (block 1030). A gate insulating layer is formed in the first gate electrode opening, the gate insulating layer covering sidewalls and a bottom surface of the respective recess (block 1040). The gate insulating layer may also cover a portion of the top surface of the insulating layer.

A plurality of first source electrodes, a plurality of second source electrodes, a plurality of first drain electrodes, and a plurality of second drain electrodes are formed in the source/drain electrode openings in the insulating layer such that the first source electrodes, the second source electrodes, the first drain electrodes, and the second drain electrodes directly contact a top surface of the gallium nitride based barrier layer (block 1050). An isolation implant process may then be performed (block 1060). First gate electrodes are formed in the first gate electrode openings on the gate insulating layer, each first gate electrode extending into a respective one of the recesses (block 1070). A second gate electrode is formed in a second gate electrode opening in the insulating layer, the second gate electrode directly contacting a top surface of the gallium nitride based barrier layer (block 1080). Each set of the first source electrode, the first drain electrode, and the first gate electrode comprises an electrode of an enhancement mode transistor, and each set of the second source electrode, the second drain electrode, and the second gate electrode comprises an electrode of a depletion mode transistor.

It will be understood that digital enhancement mode transistors (and digital depletion mode transistors) may be used to implement a variety of different circuits such as digital control circuitry, digital logic, and digital RF drivers.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this specification, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements present.

Relative terms, such as "below" or "above" or "upper" or "lower" or "horizontal" or "lateral" or "vertical" may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

Embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. The thickness of regions and layers in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing.

In the drawings and specification, there have been disclosed typical embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.