阅读说明：本技术 图像显示系统 (Image display system ) 是由 房雄·石井 维克托·斯通 鸟俊孝 于 2019-07-02 设计创作，主要内容包括：一种图像显示系统包括像素元件阵列、列驱动器、行驱动器、查找表存储器和控制器。接收包括输入图像的灰度信息的输入视频数据。根据查找表的规则,将输入视频数据分配给多个组,使用分配给每个组的各个输入视频数据为各个组生成二进制信号,至少一些组中的二进制信号的顺序被重新排列以形成各个二进制控制信号而状态变化不会发生冲突。控制器将二进制控制信号发送到列驱动器,并发送选择行驱动器的选择信号。或者,控制器将二进制控制信号发送到行驱动器,并发送选择列驱动器的选择信号。选择信号和二进制控制信号与时钟信号同步。(An image display system includes an array of pixel elements, a column driver, a row driver, a lookup table memory, and a controller. Input video data including grayscale information of an input image is received. According to the rule of the look-up table, input video data is assigned to a plurality of groups, binary signals are generated for the respective groups using the respective input video data assigned to each group, and the order of the binary signals in at least some of the groups is rearranged to form respective binary control signals without collision of state changes. The controller sends a binary control signal to the column driver and sends a select signal that selects the row driver. Alternatively, the controller transmits a binary control signal to the row driver and transmits a selection signal that selects the column driver. The selection signal and the binary control signal are synchronized with the clock signal.)

1. An image display system comprising:

a plurality of pixel elements arranged in an array;

a plurality of column drivers, each column driver electrically coupled to a column of the array, respectively;

a plurality of row drivers, each row driver electrically coupled to a respective row of the array;

a lookup table memory storing at least one lookup table, each lookup table including a rule for converting input video data into a control signal; and

a controller, the controller

Receiving the input video data composed of gray scale information of an input image including a plurality of rows and columns of a frame;

according to the rules of said look-up table

Assigning the input video data to a plurality of groups;

generating binary signals for respective groups of the plurality of groups using respective input video data assigned to each group; and is

Rearranging an order of the binary signals in at least some of the plurality of groups to form respective binary control signals, wherein state changes of the binary control signals in the plurality of groups do not conflict with each other;

performing one of:

sending the binary control signals to the plurality of column drivers to control the state of columns of the array of pixel elements and sending select signals that select the plurality of row drivers to select rows of the array of pixel elements to receive the binary control signals; or

Sending the binary control signals to the plurality of row drivers to control the state of rows of the array of pixel elements and sending select signals that select the plurality of column drivers to select columns of the array of pixel elements to receive the binary control signals; wherein:

the selection signal and the binary control signal are synchronized with a clock signal of the controller.

2. The system of claim 1, wherein the lookup table memory stores a plurality of lookup tables and the controller selects a lookup table from the plurality of lookup tables.

3. The system of claim 2, wherein the controller randomly selects a look-up table from the plurality of look-up tables.

4. The system of claim 2, wherein the input video data is received on a frame-by-frame basis, and the controller selects a look-up table for each frame from the plurality of look-up tables.

5. The system of claim 1 or 2, wherein the controller selects the look-up table to be used from the plurality of look-up tables in a predetermined order.

6. The system of claim 1 or 2, wherein the controller divides the input video data into a plurality of blocks and assigns the plurality of groups to the plurality of blocks.

7. The system of claim 6, wherein the controller assigns the plurality of groups to the plurality of blocks by assigning each of the plurality of groups to respective blocks of the plurality of blocks in one of a random order or a predetermined order.

8. The system of claim 7, wherein each block includes a plurality of rows of the array, and the predetermined order specifies that each of the plurality of groups is assigned to respective ones of the plurality of rows in respective blocks in one of a same order or a different order.

9. The system of claim 7, wherein the controller assigns the plurality of groups to the plurality of blocks by interleaving rows of the plurality of blocks.

10. The system of claim 1 or 2, wherein the selection signal is a row selection signal, the system further comprising a sequencer connected with the plurality of row drivers and receiving the row selection signal from the controller to sequentially select the plurality of row drivers.

11. The system of claim 1 or 2, further comprising a frame memory for temporarily storing the input video data, wherein the controller receives the input video data from the frame memory.

12. An image display method comprising:

receiving input video data composed of gray scale information of an input image including a plurality of rows and columns of a frame;

accessing a look-up table memory storing at least one look-up table, each look-up table comprising rules for converting the input video data into control signals;

according to the rules of the lookup table:

assigning the input video data to a plurality of groups;

generating binary signals for respective groups of the plurality of groups using respective input video data assigned to each group; and is

Rearranging an order of the binary signals in at least some of the plurality of groups to form respective binary control signals, wherein state changes of the binary control signals in the plurality of groups do not conflict with each other;

performing one of:

sending the binary control signals to a plurality of column drivers to control the state of columns of the array of pixel elements and sending select signals to select a plurality of row drivers to select rows of the array of pixel elements to receive the binary control signals; or

Sending the binary control signals to a plurality of row drivers to control the state of rows of the array of pixel elements and sending select signals that select a plurality of column drivers to select columns of the array of pixel elements to receive the binary control signals; wherein:

the selection signal and the binary control signal are synchronous with a clock signal of a controller;

the plurality of column drivers are electrically coupled to columns of the array, respectively, and

the plurality of row drivers are electrically coupled to rows of the array, respectively.

13. The method of claim 12, further comprising:

temporarily storing the input video data in a frame memory, wherein receiving the input video data comprises receiving the input video data from the frame memory at a controller.

14. The method of claim 12 or 13, wherein the look-up table memory stores a plurality of look-up tables, the method further comprising:

a look-up table is selected from the plurality of look-up tables.

15. The method of claim 14, wherein receiving the input video data comprises: receiving the input video data on a frame-by-frame basis; selecting the lookup table comprises: a respective look-up table for each frame is selected from the plurality of look-up tables.

16. The method of claim 12 or 13, wherein selecting the lookup table comprises: the lookup table to be used is selected from the plurality of lookup tables in a predetermined order.

17. The method of claim 12 or 13, further comprising:

dividing the input video data into a plurality of blocks; and

assigning the plurality of groups to the plurality of blocks.

18. The method of claim 17, wherein assigning the plurality of groups comprises: each of the plurality of groups is assigned to a respective block of the plurality of blocks in one of a random order or a predetermined order.

19. The method of claim 18, wherein each block includes a plurality of rows of the array, and the predetermined order specifies that each of the plurality of groups is assigned to respective ones of the plurality of rows in respective blocks in one of a same order or a different order.

Technical Field

The present disclosure relates to a display device including a control circuit to receive a digital image signal and to apply the digital image signal to control image display. More particularly, the present disclosure relates to a signal control method for controlling the non-sequence and timing of input status signals.

Background

When the display image is digitally controlled, the image quality is adversely affected because the image is not displayed in sufficient halftone. To increase the number of halftones, a higher input data rate is required.

However, to achieve higher input data rates in high resolution systems, the number of Integrated Circuit (IC) connection pads is increased.

Disclosure of Invention

A hardware structure including a display device and a control circuit using a digital image data processing method is proposed in us patent 8,228,595B 2. This disclosure describes how to display digital image data using binary digital pulse width modulation to control halftoning (also known as gray scale or gray scale) and with a reduced number of IC connection pads.

The image display system includes: a plurality of pixel elements arranged in an array; a plurality of column drivers, each column driver electrically coupled to a column of the array, respectively; a plurality of row drivers, each row driver electrically coupled to a respective row of the array; a lookup table memory storing at least one lookup table, each lookup table including a rule for converting input video data into a control signal; and a controller. The controller receives the input video data composed of gray scale information of an input image including a plurality of rows and columns of frames; and assigning the input video data to a plurality of groups according to rules of the look-up table; generating binary signals for respective groups of the plurality of groups using respective input video data assigned to each group; and rearranging an order of the binary signals in at least some of the plurality of groups to form respective binary control signals, wherein state changes of the binary control signals in the plurality of groups do not conflict with each other. The controller sends the binary control signals to the plurality of column drivers to control the state of columns of the array of pixel elements and sends select signals that select the plurality of row drivers to select rows of the array of pixel elements to receive the binary control signals. Alternatively, the controller sends the binary control signal to the plurality of row drivers to control a state of a row of the pixel element array, and sends a selection signal selecting the plurality of column drivers to select a column of the pixel element array to receive the binary control signal. The selection signal and the binary control signal are synchronized with a clock signal of the controller.

An image display method comprising: receiving input video data composed of gray scale information of an input image including a plurality of rows and columns of a frame; accessing a look-up table memory storing at least one look-up table, each look-up table comprising rules for converting the input video data into control signals; and, assigning the input video data to a plurality of groups according to the rules of a look-up table; generating binary signals for respective groups of the plurality of groups using respective input video data assigned to each group; and rearranging an order of the binary signals in at least some of the plurality of groups to form respective binary control signals, wherein state changes of the binary control signals in the plurality of groups do not conflict with each other. The method further comprises one of: sending the binary control signals to a plurality of column drivers to control the state of columns of the array of pixel elements and sending select signals to select a plurality of row drivers to select rows of the array of pixel elements to receive the binary control signals; alternatively, the binary control signals are sent to a plurality of row drivers to control the state of rows of the pixel element array, and selection signals that select a plurality of column drivers are sent to select columns of the pixel element array to receive the binary control signals. The select signal and the binary control signal are synchronized with a clock signal of a controller, the plurality of column drivers are electrically coupled to columns of the array, respectively, and the plurality of row drivers are electrically coupled to rows of the array, respectively.

Details of these and other embodiments and variations thereof as taught herein are described in detail below.

Drawings

The disclosure can be understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, according to common practice, the various features of the drawings are not to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. Moreover, unless otherwise indicated, like reference numerals refer to like elements.

Fig. 1 is a block diagram showing a configuration of an image display system.

Fig. 2 is a diagram for explaining a structure of representing video data having 16 gradations of 4 bits inputted to one pixel element.

Fig. 3 shows an example of invalid block and group combination in which the number of block writes occurring in a unit time exceeds 1.

Fig. 4 shows an example of an effective group combination using the group of fig. 3.

Fig. 5 shows an example of an effective group combination using the group of fig. 4.

Fig. 6A shows an arrangement of input video data.

Fig. 6B shows a matrix of video data.

Fig. 7 is a conceptual diagram of converting data inside the matrix shown in fig. 6B.

Fig. 8 shows bit data to be sent to the column driver and column select signals to be sent to the row driver.

Fig. 9 shows a flowchart of a display process of the image display system.

Fig. 10A shows a conceptual diagram of an example in which a row is divided into four blocks and displayed.

Fig. 10B shows a conceptual diagram of an example of interleaving display groups within four blocks of fig. 10A.

Fig. 10C shows a conceptual diagram of an example in which four blocks are dispersed and interleaved.

Detailed Description

The block diagram of fig. 1 shows the configuration of an image display system 101. The image display system includes an interface 111, a controller 112, a frame memory 113, a look-up table memory 114, a sequencer 115, a plurality of column drivers 116, a plurality of row drivers 117, and an array of pixel elements 118.

The array of pixel elements 118 may vary from image display system 101 to image display system. For example, if the image display system 101 is a High Definition Television (HDTV) system, the array 118 has 1920 (horizontal) × 1080 (vertical) pixel elements. Each pixel element is composed of a device that emits light (e.g., a plasma or Organic Light Emitting Diode (OLED)), a device that reflects light (e.g., a Liquid Crystal On Silicon (LCOS) or a micro-mirror), or a device that modulates light (e.g., a Liquid Crystal Display (LCD)) to create an image. In one example of operation, the column driver 116 sends control signals to the pixel elements in the row selected by the row driver 117. Signals sent by the column drivers 116 will be transferred to the pixel elements in the row. Assuming there are no duplicate images in the display, system 101 selects only one row at a time.

The controller 112 of fig. 1 controls which row should be selected by the sequencer 115 (e.g., by sequential selection) and signals are transmitted to the pixel elements in that row by the column drivers 116. The pixel element receiving the signal will emit, reflect or modulate light depending on the signal and the type of device forming the pixel element. Because the signals to the inputs of the interface 111 are continuous from top to bottom rows (see fig. 6A), the controller 112 also sends signals from top to bottom rows. The input data typically contains three parallel colors, either as High Definition Multimedia Interface (HDMI) or Video Graphics Array (VGA) signals. Depending on the type of display, the array of pixel elements 118 may require three colors, either in parallel or in sequence, for each color. If the display is a color sequential display, the array of pixel elements 118 requires each color sequentially. Herein, the terms "data" and "signal" are used interchangeably.

Interface 111 may be any type of wired or wireless connection to allow signals to be transmitted from outside of controller 112 to controller 112. These signals may be referred to herein as input video data and include or consist of gray scale information for an input image comprising a plurality of rows and columns of a frame. The interface 111 may be incorporated into the controller 112 or may be a separate device in communication with an input of the controller 112. One device that may be used for interface 111 is the Sil9187B HDMI port processor from Silicon Image, Inc. of Sonerville, Calif.

The timing of the input data and the timing of writing the signal to the pixel element do not generally match. It is desirable for the frame memory 113 to store (e.g., temporarily) the input data to adjust the timing and/or sequence of signals between the input data and the display device. In addition, the image display system 101 uses a memory that stores a sequence of rows and a sequence of data bits to write signals to the pixel elements. This memory is referred to as a look-up table (LUT) memory 114, as shown in fig. 1. The sequence of rows and data bits may be stored in the LUT memory 114.

Fig. 2 is a diagram for explaining a structure of representing video data having 16 gradations of 4 bits inputted to one pixel element. Line (a) in fig. 2 shows a temporal change of the 4-bit data string, and the horizontal axis shows time. Similarly, the D0, D1, D2 and D3 bits are allocated starting from the left. D0 is the Most Significant Bit (MSB) and D3 is the Least Significant Bit (LSB). When a signal is input and light is emitted, reflected, or modulated, one pixel element is a time corresponding to the elapsed time of the bit. The time of D1 is half that of D0(MSB), the time of D2 is half that of D1, and the time of D3(LSB) is half that of D2. The video data is controlled in synchronization with a system clock signal (e.g., from the controller 112). The length of D3(LSB) is determined by a predetermined number of clocks, which is defined as one unit (1U). The total time of D0 to D3(LSB) is 1U +2U +4U + 8U-15U, which is 15 times the length of the time of D3(LSB), which, by doing so and properly selecting the bits in D0 to D3, may produce 16 halftones. For example, when D0 is 1, the state remains for a time corresponding to 8U of the clock signal, and similarly, when D2 is 1, the state corresponding to 2U of the clock signal is maintained.

Line (b) included in fig. 2 shows an example of video data, which is represented 1010 in a 4-bit binary code. The pixel element remains ON for the time corresponding to D0 and D2. Thus, the pixel element can display 10/15 gray levels. Line (c) included in fig. 3 shows an example of video data, which represents 0110 in a 4-bit binary code. The pixel elements are turned on for the times corresponding to D1 and D2. Thus, the pixel element can display 6/15 gray levels.

Fig. 3 shows an example of an invalid 4-bit video data set. Each video data group is added to bits of D0 to D3, and finally 1 is added as an end bit. The lowermost row included in fig. 3 is data for determining a group to be selected in synchronization with a clock signal. In order to avoid collision between each video data, the start bit of each video data is shifted by 1U unit and arranged. However, for example, D2 of group i conflicts with D1 of group iv. Likewise, the end bit of group i conflicts with D3 of group ii and D2 of group iii. The end bit of group ii conflicts with D2 of group iv, and the end bit of group iii conflicts with D3 of group iv. Therefore, the video data of the groups i-iv cannot be transmitted by one signal line.

Fig. 4 shows an example of a valid 4-bit video data set (also referred to as table 1). Fig. 4 shows an active set constructed by swapping the order of the bits of fig. 3. Assuming that the arrangement order of the bits of the group i included in fig. 3 is 3210, the rearrangement order of the group i included in fig. 4 is 1230. Similarly, group ii is ordered 3102, group iii is ordered 2013, and group iv is ordered 0321. Thus, the video data of each group can be converted into video data in the order of 'i-ii-i-iii-iv-iv-i-iii-iii-ii-iii-ii-iv-i-i-ii-iv-iii'. Thus, each group can transmit without collision.

Fig. 5 shows another example of a valid 4-bit video data set (also referred to as table 2). Fig. 5 also shows an active set formed by swapping the order of the bits in fig. 3. The group i included in fig. 4 is sorted in the order of 3201. Similarly, group ii is ranked 0321, group iii is ranked 1230, and group iv is ranked 1023. Thus, the video data for each group may be represented in the order of 'i-ii-ii-iii-iv-iii-iv-iv-i-iii-ii-ii-iii-iv'. Thus, each group can transmit without collision.

In the case where the video data is 4 bits, when the groups i-iv are shifted by 5U at most, the arrangement of the effective groups exists in both modes of fig. 4 and 5. The information of one or both of fig. 4 and 5 is stored as a LUT in the LUT memory 114.

Fig. 6A shows that one frame of input data sequentially goes to the interface 111 from the top row to the bottom row. The inputted data shows the gradation of each pixel element written in hexadecimal.

Fig. 6B shows that the controller 112 stores the input data shown in fig. 6A in the frame memory 113. On the left side of fig. 6B is an image of data in the frame memory 113, which is arranged in a matrix corresponding to rows and columns of the pixel element array 118. The data in the right image of fig. 6B is shown in binary notation.

Fig. 7 is an image of converting data inside the matrix shown in fig. 6B. The data conversion is performed by interchanging the order of the bits according to the active set (stored as a LUT in the LUT memory 114) shown in fig. 4. For example, according to FIG. 2, column 2, row 0 data 1010 is expanded to control signals '10000000,0000,10, 0'. That is, since D0 is 1, this signal indicates that the pixel element is kept ON (and thus emits light, reflects light, or modulates light) for a time corresponding to 8U of the clock signal; since D1 is 0, the pixel element is kept OFF (no light is emitted, reflected light, or modulated light) for a time corresponding to 4U of the clock signal; since D2 is 1, the pixel element is kept ON for a time corresponding to the clock signal 2U; since D3 is 0, the pixel element is held OFF for a time corresponding to the clock signal 1U. The expanded control signals (e.g., corresponding to the sequence 3210 depicted in fig. 3) are translated or rearranged into control signals '10,0000,10000000,0' according to the LUT (e.g., corresponding to the sequence 1230 depicted in fig. 4). The converted control signals are sent to the column driver 116. The expansion and transformation of each data is performed in the same manner, as shown in detail in fig. 7. In this case, the conversion rules of group i are assigned to row 0 of the matrix, the conversion rules of group ii are assigned to row 1 of the matrix, the conversion rules of group iii are assigned to row 2 of the matrix, and the conversion rules of group iv are assigned to row 3 of the matrix. The allocation of the conversion rules may be replaced as appropriate.

More generally, the LUT stored in LUT memory 114 includes one or more rules for converting input data (e.g., data from interface 111) into control signals to drive the light emitting devices of an array of pixel elements (e.g., array of pixel elements 118). The rule describes the expansion of the input data into an expanded signal. By expanding the input data or signals, the present disclosure relates to a method of converting input data (e.g., initially in hexadecimal or binary format) into control signals (i.e., expanded signals) corresponding to a defined clock cycle duration during which the state of each bit of the input data is maintained. This may also be referred to as synchronizing the input data with the clock of the controller 112. For example, as shown in FIG. 2, the state of each bit of input data (in binary format) is distributed to hold a plurality of clocks or clock units U. These may be considered write signals for one or more pixel elements of the array, such that the pixel elements display gray scale in response to input data. The rules for converting the input data describe converting or rearranging the expanded signals into a defined order, as shown in the example of fig. 7. The defined order is such that: when used in conjunction with the rearranged spread signals of other pixel elements in the array, the resulting sequence provides a control signal that can control multiple pixels in rows and columns without conflict when signaling the new state of the pixel, as shown in the example of fig. 8. The LUT may also include rules for defining the groups. The LUT may define each rule based on the number of gray levels indicated in the input data, the input signal size for each pixel, the number of clock cycles of the input signal, the length of the extension signal, the size of the array, etc., or any combination of these characteristics.

Fig. 8 shows the sequence in which the converted control signals shown in fig. 7 are sent to the pixel element array 118. For simplicity of explanation, fig. 8 uses a display system composed of 16 pixel elements arranged in a 4 × 4 matrix. The control signal for each row ends with an end bit. The sequential signal is sequentially sent to the column driver 116 in synchronization with the clock signal. The transmitted signal is the shaded portion of fig. 8. For example, the control signal transmitted to column 1 is '0-1-1-1-1-1-0-0-1-1-1-1-1-0-0-1-1-0-1-1'. In addition, a row selection signal for selecting a row is sent from the controller 112 to the sequencer 115 according to the LUT. In this case, the row selection signal of the sequencer 115 is synchronized with the clock signal in the order of 'i-ii-i-iii-iv-iv-i-iii-iii-ii-iii-ii-ii-iv-i-i-ii-iv-iii-iv'. The sequencer 115 selects the row driver 117 according to a row selection signal. Thus, for example, in column 1, the first control signal '0' sent is sent to the column 1, row 0 pixel elements. The control signal '1' sent next is sent to the pixel elements of column 1, row 1. Further, a control signal '1' to be transmitted next is transmitted to the pixel elements of column 1 and row 0. That is, in the pixel elements of column 1, row 0, '0' is held for a time of 2U (corresponding to an OFF state), and then, '1' (corresponding to an ON state) is input. In other words, sequencer 115 sequentially selects a plurality of row drivers (or column drivers in an alternative arrangement). Sequencer 115 may be, for example, a Complementary Metal Oxide Semiconductor (CMOS) logic circuit that provides an address sequence for the row and column drivers.

As described above, by transmitting the control signals, the control signals of each row can be superimposed and transmitted to each column driver 116.

Although a display system consisting of 16 pixel elements of a 4 x 4 matrix has been described above, a higher resolution display system may also be used. For example, this system may also be used with a full High Definition (HD) of 1920 × 1080 or a 4K display system of 3840 × 2160. In this case, a demultiplexer (Demux) may be placed between the controller 112 and the column driver 116 because the columns are 1920 or 3840 pixel elements. Since the rows become 1080 or 2160 pixel elements, control can be performed using 270 or 540 blocks, respectively, when the control signals are divided into 4 groups. In addition, although the video data has been described as 4-bit data, 8-bit or 10-bit data may be used in order to further enhance the grayscale brightness. In this case, the combination of the effective solutions is two or more. For 10 bits of data, there are 70 effective solutions for partitioning. Thus, 1080 rows can be controlled with 16 sets.

According to the above system, a display system with high resolution of gray scale can be realized without complicating the structure of wiring and the like.

The controller 112 may select a look-up table to be used for each frame from a plurality of LUTs stored in the LUT memory 114. For example, by switching between table 1 and table 2 on a frame-by-frame basis, the mode of displaying a sequence of rows of video data corresponding to the rows will change from frame to frame. The viewer will recognize fewer artifacts using a non-sequential row driver. That is, for example, if a line is divided into some blocks such as Group 1-1-100, Group 2-101-200, etc., there is an irregularity between the 100 th and 101 th rows. If the boundary between blocks changes once per frame, this is an artifact that may be masked by the teachings herein. The controller may select a lookup table to be used from the plurality of lookup tables in a predetermined order. The controller may randomly select a look-up table to use from a plurality of look-up tables.

Referring to fig. 9, fig. 9 describes a display process of the image display system 101. Fig. 9 is a flow chart of the data and signal processing steps of the controller 112. The controller 112 may be implemented in hardware, software, or any combination thereof. The hardware may include a computer, an Application Specific Integrated Circuit (ASIC), a programmable logic array, an optical processor, a programmable logic controller, microcode, a microcontroller, a server, a microprocessor, a digital signal processor, or any other suitable circuit. The controller 112 may contain any of the foregoing hardware, alone or in combination. The controller 112 may be implemented using a general purpose computer or a general purpose processor having a computer program that, when executed, performs any of the respective methods, algorithms, and/or instructions described herein. A specific use computer/processor containing other hardware for carrying out any of the methods, algorithms, or instructions described herein may be employed.

In step S101, the controller 112 receives video data, for example, HDMI, from an external device via the interface 111.

In step S102, the controller 112 optionally stores the received video data in the frame memory 113.

In step S103, the controller 112 reads the video data stored in the frame memory 113 according to the LUT stored in the LUT memory 114. The LUT may be one of a plurality of LUTs stored in advance to define the valid group as described above. The LUT may be stored according to the display resolution, number of groups, or other characteristics of the system 101.

Each of the frame memory 113 and the LUT memory 114 may include any type of hardware memory. For example, each may be a Read Only Memory (ROM) device, a Random Access Memory (RAM) device, other types of memory, or a combination thereof. Any other suitable type of storage device or non-transitory storage medium may be used. The frame memory 113 and the LUT memory 114 may be the same or different types of memory. One or both of the frame memory 113 and the LUT memory 114 may be integrated with the controller 112 rather than being separate devices. The frame memory 113 and the LUT memory 114 may be combined in a single memory device.

In step S104, the controller 112 arranges the data order according to the LUT, and generates a control signal.

In step S105, the controller 112 transmits a control signal to the column driver 116.

In step S106, the controller 112 transmits a row selection signal to the sequencer 115 according to the LUT.

In step S107, the pixel element array 118 displays a selected pixel element based on a control signal from the column driver 116 and a row selection signal from the sequencer 115.

Fig. 10A to 10C show different allocation cases in which, in the case of dividing input video data into a plurality of blocks, a plurality of groups (e.g., groups i-iv in this example) are allocated to the plurality of blocks. As shown below, assigning the plurality of groups to the blocks may include assigning each of the plurality of groups to a respective block in a random order or a predetermined order. The predetermined order may specify that each group of the plurality of groups is assigned to a respective row of the plurality of rows in a respective block in a same order per block or in a different order per block.

In the example of fig. 10A, the row is divided into four blocks and displayed. In this case, the group displayed in each block is moved from group i to group iv in U units. Therefore, seams (e.g., boundaries) between the periodically occurring blocks may be uncomfortable to the viewer (e.g., identify discontinuities).

Fig. 10B is a conceptual diagram of an example of interleaving display groups within four blocks. In this case, the groups in each block are not arranged in the order of the groups i to iv. Thus, for example, by switching between the displays of fig. 10A and 10B, seams between blocks that occur periodically do not cause discomfort to the viewer.

Fig. 10C is a conceptual diagram of an example in which four blocks are dispersed and interleaved. In this case, different blocks are allocated to each row, and the boundaries between blocks are well dispersed. Thus, the viewer observes fewer boundaries between the periodically occurring blocks. In addition, switching between the displays of fig. 10A and 10C would make the seam less noticeable.

In this way, the controller 112 divides the video data of the frame memory 113 into a plurality of blocks according to the lookup table, and assigns a group to each video data constituting each block. In addition, the controller 112 may assign a group to each video data constituting each block according to a look-up table for each frame. In addition, the controller 112 may assign groups to each video data constituting each block in a predetermined order according to a lookup table. In addition, the controller 112 may assign groups to each video data constituting each block randomly (i.e., in a random order) according to the lookup table.

While the present invention has been described in terms of certain embodiments, it is to be understood that such disclosure is not to be interpreted as limiting. Various alterations and modifications will become apparent to those skilled in the art upon reading this disclosure. Accordingly, the appended claims should be construed to cover all such alternatives and modifications as fall within their scope.