Digital and PWM composite controller

文档序号：89480 发布日期：2021-10-08 浏览：16次中文

阅读说明：本技术 一种数字与pwm复合控制器 (Digital and PWM composite controller ) 是由陈小龙张弢骆建勇于 2021-07-29 设计创作，主要内容包括：本发明公开了一种数字与PWM复合控制器,包括一壳体,壳体内设有一电路板,电路板上集成了模拟量传输模块、数字量传输模块、控制模块、编译码模块、手轮处理模块、PWM输出模块和通讯模块；所述控制模块连接模拟量传输模块、编译码模块、手轮处理模块、PWM输出模块和通讯模块；编译码模块连接手轮处理模块、模拟量传输模块和数字量传输模块；将数字量输入输出、模拟量输入输出和PWM输出模块集成在一起,与现有各种功能分开设计模块相比,各模块之间的连线由电路板布局来实现,大大减小了接线麻烦和信号传输时的外部干扰。(The invention discloses a digital and PWM (pulse-width modulation) composite controller, which comprises a shell, wherein a circuit board is arranged in the shell, and an analog quantity transmission module, a digital quantity transmission module, a control module, a coding and decoding module, a hand wheel processing module, a PWM output module and a communication module are integrated on the circuit board; the control module is connected with the analog quantity transmission module, the coding and decoding module, the hand wheel processing module, the PWM output module and the communication module; the coding and decoding module is connected with the hand wheel processing module, the analog quantity transmission module and the digital quantity transmission module; the digital input/output module, the analog input/output module and the PWM output module are integrated, compared with the existing modules with various functions separately designed, the connection between the modules is realized by the layout of a circuit board, and the wiring trouble and the external interference during signal transmission are greatly reduced.)

1. A digital and PWM composite controller comprises a shell, and is characterized in that a circuit board is arranged in the shell, and an analog quantity transmission module, a digital quantity transmission module, a control module, a coding and decoding module, a hand wheel processing module, a PWM output module and a communication module are integrated on the circuit board; the control module is connected with the analog quantity transmission module, the coding and decoding module, the hand wheel processing module, the PWM output module and the communication module; the coding and decoding module is connected with the hand wheel processing module, the analog quantity transmission module and the digital quantity transmission module;

the analog quantity transmission module performs analog-to-digital conversion on an externally input analog quantity signal and then transmits the analog quantity signal to the control module for processing, and the signal transmission state is monitored and fed back to the control module through the coding and decoding module; the analog output signal output by the control module is output after being subjected to digital-to-analog conversion by the analog transmission module;

the digital quantity transmission module isolates an externally input digital quantity signal and transmits the signal to the control module for processing through the coding and decoding module; the digital output signal output by the control module is transmitted to the analog transmission module through the coding and decoding module, and the analog transmission module is isolated and then output;

the coding and decoding module is used for expanding the interface of the control module and transmitting signals;

the hand wheel processing module transmits hand wheel data to the control module through the coding and decoding module, transmits hand wheel signals to the control module after isolating the hand wheel signals, and also outputs hand wheel control signals output by the control module after isolating the hand wheel control signals;

the PWM output module outputs a corresponding PWM signal after isolating, voltage converting and driving the PWM control signal output by the control module;

the communication module is in communication connection with the upper computer, and data transmission is carried out between the control module and the upper computer.

2. The digital-to-PWM composite controller according to claim 1, wherein the analog transmission module comprises an analog input unit and an analog output unit; the analog input unit is connected with the analog output unit and the control module, and the analog output unit is connected with the coding and decoding module;

the analog quantity input unit filters, amplifies and converts an externally input analog quantity signal and then transmits the analog quantity signal to the control module;

the analog quantity output unit monitors the signal transmission state and feeds back the signal transmission state to the control module through the coding and decoding module; the analog output signal output by the control module is output after being subjected to digital-to-analog conversion by the analog output unit.

3. The digital and PWM composite controller according to claim 2, wherein the analog input unit comprises a first interface, an analog input chip, a first operational amplifier circuit, a second operational amplifier circuit, a third operational amplifier circuit and a fourth operational amplifier circuit;

the 1 st pin and the 2 nd pin of the first interface are in one-to-one connection with the first input pin and the second input pin of the first operational amplifier circuit; the 3 rd pin and the 4 th pin of the first interface are in one-to-one connection with the first input pin and the second input pin of the second operational amplifier circuit; the 5 th pin and the 6 th pin of the first interface are in one-to-one connection with the first input pin and the second input pin of the third operational amplifier circuit; the 7 th pin and the 8 th pin of the first interface are in one-to-one connection with the first input pin and the second input pin of the fourth operational amplifier circuit; the 9 th pin of the first interface is connected with the 10 th pin and the shielding ground; a first output pin and a second output pin of the first operational amplifier circuit are connected with an AIN _0P pin and an AIN _0GND pin of the analog input chip in a one-to-one manner; a first output pin and a second output pin of the second operational amplifier circuit are connected with an AIN _1P pin and an AIN _1GND pin of the analog input chip in a one-to-one manner; the first output pin and the second output pin of the third operational amplifier circuit 3 are connected with an AIN _2P pin and an AIN _2GND pin of the analog input chip in a one-to-one manner; a first output pin and a second output pin of the fourth operational amplifier circuit are connected with an AIN _3P pin and an AIN _3GND pin of the analog input chip in a one-to-one mode; the AVDD pin of the analog input chip inputs a first voltage, the DVDD pin of the analog input chip inputs a second voltage, and the AUX _ IN pin of the analog input chip is connected with the AUX _ GND pin and the analog ground; the REFIO pin and the REFCAP pin of the analog input chip are respectively connected with analog ground through a capacitor; of analogue input chipsA foot part,Foot and ALARM foot connection controlA module; the SCLK pin, the SDI pin and the SDO pin of the analog input chip are connected with the analog output unit and the control module; RDFGND pin of analog input chip,The pin, the AGND pin, the DA/SY pin and the DGND pin are all grounded.

4. The digital-to-PWM composite controller according to claim 3, wherein the analog output unit comprises a second interface, an analog output chip, a fifth resistor, a sixth resistor, a first output circuit, a second output circuit, a third output circuit and a fourth output circuit;

the DVcc pin of the analog output chip inputs a third voltage, and the analog output chipThe pin is connected with a digital ground; of analogue output chipsA foot part,Foot andthe pins are all connected with the control module; the SDIN pin of the analog quantity output chip is connected with the SDI pin of the analog quantity input chip and the control module, the SDO pin of the analog quantity output chip is connected with the SDO pin of the analog quantity input chip and the control module, the REFIN/REFOUT pin of the analog quantity output chip is connected with the GND pin of the analog quantity output chip and a digital ground through a capacitor, and the AVdd pin of the analog quantity output chip inputs a first voltage; VoutA pin, VoutB pin, VoutC pin and VoutD pin of analog output chip, first input pin of first output circuit, first input pin of second output circuit and first input pin of third output circuitThe input pin and the first input pin of the fourth output circuit are connected in a one-to-one manner; the AVss pin, the SIG _ GND pin, the DAC _ GND pin and the EPAD pin of the analog quantity output chip are all connected with an analog ground; a first output pin and a second output pin of the first output circuit are in one-to-one connection with a10 th pin and a9 th pin of the second interface; a first output pin and a second output pin of the second output circuit are in one-to-one connection with a pin 8 and a pin 7 of the second interface; the first output pin and the second output pin of the third output circuit are in one-to-one connection with the 6 th pin and the 5 th pin of the second interface; a first output pin and a second output pin of the fourth output circuit are in one-to-one connection with a4 th pin and a3 rd pin of the second interface; the 1 st pin of the second interface is connected with the 2 nd pin and the shielding ground, and the third output pins from the first output circuit to the fourth output circuit are all connected with the coding and decoding module; one end of the fifth resistor is used for inputting the first voltage, the other end of the fifth resistor is connected with one end of the sixth resistor and the second input pin of each output circuit, and the other end of the sixth resistor is connected with the analog ground.

5. The digital and PWM composite controller according to claim 4, wherein the digital quantity transmission module comprises a third interface, a fourth interface, a fifth interface, a sixth interface, a seventh interface, 48 digital quantity input units, 8 digital quantity output units and a monitoring feedback unit;

the 1 st pin of the third interface is connected with the input pin of the first digital quantity input unit, the 2 nd pin of the third interface is connected with the input pin of the second digital quantity input unit, and the 15 th pin of the third interface is connected with the input pin of the sixteenth digital quantity input unit; each pin of the fourth interface is correspondingly connected with the input pins from the seventeenth digital quantity input unit to the thirty-second digital quantity input unit, each pin of the fifth interface is correspondingly connected with the input pins from the thirty-third digital quantity input unit to the forty-eighth digital quantity input unit, and the output pins of each digital quantity input unit are connected with the coding and decoding module; and output pins of the first digital quantity output unit to the fourth digital quantity output unit are connected with the sixth interface, output pins of the fifth digital quantity output unit to the eighth digital quantity output unit are connected with the seventh interface, and input pins of the digital quantity output units are connected with the coding and decoding module.

6. The digital and PWM composite controller according to claim 5, wherein the control module comprises a main control chip and a burning interface; the PA0_ WKUP pin, the PA1 pin and the PD13 pin of the main control chip are all connected with a handwheel processing module; the PA2 pin, the PA3 pin, the PA4 pin, the PA5 pin, the PA6 pin, the PA7 pin, the PC8 pin and the PC9 pin of the main control chip are all connected with the communication module; the PA8 pin and the PD15 pin of the main control chip are both connected with the PWM output module; the PA9 pin, the PA10 pin and the PA13/JTMS/SWDIO pin of the main control chip are connected with the No. 2 pin, the No. 1 pin, the No. 5 pin and the No. 6 pin of the burning interface in a one-to-one manner; the PB8 pin, PB9 pin and PB12 pin of the main control chip and the analog output chipA foot part,A foot part,The feet are connected in a one-to-one way; PB10 pin, PB11 pin, PB13 pin, PB14 pin, PB15 pin, PE15 pin of the main control chip and analog input chipFoot, ALARM foot, SCLK foot, SDO foot, SDI foot,The feet are connected in a one-to-one way; the pins PC0 to PC7, PD0 to PD12 and PE5 of the main control chip are all connected with the coding and decoding module.

7. The digital and PWM composite controller according to claim 6, wherein the coding and decoding module comprises 9 decoding units and 4 latch units; each decoding unit and each latch unit are connected with the control module;

the first decoding unit to the seventh decoding unit are connected with the digital quantity transmission module and are used for decoding the digital quantity signals input by the digital quantity transmission module and then transmitting the digital quantity signals to the control module;

the eighth decoding unit is connected with the analog quantity transmission module and used for decoding the monitoring signal output by the analog quantity transmission module and transmitting the monitoring signal to the control module;

the ninth decoding unit is connected with the hand wheel processing module and is used for decoding hand wheel data transmitted by the hand wheel processing module and transmitting the decoded hand wheel data to the control module;

the first latch unit to the fourth latch unit are connected with the control module and the digital quantity transmission module, and are used for latching the digital quantity output signal output by the control module and then outputting the signal to the digital quantity transmission module.

8. The digital-to-PWM composite controller according to claim 7, wherein the handwheel processing module comprises a handwheel interface, a third optical coupler, a fourth optical coupler, a fifth optical coupler, a sixth optical coupler, a fourth resistor, a fifth resistor, a twelfth resistor, a thirteenth resistor, a seventh capacitor and an eighth capacitor;

a1 st pin and a2 nd pin of the hand wheel interface input a fifth voltage, and a9 th pin and a10 th pin of the hand wheel interface are connected and isolated; the 3 rd pin, the 4 th pin, the 5 th pin and the 6 th pin of the hand wheel interface are connected with the 1 st pin, the 3 rd pin, the 5 th pin and the 7 th pin of the third optical coupler in a one-to-one manner; the 11 th pin, the 12 th pin, the 13 th pin and the 7 th pin of the hand wheel interface are connected with the 3 rd pin, the 5 th pin, the 7 th pin and the 1 st pin of the fourth optocoupler in a one-to-one manner; the 14 th pin and the 15 th pin of the hand wheel interface are in one-to-one connection with the 1 st pin and the 4 th pin of the sixth optocoupler; the 8 th pin of the hand wheel interface J1 is connected with the E pin of the fifth optical coupler; the No. 2 pin, No. 4 pin, No. 6 pin and No. 8 pin of the third optocoupler are respectively connected with the ground in an isolated way through an indicator light; the 2 nd pin, the 4 th pin, the 6 th pin and the 8 th pin of the fourth optocoupler are respectively connected with the ground in an isolated way through an indicator light; the 16 th pin, the 14 th pin, the 12 th pin and the 10 th pin of the third optocoupler are connected with the 1 st pin, the 2 nd pin, the 3 rd pin and the 4 th pin of the fourth resistor in a one-to-one manner; the 16 th pin of the third optical coupler is connected with the 1 st pin of the fourth resistor and the A1 pin of the logic chip in the ninth decoding unit, the 14 th pin of the third optical coupler is connected with the 2 nd pin of the fourth resistor and the A2 pin of the logic chip in the ninth decoding unit, the 12 th pin of the third optical coupler is connected with the 3 rd pin of the fourth resistor and the A3 pin of the logic chip in the ninth decoding unit, the 10 th pin of the third optical coupler is connected with the 4 th pin of the fourth resistor and the A4 pin of the logic chip in the ninth decoding unit, the 16 th pin of the fourth optical coupler is connected with the 1 st pin of the fifth resistor and the A5 pin of the logic chip in the ninth decoding unit, the 14 th pin of the fourth optical coupler is connected with the 2 nd pin of the fifth resistor and the A6 pin of the logic chip in the ninth decoding unit, the 12 th pin of the fourth optical coupler is connected with the 3 rd pin of the fifth resistor and the A7 pin of the logic chip in the ninth decoding unit, and the 10 th pin of the fourth optical coupler is connected with the 4 th pin of the logic chip in the ninth decoding unit and the A8 pin of the ninth decoding unit, a fourth voltage is input to pins 5 to 8 of the fourth resistor and the fifth resistor; the 15 th pin, the 13 th pin, the 11 th pin and the 9 th pin of the third optical coupler and the fourth optical coupler are all connected with digital ground; a pin C of the fifth optical coupler inputs fifth voltage, a pin A of the fifth optical coupler inputs fourth voltage, a pin K of the fifth optical coupler is connected with a pin PD13 of the main control chip, and a pin 1 of the sixth optical coupler is connected with one end of a seventh capacitor and one end of a thirteenth resistor; a2 nd pin of the sixth optocoupler is connected with the other end of the seventh capacitor, the other end of the thirteenth resistor and the shielding ground; a4 th pin of the sixth optocoupler is connected with one end of the eighth capacitor and one end of the twelfth resistor; a pin 3 of the sixth optical coupler is connected with the other end of the eighth capacitor, the other end of the twelfth resistor and the shielding ground, a pin 8 of the sixth optical coupler inputs a fourth voltage, and a pin 7 and a pin 6 of the sixth optical coupler are connected with a pin PA0-WKUP and a pin PA1 of the main control chip in a one-to-one manner; the 5 th pin of the sixth optical coupler is connected with digital ground.

9. The type-B ultrasonic main control chip control system according to claim 8, wherein the PWM output module comprises an output voltage isolation chip, a second driving chip, a third driving chip, a fourth driving chip, a serial port, a first transient suppressor, a second transient suppressor, a fourteenth resistor and a fifteenth resistor;

a VCC1 pin of the output voltage isolation chip inputs a fourth voltage, an INA pin of the output voltage isolation chip is connected with one end of the fourteenth resistor and a PD15 pin of the main control chip, and an INB pin of the output voltage isolation chip is connected with one end of the fifteenth resistor and a PA8 pin of the main control chip; the GND1 pin of the output voltage isolation chip is connected with the other end of the fourteenth resistor, the other end of the fifteenth resistor and the digital ground; a VCC2 pin of the output voltage isolation chip inputs a sixth voltage, a GND2 pin of the output voltage isolation chip is connected with the ground, an OUTA pin of the output voltage isolation chip is connected with an INA pin of the second driving chip and an IN + pin of the fourth driving chip, and an OUTB pin of the output voltage isolation chip is connected with an INB pin of the second driving chip and an IN + pin of the third driving chip; a sixth voltage is input to an ENA pin, an ENB pin and a VDD pin of the second driving chip; the GND pin of the second driving chip is connected with the ground in an isolated mode, the OUTA pin of the second driving chip is connected with the 2 nd pin of the first transient suppressor and the 4 th pin of the serial port, the OUTB pin of the second driving chip is connected with the 1 st pin of the first transient suppressor and the 5 th pin of the serial port, the EN pins of the third driving chip and the fourth driving chip input sixth voltage, the GND pins of the third driving chip and the fourth driving chip are connected with the ground in an isolated mode, the VDD pins of the third driving chip and the fourth driving chip input fifth voltage, the OUT pin of the third driving chip is connected with the 2 nd pin of the second transient suppressor and the 1 st pin of the serial port, and the OUT pin of the fourth driving chip is connected with the 1 st pin of the second transient suppressor and the 2 nd pin of the serial port; the 3 rd pin of the first transient suppressor, the 3 rd pin of the second transient suppressor, and the 6 th pin, the 7 th pin, the 3 rd pin, the 8 th pin and the 9 th pin of the serial port are connected and isolated; the shell of the serial port is connected with a shielding ground.

10. The B-ultrasonic main control chip control system according to claim 9, wherein the communication module comprises a communication chip, a first ESD protection tube, a second ESD protection tube, a first net port, a second net port, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a ninth capacitor, a tenth capacitor, an eleventh capacitor and a twelfth capacitor;

the OE _ EXT/LRDn/SCLK pin, OUTLDL/LWRn/MOSI pin, SOF/LECSn/SCS _ ESC pin, WD _ TRIG/LINT/SINT pin, SYNC _ LATCH [0] pin, SYNC _ LATCH [1] pin, LAT _ IN/LRDY/MISO pin, EEP _ DONE pin of the communication chip are connected with PA5 pin, PA7 pin, PA4 pin, AP2 pin, PC8 pin, PC9 pin, AP6 pin and PA3 pin of the main control chip IN a one-to-one way manner; a P0_ TXOP pin of the communication chip is connected with a TD + pin of a first network port and an IO2 pin of a first ESD protection tube, a P0_ TXON pin of the communication chip is connected with a TD-pin of the first network port and an IO3 pin of the first ESD protection tube, a P0_ RXIP pin of the communication chip is connected with an RD + pin of the first network port and an IO4 pin of the first ESD protection tube, a P0_ RXIN pin of the communication chip is connected with an RD-pin of the first network port and an IO1 pin of the first ESD protection tube, a P0_ ACT pin of the communication chip is connected with an LED2_ Yellow + pin of the first network port, a TDC pin of the first network port is digitally connected through a sixteenth resistor and a ninth capacitor in turn, a RDC pin of the first network port is digitally connected through a seventeenth resistor and a tenth capacitor in turn, a P1_ ACT pin of the communication chip is connected with a TD + pin of a second network port and an IO 637 pin of the first ESD protection tube, a TD-P53962 pin of the communication chip is connected with an IO-IO port and an IO3 ESD protection tube, the P1_ RXIP pin of the communication chip is connected with the RD + pin of the second network port and the IO4 pin of the second ESD protection tube, the P1_ RXIN pin of the communication chip is connected with the RD-pin of the second network port and the IO1 pin of the second ESD protection tube, the P1_ ACT pin of the communication chip is connected with the LED2_ Yellow + pin of the second network port, the TDC pin of the second network port is connected with the digital ground sequentially through the eighteenth resistor and the eleventh capacitor, and the RDC pin of the second network port is connected with the digital ground sequentially through the nineteenth resistor and the twelfth capacitor.

Technical Field

The invention relates to the technical field of electronics, in particular to a digital and PWM (pulse width modulation) composite controller.

Background

In the current EtherCAT bus laser scheme, if a PWM signal is needed to control a laser, a PWM module needs to be added independently; in the existing module, digital input and output, analog input and output and high-precision PWM output are designed into independent circuit modules respectively; aiming at the market of laser cutting machine tools, each module is independently separated, wiring is troublesome in field use, cost is high, the modules are easily affected by external interference when signals are transmitted, and anti-interference performance is poor.

Thus, the prior art has yet to be improved and enhanced.

Disclosure of Invention

In view of the defects of the prior art, the invention aims to provide a digital and PWM composite controller to solve the problems of wiring trouble and poor interference caused by independent separation of modules of the existing digital input/output, analog input/output and PWM output.

In order to achieve the purpose, the invention adopts the following technical scheme:

a digital and PWM composite controller comprises an analog quantity transmission module, a digital quantity transmission module, a control module, a coding and decoding module, a hand wheel processing module, a PWM output module and a communication module; the control module is connected with the analog quantity transmission module, the coding and decoding module, the hand wheel processing module, the PWM output module and the communication module; the coding and decoding module is connected with the hand wheel processing module, the analog quantity transmission module and the digital quantity transmission module;

the coding and decoding module is used for expanding the interface of the control module and transmitting signals;

the PWM output module outputs a corresponding PWM signal after isolating, voltage converting and driving the PWM control signal output by the control module;

the communication module is in communication connection with the upper computer, and data transmission is carried out between the control module and the upper computer.

In the digital and PWM composite controller, the analog transmission module comprises an analog input unit and an analog output unit; the analog input unit is connected with the analog output unit and the control module, and the analog output unit is connected with the coding and decoding module;

the analog input unit filters, amplifies and converts an externally input analog signal and transmits the analog signal to the control module;

In the digital and PWM composite controller, the analog input unit comprises a first interface, an analog input chip, a first operational amplifier circuit, a second operational amplifier circuit, a third operational amplifier circuit and a fourth operational amplifier circuit;

the 1 st pin and the 2 nd pin of the first interface are in one-to-one connection with the first input pin and the second input pin of the first operational amplifier circuit; the 3 rd pin and the 4 th pin of the first interface are in one-to-one connection with the first input pin and the second input pin of the second operational amplifier circuit; the 5 th pin and the 6 th pin of the first interface are in one-to-one connection with the first input pin and the second input pin of the third operational amplifier circuit; the 7 th pin and the 8 th pin of the first interface are in one-to-one connection with the first input pin and the second input pin of the fourth operational amplifier circuit; the 9 th pin of the first interface is connected with the 10 th pin and the shielding ground; a first output pin and a second output pin of the first operational amplifier circuit are connected with an AIN _0P pin and an AIN _0GND pin of the analog input chip in a one-to-one manner; a first output pin and a second output pin of the second operational amplifier circuit are connected with an AIN _1P pin and an AIN _1GND pin of the analog input chip in a one-to-one manner; the first output pin and the second output pin of the third operational amplifier circuit 3 are connected with an AIN _2P pin and an AIN _2GND pin of the analog input chip in a one-to-one manner; a first output pin and a second output pin of the fourth operational amplifier circuit are connected with an AIN _3P pin and an AIN _3GND pin of the analog input chip in a one-to-one mode; the AVDD pin of the analog input chip inputs a first voltage and an analog inputA DVDD pin of the chip inputs a second voltage, and an AUX _ IN pin of the analog input chip is connected with an AUX _ GND pin and an analog ground; the REFIO pin and the REFCAP pin of the analog input chip are respectively connected with analog ground through a capacitor; of analogue input chipsA foot part,The foot and the ALARM foot are both connected with the control module; the SCLK pin, the SDI pin and the SDO pin of the analog input chip are connected with the analog output unit and the control module; RDFGND pin of analog input chip,The pin, the AGND pin, the DA/SY pin and the DGND pin are all grounded.

In the digital and PWM composite controller, the analog output unit comprises a second interface, an analog output chip, a fifth resistor, a sixth resistor, a first output circuit, a second output circuit, a third output circuit and a fourth output circuit;

the DVcc pin of the analog output chip inputs a third voltage, and the analog output chipThe pin is connected with a digital ground; of analogue output chipsA foot part,Foot andthe pins are all connected with the control module; the SCLK pin of the analog output chip is connected with the SCLK pin and the control module of the analog input chip, the SDIN pin of the analog output chip is connected with the SDI pin and the control module of the analog input chip, and the SDO pin of the analog output chip is connected with the S pin of the analog input chipThe device comprises a DO pin and a control module, wherein the REFIN/REFUT pin of an analog output chip is connected with a GND pin and a digital ground of the analog output chip through a capacitor, and an AVdd pin of the analog output chip inputs a first voltage; the VoutA pin, the VoutB pin, the VoutC pin and the VoutD pin of the analog quantity output chip are connected with the first input pin of the first output circuit, the first input pin of the second output circuit, the first input pin of the third output circuit and the first input pin of the fourth output circuit in a one-to-one mode; the AVss pin, the SIG _ GND pin, the DAC _ GND pin and the EPAD pin of the analog quantity output chip are all connected with an analog ground; a first output pin and a second output pin of the first output circuit are in one-to-one connection with a10 th pin and a9 th pin of the second interface; a first output pin and a second output pin of the second output circuit are in one-to-one connection with a pin 8 and a pin 7 of the second interface; the first output pin and the second output pin of the third output circuit are in one-to-one connection with the 6 th pin and the 5 th pin of the second interface; a first output pin and a second output pin of the fourth output circuit are in one-to-one connection with a4 th pin and a3 rd pin of the second interface; the 1 st pin of the second interface is connected with the 2 nd pin and the shielding ground, and the third output pins from the first output circuit to the fourth output circuit are all connected with the coding and decoding module; one end of the fifth resistor is used for inputting the first voltage, the other end of the fifth resistor is connected with one end of the sixth resistor and the second input pin of each output circuit, and the other end of the sixth resistor is connected with the analog ground.

In the digital and PWM composite controller, the digital quantity transmission module comprises a third interface, a fourth interface, a fifth interface, a sixth interface, a seventh interface, 48 digital quantity input units, 8 digital quantity output units and a monitoring feedback unit;

In the digital and PWM composite controller, the control module comprises a main control chip and a burning interface; the PA0_ WKUP pin, the PA1 pin and the PD13 pin of the main control chip are all connected with a handwheel processing module; the PA2 pin, the PA3 pin, the PA4 pin, the PA5 pin, the PA6 pin, the PA7 pin, the PC8 pin and the PC9 pin of the main control chip are all connected with the communication module; the PA8 pin and the PD15 pin of the main control chip are both connected with the PWM output module; the PA9 pin, the PA10 pin and the PA13/JTMS/SWDIO pin of the main control chip are connected with the No. 2 pin, the No. 1 pin, the No. 5 pin and the No. 6 pin of the burning interface in a one-to-one manner; the PB8 pin, PB9 pin and PB12 pin of the main control chip and the analog output chipA foot part,A foot part,The feet are connected in a one-to-one way; PB10 pin, PB11 pin, PB13 pin, PB14 pin, PB15 pin, PE15 pin of the main control chip and analog input chipFoot, ALARM foot, SCLK foot, SDO foot, SDI foot,The feet are connected in a one-to-one way; the pins PC0 to PC7, PD0 to PD12 and PE5 of the main control chip are all connected with the coding and decoding module.

In the digital and PWM composite controller, the coding and decoding module comprises 9 decoding units and 4 latch units; each decoding unit and each latch unit are connected with the control module;

In the digital and PWM composite controller, the hand wheel processing module comprises a hand wheel interface, a third optical coupler, a fourth optical coupler, a fifth optical coupler, a sixth optical coupler, a fourth resistor, a fifth resistor, a twelfth resistor, a thirteenth resistor, a seventh capacitor and an eighth capacitor;

In the digital and PWM composite controller, the PWM output module comprises an output voltage isolation chip, a second driving chip, a third driving chip, a fourth driving chip, a serial port, a first transient suppressor, a second transient suppressor, a fourteenth resistor and a fifteenth resistor;

In the digital and PWM composite controller, the communication module comprises a communication chip, a first ESD protection tube, a second ESD protection tube, a first network port, a second network port, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a ninth capacitor, a tenth capacitor, an eleventh capacitor and a twelfth capacitor;

Compared with the prior art, the digital and PWM composite controller provided by the invention comprises a shell, wherein a circuit board is arranged in the shell, and an analog quantity transmission module, a digital quantity transmission module, a control module, a coding and decoding module, a hand wheel processing module, a PWM output module and a communication module are integrated on the circuit board; the control module is connected with the analog quantity transmission module, the coding and decoding module, the hand wheel processing module, the PWM output module and the communication module; the coding and decoding module is connected with the hand wheel processing module, the analog quantity transmission module and the digital quantity transmission module; the analog quantity transmission module performs analog-to-digital conversion on an externally input analog quantity signal and then transmits the analog quantity signal to the control module for processing, and the signal transmission state is monitored and fed back to the control module through the coding and decoding module; the analog output signal output by the control module is output after being subjected to digital-to-analog conversion by the analog transmission module; the digital quantity transmission module isolates an externally input digital quantity signal and transmits the signal to the control module for processing through the coding and decoding module; the digital output signal output by the control module is transmitted to the analog transmission module through the coding and decoding module, and the analog transmission module is isolated and then output; the coding and decoding module is used for expanding the interface of the control module and transmitting signals; the hand wheel processing module transmits hand wheel data to the control module through the coding and decoding module, transmits hand wheel signals to the control module after isolating the hand wheel signals, and also outputs hand wheel control signals output by the control module after isolating the hand wheel control signals; the PWM output module outputs a corresponding PWM signal after isolating, voltage converting and driving the PWM control signal output by the control module; the communication module is in communication connection with the upper computer, and data transmission is carried out between the control module and the upper computer. The digital input/output module, the analog input/output module and the PWM output module are integrated, compared with the existing modules with various functions separately designed, the connection between the modules is realized by the layout of a circuit board, and the wiring trouble and the external interference during signal transmission are greatly reduced.

Drawings

Fig. 1 is a block diagram of a digital and PWM composite controller according to the present invention.

Fig. 2 is a circuit diagram of an analog input unit according to the present invention.

Fig. 3 is a circuit diagram of a part of the analog output unit provided by the invention.

Fig. 4 is another circuit diagram of a portion of the analog output unit provided by the present invention.

Fig. 5 is a circuit diagram of a portion of the digital transmission module provided in the present invention.

Fig. 6 is another circuit diagram of a digital transmission module according to the present invention.

Fig. 7 is a circuit diagram of a first digital input unit provided by the present invention.

Fig. 8 is a circuit diagram of a first digital quantity output unit provided by the present invention.

Fig. 9 is a circuit diagram of a monitoring feedback unit provided by the present invention.

Fig. 10 is a circuit diagram of a control module provided in the present invention.

FIG. 11 is a block diagram of 9 decoding units according to the present invention.

Fig. 12 is a block diagram of 4 latch units according to the present invention.

FIG. 13 is a circuit diagram of a first decoding unit according to the present invention.

FIG. 14 is a circuit diagram of a seventh decoding unit according to the present invention.

FIG. 15 is a circuit diagram of an eighth decoding unit according to the present invention.

FIG. 16 is a circuit diagram of a ninth decoding unit according to the present invention.

Fig. 17 is a circuit diagram of a first latch unit according to the present invention.

Fig. 18 is a circuit diagram of a portion of a handwheel processing module in accordance with the present invention.

Fig. 19 is another circuit diagram of a handwheel processing module according to the present invention.

Fig. 20 is a circuit diagram of a PWM output module according to the present invention.

Fig. 21 is a circuit diagram of a first part of a communication module provided by the present invention.

Fig. 22 is a circuit diagram of a second part of the communication module provided by the invention.

Fig. 23 is a circuit diagram of a third part of the communication module provided by the invention.

Detailed Description

The invention provides a digital and PWM composite controller. In order to make the objects, technical solutions and effects of the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Referring to fig. 1, a digital and PWM composite controller (having a housing with a circuit board therein) provided in an embodiment of the present invention is disposed on a machine tool and communicates with a CNC system on an upper computer; the circuit board is integrated with an analog quantity transmission module 10, a digital quantity transmission module 20, a control module 30, a coding and decoding module 40, a hand wheel processing module 50, a PWM output module 60 and a communication module 70. The control module 30 is connected with the analog quantity transmission module 10, the coding and decoding module 40, the hand wheel processing module 50, the PWM output module 60 and the communication module 70; the codec module 40 is connected with the handwheel processing module 50, the analog quantity transmission module 10 and the digital quantity transmission module 20.

The analog transmission module 10 performs analog-to-digital conversion on an externally input analog signal, transmits the analog signal (transmitted through an SPI bus) to the control module 30 (the processing method is the prior art), monitors a signal transmission state (whether short circuit, overload or overheating occurs, and transmits a dactat [1..4] signal), and feeds the signal back to the control module 30 through the coding and decoding module; the control module 30 controls the voltage (e.g. 0-10V) of the analog output signal to be output, and the analog transmission module 10 performs digital-to-analog conversion and then outputs the analog output signal to control the working state (e.g. height, gas size, proportional valve, motor rotation speed, laser energy, etc.) of the connected device.

After the digital quantity transmission module 20 isolates the digital quantity signal (24V) input from the outside, the signal is transmitted to the control module 30 through the coding and decoding module to be processed (the processing mode is the prior art); the control module 30 transmits the digital output signal DB _ [0..7] to be output to the analog transmission module 10 through the codec module, and outputs and controls the working state of the connected device (e.g. the on/off of the relay) after the isolation.

The codec module 40 is used to extend the interface of the control module 30 and perform parallel communication.

The hand wheel processing module 50 transmits externally input hand wheel data to the control module 30 through the codec module 40, transmits hand wheel signals to the control module 30 after isolating the hand wheel signals, and outputs hand wheel control signals output by the control module 30 after isolating the hand wheel signals.

The PWM output module 60 isolates, converts, and drives the PWM control signals (FOUT signal and PWM signal) output by the control module 30 to output corresponding PWM signals (FOUT 5V signal, FOUT24V signal, PWM5V signal, and PWM24V signal).

The communication module 70 is externally connected with the upper computer and is used for realizing the data link layer communication between the control module 30 and the upper computer.

During specific implementation, for example, the distance between the cutting head on the machine tool and the steel plate to be cut is different, the generated voltage is also different (voltage range is 0-10V), the voltage (such as 5V) fed back by the cutting head is an analog signal, the analog signal is transmitted to the control module 30 for processing after analog-to-digital conversion by the analog transmission module 10, the control module 30 uploads the voltage value to the CNC system on the upper computer through the communication module 70, the CNC system can judge whether the current distance is proper (too high cutting cannot be achieved, too low steel plate burning can be achieved) according to the voltage value, the CNC system outputs the height value of the shaft to be adjusted according to the distance, the height value is transmitted to the control module 30 through the communication module 70, the control module 30 transmits the height value to the analog transmission module 10 for digital-to-analog conversion, and then outputs the corresponding height voltage to the shaft, and the height of the shaft can be adjusted.

The digital quantity signal is similar to the analog quantity signal, except that the input path sequentially passes through the digital quantity transmission module 20, the coding and decoding module 40 and the control module 30 and then reaches the communication module 70, and is uploaded to the upper computer for processing through an EtherCAT bus; the output path is the opposite of the input path. The digital quantity signal is used for other controls, such as all switches are controlled by the digital quantity signal.

The input and output of the analog quantity transmission module 10, the digital quantity transmission module 20, the handwheel processing module 50, the PWM output module 60 and the communication module 70 are not in sequence, and each module can work as long as signals are provided or required to be output from the outside.

Compared with the existing design that each module is separately and independently designed, the present embodiment integrates various functions on one circuit board, and the connection between the modules is through the wiring connection on the circuit board. One integrated module can completely solve all application scenes without redundant control modules; the connecting wire required by the connection between the modules in the prior art is omitted, the wiring trouble and the external interference during signal transmission are greatly reduced, the cost is saved, and the anti-interference performance is improved.

Referring to fig. 2, the analog transmission module 10 includes an analog input unit 110 and an analog output unit 120; the analog input unit 110 is connected to the analog output unit 120 and the control module 30, and the analog output unit 120 is connected to the codec module 40. The analog quantity input unit filters, amplifies and converts an externally input analog quantity signal and then transmits the analog quantity signal to the control module; the analog quantity output unit monitors the signal transmission state and feeds back the signal transmission state to the control module through the coding and decoding module; the analog output signal output by the control module is output after being subjected to digital-to-analog conversion by the analog output unit.

It should be understood that in each circuit diagram, the triangles indicate the analog lines successively shortened to indicate the digital ground, the EARTH marks indicate the shielding ground (connecting the housing), and the 0V marks indicate the isolation of 24V.

In this embodiment, the analog input unit 110 includes a first interface P1, an analog input chip U1 with a model number of ADS8664IDBT being preferred, a first operational amplifier circuit 111, a second operational amplifier circuit 112, a third operational amplifier circuit 113, and a fourth operational amplifier circuit 114; the 1 st pin and the 2 nd pin of the first interface P1 are connected with the first input pin and the second input pin of the first operational amplifier circuit 111 in a one-to-one manner; the 3 rd pin and the 4 th pin of the first interface P1 are connected with the first input pin and the second input pin of the second operational amplifier circuit 112 in a one-to-one manner; the 5 th pin and the 6 th pin of the first interface P1 are connected with the first input pin and the second input pin of the third operational amplifier circuit 113 in a one-to-one manner; the 7 th pin and the 8 th pin of the first interface P1 are connected with the first input pin and the second input pin of the fourth operational amplifier circuit 114 in a one-to-one manner; the 9 th pin of the first interface P1 is connected with the 10 th pin and the shielding ground (all EARTH in this embodiment means shielding ground); the first output pin and the second output pin of the first operational amplifier circuit 111 are connected with an AIN _0P pin and an AIN _0GND pin of the analog input chip U1 in a one-to-one manner; the first output pin and the second output pin of the second operational amplifier circuit 112 are connected with the AIN _1P pin and the AIN _1GND pin of the analog input chip U1 in a one-to-one manner; the first output pin and the second output pin of the third operational amplifier circuit 113 are connected with the AIN _2P pin and the AIN _2GND pin of the analog input chip U1 in a one-to-one manner; the first output pin and the second output pin of the fourth operational amplifier circuit 114 are connected with the AIN _3P pin and the AIN _3GND pin of the analog input chip U1 in a one-to-one manner; the AVDD pin of the analog input chip U1 inputs a first voltage +5V (connected to the first power supply terminal, in specific implementation, the AVDD pin can be grounded through two capacitors connected in parallel, and the capacitors filter the input first voltage + 5V), the DVDD pin of the analog input chip U1 inputs a second voltage +3V3_ AD (connected to the second power supply terminal, in specific implementation, the DVDD pin can be connected in parallel through two capacitorsThe capacitor is grounded, the capacitor is used for filtering the second voltage +3v3_ AD), the AUX _ IN pin of the analog input chip U1 is connected (specifically, connected through a resistor) with the AUX _ GND pin and the analog ground (the triangle symbol represents the analog ground); the REFIO pin and the REFCAP pin of the analog input chip U1 are respectively connected with analog ground through a capacitor; of analogue input chips U1A foot part,The foot and the ALARM foot are both connected with the control module 30; the SCLK pin, SDI pin and SDO pin of the analog input chip U1 are connected with the analog output unit 120 and the control module 30; RDFGND pin of analog input chip U1,The pin, the AGND pin, the DA/SY pin and the DGND pin are all grounded.

The first interface P1 transmits 4 analog quantity signals (the first analog signal AIN0 ±, the second analog signal AIN1 ±, the third analog signal AIN2 ± and the fourth analog signal AIN3 ±) input from the outside to the corresponding operational amplifier circuits, each operational amplifier circuit filters and amplifies the analog signal of the corresponding circuit and outputs the analog signal to the 4-channel analog quantity input chip U1 with 12-bit precision, the voltage range of the 4-channel analog quantity is 0V ~ +10V, the analog quantity input chip U1 can directly bear the voltage of 10V and directly input, the middle high-precision operational amplifier is saved, and the first interface P1 has an SPI interface and can directly communicate with the main control chip in the control module 30.

Each operational amplifier circuit has the same function and circuit structure, but the input and output signals are different, and here, the first operational amplifier circuit 111 is taken as an example, and includes a first operational amplifier M1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first protection diode DS1, a first capacitor C1 and a second capacitor C2; one end of the first resistor R1 (i.e., the first input pin of the first operational amplifier circuit 111, connected to the 1 st pin of the first interface P1) is connected to one end of the second resistor R2, and the other end of the first resistor R1 (i.e., the second input pin of the first operational amplifier circuit 111, connected to the 2 nd pin of the first interface P1) is connected to one end of the third resistor R3; the other end of the second resistor R2 is connected with one end of the first capacitor C1, one end of the first protection diode DS1 and a non-inverting input pin of the first operational amplifier; the other end of the third resistor R3 (i.e., the second output pin of the first operational amplifier circuit 111) is connected to the other end of the first capacitor C1, the other end of the first protection diode DS1 and the AIN _0GND pin of the analog input chip U1; the inverting input pin of the first operational amplifier is connected to the output pin of the first operational amplifier and one end of the fourth resistor R4, the other end of the fourth resistor R4 (i.e., the first output pin of the first operational amplifier circuit 111) is connected to one end of the second capacitor C2 and the AIN _0P pin of the analog input chip U1, and the other end of the second capacitor C2 is grounded.

The first resistor R1 is used for providing a voltage potential, the R2, the R3 and the C1 form a pi-type filter circuit, the first protection diode DS1 is used for protecting the operational amplifier, and the R4 and the C2 form an RC filter circuit. It should be understood that, in the implementation, a four-operational amplifier chip of the type LM224 may be used, and four operational amplifiers are integrated therein, which may replace the operational amplifier in each operational amplifier circuit, thereby further improving the integration level of the circuit. As shown in fig. 2, the letter A, B, C, D in each op-amp represents four op-amps in a four op-amp chip, and pins 1-14 at the periphery of the four op-amps are the pins of the four op-amp chip.

Referring to fig. 3 and 4, the analog output unit 120 includes a second interface P2, an analog output chip U2 with a model number of AD5724R, a fifth resistor R5, a sixth resistor R6, a first output circuit (composed of two parts, respectively numbered 121_1 and 121_ 2), a second output circuit (composed of two parts, respectively numbered 122_1 and 122_ 2), a third output circuit (composed of two parts, respectively numbered 123_1 and 123_ 2), and a fourth output circuit (composed of two parts, respectively numbered 124_1 and 124_ 2); the DVcc pin of the analog output chip U2 inputs a third voltage +3V3_ DAC (connected with a third power supply terminal), and the analog output chip U2The pin is connected with a digital ground; of analog output chip U2A foot part,Foot andthe feet are all connected with the control module 30; the SCLK pin of the analog output chip U2 is connected with the SCLK pin of the analog input chip U1 and the control module 30, the SDIN pin of the analog output chip U2 is connected with the SDI pin of the analog input chip U1 and the control module 30, the SDO pin of the analog output chip U2 is connected with the SDO pin of the analog input chip U1 and the control module 30, the REFIN/REFOUT pin of the analog output chip U2 is connected with the GND pin of the analog output chip U2 and the digital ground through a capacitor, and the AVdd pin of the analog output chip U2 inputs a first voltage + 5V; the VoutA pin, the VoutB pin, the VoutC pin and the VoutD pin of the analog output chip U2 are connected with the first input pin of the first output circuit, the first input pin of the second output circuit, the first input pin of the third output circuit and the first input pin of the fourth output circuit in a one-to-one manner; the AVss pin, the SIG _ GND pin, the DAC _ GND pin and the EPAD pin of the analog quantity output chip U2 are all connected with an analog ground; the first output pin and the second output pin of the first output circuit are in one-to-one connection with the 10 th pin and the 9 th pin of the second interface P2; the first output pin and the second output pin of the second output circuit are in one-to-one connection with the 8 th pin and the 7 th pin of the second interface P2; the first output pin and the second output pin of the third output circuit are in one-to-one connection with the 6 th pin and the 5 th pin of the second interface P2; the first output pin and the second output pin of the fourth output circuit are in one-to-one connection with the 4 th pin and the 3 rd pin of the second interface P2; the 1 st pin of the second interface P2 is connected to the 2 nd pin and the shielding ground, and the third output pins of the first to fourth output circuits are all connected to the codec module 40; one end of the fifth resistor R5 receives the first voltage +5V, the other end of the fifth resistor R5 is connected to one end of the sixth resistor R6 and the second input pin of each output circuit, and the other end of the sixth resistor R6 is connected to the analog ground.

The voltage range of the analog output unit 120 is 0V to 10V, the SPI signal (including the SPI2_ SCLK signal, the SPI2_ MOSIO signal, and the SPI2_ MISO signal) is directly connected to and communicates with the main control chip in the control module 30, and data in the SPI signal is used to control the output state of the analog output chip U2, for example, which of the VoutA to VoutD pins is output, which of the several pins is output simultaneously or one-way output.The signal is a serial interface frame synchronization signal, the falling edge of the signal is used for data transmission, and the rising edge of the signal is used for data locking;the signal is used to select whether to update the analog output or to latch control if during the write cycleThe signal remains high, the input to the DAC register is updated, but atThe output is not updated until the falling edge of the signal, and all analog outputs may be atUpdating the falling edges of the signals simultaneously;the signal is used to set a DAC register built in the analog output chip U2 to a zero level code or an intermediate level code. The second interface P2 is an output terminal, and can be externally connected with devices requiring analog quantity signals, such as a proportional valve, laser power control, and the like; the output analog quantity signals (DA _ OUT1 +/-DA _ OUT4 +/-are used for controlling the working states of the devices.

Each output circuit has the same function and circuit structure, but the input and output signals are different, and here, the first output circuit is taken as an example and comprises a second operational amplifier M2, a third operational amplifier M3, a first common mode inductor L1, a seventh resistor R7 and a first switching tube Q1 (NMOS tube); the non-inverting input pin of the second operational amplifier M2 (i.e., the first input pin of the first output circuit) is connected to the VoutA pin of the analog output chip U2, the inverting input pin of the second operational amplifier M2 is connected to the output pin of the second operational amplifier M2 and the 1 st pin of the first common-mode inductor, the 2 nd pin of the first common-mode inductor (i.e., the first output pin of the first output circuit) is connected to the 10 th pin of the second interface P2, the 3 rd pin of the first common-mode inductor is grounded, the 4 th pin of the first common-mode inductor (i.e., the second output pin of the first output circuit) is connected to the 9 th pin of the second interface P2, the output pin of the second operational amplifier M2 is connected to the inverting input pin of the third operational amplifier M3, the non-inverting input pin of the third operational amplifier M3 (i.e., the second input pin of the first output circuit) is connected to the other end of the fifth resistor R5, the output pin of the third operational amplifier M3 is connected to the one end of the seventh resistor R637 and the other end of the first switch R5392, the seventh input voltage of the seventh switch R7, the source of the first switch Q1 is connected to the digital ground, and the drain of the first switch Q1 (i.e., the third output pin of the first output circuit) is connected to the codec module 40 (specifically, the codec module 40 may be connected through a resistor, which is a resistor with 4 resistor combinations in fig. 3).

The second operational amplifier M2 plays a role in isolation, and is used for preventing the analog output chip U2 from being burned out, and meanwhile, the driving capability is increased. The circuit in fig. 4 is used for monitoring whether an analog signal is output, the divided voltage of R5 and R6 provides a fixed reference level, when the analog output chip U2 does not output or outputs a low level (at this time, the voltage of the DIG _ DA1 signal is 0V-0.5V), the third operational amplifier M3 (comparator) outputs a high level to control the Q1 to be turned on, and the dacat 1 signal is a low level and is fed back to the main control chip through the codec module. When the analog signal is output (at this time, the voltage of the DIG _ DA1 signal is greater than 0.5V and less than or equal to 10V), the third operational amplifier M3 outputs a low level, Q1 is turned off, and the dacsat 1 signal is a high level. The main control chip can judge whether the analog quantity signal (DA _ OUT1 +/-DA _ OUT4 +/-is output or not and which one is output according to the high and low levels of the DACSTAT [1..4] signal.

Referring to fig. 5 and 6, the digital transmission module 20 includes a third interface P3, a fourth interface P4, a fifth interface P5, a sixth interface P6, a seventh interface P7, 48 digital input units (a first digital input unit to a forty-eighth digital input unit 48), 8 digital output units (a first digital output unit to an eighth digital output unit), and a monitoring feedback unit; the 1 st pin of the third interface P3 is connected with the input pin of the first digital quantity input unit, the 2 nd pin is connected with the input pin of the second digital quantity input unit, and so on until the 15 th pin of the third interface P3 is connected with the input pin of the sixteenth digital quantity input unit; similarly, each pin of the fourth interface P4 is correspondingly connected to the input pins of the seventeenth digital input unit to the thirty-second digital input unit, each pin of the fifth interface P5 is correspondingly connected to the input pins of the thirty-third digital input unit to the forty-eighth digital input unit, and the output pin of each digital input unit is connected to the codec module 40; the output pins of the first digital quantity output unit to the fourth digital quantity output unit are all connected with the sixth interface P6, the output pins of the fifth digital quantity output unit to the eighth digital quantity output unit are all connected with the seventh interface P7, and the input pins of the digital quantity output units are all connected with the coding and decoding module 40.

The functions and circuit structures of the digital input units are the same, but the input and output signals are different, and here, the first digital input unit is taken as an example, please refer to fig. 7, which includes a first optical coupler a1, a first indicator light G1, an eighth resistor R8, a ninth resistor R9, a third capacitor C3 and a fourth capacitor C4; one end of the third capacitor C3 is connected with one end of the eighth resistor R8 and the 1 st pin (i.e. the input pin of the first digital quantity input unit) of the first optical coupler a1, the other end of the third capacitor C3 is connected with the other end of the eighth resistor R8, the negative pole of the first indicator light G1 and the isolated ground, the 2 nd pin of the first optical coupler a1 is connected with the positive pole of the first indicator light G1, and the 3 rd pin of the first optical coupler a1 is connected with the digital ground; the 4 th pin (i.e. the output pin of the first digital input unit) of the first optical coupler a1 is connected to one end of the ninth resistor R9, one end of the fourth capacitor C4 and the codec module 40, the other end of the ninth resistor R9 is input with a fourth voltage +3V3 (connected to the fourth power supply end), and the other end of the fourth capacitor C4 is connected to a digital ground.

The third interface P3 to the fifth interface P5 are 24V INPUT terminals, are connected to an external 24V voltage INPUT, have 48 INPUTs (i.e., digital signal INPUT _ [1..48 ]), are isolated by each digital INPUT unit, output a corresponding INPUT _ CPU _ [1..48] signal, and transmit the signal to the main control chip through the codec module. As shown in fig. 7, the first optical coupler a1 is used to isolate 3.3V from 24V, when the INPUT _1 signal is at high level 24V, the first indicator light G1 is turned on, the first optical coupler a1 is turned on, and the INPUT _ CPU _1 signal is at low level. When the INPUT _1 signal is at a low level of 24V, the first indicator light G1 is turned off, the first optocoupler a1 is turned off, and the INPUT _ CPU _1 signal is pulled up to a high level by R9. Corresponding data is transmitted through the high-low level change of the INPUT _1 signal.

In specific implementation, in order to improve the integration level, a group of four digital input units can be adopted, and a photoelectric coupler with the model of TCMT4100 can be adopted, and 4 optical couplers are integrated inside the photoelectric coupler to replace the optical couplers in each digital input unit; similarly, the resistances of the 4 output pins (corresponding to R9) in the four digital input units can be replaced by resistors integrating 4 resistances, and the capacitances of the 4 output pins (corresponding to C4) can be replaced by capacitors integrating 4 capacitances.

The functions and circuit structures of the digital output units are the same, but the input and output signals are different, and here, taking the first digital output unit as an example, please refer to fig. 8 together, which includes a first driving chip U3 with a model of BTS716G being preferred, a second optical coupler a2 with a model of TCMT4100 being preferred, a first resistor RP1 (only 4 resistors are integrated together to reduce the volume so as to reduce the space of the PCB board without connection), a second resistor RP2, a third resistor RP3, and a first capacitor CP1 (only 4 capacitors are integrated together to reduce the volume so as to reduce the space of the PCB board without connection); the 1 st pin, the 3 rd pin, the 5 th pin and the 7 th pin of the second optical coupler A2 are in one-to-one connection with the 4 th pin, the 3 rd pin, the 2 nd pin and the 1 st pin of a first resistor RP 1; the 2 nd pin, the 4 th pin, the 6 th pin and the 8 th pin of the second optical coupler a2 (namely, the 4 input pins of the first digital quantity output unit) are all connected with the coding and decoding module 40; the 16 th pin, the 14 th pin, the 12 th pin and the 10 th pin of the second optical coupler A2 are in one-to-one connection with the 1 st pin, the 2 nd pin, the 3 rd pin and the 4 th pin of the second resistor RP 2; a 15 th pin of the second optical coupler A2 is connected with a1 st pin of the third resistor RP3, a1 st pin of the first capacitor CP1 and an IN1 pin of the first driving chip U3; the 13 th pin of the second optical coupler A2 is connected with the 2 nd pin of the third resistor RP3, the 2 nd pin of the first capacitor CP1 and the IN2 pin of the first driving chip U3; the 11 th pin of the second optical coupler A2 is connected with the 3 rd pin of the third resistor RP3, the 3 rd pin of the first capacitor CP1 and the IN3 pin of the first driving chip U3; the 9 th pin of the second optical coupler A2 is connected with the 4 th pin of the third resistor RP3, the 4 th pin of the first capacitor CP1 and the IN4 pin of the first driving chip U3; the pins 5 to 8 of the first resistor RP1 all input a fourth voltage +3V3, the pins 5 to 8 of the second resistor RP2 all input a fifth voltage +24V (connected to the fifth power supply terminal), the pins 5 to 8 of the third resistor RP3 and the pins 5 to 8 of the first capacitor CP1 are all connected to the ground, and the VBB pin of the first driver chip U3 inputs a fifth voltage + 24V; the OUT1 pin, the OUT2 pin, the OUT3 pin and the OUT4 pin of the first driving chip U3 are in one-to-one connection with the 16 th pin, the 15 th pin, the 14 th pin and the 13 th pin of the sixth interface P6; the ST1/2 pin of the first driver chip U3 is connected with the ST2/4 pin connection monitoring feedback unit.

The main control chip outputs digital signals to be output through a codec module, that is, O _ CPU _ [1..32] signals, and the signals are isolated by a corresponding digital output unit, driven by a first driver chip U3 (a high-side output first driver chip), and output through two output terminals, namely a sixth interface P6 and a seventh interface P7. When the O _ CPU _1 signal OUTPUTs low level and a2 is turned on, the signal of the IN1 interface of U3 is pulled up to high level by a resistor IN RP3, and U3 OUTPUTs 24V digital OUTPUT 1. When the O _ CPU _1 signal OUTPUTs a high level and a2 is turned off, the voltage of the signal of the IN1 interface of U3 becomes a low level by being discharged to the ground through the corresponding capacitor IN CP1, and U3 OUTPUTs the digital signal OUTPUT1 of a low level.

The circuit shown in fig. 9 is used for monitoring the OUTPUT of the digital OUTPUT signal OUTPUT [1..32], when the OUTPUT is short-circuited or overloaded or the temperature is too high, the first driving chip U3 OUTPUTs a DIAG _ signal with a high level, the corresponding optical coupler is turned on, and the signal ntottat 1 is pulled down to a low level; nOUTAT [1..8] signals are fed back to the main control chip through the coding and decoding module, and the main control chip can realize short circuit, overload or over-temperature monitoring according to the high and low levels of the signals. An indicator lamp can be connected to the pins OUT1 to OUT4 of the first driving chip U3 respectively, and the corresponding indicator lamp is turned on during signal transmission of OUTPUT1-4, so that a user can know the current digital quantity OUTPUT condition conveniently.

Referring to fig. 10, the control module 30 includes a main control chip U4 (preferably, a single chip microcomputer of STM32F103 VC) and a burning interface JP; the PA0_ WKUP pin, the PA1 pin and the PD13 pin of the main control chip U4 are all connected with the handwheel processing module 50; the PA2 pin, the PA3 pin, the PA4 pin, the PA5 pin, the PA6 pin, the PA7 pin, the PC8 pin and the PC9 pin of the main control chip U4 are all connected with the communication module 70; the PA8 pin and the PD15 pin of the master control chip U4 are both connected with the PWM output module 60; the PA9 pin, the PA10 pin and the PA13/JTMS/SWDIO pin of the main control chip U4 are connected with the No. 2 pin, the No. 1 pin, the No. 5 pin and the No. 6 pin of the burning interface JP in a one-to-one manner; PB8 pin, PB9 pin, PB12 pin of the main control chip U4 and analog output chip U2A foot part,A foot part,The feet are connected in a one-to-one way; PB10 pin, PB11 pin, PB13 pin, PB14 pin, PB15 pin and PE15 pin of the main control chip U4 and of the analog input chip U1Foot, ALARM foot, SCLK foot, SDO foot, SDI foot,The feet are connected in a one-to-one way; the pins PC0 to PC7, PD0 to PD12 and PE5 of the main control chip U4 are all connected with the encoding and decoding module 40.

Wherein the main control chip U4 is a mainstream enhanced ARM Cortex-M3 MCU, and is internally provided with 256 KB Flash, 48KB RAM, 72 MHz CPU,Modules and functions of motor control, USB and CAN; the communication with the communication chip U11 in the communication module 70 is performed through an SPI interface, the communication with the DA and the AD is also performed through an SPI interface, and the digital input and output are performed through an IO interface parallel interface. Among the signals, the ENCA signal is input by a hand wheel a phase signal, the ENCB signal is input by a hand wheel B phase signal, the ENCB signal is transmitted to the main control chip through the hand wheel processing module, and the signal processing is performed by a timer coding module inside the main control chip (the specific processing mode is the prior art). The SINT signal is an EtherCAT communication interrupt signal, the EEP _ DONE signal is an XML file loading success signal, the SCS _ ESC signal is an EtherCAT communication chip selection signal, the SCLK signal is a clock signal of an EtherCAT communication SPI, the SMISO signal is an input signal of the EtherCAT communication SPI, the SMOSI signal is an output signal of the EtherCAT communication SPI, the SYNC _ L0 signal is an EtherCAT communication synchronous signal 0, and the SYNC _ L1 signal is an EtherCAT communication synchronous signal 1; these signals constitute EtherCAT communication, and communicate with the upper computer through a communication chip (AX 58100) in the communication module 70. The PWM signal is output by the main control chip and used for realizing PWM control and is used when the cutting speed is low; the FOUT signal is a fast PWM output signal that is used when fast cuts are required. The UART1_ TX signal (serial communication output signal) and the UART1_ RX (serial communication input signal) transmitted between the main control chip and the burning interface JP are used for printing data during debugging, so that various working states can be observed conveniently. The uC _ SWDIO signal (data input/output of SW interface (a general interface)) and the uC _ SWCLK signal (clock signal of SW interface) transmitted between the main control chip and the programming interface JP are used for debugging, programming and simulating a program. The BOOT1 signal and the BOOT0 signal are input into configuration pins of the main control chip and are used for determining where the program starts to run after the single chip microcomputer is started. Output of main control chipThe signals configure the DAC registers built into the analog output chip U2,the signal is used to update the DAC register to update the analog output,the signal is a serial interface frame sync signal, the ADC _ CS signal is used for chip selection,the signal is used for resetting, and the ADC _ ALARM signal is an ALARM signal when the input analog quantity signal and the digital quantity signal are detected to be abnormal. The SPI2_ SCLK signal is the clock signal of the communication bus SPI2, the SPI2_ MISO signal is the input signal of the communication bus SPI2, and the SPI2_ MOSI signal is the output signal of the communication bus SPI2, which are used for SPI2 bus communication, shared by the ADC and DAC, and when it is necessary to communicate with which chip, the control pin can be disabled. The DB _0 to DB _7 signals are 8-bit parallel port bus communication signals and can be input or output. Signals OE0-OE 7 are enable signals, when the signals are low level, the chips in the decoding unit are enabled, and then the data on the DB _0 to DB _7 interfaces are the real-time data on the INPUT _ CPU _1 to INPUT _ CPU _ 8; when the optical switch is not used, the main control chip pulls the level of the corresponding OE signal high. Signals LE 0-LE 3 are latch control pins of the 74HC373 chip in the latch unit, and are output at the falling edge and latched at the rising edge until the next data is updated. The OE _ DO signal is an enable chip selection signal of the output chip of the latch unit, when the master chip controls the output chip to be in a low level, data on DB _0 to DB _7 are input to 4 latch chips, and specifically, which chip is selected for output is updated by signals LE0 to LE 3. The OUT _ LED signal is used to control an LED light to indicate an operational state of the product, such as standby, running, or malfunctioning.

Referring to fig. 11 and 12, the codec module 40 includes 9 decoding units and 4 latch units, and each decoding unit and each latch unit are connected to the control module; the first decoding unit to the seventh decoding unit are connected with the digital quantity transmission module and are used for decoding the digital quantity signals input by the digital quantity transmission module and then transmitting the digital quantity signals to the control module; the eighth decoding unit is connected with the analog quantity transmission module (specifically, the analog quantity output unit) and is used for decoding the monitoring signal output by the analog quantity transmission module and transmitting the monitoring signal to the control module; the ninth decoding unit is connected with the hand wheel processing module and is used for decoding hand wheel data transmitted by the hand wheel processing module and transmitting the decoded hand wheel data to the control module; the first latch unit to the fourth latch unit are connected with the control module and the digital quantity transmission module, and are used for latching the digital quantity output signal output by the control module and then outputting the signal to the digital quantity transmission module.

The functions and circuit structures of the decoding units are the same, but the input signals are different, and the corresponding external pins are different, here, taking the first decoding unit as an example, please refer to fig. 13 together, which includes a first logic chip U5, a tenth resistor R10 and a fifth capacitor C5, the model of which is NXP74HC244 PW; of the first logic chip U5Foot connectionThe pin, one end of the tenth resistor R10 and the PD0 pin of the main control chip U4; the other end of the tenth resistor R10 inputs a fourth voltage +3V3, and the a1 pin, the a2 pin, the A3 pin, the a4 pin, the a5 pin, the a6 pin, the a7 pin, and the A8 pin of the first logic chip U5 are connected to the output pin of the first digital quantity input unit (i.e., the 4 th pin of the internal optical coupler), the output pin of the second digital quantity input unit, the output pin of the third digital quantity input unit, the output pin of the fourth digital quantity input unit, the output pin of the fifth digital quantity input unit, the output pin of the sixth digital quantity input unit, the output pin of the seventh digital quantity input unit, and the output pin of the eighth digital quantity input unit in a one-to-one manner; the VCC pin of the first logic chip U5 inputs a fourth voltage +3V3 and is also connected to the digital ground through a fifth capacitor C5; the Y1 pin, the Y2 pin, the Y3 pin, the Y4 pin, the Y5 pin, the Y6 pin, the Y7 pin and the Y8 pin of the first logic chip U5 are connected with the PC0 pin, the PC1 pin, the PC2 pin, the PC3 pin, the PC4 pin, the PC5 pin, the PC6 pin and the PC7 pin of the main control chip U4 in a one-to-one manner.

The OE0-OE8 signal is used for selecting the chips needing communication, namely when the OE0-OE8 signal is effective (such as low level), the pin A1 is communicated with the pin Y1, and the signal on the pin A1 is transmitted to the pin Y1; the pin A2 is communicated with the pin Y2, the signal on the pin A2 is transmitted to the pin Y2, and so on.

The input signals of the seventh to ninth decoding units are different from those of the other decoding units, the specific circuit of the seventh decoding unit is shown in fig. 14, the specific circuit of the eighth decoding unit is shown in fig. 15, and the specific circuit of the ninth decoding unit is shown in fig. 16.

The functions and circuit structures of the latch units are the same, but the output signals are different, and the corresponding external pins are different, here, taking the first latch unit as an example, please refer to fig. 17 together, which includes a first latch chip (preferably, a latch of type 74HC 373) U6, an eleventh resistor R11, a twelfth resistor R12 and a sixth capacitor C6; of said first latch chip U6One end of the eleventh resistor R11 and a PE5 pin of the main control chip U4 are connected through pins, the other end of the eleventh resistor R11 inputs a fourth voltage +3V3, and a D0 pin, a D1 pin, a D2 pin, a D3 pin, a D4 pin, a D5 pin, a D6 pin and a D7 pin of the first latch chip U6 are connected with XX in a one-to-one mode; the VCC pin of the first latch chip U6 inputs a fourth voltage +3V3 and is also connected to the digital ground through a sixth capacitor C6; the pins Q0, Q1, Q2 and Q3 of the first latch chip U6 are connected with the 4 input pins (i.e. the 2 nd pin, the 4 th pin, the 6 th pin and the 8 th pin of the second optical coupler a 2) of the first digital quantity output unit in a one-to-one manner; the pins Q4, Q5, Q6 and Q7 of the first latch chip U6 are connected with the 4 input pins of the first digital quantity output unit in a one-to-one manner; the LE pin of the first latch chip U6 is connected to the PD9 pin of the main control chip U4 and is also connected to the digital ground through a twelfth resistor R12.

When the main control chip controls the OE _ DO signal to be at a low level, the first latch chip U6 is selected to be in a latch state, and when the LE0 signal is active (e.g., at a high level), the DB _0 signal is output as a corresponding O _ CPU _1 signal through the first latch chip U6, and other signals are correspondingly output in the same way, that is, the pin D0 is output in communication with the pin Q0, the pin D1 is output in communication with the pin Q1, and so on. .

Referring to fig. 18 and 19 together, the handwheel processing module 50 includes a handwheel interface J1 (model is preferably TCMT 4100), a third optical coupler A3 and a fourth optical coupler a4, which model is preferably TCMT4100, a fifth optical coupler a5, which model is preferably HCPL-181000E, a sixth optical coupler a6 (dual-channel high-speed optical coupler), which model is preferably EL0631, a fourth resistor RP4, a fifth resistor RP5, a twelfth resistor R12, a thirteenth resistor R13, a seventh capacitor C7 and an eighth capacitor C8; the 1 st pin and the 2 nd pin of the handwheel interface J1 input a fifth voltage of +24V, and the 9 th pin and the 10 th pin of the handwheel interface J1 are connected and isolated; the 3 rd pin, the 4 th pin, the 5 th pin and the 6 th pin of the handwheel interface J1 are connected with the 1 st pin, the 3 rd pin, the 5 th pin and the 7 th pin of the third optocoupler A3 in a one-to-one manner; the 11 th pin, the 12 th pin, the 13 th pin and the 7 th pin of the handwheel interface J1 are connected with the 3 rd pin, the 5 th pin, the 7 th pin and the 1 st pin of the fourth optical coupler A4 in a one-to-one manner; the 14 th pin and the 15 th pin of the handwheel interface J1 are connected with the 1 st pin and the 4 th pin of the sixth optical coupler A6 in a one-to-one manner; the 8 th pin of the handwheel interface J1 is connected with the E pin of the fifth optocoupler A5; the 2 nd pin, the 4 th pin, the 6 th pin and the 8 th pin of the third optical coupler A3 are respectively connected and isolated through an indicator light; the 2 nd pin, the 4 th pin, the 6 th pin and the 8 th pin of the fourth optical coupler A4 are respectively connected and isolated through an indicator light; the 16 th pin, the 14 th pin, the 12 th pin and the 10 th pin of the third optical coupler A3 are in one-to-one connection with the 1 st pin, the 2 nd pin, the 3 rd pin and the 4 th pin of the fourth resistor RP 4; a 16 pin of a third optical coupler A3 is connected with a1 pin of a fourth resistor RP4 and an A1 pin of a logic chip in a ninth decoding unit, a 14 pin of a third optical coupler A3 is connected with a2 pin of a fourth resistor RP4 and an A2 pin of the logic chip in the ninth decoding unit, a 12 pin of a third optical coupler A3 is connected with A3 pin of the fourth resistor RP4 and an A3 pin of the logic chip in the ninth decoding unit, a10 pin of a third optical coupler A3 is connected with A4 pin of the fourth resistor RP4 and an A4 pin of the logic chip in the ninth decoding unit, a 16 pin of a fourth optical coupler A4 is connected with a1 pin of a fifth resistor RP5 and an A5 pin of the logic chip in the ninth decoding unit, a 14 pin of a fourth optical coupler A4 is connected with a2 pin of the fifth resistor RP 29 and an A6 pin of the logic chip in the ninth decoding unit, and a 4642 pin of the fourth optical coupler A4642 is connected with a ninth decoding unit 7 pin of the ninth decoding unit, a10 th pin of the fourth optical coupler A4 is connected with a4 th pin of a fifth resistor RP5 and A8 pin of a logic chip in the ninth decoding unit, and the 5 th pin to the 8 th pin of the fourth resistor RP4 and the fifth resistor RP5 are all inputted with a fourth voltage +3V 3; the 15 th pin, the 13 th pin, the 11 th pin and the 9 th pin of the third optical coupler A3 and the fourth optical coupler A4 are all connected with digital ground; a pin C of the fifth optical coupler A5 inputs a fifth voltage +24V, a pin A of the fifth optical coupler A5 inputs a fourth voltage +3V3, a pin K of the fifth optical coupler A5 is connected with a pin PD13 of the main control chip U4, and a pin 1 of the sixth optical coupler A6 is connected with one end of a seventh capacitor C7 and one end of a thirteenth resistor R13; a2 nd pin of the sixth optical coupler A6 is connected with the other end of the seventh capacitor C7, the other end of the thirteenth resistor R13 and the shielding ground; a4 th pin of the sixth optical coupler A6 is connected with one end of an eighth capacitor C8 and one end of a twelfth resistor R12; a3 rd pin of the sixth optical coupler a6 is connected with the other end of the eighth capacitor C8, the other end of the twelfth resistor R12 and the shielding ground, A8 th pin of the sixth optical coupler a6 inputs a fourth voltage +3V3, and a7 th pin and a6 th pin of the sixth optical coupler a6 are connected with a PA0-WKUP pin and a PA1 pin of the main control chip U4 in a one-to-one manner; the 5 th pin of the sixth optical coupler a6 is connected to digital ground.

The hand wheel interface J1 plays a role in isolation, and hand wheel data input by an external hand wheel are transmitted to the data processing unit in the main control chip for processing. In the handwheel data, X, Y, Z, 4 and 5 indicate that 5 shaft selections can be provided, and X1, X10 and X100 correspond to the multiplying power of the handwheel. A and B correspond to hand wheel signals expressed as an A phase and a B phase, and the hand wheel signals are isolated by a sixth optical coupler A6 and then corresponding ENCA signals and ENCB signals are output. And a handwheel control signal OUT _ LED output by the main control chip is isolated by a fifth optocoupler A5 and then output from a handwheel interface J1.

It should be understood that there are other elements in the handwheel processing module 50, such as resistors, capacitors, indicator lights connected to the 1 st pin to the 8 th pin of the third optical coupler A3 and the fourth optical coupler a4, which have the same structure and function as the corresponding elements in the first digital value input unit, and pull resistors connected to the 7 th pin and the 6 th pin of the sixth optical coupler a6, and the details are shown in fig. 18.

Referring to fig. 20, the PWM output module 60 includes an output voltage isolation chip U7 with a model of ISO7342C, a second driver chip U8 with a model of UCC27524D, a third driver chip U9 with a model of UCC27537DBVT, a fourth driver chip U10 with a model of UCC27537DBVT, a serial port J2, a first transient suppressor D1 with a model of PESD5V2S2UT, a second transient suppressor D2, a fourteenth resistor R14 and a fifteenth resistor R15; a pin VCC1 of the output voltage isolation chip U7 inputs a fourth voltage +3V3, an INA pin of the output voltage isolation chip U7 is connected with one end of a fourteenth resistor R14 and a pin PD15 of the main control chip U4, and an INB pin of the output voltage isolation chip U7 is connected with one end of a fifteenth resistor R15 and a pin PA8 of the main control chip U4; the GND1 pin of the output voltage isolation chip U7 is connected with the other end of the fourteenth resistor R14, the other end of the fifteenth resistor R15 and the digital ground; a pin VCC2 of the output voltage isolation chip U7 inputs a sixth voltage 5V0 (connected with a sixth power supply end), a pin GND2 of the output voltage isolation chip U7 is connected with the ground IN an isolation manner, a pin OUTA of the output voltage isolation chip U7 is connected with a pin INA of the second drive chip U8 and a pin IN + of the fourth drive chip U10, and a pin OUTB of the output voltage isolation chip U7 is connected with a pin INB of the second drive chip U8 and a pin IN + of the third drive chip U9; the ENA pin, the ENB pin and the VDD pin of the second driving chip U8 are all input with a sixth voltage of 5V 0; the GND pin of the second driving chip U8 is isolated, the OUTA pin of the second driving chip U8 is connected to the 2 nd pin (the cathode of one diode) of the first transient suppressor D1 and the 4 th pin of the serial port J2, the OUTB pin of the second driving chip U8 is connected to the 1 st pin (the cathode of the other diode) of the first transient suppressor D1 and the 5 th pin of the serial port J2, the EN pins of the third driving chip U9 and the fourth driving chip U10 are both inputted with the sixth voltage 5V0, the GND pins of the third driving chip U9 and the fourth driving chip U10 are both isolated, the VDD pins of the third driving chip U9 and the fourth driving chip U10 are both inputted with the fifth voltage +24V, the OUT pin of the third driving chip U9 is connected to the 2 nd pin (the cathode of one diode) of the second transient suppressor D2 and the 1 st pin of the serial port J2, and the OUT pin of the fourth driving chip U10 is connected to the cathode of the second transient suppressor D2 (the serial port J2); the 3 rd pin (anodes of two diodes) of the first transient suppressor D1, the 3 rd pin of the second transient suppressor D2, and the 6 th, 7 th, 3 rd, 8 th and 9 th pins of the serial port J2 are connected and isolated; the shells (PE 1 and PE 2) of the serial port J2 are connected with a shielding ground.

The FOUT signal and the PWM signal output by the main control chip are 3.3V signals, but 5V and 24V are actually needed, the FOUT signal and the PWM signal are isolated by the output voltage isolation chip U7 and then output 5V zFOUT signal and zPWM signal, the zFOUT signal is driven by the second drive chip U8 and then output 5V FOUT5V signal, the zFOUT signal is driven by the fourth drive chip U10 and then output 24V FOUT24V signal, the zPWM signal is driven by the second drive chip U8 and then output 5V PWM5V signal, the zPWM signal is driven by the third drive chip U9 and then output 24V PWM24V signal, and the signals are output to an external laser through the serial port J2, so that PWM control can be realized.

Preferably, the pin OUT of the third driver chip U9 is connected to the indicator lamp through a resistor in sequence, so that the indicator lamp is turned on when the PWM24V signal is output, thereby facilitating observation; the OUT pin of the fourth driver chip U10 also has corresponding components.

Referring to fig. 21, 22 and 23, the communication module 70 includes a communication chip U11 with a model number of AX58100, a first ESD protection tube U12 with a model number of AZ1213-04S, a second ESD protection tube U13 (AZ 1213-04S), a first net port HR1, a second net port HR2, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11 and a twelfth capacitor C12; OE _ EXT/LRDn/SCLK foot, OUTLVLD/LWRn/MOSI foot, SOF/LECSn/SCS _ ESC foot, WD _ TRIG/LINT/SINT foot, SYNC _ LATCH [0] foot, SYNC _ LATCH [1] foot, LAT _ IN/LRDY/MISO foot and EEP _ DONE foot of the communication chip U11 are connected with PA5 foot, PA7 foot, PA4 foot, AP2 foot, PC8 foot, PC9 foot, AP6 foot and PA3 foot of the main control chip U4 IN a one-to-one manner; a P0_ TXOP pin of the communication chip U11 is connected to a TD + pin of the first network port HR1 and an IO2 pin of the first ESD protection tube U12, a P0_ TXON pin of the communication chip U11 is connected to a TD-pin of the first network port HR1 and an IO3 pin of the first ESD protection tube U12, a P0_ RXIP pin of the communication chip U11 is connected to an RD + pin of the first network port HR1 and an IO4 pin of the first ESD protection tube U12, a P0_ RXIN pin of the communication chip U11 is connected to an RD-pin of the first network port HR1 and an IO1 pin of the first ESD protection tube U12, a P1_ ACT pin of the communication chip U1 is connected to an LED 1_ Yellow + pin of the first network port HR1, a TDC 1 pin of the first network port HR1 is connected to a sixteenth resistor R1, a ninth capacitor C1 HR, a P1_ TXOP HR _ op pin of the first ESD protection tube U1 is connected to a digital resistor R1, a TD _ txu 1P 1_ txc + pin of the second ESD protection tube U1 is connected to a digital resistor R1 and a digital resistor R1 of the second ESD protection tube U1, a P1_ txu 1 is connected to a digital resistor R1 of the second ESD protection tube U1 to a second ESD protection tube U1 and an IO1 to a digital resistor R1, a P1_ RXIP pin of the communication chip U11 is connected with an RD + pin of the second network port HR2 and an IO4 pin of the second ESD protection tube U13, a P1_ RXIN pin of the communication chip U11 is connected with an RD-pin of the second network port HR2 and an IO1 pin of the second ESD protection tube U13, a P1_ ACT pin of the communication chip U11 is connected with an LED2_ Yellow + pin of the second network port HR2, a TDC pin of the second network port HR2 sequentially passes through an eighteenth resistor R18 and an eleventh capacitor C11 to be digitally connected, and an RDC pin of the second network port HR2 sequentially passes through a nineteenth resistor R19 and a twelfth capacitor C12 to be digitally connected.

The sixteenth resistor R16, the seventeenth resistor R17, the ninth capacitor C9 and the tenth capacitor C10 form an impedance matching circuit of the first network port HR 1; an eighteenth resistor R18, a nineteenth resistor R19, an eleventh capacitor C11 and a twelfth capacitor C12 form an impedance matching circuit of the second network port HR 2. The communication chip U11 is a 2/3 port EtherCAT slave station controller (ESC) integrating two fast Ethernet PHYs supporting 100Mbps full duplex operation and HP Auto-MDIX function. The communication chip U11 supports CANopen (CoE), TFTP (FoE), VoE and other standard EtherCAT protocols, and is suitable for industrial automation, motor control, motion control, robots, digital signal I/O control, analog-to-digital converter (ADC)/digital-to-analog converter (DAC) converter control, sensor data acquisition and other real-time industrial control product applications. In this embodiment, the communication chip U11 provides a three-channel PWM controller or a step controller, an increment/hall encoding interface for closed-loop control, an SPI Master interface for SPI device data acquisition and output, 32 digital control I/O suitable for industrial real-time I/O control applications, and an I/O watch provides monitoring of I/O status for proper handling to ensure safety of product functions. Two Process Data Interfaces (PDI), a Local Bus interface and an SPI slave serial interface are provided, and the communication chip U11 can be connected to an external traditional MCU/DSP industrial control machine table through the interfaces so as to support the EtherCAT function. The communication chip U11 has two memory spaces corresponding to the ESC memory and the Function buffer, respectively, and the designer can decide which memory space to access through the chip select pin. The internal bridge will automatically synchronize the contents of ESC memory and function buffer according to the set synchronization condition, and provide EtherCAT Master to remotely control the functions (PWM, SPI Master, etc.) of AX 58100. The communication chip U11 reflects ESC and application interrupt events in the interrupt status buffer and notifies the external MCU/DSP to manage these ESC and application interrupt events via conditional or edge interrupt triggered mode.

In summary, according to the digital and PWM composite controller provided by the present invention, 48 channels of digital quantity input, 32 channels of digital quantity output, 4 channels of 16-bit high-precision analog quantity input, 4 channels of 12-bit analog quantity output, high-precision PWM output of 24V and 5V, digital IO handwheel transceiving interface, RS485 expansion interface, and EtherCAT bus communication interface are integrated together into one module, and compared with the existing modules with various functions separately designed, one module can completely solve all application scenarios without redundant control modules; and a connecting line between the modules is also omitted, so that the wiring trouble and the external interference during signal transmission are greatly reduced, the cost is saved, and the anti-interference performance is improved.

The division of the functional modules is only used for illustration, and in practical applications, the functions may be distributed by different functional modules according to needs, that is, the functions may be divided into different functional modules to complete all or part of the functions described above.

It should be understood that equivalents and modifications of the technical solution and inventive concept thereof may occur to those skilled in the art, and all such modifications and alterations should fall within the scope of the appended claims.

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