阅读说明：本技术 具有可变增益的模拟计算机 (Analog computer with variable gain ) 是由 A·马丁·马林森 于 2020-02-28 设计创作，主要内容包括：通过酌量降低模拟计算机中存在的增益元件的增益来实现模拟计算机的改进的性能。当存在电路的先前输出(如果有)时,将增益元件的增益降低到足够低以至于输入信号无法通过电路传播的水平。然后,将输入信号改变为新值或一组值,同时增益元件的增益保持降低。最后,将增益元件的增益增大到足够高以允许输入信号通过电路传播的水平,从而产生作为由模拟计算机表示的问题的解的输出。(Improved performance of an analog computer is achieved by reducing the gain of gain elements present in the analog computer by an amount appropriate. When there is a previous output of the circuit (if any), the gain of the gain element is reduced to a level that is low enough that the input signal cannot propagate through the circuit. The input signal is then changed to a new value or set of values while the gain of the gain element remains reduced. Finally, the gain of the gain element is increased to a level high enough to allow the input signal to propagate through the circuit, thereby producing an output that is a solution to the problem represented by the analog computer.)

1. A method of operating an analog computer, the analog computer comprising a plurality of gain elements configured to operate on an aggregate input signal to provide a solution to a predetermined problem, the gain of each of the plurality of gain elements being variable between a level sufficient to propagate a signal input to the element and a level insufficient to propagate the signal input to the element, the method comprising:

reducing the gain of each of the plurality of gain elements to a level insufficient to propagate the signal input to the gain element;

changing the total input signal when the gain of the gain element is at the reduced level; and

increasing the gain of each of the plurality of gain elements to a level sufficient to propagate the signal input to the gain element no earlier than a time at which the input signal changes.

2. The method of claim 1, wherein the time to increase the gain of the gain element is after a change in the aggregate input signal.

3. The method of claim 1, wherein the time to increase the gain of the gain element is simultaneous with the change in the total input signal.

4. A variable gain element for use in an analog computer, comprising:

a first transistor and a second transistor, each transistor having a gate, a source, and a drain, the gate of the first transistor configured to receive an input signal and the gate of the second transistor connected to a reference point;

a first resistor and a second resistor, the first resistor being connected to the drain of the first transistor and to one side of a voltage source, and the second resistor being connected to the drain of the second transistor and to the voltage source;

a current source connected to the sources of both the first and second transistors, the current source configured to provide different levels of current in response to a control signal;

an amplifier having an input connected to the drains of the first and second transistors and the reference point and an output providing an output of the gain element; and

a control circuit configured to provide a control signal based on a preselected condition.

5. The variable gain element of claim 4 wherein the first transistor and the second transistor are n-type metal oxide semiconductor field effect transistors.

6. The variable gain element of claim 4 wherein the control circuit further comprises:

a switch; and

control logic to place the switch in a first position when the input signal changes and to place the switch in a second position when the output of the gain element changes; and is

Wherein the current source is configured to provide current when the switch is in the first position and not provide current when the switch is in the second position.

7. The variable gain element of claim 4 wherein the control circuit further comprises:

a switch; and

control logic for placing the switch in the first and second positions at preselected intervals.

8. A variable gain element for use in an analog computer, comprising:

a first amplifier configured to receive a signal at a first end and to generate an amplified signal at a second end;

a first resistive element having a first end configured to receive an input signal of the variable gain element and a second end connected to a first end of the first amplifier;

a second resistive element having a first end connected to the first end of the first amplifier and a second end connected to the second end of the first amplifier;

a switch having a first end connected to the first end of the first amplifier, a second end connected to the second end of the first amplifier, and a switch port configured to receive a control signal, the switch being in an open position or a closed position depending on the control signal;

control logic configured to provide the control signal to open or close the switch based on a preselected condition; and

a second amplifier configured to receive a signal at a first end and to generate an amplified signal at a second end, the first end of the second amplifier being connected to the second end of the first amplifier, and the second end of the second amplifier being configured to generate an output signal from the variable gain element.

9. The variable gain element of claim 8 wherein the preselected condition is changing the position of the switch when the input changes and when an output signal is also present on the output port of the second amplifier.

10. The variable gain element of claim 8 wherein the preselected condition is changing the position of the switch at preselected intervals.

11. An analog computer, comprising:

a plurality of gain elements configured to operate on the aggregate input signal to provide a solution to a predetermined problem, the gain of each gain element being variable between a level sufficient to propagate a signal input to the element and a level insufficient to propagate the input signal;

a gain control device configured to switch a gain of the gain element between a level sufficient to propagate the input signal and a level insufficient to propagate the input signal based on a control signal; and

logic means configured to generate control signals such that the gain control means switches the gain of the gain element to a level insufficient to propagate the input signal before a change in the aggregate input signal occurs and switches the gain of the gain element to a level sufficient to propagate the input signal no earlier than the time the input signal changes.

12. The analog computer of claim 11, wherein the gain element comprises a transistor and the gain control device is a current source that reduces current in the transistor below a point at which the transistor conducts current.

13. The analog computer of claim 11, wherein the gain element includes a resistive feedback loop and the gain control device is a switch that short circuits a feedback resistor and drops the gain of the gain element to approximately zero.

Technical Field

The present invention relates generally to analog computers, and more particularly to analog computers having variable gain.

Background

Simulation computers are a type of computer that uses continuously variable aspects of some physical phenomenon (e.g., electrical, mechanical, or hydraulic quantities) to model a problem requiring a solution. In contrast, a digital computer symbolically and by discrete values of both time and amplitude represents the amount of change. A slide rule is one of the simplest analog computers. Although digital computers have replaced analog computers in many applications, analog computers have still been used to advantage to solve some of the problems.

The method is directed to an electrical simulation computer that models problems in the electrical domain. Such analog computers are based on components with gain, typically operational amplifiers ("op-amps") that conventionally have high gain. For example, the solution of a complex equation (such as Schrodinger equation) can be modeled in the electrical components of a simulation computer.

The principle is that the differential schrodinger equation, which may involve time, can be solved by mapping it into its electrical simulation (i.e., by kirchhoff's current law for circuits that use equivalent constraints as solutions to the problem). When one or more inputs are applied to a constrained network modeling a problem, the analog voltage and current within the analog computer will vary as the network reaches a solution that represents the solution to the problem.

The network of analog computers may be static, where a solution is obtained when the electrical parameters converge to a static result; or the network of analog computers may be dynamic, with the solution being provided by periodic steady-state of electrical parameters.

One problem that arises with such electrically simulated computers is the response of the network to input modifications. When the input is changed, the analog voltage and current in the computer must be changed again to solve the problem again now using the new input parameters. As is known in the art, the time taken to establish a new solution is limited and depends on the gain bandwidth of the high gain element and the feedback (if any) around the high gain element. This can result in transients between the "old" solution (i.e., the solution for the previous input) and the "new" solution for the new input.

This transient is present in the configuration of the gain elements forming the analog computer, as it adapts to the new input, whether the network is static or dynamic. Transient events in a static network are the time it takes for the electrical parameters to converge again to a new static result. Transient events in a dynamic network are the time required to move between two periodic steady-state solutions: as a periodic steady state solution for the previous input state and a new periodic steady state solution for the current input state.

In some cases, the delay in transients may be significant. Therefore, it is desirable to shorten the length of the transient so that the analog computer can provide a faster solution to the desired problem represented by the network of computer elements.

Disclosure of Invention

This application describes apparatus and methods for improving the performance of analog computers.

One embodiment describes a method of operating an analog computer, the analog computer including a plurality of gain elements configured to operate on an aggregate input signal to provide a solution to a predetermined problem, the gain of each of the plurality of gain elements being variable between a level sufficient to propagate a signal input to the element and a level insufficient to propagate the signal input to the element, the method comprising: reducing the gain of each of the plurality of gain elements to a level insufficient to propagate the signal input to the gain element; changing the total input signal when the gain of the gain element is at the reduced level; and increasing the gain of each of the plurality of gain elements to a level sufficient to propagate the signal input to the gain element no earlier than a time at which the input signal changes.

Another embodiment describes a variable gain element for an analog computer, comprising: a first transistor and a second transistor, each transistor having a gate, a source, and a drain, the gate of the first transistor being configured to receive an input signal, and the gate of the second transistor being connected to a reference point; a first resistor connected to a drain of the first transistor and to one side of the voltage source, and a second resistor connected to a drain of the second transistor and to the voltage source; a current source connected to the sources of both the first and second transistors, the current source configured to provide different levels of current in response to a control signal; an amplifier having an input terminal connected to the drains of the first and second transistors and a reference point and an output terminal providing an output of the gain element; and a control circuit configured to provide a control signal based on a preselected condition.

Another embodiment describes a variable gain element for an analog computer, comprising: a first amplifier configured to receive a signal at a first end and to produce an amplified signal at a second end; a first resistive element having a first end configured to receive an input signal of the variable gain element and a second end connected to the first end of the first amplifier; a second resistive element having a first end connected to the first end of the first amplifier and a second end connected to the second end of the first amplifier; a switch having a first end connected to the first end of the first amplifier, a second end connected to the second end of the first amplifier, and a switch port configured to receive a control signal, the switch being in an open position or a closed position depending on the control signal; control logic configured to provide a control signal to open or close the switch based on a preselected condition; and a second amplifier configured to receive the signal at a first end and to generate an amplified signal at a second end, the first end of the second amplifier being connected to the second end of the first amplifier, and the second end of the second amplifier being configured to generate an output signal from the variable gain element.

Yet another embodiment describes a simulation computer comprising: a plurality of gain elements configured to operate on the aggregate input signal to provide a solution to a predetermined problem, the gain of each gain element being variable between a level sufficient to propagate a signal input to the element and a level insufficient to propagate the input signal; a gain control device configured to switch a gain of the gain element between a level sufficient to propagate the input signal and a level insufficient to propagate the input signal based on the control signal; and logic means configured to generate a control signal that causes the gain control means to switch the gain of the gain element to a level insufficient to propagate the input signal before a change in the aggregate input signal occurs, and to switch the gain of the gain element to a level sufficient to propagate the input signal no earlier than the time at which the input signal changes.

Drawings

Fig. 1 shows a gain element with variable gain according to an embodiment.

Fig. 2a and 2b are graphs showing gain characteristics of the gain element of fig. 1.

Fig. 3 is a block diagram illustrating a circuit including multiple gain elements (e.g., the multiple gain elements shown in fig. 1) placed in series.

FIG. 4 is a timing diagram of the output of the circuit of FIG. 3 in response to a new input, both under the prior art and an embodiment of the method described herein.

FIG. 5 is a graph of a plurality of random simulations of the operation of the circuit of FIG. 3 in one embodiment.

Fig. 6 is a block diagram illustrating an example of a simulated neural network known in the art.

Fig. 7-9 are graphs of an example of one of the outputs of the simulated neural network of fig. 6.

Fig. 10 shows a block diagram of an embodiment and a block diagram of a prior art circuit providing similar functionality.

Fig. 11 and 12 are graphs of comparative speeds for the circuit of fig. 10.

Fig. 13 is a diagram of an inverter circuit illustrating certain aspects of the methods described herein.

Fig. 14 shows a graph of the results of sending logic signals through a series of examples of the inverter circuit of fig. 13 at different values of the control signal.

FIG. 15 is a circuit diagram of one embodiment of a differential circuit according to one embodiment.

Fig. 16 is a circuit diagram of a circuit in which the differential circuit of fig. 15 is used in an amplifier as an element of an analog computer according to an embodiment.

FIG. 17 is a circuit diagram of a circuit in which an analog computer may be implemented using multiple instances of the circuit of FIG. 16, according to one embodiment.

Fig. 18 is a circuit diagram of a circuit in which the amplifier of fig. 15 can be changed to any type of two-input gate, according to an embodiment.

FIG. 19 is a flow diagram of a method of operating a simulation computer according to one embodiment of the method.

Detailed Description

Described herein are apparatus and methods for improving the performance of analog computers. The described apparatus and methods utilize a trade-off reduction in gain of high gain elements present in an analog computer, either globally (i.e., across all instances of the high gain element) or in a meaningful block or subset of the high gain elements.

Those skilled in the art will appreciate that in analog computers, the conventional solution to the problem to be solved is determined by the simplified assumption of high gain in operational amplifiers configured within the analog computer.

As described above, there is a transient of some finite duration between the "old" solution of an input (or set of inputs) and the "new" solution of a new input. However, rather than waiting for this limited duration to obtain a new solution, according to the present method, empirical observations have shown that if the gain elements of the analog computer are all reduced to a gain insufficient to propagate the solution within the computer network, the analog computer need not perform a transient response from the old input to the new input.

In particular, the method of the invention is illustrated by a series of steps:

first, when the old input state is present on the computer, the gain of the computational element within the analog computer is reduced to a level insufficient for the gain element to propagate a signal. This will result in the degradation of the current input: in the extreme case where the gain goes to zero, the voltage and current in the computer will be reduced to only thermal disturbances. Thus, a signal that is assumed to still be present at the computer input cannot propagate through the computing element and will "disappear" in an element that is sufficiently far (in terms of connectivity) from the input.

Next, when the analog computer is in such a degraded state with insufficient gain, the input (or set of inputs) is adjusted to a new input value (or set of values). This has little impact on the computer because the effect of the first step above is that the gain is too low to solve the new problem.

Finally, the gain of the computational element is then restored slightly after or while applying the new input to a level of gain sufficient for the gain element of the analog computer to propagate the signal, thereby solving the problem now presented by the new input.

The benefit of this procedure is that even in the case where there are these three steps, the time taken to respond to a new input is shorter than would result if the gain did not decrease as the input changed. Contrary to what one skilled in the art would expect. For example, reducing the power supply to a Complementary Metal Oxide Semiconductor (CMOS) logic chip typically reduces speed rather than increases speed; for example, a computer processor may slow in response to a decrease in available power, and thus performance may slow rather than fast.

This process can be viewed as changing the "noise margin" of the system. As is known in the art, in order to be detectable and useful, the signal must exceed the noise that necessarily accompanies it by a sufficient amount so that the signal can be distinguished from the noise; the noise margin is the ratio of the signal over the minimum acceptable amount.

In an analog computer, the signal must exceed the noise to a tolerable error rate. Since noise has a gaussian distribution and is theoretically infinite in amplitude, the noise margin can be considered as the number of standard deviations that the signal must exceed to meet the average noise for a given error rate. For example, a signal with three standard deviations in amplitude from the average noise will be noisy for more than about 0.3% of the time, while a signal with six standard deviations in amplitude from the average noise will be noisy for more than only 0.0000002% of the time.

Using the concept of noise margin, the methods described herein can be described as allowing the noise margin of the previous input state of the analog computer to degrade to the point where the signal is indistinguishable from noise, i.e., the noise margin is zero. The new input is then applied and results in an increase in noise margin. All signals then begin to separate from the noise and converge to a new solution. The convergence from noise to a new state is faster than the time required to transition from an old state to a new state across the noise margin in prior known systems.

Thus, the described method speeds up the simulation computer by defining a non-propagating, noise-limited state as an intermediate state between the two solutions. Further, in addition to running the analog computer faster, such acceleration may translate into reduced power operation of the analog computer, as will be appreciated by those skilled in the art in light of the teachings herein.

One simulation that may help understand the present method is the problem of placing grocery items on the shelves of a supermarket. Store employees have shopping carts filled with items and place the items on shelves in a certain order (e.g., alphabetically). After the task is completed, the manager considers this to be not an optimal arrangement and requires the staff to rearrange the items on the shelves so that the items are placed in food type rather than alphabetical order.

The employee must now remove the items from the shelf and rearrange them. This is time consuming for several reasons; the employee must remove each "misplaced item from its location and then place it in a new location. But the new location may have been occupied by another item placed in the previous order. Thus, the employee must first move other items, and so on.

In this context, the method may be considered as a switch for all shelves, or as a separate switch for each shelf in a group of shelves. When activated, the switch will throw all items back into the cart. Thus, the employee must start over again to remove each item, this time arranging the items on the shelf according to the type of food. However, the process is faster because no item is still in its previous location, the employee never has to remove the item from the "wrong" location, and the new placement of the item is not blocked by the previously placed item.

Randomly placing items in the shopping cart before the items in the cart are shelved; thus, without ordering, the "noise margin" of the article is zero. The sequence is applied when the employee puts the item on shelf, so there is now a noise margin. In this example, returning to the unordered state by dropping all items from the shelves between the first alphabetical racking operation and the second food type racking is faster than an arrangement that actually moves all items directly from alphabetical to food types.

Fig. 1 shows one type of gain element that may be used, for example, in an analog computer. The circuit 100 will be recognized by those skilled in the art as a type of differential amplifier known as a long tail pair circuit with a resistive load and an additional current source I1. The circuit 100 includes two N-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) M1 and M2, two resistors R1 and R2 connected between a power supply VDD and the drains of the transistors M1 and M2, respectively, an amplifier U, and a current source I1.

In this case, the amplifier U is a voltage controlled voltage source with a gain of 1 and the voltage difference between the resistive loads R1 and R2 is conveyed to the output Out and hence to the next circuit. Point REF is ground which sets a threshold for whether the input signal is a high level signal or a low level signal and allows amplifier U to output a signal compatible with the next similar gain element.

However, while the amplifier has a gain of 1, the circuit 100 may have a gain greater than or less than 1. In the present approach, the current source I1 is capable of providing different levels of current (as explained further below) in response to a switch or control circuit. Fig. 2a and 2b show the changing characteristics of the circuit 100 when the current through the current source I1 is changed from 2 μ a to 8 μ a in steps of 2 microamperes (μ a). Over a certain input range (here +400 millivolts), the change in output (y-axis) with respect to input (x-axis) is less than 1 at a current of 2 μ A through current source I1, and the gain is greater than 1 at a current of 8 μ A.

This is because when the current level through the current source Il is sufficiently low, the transconductance of the transistors Ml and M2 drops and there is no current between the source and drain of the transistors, so no current flows through the resistors Rl and R2 and there is no output from the circuit 100. Thus, by reducing the current through current source I1, the gain of circuit 100 is reduced.

Thus, one way to increase the gain of a gain element, such as the circuit 100 of fig. 1, from a level insufficient to propagate a signal to a level required to propagate a signal is to add a switch or other element that increases the current through the current source I1 and control logic that causes the switch or other element to do so at an appropriate time (i.e., shortly before or simultaneously with a change in the input to the circuit 100). Another example of a method of reducing the element gain is described below with reference to fig. 10.

If the gain is to be increased after a change in the input signal, some type of detection and control circuit or logic may be used to determine that the input has changed and in response cause the gain of the gain element to increase. For example, a differential amplifier circuit may be sufficient to detect even small input variations and then generate a control signal to increase the gain of the gain element; after a time sufficient for the analog computer to propagate the input signal and reach the output, the gain is reduced again. In some cases, the gain of the gain element may be increased to a level sufficient to propagate the input signal while the input is varied; for example, if the input changes at regular intervals, a timing circuit may be used to increase the gain based on a preselected condition corresponding to the timing of the expected input signal (i.e., at a preselected time or interval at which the input signal is expected to change), and then decrease the gain again to a level insufficient to propagate the signal after a known period of time that the analog computer is able to propagate the signal and derive a new output solution. Note that in this case, increasing the gain "at the same time" as the input changes may even include: if the time for the gain increase to precede the input change is too short for the gain element to respond quickly enough to operate on the previous input signal (if any), the gain is increased slightly before the input signal actually changes. Alternatively, as will be appreciated by those skilled in the art in light of the teachings herein, the problem of input signals being somewhat premature may be addressed by using logic elements such as inverters, unity gain operational amplifiers, or similar devices that would introduce predictable short delays.

Consider now what happens when multiple gain elements, such as circuit 100 of fig. 1, are connected in series. Fig. 3 is a block diagram of a circuit 300 showing such an arrangement of gain elements; the gain element is designated U1 and the numeral 64 indicates that there are 64 such gain elements connected in series. The first total input a is applied to a first gain element whose output is output X; the output x becomes the input a of the next gain element and so on until the output of the last gain element is considered as the total output Y.

By such series-connected gain elements, it is then possible to compare the time taken to obtain a solution Y to the problem represented by the total input a in two different situations. In this example, it is assumed that there is no problem to be solved, but the output of the circuit is simply a duplicate input, in any case, time delays are inherently present in the conventional methods or the methods described herein.

In one case, conventional techniques, where the previous input and solution is replaced by a new input and solution, as described above, transients may occur in conventional analog computers, so the solution is only reached after the new total input a has propagated through all 64 active gain elements to determine the solution Y. In the second case, the method described herein, the gain of the gain element has been reduced to zero and then increased at a particular point in time.

FIG. 4 shows a graph of the results of an integrated circuit emphasis simulation program ("SPICE") simulation of the circuit 300 of FIG. 3 in both cases.

The input signal, the rectangular clock type signal, is shown by curve a in fig. 4, while the output signal is shown by curve B. Curve C in fig. 4 indicates the gain variation of the gain element.

As shown in curve C of fig. 4, by increasing the current through current source I1 from 2 μ a to 8 μ a, the gain of the gain element in circuit 300 increases at a time of 65.01 nanoseconds (nS). As mentioned above, before that, the gain of the gain element is low, so no signal propagates from the input and the output is therefore zero as shown in curve B.

Once the gain of the gain element is increased at 65.01nS, the circuit is able to propagate the input signal. Note that in this case, no gain element has a previous state, since the gain of the gain element was previously zero. Thus, when the gain is first increased, the circuit 300 operates according to the present method. As shown in curve B of fig. 4, the output reflects the input at 65.12nS time; in other words, it takes 0.11 nanoseconds or 110 picoseconds (pS) for the circuit 300 to reach the output from the disordered state of zero gain.

Now, with high gain and then no decrease, the circuit 300 will continue to operate, but now in a conventional manner, i.e., with a transient between the output produced by the input and the next output produced by the changed input. The first change in the input after the gain increase is the falling edge of the rectangular signal at 71.01 nS; the output changes at 72.14nS in response to changes in the input. Therefore, the transition time from the previous output to the new output is 1.13nS, which is more than 10 times the above-mentioned 0.11nS change without the previous output.

The next change in input as the input signal continues is the rising edge of the rectangular signal at 81.01 nS. Since the gain remains high, the circuit 300 again operates in a conventional manner of the prior art. The output changes at 81.71nS in response to the rising edge of the input signal, thus resulting in a transition time of 0.7 nS. Although this is shorter than the transition time in the case of a falling edge (this asymmetry caused by different rise and fall times is not uncommon), it is still more than six times as much as without the previous state.

In addition to faster processing times, the described method has additional benefits; when operating without gain, the circuit 300 uses much less power than when operating in a conventional manner.

In normal operation, all 64 gain elements of circuit 300 would require a continuous current through Il of 8 μ A for a total current of 512 μ A. In contrast, when operating in the manner described herein, each gain element only requires 2 μ Α or 128 μ Α except for the time period for which the circuit 300 must respond to changes in the input, i.e. approximately 110pS for each input change (again allowing for different rise and fall times). It can therefore be seen that if the gain of the gain element is increased when an input change is applied and then decreased after a new output is obtained, the total current consumed will be only slightly higher than a quarter of the current consumed in normal operation.

Fig. 5 is a graph of 16 random simulations of the operation of the circuit 300 of fig. 3 using the present method described herein. As can be observed by line 502, the input is provided at the same time as the gain is increased (in this example at 65 nS). The shaded area 504 in fig. 5 is the outline of all responses in the 16 simulations. In the best case, circuit 300 reaches the output before a time of 65.1nS (i.e., less than 100pS), as observed at point 506, and in the worst case, the output reaches the effective level before a time of 65.5nS (i.e., less than 500pS), as observed at point 508, even with random variations in the configuration of a given gain element. This is still less than half the time of 1.13nS found in idealized simulations of circuits operating in a conventional manner (as discussed above with respect to fig. 4), thus demonstrating the benefits of the present approach, even in the presence of random manufacturing errors.

One area that may benefit from the present approach is the design of analog Artificial Intelligence (AI) processing units. The simulated AI computer may be made up of a plurality of circuits, such as circuit 100 of fig. 1, using a T-model implementation of an AI network as is known in the art.

AI neural networks are known to have "layers". The higher the number of layers, the greater the benefit that the method can provide, as the benefit increases as the number of layers through which the input signal must propagate increases.

Fig. 6 is a block diagram illustrating a simulated neural network 600 as known in the art. As shown, the neural network 600 has eight layers, each layer including elements Xn, thus producing eight outputs. Each element Xn has 8 neurons in a vertical column, each neuron has 8 resistances, and thus each element Xn has 64 weights; since there are 8 elements Xn in the horizontal direction, there are 64 neurons and 512 weights in total.

Fig. 7-9 also show a comparison of one of the eight outputs of the AI neural network 600 of fig. 6 under two different conditions (one being conventional in the prior art and the other being the method of the current invention described herein). In fig. 7 to 9, two input modes alternating every 10nS are applied. In the curve 702, the gain of the gain element of the AI neural network 600 simultaneously increases with one change in the input pattern at a time of 30 nS; in curve 704, the gain is simultaneously increased with another change in the input pattern at 40 nS.

When the input mode changes from low to high at 40nS, the AI neural network 600 is in normal operation because the gain has been high since 30nS, so there are previous output states and transition times as described above. Solid line 702 shows the output switching from its low level (approximately-300 mV) to its high level (+300mV), and reaching a high level at 46.61nS at point 706, as observed in more detail in fig. 8.

When the gain increases (while the input changes from low to high) at 40nS, the AI neural network 600 operates using the method of the present invention and there is no previous state (previous output is zero). Dashed line 704 indicates that although the output begins negative at portion 708 first in the wrong direction, the output still reaches its high level faster at 45.16nS (fig. 8) at point 710. Thus, using the method of the present invention, a high level output is reached after 5.16nS at point 708, i.e., about 30% faster than normal operation, compared to 6.61nS at point 710 in normal operation.

Fig. 7 to 9 also show that the present method results in reaching the output in a shorter time, i.e. allows asymmetry in rise and fall times, even when the input mode is switched in the other direction. When the gain increases at 30nS with a change in the input mode, the AI neural network 600 again operates by the method of the present invention because there is also no previous state (previous output is zero). Here, the output reaches its low level at 3.28nS at point 712.

However, when the input mode is changed at 50nS, the AI neural network 600 operates in a conventional manner because the gain of the gain element is not reduced. The output returns to its low level at 54.37nS (i.e., 4.37nS later at point 714). Thus, switching the input mode from high to low will result in reaching a low output after 3.28nS using the method of the present invention, and still about 30% faster, than at 4.37nS using conventional operation.

Figure 10 shows a block diagram of an embodiment of the method compared to a prior art circuit providing a somewhat similar functionality but not using the method of the invention. Simulations using the circuit of fig. 10 provide additional evidence of the speed improvement obtained by using the described method rather than the prior art.

Each circuit 1002, 1004 and 1006 in fig. 10 comprises a first amplifier Ul and a second amplifier U2, feedback components Rl and R2 and a capacitor Cl. The amplifier U1 has a gain of, for example, -10,000, and those skilled in the art will appreciate that the amplifier U1 will therefore operate as a high gain stage with a signal gain defined by the feedback components R1 and R2 (i.e., gain-R1/R2), while the second amplifier U2 operates as a signal inverter, such that the output of the circuit 1002 is not inverted and the overall gain of the circuit 1002 is R1/R2. Capacitor C1 defines a finite bandwidth for the gain of each circuit so that the delay of each circuit can be accurately compared, which is not otherwise necessary for the function of circuits 1002, 1004, and 1006.

In this example, each circuit 1002, 1004, and 1006 is connected in a chain of 1000 such circuits, as shown by the bracketed symbols 1002[1000], 1004[1000], and 1006[1000 ]. In contrast, the conductors to the left of R2 and to the right of U2, when present from each repeated instance of circuitry, have a bus width of 1000 and are therefore different in each repeated instance of circuitry.

The thousands of elements on the bus to the left of R2 consist of: first the input line In for the Least Significant Bit (LSB) location and then the elements 998 to 0 from the output bus Out of the previous circuit. This nomenclature results In a series connection of 1000 instances of X1, since In enters element 0 of R2 and a signal appears on element 0 of bus Out. The 0 th element of the bus is then connected to the next LSB, i.e. the first instance of the repeating circuit whose output is again the first element of the output Out of the first instance of the circuit, which is connected to the instance of the second circuit, and so on. The intended result of all one thousand X1 series connections is achieved through this nomenclature and the use of a bus.

Using the bus and iteration instances in this manner allows for a reasonable representation of complex circuits when (as in the present description) it is assumed that each iteration instance may be different. It is this difference in the iteration example that allows for the variation of the circuit and the implementation of a network of code expressions similar to the methods commonly used in the field of AI development.

Circuit 1002 of fig. 10 is an embodiment of a method of using the present invention. As mentioned above, the method of the present invention has means to reduce the gain of the gain element; in circuit 1002, such a device is shown as switch S1 having a control port that receives a control signal C, which is driven by control logic 1008 that determines the state of the control signal C.

If the control signal C is active, switch Sl closes, thereby significantly reducing the gain, because closing switch Sl shorts out resistor Rl, reducing Rl/R2 to near zero. Note that control signal C is common to all 1000 instances of circuit 1002 and is received by all instances of circuit 1002, as shown by the fact that the conductor from C to repeating element 1002 is not a bus, but has a width of 1. If R1 is equal to R2, the nominal gain of circuit 1002 is 1.

The circuit 1006 of fig. 10 is an example of a linear amplifier used for analog computation that does not have the benefits of the present approach because the circuit 1006 does not contain a means to reduce its gain. As with circuit 1002, if R1 is equal to R2, the nominal gain of circuit 1006 is 1.

The circuit 1004 is a model of a logic gate as is known in the art. In circuit 1004, the value of R1 is much higher than the value of R1 in circuits 1002 or 1006. Thus, the gain of circuit 1004 from the R2 input to the U2 output is higher than circuits 1002 or 1006. However, the gain is limited by the back-to-back diodes D1 and D2. The result is that the circuit 1004 operates in a logic gate-like mode, i.e., there is a high gain region near the nominal zero input point, but the output is limited to a limited range by some means (typically the power supply rail in the case of CMOS).

By connecting 1000 instances of each of circuits 1002, 1004, and 1006 in series separately, a test bench can be created to simultaneously compare three different methods for signal processing.

In this example, all resistors Rl and R2 are set to a value of 10k Ω, except that resistor Rl in circuit 1004 is set to 100k Ω. Thus, the gain of circuit 1004 from the R2 input to the U2 output is nominally 10, rather than 1 as in the case of circuits 1002 and 1006.

Fig. 11 and 12 are graphs of comparative speeds for the circuit of fig. 10. As a test, the input signal In of each series circuit 1002, 1004, and 1006 was initially set to-0.5V and switched to +0.5V at a time of 1 nS. The signal C used as control in the circuit 1002 is initially set to 1V, keeping the switch S1 closed and keeping the circuit 1002 in a low gain, non-propagating state. At a time of 4nS (i.e., 3nS after the input change), signal C becomes 0V, opening switch S1 and increasing the gain in circuit 1002, allowing the signal to propagate. The In and C signals are shown In curve a of fig. 11.

The response of the various circuits is shown in curve B of fig. 11. As shown by curve 1104, the serial digital logic circuit 1004 of fig. 10 has switched at approximately 1.4 microseconds (μ S). Plot 1106 shows that the linear circuit 1006 of figure 10 without the use of the present method has switched at about 1 mus. Thus, even without the benefit of the method of the present invention, chains of linear amplifiers, each having the same gain-bandwidth product as a logic gate, will respond faster than a series of logic gates. Note that in both of these circuits, the output must change from a low value due to the presence of the previous state.

The circuit 1002 of fig. 10 using this method shows the fastest response. Prior to the gain change at time 0 on the X-axis, circuits 1004 and 1006 are in the previous state, as shown by curves 1104 and 1106, respectively. However, the circuit 1002 is in a zero state (as is the next gate in the chain), but there is no noise margin at this time, only a thermal variation. All three circuits start to respond once the input signal and gain change. If the 100mV output signal is of acceptable tolerance, as shown by curve 1102 of FIG. 11, the output of series circuit 1002 rises from a zero state to a level beginning at about 800nS, which again is significantly faster than the other circuits 1004 or 1006 reaching that output level at about 1.4 μ S and 1.1 μ S, respectively, and approaches their final values faster than circuits 1004 or 1006.

Another comparison between the series linear amplifier circuit 1002 benefiting from the present method and the one without such benefit 1006 is shown in figure 12. It is assumed here that the output cannot be assumed to be valid until the output reaches half its value, or about 220mV, as shown in fig. 11.

Fig. 12 is a graph of position in the chain of elements in series circuits 1002 and 1006 versus digital delay percentage. Curve 1202 shows the result of the series linear amplifier circuit 1002 of fig. 10 using the present method. Curve 1206 shows the result of the series linear amplifier circuit 1006 without the benefit of the present approach.

The X-axis of fig. 12 is logarithmic and indicates the location where the delay comparison is made in the series circuit. The Y-axis is the percentage speed improvement of the series circuit relative to the digital circuit 1004 of fig. 10.

As observed in curve 1206, the series circuit 1006 progressively approaches a 25% decrease in delay as compared to the series logic gates as the number of connected elements increases. The series circuit 1002 using the present method shows a greater speed improvement up to about 500 circuits connected in series. The present approach can increase speed by about 28% in the typical case of using up to 20 layers in a neural network.

Note that these results also greatly underestimate the advantages of analog computers over digital computers in certain applications, since complex computations can be done in analog computers within only a few equivalent gate delays. For example, an analog computer configured to solve the fourier transform of a signal over 128 packets requires 8 layers of analog processing units. As shown in fig. 12, these 8 cells will operate approximately 70% of the time for the 8 series logic gates.

However, of the 8 logic gate delays, almost nothing in the digital processor can be done; in a digital computer, the fourier transform may require thousands of gate delay equivalents. Thus, in some types of applications, analog computation may be thousands of times faster than digital equivalents, and even faster by using the present method.

Fig. 13 is a diagram of a circuit 1300, and fig. 13 illustrates certain aspects of the present method, namely the speed increase and control mechanism that can be achieved when noise margin is reduced.

Element U3 in circuit 1300 is a conventional inverter known in the art. R1 and R2 are ideal resistors, and the resistance of R1 can be adjusted in response to the voltage applied at port C, which serves as a control signal. The control logic 1302, which may be a detection of the timing circuit as described above, determines what voltage is applied at port C. For demonstration, R1 may be a macro model, i.e. a code model of an electrical device. Examples of code models that describe R1 are:

AR1 AB i ═ V (a, B)/(10k + V (c) × 40k) (equation 1)

This indicates that the adjustable resistor 1 has current flowing between terminals a and B of R1, which R1 varies based on the voltage v (C) applied at port C, corresponding to a resistance of 10 kilo-ohms when v (C) is 0 volts, 50 kilo-ohms when v (C) is 1 volt, 540 kilo-ohms when v (C) is 10 volts, and so on (the choice of 40 kilo-ohms value in equation 1 is arbitrary). Thus, R1 can be adjusted between 10 kilo-ohms and 50 kilo-ohms when a control signal of up to 1 volt can be provided. In this case, a suitable value for R2 is 10 kilo-ohms.

Circuit 1300 also includes buffers Ul and U2, which do not change the voltage applied to them but are used to reduce the voltage gain of inverter U3. The buffer U1 prevents the current flowing through R1 from creating a load on the output of the inverter U3, and the buffer U2 prevents any element of the drive input port from being loaded by the resistor R2. The input node of inverter U3 is assumed to be high impedance and therefore is not affected by the presence of resistors R1 and R2 on the input node.

As is known in the art, the gain of the circuit 1300 is limited by the feedback loop and has the highest gain of R1/R2. Thus, under the constraint that V (C) tends to infinity, circuit 1300 looks like a conventional inverter of the prior art. The input signal to inverter U3 arrives through input port X, buffer U2, and resistor R2. The output signal appears on port Y and since v (c) is assumed to be a high voltage, R1 has a high impedance and has no effect on the input signal arriving via R2. Furthermore, the presence of R1 has no effect on the output of inverter U3 because buffer U1 removes the resistive load.

Even a relatively high voltage v (c) does not significantly limit the gain of the inverter. For example, if V (C) is 10 volts, then the value of R1 is 540 kilo-ohms. Since the value of R2 is 10 kilo-ohms, the gain of inverter U3 is again limited by resistors R1 and R2 to R1/R2, i.e., 54; however, this is typically higher than the inherent gain or "self-gain" of inverter U3. Therefore, the transfer of the signal from the input port X to the output port Y is not affected, and is not affected by any of the variable gain aspects of the method.

However, as the control signal voltage v (c) decreases, the inverter gain begins to be limited. As described above, when v (c) is 1 volt, the value of R1 is actually 50 kilo ohms, so R1/R2 is 5 and the inverter gain limit is 5. The circuit 1300 of fig. 13 can thus be used as a "test stand" where varying values of v (c), and thus various gains, can be applied to the inverter U3.

Fig. 14 shows a graph of the result of sending a logic signal that goes from low (zero) to high (one) through a series example of 32 circuits 1300 of fig. 13 at different values of the control signal v (c). The rightmost curve 10 of fig. 14 is for v (c) 10v and corresponds to a known technique where the inverter gain is substantially unlimited, without the benefit of the present method. The Y-axis shows the output of the series circuit.

The X-axis of fig. 14 shows the time it takes for the series circuit to change the output from low to high, and is marked to show that the delay of the series circuit 1300 operating as in the prior art is nominally zero. As can be seen from the other curves of fig. 14, as the voltage v (c) decreases, the input signal can propagate through the series circuit more quickly.

This demonstrates one aspect of the method: the delay of the event chain (whether logic delay in this example or an analog signal through the amplifier chain) is affected by the gain each element has. This is in contrast to what one skilled in the art would expect to increase the delay with decreasing gain rather than the decrease in delay seen here.

One possible conclusion from this effect is that if a certain signal-to-noise ratio is required, the signal amplitude must exceed a calculable amount of noise in the circuit. As the gain of each element decreases, the signal amplitude also decreases: this can be seen in fig. 14, where the highest and lowest levels of the waveform vary as the gain decreases. In other words, the noise margin, i.e. the extent to which the signal exceeds the noise, is reduced. In certain configurations that are the subject of the present method, reducing the noise margin allows for higher speeds.

It may be argued that the results of fig. 14, while interesting and demonstrating a compromise between noise margin and speed, indicate that the method is not practical. First, gain reduction in prior art inverters is achieved by limiting their output swing through feedback. It is well known that this can significantly increase gate power consumption (since the output of a CMOS logic gate can cause DC current to flow through both N-type metal oxide semiconductor ("NMOS")) and P-type metal oxide semiconductor ("PMOS") devices if the voltage between the power supply rails is maintained).

Second, a reduced noise margin, i.e., a reduction in signal-to-noise ratio, will be considered unacceptable in terms of Bit Error Rate (BER) requirements. For example, if a one-bit-per-billion error is desired, the signal-to-noise ratio in the logic (or analog) circuit must be high, which means that the noise margin must be relatively large. The noise margin required to meet the ideally very low BER does not result in a reduction in delay. Nevertheless, fig. 14 shows that the present method can speed up the performance of the circuit by using a control signal (v (c) in this example) that dynamically controls the gain of the circuit.

However, the noise margin does not have to remain at the final noise margin throughout the operating time. At the beginning of the calculation interval (i.e., when the circuit first starts calculating a new result), the noise margin may be low and the delay short, as described above. As the calculation interval evolves, the noise margin rises, so at the end of the calculation interval, the noise margin is large enough to support the required BER.

Some of the internal calculations (e.g. changes in electrical parameters such as voltages on logic gates, outputs of operational amplifiers or similar terms in an analog computer) required to calculate the final output evolve in the first part of the calculation interval when the noise margin is low, thus benefiting from reduced delay. Due to the fact that some of these calculations occur during low noise margins (higher speed environments for the first part of the calculation interval), the total time to reach the desired bit error rate is reduced. This is another benefit of the present method.

Also, some skilled in the art will recognize that many means of reducing noise margin (e.g., reducing the supply voltage of a CMOS logic circuit or operational amplifier) do not result in an increase in speed. However, as described above, the present method is a case: the reduced noise margin does result in an increase in speed, as shown in fig. 14. Of course, there are still some issues to be considered for the circuit 1300 of fig. 13.

As mentioned above, the first problem is that a certain noise margin is required to meet a given BER; also as described above, the noise margin is variable within the calculation interval and the desired noise margin is reached before the end of the interval. The second problem is that the circuit 1300 of fig. 13 consumes significantly more power in the low noise margin, high speed state. Thus, the speed-power product of the circuit 1300 of fig. 13 may not be as good as a circuit that does not benefit from the present approach.

There are many techniques available in the known art for accelerating computers; for example, by advancing the process to sub-10 nanometer dimensions, or by parallel connection of CMOS devices (increasing width), the gate size can be changed to provide more current during the transition. It is well known that these result in some speed-power product: at this point in the technical roadmap, the velocity-power product has a specific value. The current approach may be a less useful innovation if noise margin is to be reduced and speed is to be increased at the expense of consuming more power. However, the method may also improve the speed-power product.

Embodiments of the present method, which will now be described, alleviate these problems of the circuit 1300 of fig. 13. In particular, this embodiment takes advantage of the observation that the computing device, whether an asynchronous logic gate chain (e.g., a known set of several gates forming a seven-segment decoder, or a very large number of gates forming a digital multiplier) or a set of interconnected analog computing elements (e.g., operational amplifiers configured to solve differential equations), has limited operating time and accuracy (i.e., no significant BER) depending on the final result of the noise margin described above.

Note that in each example of the present method, there is at least one control signal corresponding to signal v (C) on node C of circuit 1300 in fig. 13. This control signal will cause the noise margin to change during the calculation interval of the system that benefits from the present method.

FIG. 15 is a circuit diagram of one embodiment of a differential circuit 1500 using the present method that may be used in an analog computer.

Similar to the differential circuit 100 of fig. 1, In the circuit 1500, a differential amplifier is formed by transistors M6 and M11 that receive the non-inverting input signal In, and transistors M7 and M11 "that receive the inverting input signal" Inb "or" In-bar "(shown In fig. 15 with a line above In to indicate inversion, as is common In the art). The inverted output signal "Outb" (shown similarly as a line above "Out") emerges from the common drain connection of transistors M6 and M10, and the non-inverted output signal "Out" emerges from the common drain of transistors M7 and M11.

These nodes Out and Outb are fed back to a bias control device formed by transistors M2, M3, M4 and M5 and transistors M12, M13, M14 and M15 (the latter being referred to as sub-circuit 1502 in fig. 15), which is equivalent to current source I1 in the circuit 100 of fig. 1. The bias control is insensitive to the normal mode output voltage (i.e., the voltage difference between Out and Outb), but is responsive to the common mode output voltage (the average of the voltages on Out and Out).

It will be seen that as shown here, transistors M10-M15 are NMOSFETs, while transistors M2-M7 are PMOSFETs, and form mirror images of transistors M10-M15. The transistors in circuit 1500 operate at a source-drain voltage that is lower than the source-gate voltage, and the amplifier does not consume any current other than the current flowing through the input device. Thus, the circuit 1500 efficiently utilizes current when operating during a calculation interval, which is a fraction of the time, as will be described below.

The circuit 1500 utilizes a control node K that can disconnect the transistors M2-M15 from the power supply DVcc. When the voltage on node K is high, PMOS device M1 turns off and no current flows from the power supply. Node K is also connected to transistors M8 and M9, transistors M8 and M9 being NMOS devices. Thus, when the power supply is turned off due to the signal on node K going high, the output is shorted to the input through transistors M8 and M9. This is done to prevent the unknown voltage from being output as an input to the next series circuit.

Those skilled in the art will note that this connection of node K to the turn-off device transistor Ml and the short-circuit device transistors M8 and M9 need not be a direct connection as shown in fig. 15. Two separate control lines may be used, one for the turn-off and the other for the short-circuiting device; this will allow the timing of the two actions to be different, which may be advantageous in some situations. For example, separate control of the power down and shorting devices may reduce computational errors due to device parameter mismatch (which may be nominally fixed or variable with source-drain current).

This is because the improved speed-power product of this embodiment is achieved by reducing the amplifier current to zero and using a virtual ground configuration when active (i.e., during the calculation interval). The virtual ground configuration discussed below does not create an ideal virtual ground because threshold voltage mismatches may make it inaccurate. This virtual ground error voltage can be stored on a capacitor (as described below) when the amplifier is powered up to an active state, and is achieved by first powering up the circuit and then removing the shorting device after a short delay. This is an example where separate control of the power-down device and the short-circuit device may be advantageous.

Those skilled in the art will appreciate that if the input common mode voltage can be a fixed value (as can be achieved by using capacitors surrounding the circuit 1500 as shown below), the bias control device 1502 formed by transistors M12, M13, M14, and M15 can be omitted and the sources of M10 and M11 can be directly connected to ground DGnd.

Fig. 16 shows a circuit 1600 in the simplest configuration of the elements of an analog computer using the present method, where the component of fig. 15 is used as an amplifier U1. Those skilled in the art will recognize circuit 1600 as a virtual ground configuration, which is a configuration known in the art, except for the specific implementation of amplifier U1.

As discussed above with respect to circuit 1500 of fig. 15, when the control signal on node K is high, both the power down device and the short circuit device within amplifier Ul are active, and thus circuit 1600 is in a quiescent state. The capacitors C1 and C2 are shorted by an internal shorting device of the amplifier U1. The switches S1 and S2 connect the capacitors C2 and C4 to the input signal nodes In and Inb. This state may exist as long as desired; no calculations are performed and no power is consumed.

The calculation interval begins when the control signal on node K goes low. At this point, the gain element in amplifier U1 is energized and the shorting device is removed. (As noted above, the removal of the shorting device may be delayed slightly by using separate controls for the shorting and deenergizing devices

Simultaneously with the supply of power to the amplifier Ul, the switches Sl and S2 now connect the left side of the capacitors C2 and C4 to ground (this is the switch configuration shown in fig. 16, as is conventional in the art for virtual ground configurations). Capacitors C2 and C4 have a charge on them due to the time it takes to connect to the input signals In and Inb. This charge is transferred to capacitors C1 and C3 and appears as an output voltage. When this voltage occurs, the calculation interval is complete and the circuit can return to the quiescent state by driving the control signal on node K high again. The circuit 1600 of fig. 16 is an example of one embodiment of the present method, but the circuit 1600 itself appears to accomplish what seems trivial, namely that the circuit 1600 transmits the input voltage difference between In and Inb to the output terminals Out and Outb during the calculation interval, possibly with a gain or attenuation determined by the ratio of the capacitors as is well known In the art. However, the action of circuit 1600 remains the basis for potentially more complex computations.

Circuit 1700 of fig. 17 illustrates how multiple instances of circuit 1600 of fig. 16 may be used to implement an analog computer capable of complex computations while retaining the advantages of the present approach, i.e., faster speed and reduced power consumption.

The circuit 1700 may be viewed as a two-dimensional array of multiple instances of the circuit 1600 of FIG. 16. As shown in fig. 17, circuit 1700 has four such instances, as shown by four amplifiers Ul through U4; again, each amplifier U1-U4 contains an example of the circuit 1500 of fig. 15. The four instances of the circuit 1600 in the circuit 1700 are arranged in a two-dimensional array having two rows and two columns, a first column with amplifiers U1 and U2 and a second column with amplifiers U3 and U4, a first row with amplifiers U1 and U3 and a second row with amplifiers U2 and U4. The array can have any desired number of such instances of circuitry 1500 in a given configuration, and thus can have any desired number of rows and columns.

Each amplifier Ul to U4 contains the turn-off and short-circuit devices described with respect to circuit 1500 in fig. 15 above, and all receive the same control signals discussed above. However, for convenience of representation, the node K receiving the control signal and the signal line supplying the control signal to each of the amplifiers U1 to U4 are not shown in the circuit 1700.

Connecting multiple instances of circuit 1600 in this manner allows for some variation in the implementation of each instance of circuit 1600. First, each amplifier in the first column, i.e., amplifiers Ul and U2, may receive a different input signal. Furthermore, multiple inputs of a single amplifier may be used by adding capacitors between the multiple inputs and the amplifier; thus, for example, in addition to the capacitors C2 and C4 shown in fig. 16, the additional capacitors C5 and C6 allow for additional inputs to the amplifier U1 and also allow for these inputs to have different weights by selecting different values for the capacitors. The use of such additional capacitors may be applied to all of the amplifiers U1 through U4 as shown in fig. 17; however, while fig. 17 shows all of the amplifiers U1-U4 having the same number of inputs, this is not required and each amplifier may have a different number of weighted inputs where appropriate in a given circuit.

Further, as shown in fig. 17, in the case where the input of the amplifier in the second column is from the output of the amplifier in the first column, the switches Sl and S2 are not required in the second row, because the positions of the switches connecting the first column amplifiers U1 and U2 to the input signal are also operated by the above-described control signal K.

Those skilled in the art will appreciate that the arrangement of columns and rows described herein and shown in the figures is similar to the arrangement of neurons in a layer in a neural network. As in the first column of fig. 17, the first layer of the neural network includes some number of switches that sample the input voltage, with subsequent layers being directly connected to the outputs of the previous layers. The connections between the layers may be arbitrarily complex, as a given amplifier may have any number of inputs. Furthermore, the sum of the voltages into each neuron in the neural network can be arbitrarily weighted, as can the difference in the values of the capacitors in circuit 1700.

The circuit 1700 of fig. 17 is a simple circuit used to show how layers and connectivity used in a neural network can be arranged using the present method with multiple amplifiers of the type shown in the circuit 1500 of fig. 15. In practice, a useful case of the method may have 4000 or more such amplifiers in each column or layer, and as many as 100 or more such layers. Connectivity between layers will be achieved by using capacitors of different values to create the required signal weights.

When the global control signal goes low as described above, the charge on the capacitors connected to the input (e.g., capacitors C2, C4, C5, and C6 in circuit 1700) is pushed into the amplifiers of the first tier (e.g., amplifiers U1 and U2 of circuit 1700). This causes the output of the first layer to push charge into the second layer, which in turn pushes the output of the second layer into the third layer (if present). This is a transient, i.e. a calculation interval as described earlier.

At a much more complex level than fig. 17, it will be seen that the calculation interval is the time for charge to flow from the input to the various nodes of the network. The circuit of fig. 17 and all such similar circuits can be viewed as a "charge redistribution network" that manipulates charge similar to the problem that the network is intended to solve. The amplifier only needs to remain active when charge redistribution occurs; once this activity subsides, the voltage on the network outputs (output signal lines Out1 and Out2 of fig. 17) may be sampled as is known in the art, and the control signal for the entire network may return to a high level, thereby shutting off power as described above. Note that the output sampling can be done by a second instance of a complex network using the present method. Thus, many such complex networks may be cascaded, each of which may contain thousands of amplifier elements as described in the present invention.

One example of a problem that may be solved by a network as described above is the Fast Fourier Transform (FFT). Simulations show that a circuit containing slightly less than 800 amplifier elements (e.g., circuit 1500 of fig. 15) and appropriate values of associated capacitors is capable of calculating an FFT in significantly less than 1nS, which is many times faster than a digital computer, and typically consumes one thousandth of the power of a digital equivalent. This speed and power improvement is an effect of the present invention.

Those skilled in the art will note that the above description relates primarily to use in devices such as analog computers where each amplifier element is the same, and therefore functionality is primarily created by using different weighting elements around a set of identical elements described as an amplifier. However, the invention has other uses.

Fig. 18 is a circuit diagram of circuit 1800 in which circuit 1800 the amplifier of fig. 15 can be changed to any type of two-input gate by defining which signal is considered to be the inverted signal, so that an AND, OR, NAND OR NOR gate can all be constructed using the same circuit.

The circuit 1800 adds transistors M16-M21. The input can now be considered a logic signal and the series/parallel arrangement of transistors M6, M16, M10 and M20 on one side and transistors M7, M19, M21 and M11 on the other side creates a two-input gate. This two-input gate can be duplicated multiple times and then connected directly without capacitors to form a digital network as is well known in the art. Thus, circuit 1800 is similar to circuit 1300 in FIG. 13 in that it runs faster than an equivalent digital network; unlike circuit 1300, however, circuit 1800 will operate at a lower power, circuit 1300 consuming more power than is possible with known techniques.

One skilled in the art may want to know whether the speed increase resulting from using the method described as shown in fig. 12 is significant enough to justify the additional complexity and circuitry required to change the gain of the circuit as described above.

However, as above, in some embodiments, reducing the gain of the amplifier circuit also reduces power consumption (although this is in the circuit 1002 of fig. 10 and not so, because the current in the amplifier Ul is not reduced by shorting the resistor R1 of the circuit 1002). In the discussion of fig. 6 above, it is noted that operation using the present method in this case will result in a reduction in power consumption of approximately 75%.

The application of the method in the calculation of the fourier transform of a signal is also considered. The required repetition rate of the fourier transform may be, for example, one million calculations per second. However, it may only take 10nS or less to perform each such calculation. Thus, the gain element only needs to be active for about 1% of the time, requiring more power. In this case the full benefit of the method can be seen, since the operation is faster, usually even faster than a few logic gates, and much lower power is used, since high power is only needed during the actual computation.

FIG. 19 is a flow diagram of a method 1900 of operating a simulation computer according to one embodiment of the present method described above.

At optional step 1902, inputs are applied to a plurality of gain elements having variable gains, such as the circuits 100 and 1002 above, which are placed in an appropriate circuit configuration of an analog computer to solve a predetermined, desired problem. For example, the gain element may be of the type shown as circuit 100 in fig. 1, with the addition of a circuit for reducing the current from current source I1, or as circuit 1002 of fig. 2. The gain elements may form a neural network as shown in fig. 6, or may be placed in different configurations to perform fourier transforms or other operations. Step 1902 is considered optional because in the case where the input is first applied to an analog computer, there will be no previous input.

At step 1904, when the previous output of the circuit (if any) is present, the gain of the gain element is reduced to a level low enough that the input signal cannot propagate through the circuit. As described above, this may be accomplished in the circuit 100 of fig. 1 by reducing the current through the current source I1 or by closing the switch S1 in the circuit 1002 of fig. 10.

At step 1906, the input signal is changed to a new value or set of new values while the gain of the gain element remains reduced.

Finally, at step 1908, the gain of the gain element is increased to a level high enough to allow the input signal to propagate through the circuit, thereby producing an output that is a solution to the problem represented by the analog computer. This may be accomplished in the circuit 100 of fig. 1 by increasing the current through the current source I1 or by opening the switch S1 in the circuit 1002 of fig. 10, as opposed to the gain reduction in step 1904.

As described above, in some embodiments, the gain of the gain element may be increased simultaneously with changes in the input signal, rather than after the input signal changes.

According to the method, an analog computer can be constructed with series gain elements having faster operation and lower power consumption compared to the prior art. Based on the teachings herein one skilled in the art will appreciate that an analog computer may be constructed in accordance with these principles.

The disclosed systems and methods have been described above with reference to several embodiments. Other embodiments will be apparent to those skilled in the art in light of this disclosure. Certain aspects of the described methods and apparatus may be readily implemented using configurations other than those described in the embodiments above, or in combination with elements other than, or in addition to, those described above.

For example, various options will be apparent to those skilled in the art, as is well known to those skilled in the art. Further, the illustrations of transistors, other circuitry and associated feedback loops, resistors, etc. are exemplary; those skilled in the art will be able to select the appropriate number of transistors and associated components as appropriate for a particular application.

These and other variations to the embodiments are intended to be covered by the present disclosure, which is limited only by the appended claims.