阅读说明：本技术 基于非晶氧化物半导体浮栅晶体管的器件及制作方法 (Device based on amorphous oxide semiconductor floating gate transistor and manufacturing method ) 是由 何勇礼 万青 于 2020-11-06 设计创作，主要内容包括：本公开涉及一种基于非晶氧化物半导体浮栅晶体管的神经形态器件的制作方法,该晶体管可以包括源漏电极、沟道、叠层栅介质和栅电极,其中叠层栅介质为三层结构,包括电荷隧穿层、电荷存储层和电荷阻挡层。通过栅电极控制电荷存储层中电荷量的多少来控制源漏电极之间沟道层的电导,也就是调制突触器件的权重。进而将器件集成为交叉阵列结构,加速神经形态计算中的矩阵运算,以降低功耗。该制作方法与目前的大规模集成电路工艺兼容,适合大规模生产。(The transistor can comprise a source electrode, a drain electrode, a channel, a laminated gate dielectric and a gate electrode, wherein the laminated gate dielectric is of a three-layer structure and comprises a charge tunneling layer, a charge storage layer and a charge blocking layer. The conductance of the channel layer between the source electrode and the drain electrode is controlled by controlling the amount of charge in the charge storage layer through the gate electrode, namely, the weight of the synapse device is modulated. And furthermore, devices are integrated into a cross array structure, so that matrix operation in the neural morphology calculation is accelerated, and the power consumption is reduced. The manufacturing method is compatible with the current large-scale integrated circuit process and is suitable for large-scale production.)

1. A method for manufacturing a neuromorphic device based on an amorphous oxide semiconductor floating gate transistor is characterized by comprising the following steps of:

depositing an oxide semiconductor as a channel layer on an insulating substrate;

defining a source electrode and a drain electrode;

growing a charge tunneling layer;

growing a charge storage layer;

depositing a charge blocking layer;

a top gate electrode is defined.

2. The method of claim 1, wherein the method comprises:

the charge storage floating gate structure modulates the conductance of the channel layer, so that the channel layer is integrated into a cross array structure, and matrix multiplication is physically realized to accelerate neuromorphic calculation.

3. The method of claim 2, wherein the charge storage floating gate structure modulating channel layer conductance comprises:

and updating and adjusting the synaptic weight.

4. The method of claim 1, wherein the method comprises: the substrate is made of glass, a silicon wafer with an oxide layer, plastic or paper.

5. The method of claim 1, wherein said oxide semiconductor comprises zinc oxide, indium gallium zinc oxide, indium tin oxide, indium tungsten oxide, or aluminum doped zinc oxide.

6. The method of claim 1, wherein the source and drain electrodes are made of a highly conductive oxide or metal.

7. The method of claim 1, wherein the charge tunneling layer and the charge blocking layer comprise materials selected from the group consisting of: aluminum oxide, hafnium oxide, silicon nitride, yttrium oxide, zirconium oxide, or silicon oxide.

8. The method of claim 1, wherein the charge storage layer is a highly conductive oxide, the highly conductive oxide comprising: zinc oxide, indium tin oxide, indium zinc oxide, indium tungsten oxide, or aluminum-doped zinc oxide; and a dielectric material of hafnium oxide, tantalum oxide, zirconium oxide or yttrium oxide.

9. The method of claim 1, wherein the top gate electrode is made of a highly conductive oxide or metal.

10. A neuromorphic device based on amorphous-oxide-semiconductor floating-gate transistors, comprising:

an oxide semiconductor deposited on the insulating substrate as a channel layer;

a source drain electrode;

a charge tunneling layer;

a charge storage layer;

a charge blocking layer;

and a top gate electrode.

Technical Field

The invention belongs to the field of neuromorphic device manufacturing, and particularly relates to a neuromorphic device based on an amorphous oxide semiconductor floating gate transistor and a manufacturing method thereof.

Background

With the rise of the big data era in recent years, the energy efficiency bottleneck of the traditional von neumann computer is further highlighted. Inspired by the working mode of the human brain, the neural morphological calculation is expected to simulate the human brain to realize low power consumption and real-time interactive calculation, and the calculation efficiency is greatly improved. Being able to implement neuromorphic calculations on a hardware level is a key to achieving low power consumption. While the human brain is a complex neural network consisting of about 1012 neurons and 1015 synapses. Therefore, the neural component with the characteristics of the neurons and synapses is developed from the bottom-layer device, and the neural network is further constructed from bottom to top, so that the method has great significance for constructing an artificial neuromorphic system.

Disclosure of Invention

Amorphous oxide semiconductors have attracted considerable attention in flat panel display applications and neuromorphic device applications due to their inherent advantages of high mobility, high uniformity, low temperature, large area fabrication, and compatibility with existing large scale integrated circuit processes. The amount of charge stored in the charge storage layer of the floating gate stack gate dielectric can conveniently adjust the conductance (G) of the transistor channel, namely corresponding to the weight in the synaptic device. As shown in fig. 8, such a crossbar array circuit can be used as an accelerator for neural network operations because the multiplication of vectors and matrices is physically directly realized by ohm's law (the product of voltage x and conductance G) and kirchhoff's law (each column is summed with current), and the matrix operation is the most time-consuming and energy-consuming calculation in modern neural networks.

The application provides a neuromorphic device based on an amorphous oxide floating gate transistor, wherein a charge storage layer in a laminated gate medium dominates synaptic weight updating. As shown in fig. 6, when a large forward programming voltage is applied to the gate electrode, electrons are injected from the channel into the floating gate. Because the floating gate is not electrically connected with the outside, injected electrons can exist in the floating gate, and the electric field formed by the electrons in the floating gate can cause the conductance of the channel layer to be reduced. As shown in fig. 7, when a large negative programming voltage is applied to the gate electrode, electrons are released from the floating gate into the channel. After the electrons in the floating gate bleed off, the channel layer conductance becomes large. The quantity of electrons in the floating gate can be controlled by controlling the magnitude of the programming voltage and the time of the voltage pulse, so that the conductance of the channel layer can be conveniently modulated.

The invention provides a neuromorphic device based on an amorphous oxide semiconductor floating gate transistor, which is compatible with the current large-scale integrated circuit process and suitable for large-scale integration.

In order to achieve the technical purpose, the technical scheme of the invention is as follows:

a method for manufacturing a neuromorphic device based on an amorphous oxide semiconductor floating gate transistor comprises the following steps:

(1) depositing an oxide semiconductor as a channel layer on an insulating substrate;

(2) defining a source electrode and a drain electrode;

(3) growing a charge tunneling layer;

(4) growing a charge storage layer;

(5) depositing a charge blocking layer;

(6) a top gate electrode is defined.

Furthermore, the insulating substrate is made of glass, a silicon wafer with an oxide layer, plastic or paper.

Further, the oxide semiconductor used in step (1) is zinc oxide, indium gallium zinc oxide, indium tin oxide, indium tungsten oxide, or aluminum-doped zinc oxide.

Furthermore, the source and drain electrodes used in step (2) are made of high-conductivity oxide or metal.

Further, the charge tunneling layer and the charge blocking layer material grown in the steps (3) and (5) comprises: aluminum oxide, hafnium oxide, silicon nitride, yttrium oxide, zirconium oxide, or silicon oxide.

Further, the charge storage layer grown in the step (4) is a high-conductivity oxide, and comprises: zinc oxide, indium tin oxide, indium zinc oxide, indium tungsten oxide, or aluminum-doped zinc oxide; and a dielectric material of hafnium oxide, tantalum oxide, zirconium oxide or yttrium oxide.

Further, the material of the top gate electrode used in step (6) is a highly conductive oxide or metal.

The modulation of the charge storage floating gate structure on the channel layer conductance, namely the adjustment of the synaptic device weight, the device manufacturing process and the existing large-scale integrated circuit manufacturing process are compatible, and the charge storage floating gate structure is suitable for large-scale integration.

Drawings

The above and other objects, features and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. In the drawings, several embodiments of the disclosure are illustrated by way of example and not by way of limitation, and like or corresponding reference numerals indicate like or corresponding parts and in which:

fig. 1 is a flow chart of device fabrication according to an embodiment of the present invention.

Figure 2 is a schematic diagram of an oxide semiconductor channel fabrication according to one embodiment of the present invention.

Fig. 3 is a schematic diagram of defining device source and drain electrodes according to an embodiment of the present invention.

FIG. 4 is a schematic illustration of device tunneling layer, charge storage layer and blocking layer deposition, in accordance with one embodiment of the present invention.

Fig. 5 is a top gate electrode definition diagram according to an embodiment of the invention.

Figure 6 is a schematic representation of electron injection from the channel into the floating gate in accordance with one embodiment of the present invention.

Figure 7 is a schematic diagram of electrons released from the floating gate into the channel in accordance with one embodiment of the present invention.

Fig. 8 is a device crossbar array structure of one embodiment of the present invention.

Description of reference numerals:

1. an insulating substrate. 2. An oxide semiconductor channel layer. 3. A transistor source electrode. 4. And a transistor drain electrode. 5. A charge tunneling layer. 6. A charge storage layer. 7. And a barrier layer. 8. And a top gate electrode. 9. And (4) electrons.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, but not all embodiments of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

It should be understood that the terms "first," "second," "third," and "fourth," etc. in the claims, description, and drawings of the present disclosure are used to distinguish between different objects and are not used to describe a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the disclosure. As used in the specification and claims of this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this disclosure refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.

As used in this specification and claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

Specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

As shown in fig. 1, a specific manufacturing method of a neuromorphic device based on an amorphous oxide semiconductor floating gate transistor includes the following steps:

step (1): spin coating a layer of photoresist on the insulating substrate, exposing and developing, then depositing an oxide semiconductor as a channel active layer 2 of the transistor, removing the redundant oxide semiconductor by adopting a lift-off process (lift-off), and adopting a lift-off process in the subsequent photoetching process.

An etching process may also be used to remove excess semiconductor layer after photolithography. The material of the oxide semiconductor may be zinc oxide, indium gallium zinc oxide, indium tin oxide, indium tungsten oxide, or aluminum-doped zinc oxide.

Step (2): similarly, the source and drain electrodes 3 and 4 are defined by photolithography.

The material of the source and drain electrodes can be metal or high-conductivity oxide semiconductor.

And (3): a charge tunneling layer 5 is grown.

The charge tunneling layer can be aluminum oxide, hafnium oxide, silicon nitride, yttrium oxide, zirconium oxide, or silicon oxide.

And (4): a charge storage layer 6 is grown.

The charge storage layer may be a highly conductive oxide including: zinc oxide, indium tin oxide, indium zinc oxide, indium tungsten oxide, or aluminum-doped zinc oxide; and a dielectric material of hafnium oxide, tantalum oxide, zirconium oxide or yttrium oxide.

And (5): a charge blocking layer 7 is grown.

The barrier layer may be aluminum oxide, hafnium oxide, silicon nitride, yttrium oxide, zirconium oxide or silicon oxide.

And (6): the top gate electrode 8 is defined by photolithography.

The material of the top gate electrode may be a metal or a highly conductive oxide.

Example 1:

taking a floating gate transistor based on a top gate structure as an example, a specific process of device manufacturing is described. As shown in fig. 5, the transistor includes, in order from top to bottom, a top gate electrode 8, a charge blocking layer 7, a charge storage layer 6, a charge tunneling layer 5, a drain electrode 4, a source electrode 3, a semiconductor layer 2, and a substrate 1. The substrate is a silicon wafer with an oxide layer, the oxide semiconductor layer 2 is indium gallium zinc oxide grown by magnetron sputtering, the source electrode 3 and the drain electrode 4 are indium tin oxide grown by magnetron sputtering, the charge tunneling layer 5 is aluminum oxide grown by atomic layer deposition, the charge storage layer 6 is indium tin oxide grown by magnetron sputtering, the barrier layer 7 is aluminum oxide grown by atomic layer deposition, and the gate electrode 8 is indium tin oxide grown by magnetron sputtering. The specific method comprises the following steps:

spin-coating a layer of photoresist on a cleaned silicon wafer substrate with an oxide layer, after exposure and development, sputtering indium gallium zinc oxide as an oxide semiconductor layer by adopting a radio frequency magnetron sputtering method, wherein the growth temperature is room temperature, the thickness is about 30nm, then washing off the redundant semiconductor layer by adopting a lift-off process, and adopting a lift-off process for subsequent photoetching. And photoetching again, and sputtering indium tin oxide as a source electrode and a drain electrode by adopting a direct-current magnetron sputtering method at room temperature, wherein the thickness of the indium tin oxide is about 100 nm. Then, the alumina with the thickness of about 6nm (water and trimethylaluminum are precursors) is grown by adopting atomic layer deposition to be used as a charge tunneling layer, and the growth temperature is 80 ℃. The tunneling layer used here has a low thickness, mainly to allow electrons to tunnel back and forth between the floating gate and the channel when a large voltage is applied to the gate, thereby modulating the channel layer conductance. And then growing a layer of indium tin oxide with the thickness of about 15nm as a charge storage layer by adopting a direct current magnetron sputtering method at room temperature. A layer of approximately 30nm of alumina was then grown as a blocking layer using the same process as the charge tunneling layer. The thicker barrier layer thickness is used here to reduce the potential for device leakage. And then photoetching is carried out again to define a top gate electrode, and a layer of indium tin oxide with the thickness of 100nm is grown as the top gate electrode by adopting a direct current magnetron sputtering method.

Example 2:

also taking a floating gate transistor based on a top gate structure as an example, a specific flow of device fabrication will be described. As shown in fig. 5, the transistor includes, in order from top to bottom, a top gate electrode 8, a charge blocking layer 7, a charge storage layer 6, a charge tunneling layer 5, a drain electrode 4, a source electrode 3, a semiconductor layer 2, and a substrate 1. The insulating substrate is made of glass, the oxide semiconductor layer 2 is made of indium zinc oxide grown by magnetron sputtering, the source electrode 3 and the drain electrode 4 are made of thermally evaporated aluminum metal, the charge tunneling layer 5 is made of silicon nitride grown by a plasma enhanced chemical vapor deposition method, the charge storage layer 6 is made of tantalum oxide grown by magnetron sputtering, the barrier layer 7 is made of silicon nitride grown by a plasma enhanced chemical vapor deposition method, and the gate electrode 8 is made of thermally evaporated aluminum metal. The specific method comprises the following steps:

spin-coating a layer of photoresist on a cleaned glass substrate, exposing and developing, sputtering indium, zinc and oxygen as an oxide semiconductor layer by adopting a direct-current magnetron sputtering method, wherein the growth temperature is room temperature and the thickness is about 25nm, then washing off the redundant semiconductor layer by adopting a lift-off process, and adopting a lift-off process for subsequent photoetching. And then photoetching again, and evaporating metal aluminum as a source electrode and a drain electrode by adopting a thermal evaporation method, wherein the thickness of the source electrode and the drain electrode is about 30 nm. Then, a plasma enhanced chemical vapor deposition system is adopted to deposit silicon nitride (silane and nitrogen are precursors) with the thickness of 6nm as a charge tunneling layer, and the growth temperature is room temperature. The tunneling layer used here has a low thickness, mainly to allow electrons to tunnel back and forth between the floating gate and the channel when a large voltage is applied to the gate, thereby modulating the channel layer conductance. And then growing a layer of tantalum oxide with the thickness of about 15nm as a charge storage layer at room temperature by adopting a magnetron sputtering method. A layer of silicon nitride of about 30nm is then grown as a blocking layer using the same process as the charge tunneling layer. The thicker barrier layer thickness is used here to reduce the potential for device leakage. And then photoetching is carried out again to define a top gate electrode, and a layer of aluminum with the thickness of 30nm is grown as the top gate electrode by adopting a thermal evaporation method.

Example 3: also taking a floating gate transistor based on a top gate structure as an example, a specific flow of device fabrication will be described. As shown in fig. 5, the transistor includes, in order from top to bottom, a top gate electrode 8, a blocking layer 7, a charge storage layer 6, a charge tunneling layer 5, a drain electrode 4, a source electrode 3, a semiconductor layer 2, and a substrate 1. The insulating substrate is a plastic flexible substrate, the oxide semiconductor layer 2 is zinc oxide grown by magnetron sputtering, the source electrode 3 and the drain electrode 4 are molybdenum metal formed by magnetron sputtering, the charge tunneling layer 5 is aluminum oxide grown by atomic layer deposition, the charge storage layer 6 is hafnium oxide grown by atomic layer deposition, the barrier layer 7 is aluminum oxide grown by atomic layer deposition, and the gate electrode 8 is Ti/Au evaporated by electron beams. The specific method comprises the following steps:

spin-coating a layer of photoresist on a cleaned plastic substrate, exposing and developing, sputtering zinc oxide as an oxide semiconductor layer by adopting a direct-current magnetron sputtering method, wherein the growth temperature is room temperature and the thickness is about 25nm, then washing off the redundant semiconductor layer by adopting a lift-off process, and adopting a lift-off process for subsequent photoetching. And then photoetching again, and sputtering metal molybdenum as a source electrode and a drain electrode by adopting a direct-current magnetron sputtering method, wherein the thickness of the molybdenum is about 30 nm. And then growing aluminum oxide/hafnium oxide/aluminum oxide by adopting atomic layer deposition as a tunneling layer/charge storage layer/blocking layer, wherein the thickness is 6nm/8nm/30 nm. The tunneling layer used here has a low thickness, mainly to allow electrons to tunnel back and forth between the floating gate and the channel when a large voltage is applied to the gate, thereby modulating the channel layer conductance. The thicker barrier layer thickness is used to reduce the potential for device leakage. Then, photolithography was performed again to define a top gate electrode, and Ti/Au evaporated by electron beam was used as the top gate electrode, and the thickness was 10/30 nm.

The above exemplary embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modifications made on the technical scheme route according to the technical idea of the present invention fall within the protection scope of the present invention.