阅读说明：本技术 一种消除负阻效应的逆导型横向绝缘栅双极型晶体管 (Reverse conducting type transverse insulated gate bipolar transistor capable of eliminating negative resistance effect ) 是由 祝靖 崔永久 张龙 孙伟锋 时龙兴 于 2020-12-09 设计创作，主要内容包括：本发明涉及一种消除负阻效应的逆导型横向绝缘栅双极型晶体管,在N型漂移区上设有氧化层沟槽、第二氧化层埋层及第三氧化层埋层,所述氧化层沟槽位于N型缓冲层与阳极N型重掺杂区间,所述第二氧化层埋层及第三氧化层埋层沿所述晶体管横向设置于阳极N型重掺杂区的下方,在氧化层沟槽与第二氧化层埋层之间设有第一P型埋层。并且,所述第一P型埋层始自所述氧化层沟槽的边界且向所述晶体管边界延伸并至少到达与所述氧化层沟槽相邻的第二氧化层埋层的一端,第二氧化层埋层的另一端与晶体管边界之间留有N型漂移区的一部分,在氧化层沟槽内设有与阳极(A)相连接的阳极多晶硅栅且阳极多晶硅栅位于第一P型埋层的侧方位上。(The invention relates to a reverse conducting type transverse insulated gate bipolar transistor for eliminating a negative resistance effect.A N-type drift region is provided with an oxide layer groove, a second oxide layer buried layer and a third oxide layer buried layer, the oxide layer groove is positioned between an N-type buffer layer and an anode N-type heavily doped region, the second oxide layer buried layer and the third oxide layer buried layer are transversely arranged below the anode N-type heavily doped region along the transistor, and a first P-type buried layer is arranged between the oxide layer groove and the second oxide layer buried layer. And the first P-type buried layer extends from the boundary of the oxide layer groove to the transistor boundary and at least reaches one end of a second oxide layer buried layer adjacent to the oxide layer groove, a part of an N-type drift region is left between the other end of the second oxide layer buried layer and the transistor boundary, an anode polysilicon gate connected with an anode (A) is arranged in the oxide layer groove, and the anode polysilicon gate is positioned on the side direction of the first P-type buried layer.)

1. A reverse conducting type transverse insulated gate bipolar transistor for eliminating a negative resistance effect comprises a P type substrate (1), a first oxide layer buried layer (2) is arranged on the P type substrate (1), an N type drift region (3) is arranged on the first oxide layer buried layer (2), a P type body region (12), a field oxide layer (8), an N type buffer layer (4) and an anode N type heavily doped region (6) are arranged on the N type drift region (3), the P type body region (12) and the N type buffer layer (4) are respectively positioned on two sides of the field oxide layer (8), the N type buffer layer (4) is positioned between the field oxide layer (8) and the anode N type heavily doped region (6), a cathode P type heavily doped region (11) and a cathode N type heavily doped region (13) are arranged on the P type body region (12), the cathode P type heavily doped region (11) and the cathode N type heavily doped region (13) are connected with a cathode (C), an anode P-type heavily doped region (7) is arranged on the N-type buffer layer (4), the anode P-type heavily doped region (7) is connected with the anode N-type heavily doped region (6) and is connected with the anode (A), a silicon dioxide oxide layer (9) is arranged on the cathode P-type heavily doped region (11), the cathode N-type heavily doped region (13), the P-type body region (12), the field oxide layer (8), the N-type buffer layer (4), the anode P-type heavily doped region (7) and the anode N-type heavily doped region (6), a polysilicon gate (10) serving as a gate G is arranged in the silicon dioxide oxide layer (9), and the polysilicon gate (10) is positioned above a region between the cathode N-type heavily doped region (13) and the field oxide layer (8), and the N-type drift region (3) is characterized in that an oxide layer groove (20), a second buried oxide layer (15) and a third, the oxide layer groove (20) is positioned between the N-type buffer layer (4) and the anode N-type heavily doped region (6), the second buried oxide layer (15) and the third buried oxide layer (16) are arranged below the anode N-type heavily doped region (6) along the transverse direction of the transistor, a first P-type buried layer (14) is provided between the oxide trench (20) and the second buried oxide layer (15), and the first P-type buried layer (14) extends from the boundary of the oxide layer trench (20) to the transistor boundary and reaches at least one end of a second buried oxide layer (15) adjacent to the oxide layer trench (20), a part of an N-type drift region (3) is left between the other end of the second buried oxide layer (15) and the transistor boundary, an anode polysilicon gate (19) connected with the anode (A) is arranged in the oxide layer groove (20), and the anode polysilicon gate (19) is positioned on the side direction of the first P-type buried layer (14); the third buried oxide layer (16) is located below the second buried oxide layer (15), one end of the third buried oxide layer (16) is located on the transistor boundary, and a part of the N-type drift region (3) is reserved between the other end of the third buried oxide layer (16) and the oxide layer groove (20).

2. The reverse conducting lateral insulated gate bipolar transistor (igbt) with elimination of negative resistance effect according to claim 1, wherein the first P-type buried layer (14) extends to the transistor boundary and ends at the other end of the second buried oxide layer (15) to form a wrapping of the second buried oxide layer (15) by the first P-type buried layer (14).

3. The igbt according to claim 1 or 2, wherein a fourth buried oxide layer (17) is provided below the third buried oxide layer (16), a second P-type buried layer (18) is provided between one end of the fourth buried oxide layer (17) and the oxide trench (20), and the second P-type buried layer (18) extends from the boundary of the oxide trench (20) to the transistor boundary and reaches at least one end of the fourth buried oxide layer (17), and a part of the N-type drift region (3) is provided between the other end of the fourth buried oxide layer (15) and the transistor boundary, and the gate (19) of the anode polysilicon extends downward in the oxide trench (20) and is at least as deep as the bottom surface of the fourth buried oxide layer (17).

4. The reverse conducting lateral Insulated Gate Bipolar Transistor (IGBT) for eliminating negative resistance effect according to claim 3, wherein said second P-type buried layer (18) extends towards the transistor boundary and ends at the other end of said fourth buried oxide layer (17) to form a second P-type buried layer (18) wrapping the fourth buried oxide layer (17).

5. The reverse conducting lateral insulated gate bipolar transistor (igbt) according to claim 1, wherein one boundary of the oxide trench (20) touches the boundary of the N-type buffer layer (4), and the other boundary of the oxide trench (20) touches the boundary of the anode N-type heavily doped region (6).

6. The reverse conducting type lateral insulated gate bipolar transistor for eliminating the negative resistance effect as claimed in claim 1, wherein the distance between the boundary of the oxide layer trench (20) adjacent to one side of the anode N-type heavily doped region (6) and the boundary of the N-type drift region (3) adjacent to the other side of the anode N-type heavily doped region (6) is 10.0-11.0 μm, the depth of the oxide layer trench (20) is 6.5-7.0 μm, and the width of the oxide layer trench is 1.5-2.0 μm.

7. The reverse conducting lateral Insulated Gate Bipolar Transistor (IGBT) for eliminating negative resistance effect as claimed in claim 4, wherein the width of the anodic polysilicon gate (19) is 1.0-1.2 μm, the distance between the anodic polysilicon gate (19) and the boundary of the oxide trench (20) at the same side adjacent to the anodic N-type heavily doped region (6) is 0.05-0.08 μm, and the depth of the anodic polysilicon gate (19) is within the lower boundary of the second P-type buried layer (18) and the lower boundary of the oxide trench (20).

8. The reverse conducting lateral Insulated Gate Bipolar Transistor (IGBT) for eliminating negative resistance effect according to claim 4, wherein the width of said first P-type buried layer (14) and said second P-type buried layer (18) is 0.6-1.0 μm.

Technical Field

The invention relates to the technical field of power semiconductor devices, in particular to a reverse conducting type transverse insulated gate bipolar transistor for eliminating a negative resistance effect.

Background

The Lateral Insulated Gate Bipolar Transistor (LIGBT) is a novel power device produced by combining a field effect Transistor (MOS) device structure and a Bipolar Transistor structure, has the advantages of easy integration and easy driving of the MOS device, and has the characteristic of strong current driving capability of the Bipolar Transistor, so that the Lateral Insulated Gate Bipolar Transistor (LIGBT) is widely applied to the field of power semiconductor integrated circuits. However, the conventional LIGBT has a serious current tailing phenomenon during turn-off, which causes the turn-off speed of the device to be slow and turn-off loss to be large. Meanwhile, in the application of a power integrated circuit system, an additional fast recovery freewheeling diode needs to be connected in parallel at the two ends of the anode and the cathode of the LIGBT device to ensure the safety and the stability of the circuit system, but the cost of the circuit system is greatly increased, so that a reverse conducting type lateral insulated gate bipolar transistor (RC-LIGBT) with a body diode becomes the current mainstream scheme. In order to solve the above problems, a lateral insulated gate bipolar transistor (SA-LIGBT) of an anode short circuit type has been developed, which has a body diode for freewheeling integrated therein and provides an electron extraction path during turn-off, thereby increasing the turn-off speed. However, when the turn-off speed is increased, due to the existence of the N-type heavily doped region directly connected with the anode, the device has two conduction modes of a unipolar type and a bipolar type when being turned on, and when the drift region has a conductance modulation effect, a serious negative resistance phenomenon is generated. The negative resistance effect causes larger conduction voltage drop at the initial stage of conduction of the device, the conduction loss of the device is increased, and meanwhile, if the retracing voltage of the RC-LIGBT is too large, the problem that current is concentrated towards a single chip easily occurs when RC-LIGBT chips are used in parallel, so that the application of the RC-LIGBT in the high-power field is greatly limited. In order to eliminate the negative resistance effect, a separated anode short-circuit type lateral insulated gate bipolar transistor (SSA-LIGBT) structure is provided, the length of a low-doped drift region between an anode N-type heavily doped region and a anode P-type heavily doped region is increased, the equivalent short-circuit resistance is increased, and the negative resistance effect is further inhibited, but the anode short-circuit type lateral insulated gate bipolar transistor needs to occupy a larger size area and cannot completely eliminate the negative resistance effect, and meanwhile, the increased drift region increases stored unbalanced carriers and reduces the turn-off speed of the device. For a double-gate control lateral insulated gate bipolar transistor (DG-LIGBT), although a part of N regions are inverted into P regions through anode gate negative voltage, the length of an anode P type heavily doped region is increased, and further the negative resistance effect is restrained, the anode gate needs an additional circuit for control, and therefore the cost of the circuit is increased.

Therefore, effectively eliminating the negative resistance effect without sacrificing the LIGBT turn-off speed is a problem to be solved in the power semiconductor integrated circuit design.

Disclosure of Invention

The invention provides a reverse conducting type lateral insulated gate bipolar transistor structure for eliminating negative resistance effect, which is used for inhibiting and eliminating the negative resistance effect of the traditional RC-LIGBT.

The technical scheme of the invention is as follows:

a reverse conducting type transverse insulated gate bipolar transistor for eliminating negative resistance effect comprises a P-type substrate, a first oxide buried layer is arranged on the P-type substrate, an N-type drift region is arranged on the first oxide buried layer, a P-type body region, a field oxide layer, an N-type buffer layer and an anode N-type heavily doped region are arranged on the N-type drift region, the P-type body region and the N-type buffer layer are respectively positioned on two sides of the field oxide layer, the N-type buffer layer is positioned between the field oxide layer and the anode N-type heavily doped region, a cathode P-type heavily doped region and a cathode N-type heavily doped region are arranged on the P-type body region, the cathode P-type heavily doped region and the cathode N-type heavily doped region are connected with a cathode, an anode P-type heavily doped region is arranged on the N-type buffer layer, the anode P-type heavily doped region and the anode N-type heavily doped region are connected, A silicon dioxide oxidation layer is arranged on the P-type body region, the field oxidation layer, the N-type buffer layer, the anode P-type heavily doped region and the anode N-type heavily doped region, a polysilicon grid serving as a grid G is arranged in the silicon dioxide oxidation layer and positioned above the region between the cathode N-type heavily doped region and the field oxidation layer, an oxidation layer groove, a second buried oxide layer and a third buried oxide layer are arranged on the N-type drift region, the oxidation layer groove is positioned between the N-type buffer layer and the anode N-type heavily doped region, the second buried oxide layer and the third buried oxide layer are transversely arranged below the anode N-type heavily doped region along the transistor, a first P-type buried layer is arranged between the oxidation layer groove and the second buried oxide layer, the first P-type buried layer extends from the boundary of the oxidation layer groove to the boundary of the transistor and at least reaches one end of the second buried oxide layer adjacent, a part of an N-type drift region is left between the other end of the second buried oxide layer and the boundary of the transistor, an anode polysilicon gate connected with an anode is arranged in the oxide layer groove, and the anode polysilicon gate is positioned on the side of the first P-type buried layer; and the third buried oxide layer is positioned below the second buried oxide layer, one end of the third buried oxide layer is positioned on the boundary of the transistor, and a part of the N-type drift region is reserved between the other end of the third buried oxide layer and the oxide layer groove.

Compared with the prior art, the structure of the invention has the following advantages:

1. the invention can improve the turn-off speed of the device while eliminating the negative resistance effect through the equivalent short-circuit resistor with variable resistance value. When the anode voltage is lower, the device is in a unipolar conduction mode, electrons must pass through a zigzag conduction channel formed by the P-type buried layer and the oxide layer buried layer due to the isolation effect of the P-type buried layer and the oxide layer buried layer to reach the anode N-type heavily doped region, the equivalent short circuit resistance value in the unipolar conduction mode can be large by adjusting the thickness of the P-type buried layer, the P +/N-buffer junction formed by the anode P-type heavily doped region and the N-type buffer layer is opened earlier, the device is switched from the unipolar conduction mode to the bipolar conduction mode earlier, and the negative resistance effect generated at the initial conduction stage of the device is completely eliminated. After the device enters a bipolar conduction mode, with the increase of anode voltage, a conduction channel with smaller resistance value can be formed at the contact boundary of the P-type buried layer and the oxide layer groove under the action of the anode polysilicon gate, at the moment, electrons can reach an anode N-type heavily doped region along the conduction channel with smaller resistance value and the zigzag conduction channel, and due to the existence of the two electron conduction channels, the equivalent short-circuit resistor can be regarded as a small variable resistor and a large resistor which are connected in parallel, so that the larger the anode voltage is, the smaller the equivalent short-circuit resistor resistance value is. The equivalent short-circuit resistor with smaller resistance value reduces the voltage born by two ends of the anode P +/N-buffer junction, and reduces the number of holes injected into the N-type drift region, thereby reducing the number of current carriers required to be extracted when the device is turned off. The turn-off speed of the device is effectively increased because of the increase in the conduction channel and the reduction in the number of extracted carriers.

2. Compared with SSA-LIGBT, the structure of the invention has lower forward conduction voltage drop. Under the unipolar conduction mode of the device, due to the existence of the zigzag conduction channel, the equivalent short-circuit resistor of the structure has a large resistance value and is used for eliminating the negative resistance effect at the initial conduction stage of the device. After the device is changed into a bipolar conduction mode, due to the effect of the anode polysilicon gate, the resistance value of the equivalent short-circuit resistor is smaller along with the gradual increase of the anode voltage, so that the whole on-resistance of the device is obviously reduced, and the forward on-voltage drop of the device is reduced.

3. Compared with SSA-LIGBT, the structure of the invention effectively shortens the size of the device, thereby reducing the manufacturing cost of the device. The conventional SSA-LIGBT can completely suppress the negative resistance effect only when the lateral distance between the anode P-type heavily doped region and the anode N-type heavily doped region is large enough, which undoubtedly increases the size area of the device and increases the manufacturing cost of the device. The structure of the invention can obtain the equivalent short-circuit resistor with large resistance value to inhibit the negative resistance effect under the condition of relatively small size area through the zigzag conductive channel formed by the P-type buried layer and the oxide layer buried layer, thereby effectively reducing the size area and the manufacturing cost of the device.

Drawings

FIG. 1 shows the structure of SSA-LIGBT.

Fig. 2 is a block diagram of the present invention.

Fig. 3 is a schematic diagram showing the electron current flow path in the unipolar conduction mode.

Fig. 4 is a schematic diagram showing the electron current flow path in the bipolar conduction mode.

FIG. 5 is a diagram showing the structure and SSA-LIGBT forward conduction characteristics of the present invention.

Fig. 6 shows a schematic diagram of the hole concentration distribution at a cross section of Y-20 μm when the inventive structure and SSA-LIGBT are turned off.

FIG. 7 is a graph comparing the inventive structure and SSA-LIGBT turn-off characteristics.

Detailed Description

The present invention will be described in detail with reference to the accompanying drawings.

A reverse conducting type transverse insulated gate bipolar transistor for eliminating negative resistance effect comprises a P type substrate 1, a first oxide layer buried layer 2 is arranged on the P type substrate 1, an N type drift region 3 is arranged on the first oxide layer buried layer 2, a P type body region 12, a field oxide layer 8, an N type buffer layer 4 and an anode N type heavily doped region 6 are arranged on the N type drift region 3, the P type body region 12 and the N type buffer layer 4 are respectively positioned on two sides of the field oxide layer 8, the N type buffer layer 4 is positioned between the field oxide layer 8 and the anode N type heavily doped region 6, a cathode P type heavily doped region 11 and a cathode N type heavily doped region 13 are arranged on the P type body region 12, the cathode P type heavily doped region 11 and the cathode N type heavily doped region 13 are connected and connected to a cathode C, an anode P type heavily doped region 7 is arranged on the N type buffer layer 4, the anode P type heavily doped region 7 and the anode N type heavily doped region 6 are connected and connected to, a silicon dioxide oxidation layer 9 is arranged on the cathode P type heavily doped region 11, the cathode N type heavily doped region 13, the P type body region 12, the field oxidation layer 8, the N type buffer layer 4, the anode P type heavily doped region 7 and the anode N type heavily doped region 6, a polysilicon grid 10 which is used as a grid G is arranged in the silicon dioxide oxidation layer 9, the polysilicon grid 10 is positioned above the region between the cathode N type heavily doped region 13 and the field oxidation layer 8, an oxidation layer groove 20, a second buried oxide layer 15 and a third buried oxide layer 16 are arranged on the N type drift region 3, the oxidation layer groove 20 is positioned between the N type buffer layer 4 and the anode N type heavily doped region 6, the second buried oxide layer 15 and the third buried oxide layer 16 are transversely arranged below the anode N type heavily doped region 6 along the transistor, a first P type buried layer 14 is arranged between the oxidation layer groove 20 and the second buried oxide layer 15, the first P-type buried layer 14 extends from the boundary of the oxide trench 20 to the transistor boundary and reaches at least one end of the second buried oxide layer 15 adjacent to the oxide trench 20, a part of the N-type drift region 3 is left between the other end of the second buried oxide layer 15 and the transistor boundary, an anode polysilicon gate 19 connected to the anode a is provided in the oxide trench 20, and the anode polysilicon gate 19 is located on the side of the first P-type buried layer 14; the third buried oxide layer 16 is located below the second buried oxide layer 15, one end of the third buried oxide layer 16 is located on the transistor boundary, and a part of the N-type drift region 3 is left between the other end of the third buried oxide layer 16 and the oxide layer trench 20. In the present embodiment, it is preferred that,

a fourth buried oxide layer 17 is arranged below the third buried oxide layer 16, a second P-type buried layer 18 is arranged between one end of the fourth buried oxide layer 17 and an oxide layer trench 20, the second P-type buried layer 18 extends from the boundary of the oxide layer trench 20 to the transistor boundary and at least reaches one end of the fourth buried oxide layer 17, a part of an N-type drift region 3 is arranged between the other end of the fourth buried oxide layer 15 and the transistor boundary, and referring to fig. 2, the second buried oxide layer 15, the third buried oxide layer 16 and the fourth buried oxide layer 17 are arranged in an interdigital manner, so that when the device is in a single-pole conductive mode, electrons pass through a long-distance zigzag conductive channel formed by the P-type buried layer and the buried oxide layer; the gate 19 extends downward in the trench 20 and is at least deep to the lower surface of the fourth buried oxide layer 17, and more specifically, the gate 19 is deep and is located between the lower boundary of the second P-type buried layer 18 and the lower boundary of the trench 20.

In order to further eliminate the negative resistance effect and increase the device turn-off speed, the present embodiment further takes the following measures:

the first P-type buried layer 14 extends towards the transistor boundary and ends at the other end of the second buried oxide layer 15 to form a package of the first P-type buried layer 14 on the second buried oxide layer 15; the second P-type buried layer 18 extends towards the transistor boundary and ends at the other end of the fourth buried oxide layer 17 to form a package of the fourth buried oxide layer 17 by the second P-type buried layer 18;

one boundary of the oxide layer groove 20 touches the boundary of the N-type buffer layer 4, and the other boundary of the oxide layer groove 20 touches the boundary of the anode N-type heavily doped region 6;

the boundary distance between the oxide layer groove 20 adjacent to one side of the anode N-type heavily doped region 6 and the boundary between the N-type drift region 3 adjacent to the other side of the anode N-type heavily doped region 6 is 10.0-11.0 mu m, the depth of the oxide layer groove 20 is 6.5-7.0 mu m, and the width of the oxide layer groove is 1.5-2.0 mu m;

the width of the anode polysilicon gate 19 is 1.0-1.2 mu m, and the distance between the anode polysilicon gate 19 and the boundary of the oxide layer groove 20, which is adjacent to the anode N-type heavily doped region 6, on the same side is 0.05-0.08 mu m;

the width of the first P-type buried layer 14 and the width of the second P-type buried layer 18 are 0.6-1.0 mu m.

The invention is further described below with reference to the accompanying drawings.

The working principle of the invention is as follows:

when the SSA-LIGBT device is in a forward conduction state, the cathode end of the device is connected with a low potential, the substrate is connected with a low potential, the grid is connected with a high potential, and the anode end of the device is connected with a high potential. When the anode voltage is low, electrons can directly flow from the cathode N-type heavily doped region 13 to the anode N-type heavily doped region 6 through the inversion channel under the gate 10, the N-type drift region 3 and the second N-type buffer layer, so that no dead zone voltage exists when the SSA-LIGBT is in forward conduction. At this time, the lower anode voltage does not make the P +/N-buffer junction formed by the anode P-type heavily doped region 7 and the first N-type buffer layer 4 open, and the anode P-type heavily doped region 7 does not inject holes into the N-type drift region 3, so that no conductivity modulation effect occurs in the N-type drift region 3, and the device is in a unipolar conduction mode. With the increase of the anode voltage, when electrons flow to the anode N-type heavily doped region 6 through the lower part of the anode P-type heavily doped region 7, a certain potential difference is generated on the equivalent short-circuit resistor, when the potential difference gradually increases to enable a P +/N-buffer junction formed by the anode P-type heavily doped region 7 and the first N-type buffer layer 4 to be opened, the anode P-type heavily doped region 7 starts to inject holes into the N-type drift region 3, at the moment, a conductivity modulation effect occurs in the N-type drift region 3, and the device enters a bipolar conduction mode. A voltage rebound phenomenon as shown in fig. 5 occurs during the switching of the device from the unipolar conduction mode to the bipolar conduction mode, and we refer to this voltage rebound phenomenon as a negative resistance effect.

When the structure is in forward conduction, the cathode end of the device is connected with a low potential, the substrate is connected with a low potential, the anode end of the device is connected with a high potential, and the grid is connected with a high potential. When the anode voltage is low, the device is in a unipolar conductive mode, no electronic conductive channel with a low resistance value is formed at the contact boundaries of the first P-type buried layer 14, the second P-type buried layer 18 and the oxide layer trench 20, electrons can only reach the anode N-type heavily doped region 6 along the tortuous conductive channel formed by the second P-type buried layer 18, the third buried layer 17, the second buried layer 16, the second buried layer 15 and the first P-type buried layer 14, and the flow path of the electron current is shown in fig. 3. By adjusting the thicknesses of the first P-type buried layer 14 and the second P-type buried layer 18, the equivalent short circuit resistance in a unipolar conduction mode can be made to be very large, so that a P +/N-buffer junction formed by the anode P-type heavily doped region 7 and the N-type buffer layer 4 is opened earlier, a device is switched from the unipolar conduction mode to a bipolar conduction mode earlier, and then the negative resistance effect generated at the initial stage of conduction of the device is completely eliminated, as shown in fig. 5, compared with the SSA-LIGBT, the negative resistance effect is completely eliminated by the structure of the invention.

After the device is switched from the unipolar conduction mode to the bipolar conduction mode, as the anode voltage increases, an electron conduction channel with a smaller resistance value is formed at the contact boundaries of the first P-type buried layer 14 and the second P-type buried layer 18 and the oxide layer trench 20, and electrons can reach the anode N-type heavily doped region 6 along the electron conduction channel and the zigzag conduction channel at the right boundary of the oxide layer trench 20, and the electron current flow path is as shown in fig. 4. Because two electronic conducting channels exist, the equivalent short-circuit resistor can be regarded as a small variable resistor and a large resistor which are connected in parallel, and therefore the larger the anode voltage is, the smaller the resistance value of the equivalent short-circuit resistor is. The equivalent short-circuit resistor with smaller resistance value reduces the voltage born at two ends of the anode P +/N-buffer junction, reduces the number of holes injected into the N-type drift region 3, and leads the number of non-equilibrium carriers stored in the N-type drift region 3 to be obviously reduced, and fig. 6 is a hole carrier distribution schematic diagram intercepted along the longitudinal coordinate Y of the device being 20 mu m. The turn-off speed of the device is effectively increased because of the increase in the conduction channel and the reduction in the number of extracted carriers. The comparison of the turn-off characteristics of the structure of the present invention and the SSA-LIGBT structure is shown in fig. 7, which shows that the structure of the present invention has a faster turn-off speed.