阅读说明：本技术 一种半导体器件及其制备方法 (Semiconductor device and preparation method thereof ) 是由 裴晓延 于 2019-08-23 设计创作，主要内容包括：本发明公开了一种半导体器件及其制备方法,半导体器件依次包括衬底；多层半导体层和P型外延层,还包括位于P型外延层远离多层半导体层一侧的阳极以及位于多层半导体层远离衬底一侧的阴极,阳极在衬底上的垂直投影与P型外延层在衬底上的垂直投影至少部分交叠。采用上述技术方案,通过在半导体器件中增设P型外延层,通过P性外延层通过抬高能带、耗尽阳极下方的二维电子气,从而降低半导体器件的器件漏电；另一方面,本发明中的半导体器件无需对多层半导体层进行刻蚀形成阳极凹槽,不存在刻蚀损伤,避免了传统阳极凹槽结构的界面态；并且P型外延层相比阳极凹槽刻蚀工艺均匀性更好,能提高器件正向开启电压的一致性。(The invention discloses a semiconductor device and a preparation method thereof, wherein the semiconductor device sequentially comprises a substrate; the multilayer semiconductor layer and the P-type epitaxial layer further comprise an anode positioned on one side of the P-type epitaxial layer far away from the multilayer semiconductor layer and a cathode positioned on one side of the multilayer semiconductor layer far away from the substrate, and the vertical projection of the anode on the substrate is at least partially overlapped with the vertical projection of the P-type epitaxial layer on the substrate. By adopting the technical scheme, the P-type epitaxial layer is additionally arranged in the semiconductor device, and the two-dimensional electron gas below the anode is exhausted by raising the energy band through the P-type epitaxial layer, so that the device leakage of the semiconductor device is reduced; on the other hand, the semiconductor device does not need to etch the multilayer semiconductor layer to form the anode groove, so that etching damage does not exist, and the interface state of the traditional anode groove structure is avoided; and the P-type epitaxial layer has better uniformity compared with the anode groove etching process, and the consistency of the forward starting voltage of the device can be improved.)

1. A semiconductor device, comprising:

substrate:

a multilayer semiconductor layer on one side of the substrate;

the P-type epitaxial layer is positioned on one side, far away from the substrate, of the multilayer semiconductor layer;

the anode is positioned on one side, away from the multilayer semiconductor layer, of the P-type epitaxial layer, and the cathode is positioned on one side, away from the substrate, of the multilayer semiconductor layer, wherein the vertical projection of the anode on the substrate at least partially overlaps with the vertical projection of the P-type epitaxial layer on the substrate.

2. The semiconductor device according to claim 1, further comprising a passivation layer located on a side of the multilayer semiconductor layer away from the substrate and between the P-type epitaxial layer and the cathode;

the thickness h1 of the P-type epitaxial layer along the first direction meets the condition that h1 is more than or equal to 20nm and less than or equal to 70 nm; the thickness h2 of the passivation layer meets the requirement that h2 is more than or equal to 40nm and less than or equal to 90 nm; wherein the first direction is parallel to a vertical direction of the substrate.

3. The semiconductor device according to claim 2, wherein a distance L1 between the P-type epitaxial layer and the passivation layer in the second direction satisfies L1 ═ 0; wherein the second direction is parallel to a direction in which the anode points toward the cathode.

4. The semiconductor device according to claim 2, wherein a distance L1 between the P-type epitaxial layer and the passivation layer in the second direction satisfies 0.4 μm L1 μm 1 μm; wherein the second direction is parallel to a direction in which the anode points toward the cathode;

the anode comprises a first anode subsection and a second anode subsection, the first anode subsection is located on one side, far away from the substrate, of the P-type epitaxial layer, the second anode subsection is located between the P-type epitaxial layer and the passivation layer, and the second anode subsection and the multilayer semiconductor layer form Schottky contact.

5. The semiconductor device of claim 2, wherein the passivation layer near one side of the P-type epitaxial layer covers a portion of the P-type epitaxial layer, and wherein an extension length L2 of the portion of the passivation layer covering the P-type epitaxial layer along the second direction satisfies 0.4 μm & lt L2 & lt 1 μm; wherein the second direction is parallel to a direction in which the anode points toward the cathode.

6. The semiconductor device of claim 2, further comprising an anode field plate on a side of the passivation layer away from the substrate, the anode field plate being electrically connected to the anode;

along the first direction, the thickness h1 of the P-type epitaxial layer and the thickness h2 of the passivation layer meet the condition that h2-h1 are more than or equal to 5nm and less than or equal to 60 nm;

the extension length L3 of the anode field plate along the second direction satisfies 0.4 μm L3 μm 2 μm; wherein the second direction is parallel to a direction in which the anode points toward the cathode.

7. The semiconductor device according to any one of claims 1 to 6, wherein the P-type epitaxial layer is provided continuously along the second direction;

or, along the second direction, the P-type epitaxial layer comprises a plurality of first P-type epitaxial layer blocks arranged at intervals; the anode comprises a first anode subsection positioned on one side of the first P-type epitaxial layer subsection far away from the substrate and a third anode subsection positioned between two adjacent first P-type epitaxial layer subsections, and the third anode subsection forms Schottky contact with the multilayer semiconductor layer;

wherein the second direction is parallel to a direction in which the anode points toward the cathode.

8. The semiconductor device according to claim 7, wherein an extension length L4 of the first P-type epitaxial layer segment in the second direction satisfies 0.1 μm L4 0.5 μm;

the distance L5 between two adjacent first P-type epitaxial layer blocks meets the condition that L5 is more than or equal to 0.3 mu m and less than or equal to 0.5 mu m.

9. The semiconductor device according to any one of claims 1 to 6, wherein the P-type epitaxial layer is provided continuously in the third direction;

or, along the third direction, the P-type epitaxial layer includes a plurality of second P-type epitaxial layer segments arranged at intervals; the anode comprises a first anode subsection and a fourth anode subsection, the first anode subsection is located on one side, far away from the substrate, of the second P-type epitaxial layer subsection, the fourth anode subsection is located between two adjacent second P-type epitaxial layer subsections, and the fourth anode subsection and the multilayer semiconductor layer form Schottky contact;

wherein the third direction is parallel to the plane of the substrate and perpendicular to the direction in which the anode points to the cathode.

10. The semiconductor device according to claim 1, wherein a doping concentration n of the P-type epitaxial layer satisfies 1 x 10¹⁹cm^-3≤n≤5×10¹⁹cm^-3。

11. A method for manufacturing a semiconductor device, for manufacturing the semiconductor device according to any one of claims 1 to 10, comprising:

providing a substrate;

preparing a multilayer semiconductor layer on one side of the substrate;

preparing a P-type epitaxial layer on one side of the multilayer semiconductor layer far away from the substrate;

preparing an anode on the side of the P-type epitaxial layer far away from the multilayer semiconductor layer and preparing a cathode on the side of the multilayer semiconductor layer far away from the substrate, wherein the vertical projection of the anode on the substrate at least partially overlaps with the vertical projection of the P-type epitaxial layer on the substrate.

Technical Field

The embodiment of the invention relates to the technical field of microelectronics, in particular to a semiconductor device and a preparation method thereof.

Background

The semiconductor material gallium nitride has become a research hotspot at present due to the characteristics of large forbidden bandwidth, high electron saturation drift velocity, high breakdown field strength, good heat-conducting property and the like. In the aspect of electronic devices, gallium nitride materials are more suitable for manufacturing high-temperature, high-frequency, high-voltage and high-power devices than silicon and gallium arsenide, so that the gallium nitride-based electronic devices have good application prospects. The gan schottky diode has the advantages of high speed and low power consumption, and thus, the gan schottky diode is used as a next-generation low-consumption power supply device, and the research on the gan schottky diode has very important significance.

In the prior art, a method for realizing a high-voltage gallium nitride Schottky diode device mainly comprises the step of etching an anode groove structure, and the technology etches two-dimensional electron gas of a material below an anode to achieve the purpose of reducing the electric leakage of the device.

In the technology, on one hand, the anode groove etching process inevitably brings etching damage, so that the electric leakage of the device is still large due to an interface state, and the dynamic characteristic and the reliability of the device are poor due to poor etching interface quality; on the other hand, the non-uniformity of the anode groove etching results in poor uniformity of the turn-on voltage of the device.

Disclosure of Invention

In view of this, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same, so as to solve the technical problems of large device leakage, poor reliability and poor consistency of the turn-on voltage caused by the anode recess in the prior art.

In a first aspect, an embodiment of the present invention provides a semiconductor device, including:

substrate:

a multilayer semiconductor layer on one side of the substrate;

the P-type epitaxial layer is positioned on one side, far away from the substrate, of the multilayer semiconductor layer;

the anode is positioned on one side, away from the multilayer semiconductor layer, of the P-type epitaxial layer, and the cathode is positioned on one side, away from the substrate, of the multilayer semiconductor layer, wherein the vertical projection of the anode on the substrate at least partially overlaps with the vertical projection of the P-type epitaxial layer on the substrate.

Optionally, the semiconductor device further includes a passivation layer located on a side of the multilayer semiconductor layer away from the substrate and located between the P-type epitaxial layer and the cathode;

the thickness h1 of the P-type epitaxial layer along the first direction meets the condition that h1 is more than or equal to 20nm and less than or equal to 70 nm; the thickness h2 of the passivation layer meets the requirement that h2 is more than or equal to 40nm and less than or equal to 90 nm; wherein the first direction is parallel to a vertical direction of the substrate.

Optionally, in the second direction, a distance L1 between the P-type epitaxial layer and the passivation layer satisfies L1 ═ 0; wherein the second direction is parallel to a direction in which the anode points toward the cathode.

Optionally, along the second direction, a distance L1 between the P-type epitaxial layer and the passivation layer satisfies 0.4 μm ≤ L1 ≤ 1 μm; wherein the second direction is parallel to a direction in which the anode points toward the cathode;

the anode comprises a first anode subsection and a second anode subsection, the first anode subsection is located on one side, far away from the substrate, of the P-type epitaxial layer, the second anode subsection is located between the P-type epitaxial layer and the passivation layer, and the second anode subsection and the multilayer semiconductor layer form Schottky contact.

Optionally, the passivation layer near one side of the P-type epitaxial layer covers a part of the P-type epitaxial layer, and along the second direction, an extension length L2 of the part of the passivation layer covering the P-type epitaxial layer satisfies 0.4 μm ≤ L2 ≤ 1 μm; wherein the second direction is parallel to a direction in which the anode points toward the cathode.

Optionally, the semiconductor device further comprises an anode field plate located on a side of the passivation layer away from the substrate, the anode field plate being electrically connected to the anode;

along the first direction, the thickness h1 of the P-type epitaxial layer and the thickness h2 of the passivation layer meet the condition that h2-h1 are more than or equal to 5nm and less than or equal to 60 nm;

the extension length L3 of the anode field plate along the second direction satisfies 0.4 μm L3 μm 2 μm; wherein the second direction is parallel to a direction in which the anode points toward the cathode.

Optionally, the P-type epitaxial layers are continuously arranged along the second direction;

or, along the second direction, the P-type epitaxial layer comprises a plurality of first P-type epitaxial layer blocks arranged at intervals; the anode comprises a first anode subsection positioned on one side of the first P-type epitaxial layer subsection far away from the substrate and a third anode subsection positioned between two adjacent first P-type epitaxial layer subsections, and the third anode subsection forms Schottky contact with the multilayer semiconductor layer;

wherein the second direction is parallel to a direction in which the anode points toward the cathode.

Optionally, along the second direction, the extension length L4 of the first P-type epitaxial layer partition satisfies 0.1 μm ≤ L4 ≤ 0.5 μm;

the distance L5 between two adjacent first P-type epitaxial layer blocks meets the condition that L5 is more than or equal to 0.3 mu m and less than or equal to 0.5 mu m.

Optionally, the P-type epitaxial layer is continuously disposed along a third direction;

or, along the third direction, the P-type epitaxial layer includes a plurality of second P-type epitaxial layer segments arranged at intervals; the anode comprises a first anode subsection and a fourth anode subsection, the first anode subsection is located on one side, far away from the substrate, of the second P-type epitaxial layer subsection, the fourth anode subsection is located between two adjacent second P-type epitaxial layer subsections, and the fourth anode subsection and the multilayer semiconductor layer form Schottky contact;

wherein the third direction is parallel to the plane of the substrate and perpendicular to the direction in which the anode points to the cathode.

Optionally, the doping concentration n of the P-type epitaxial layer satisfies 1 × 10¹⁹cm^-3≤n≤5×10¹⁹cm^-3。

In a second aspect, an embodiment of the present invention further provides a method for manufacturing a semiconductor device, including:

providing a substrate;

preparing a multilayer semiconductor layer on one side of the substrate;

preparing a P-type epitaxial layer on one side of the multilayer semiconductor layer far away from the substrate;

preparing an anode on the side of the P-type epitaxial layer far away from the multilayer semiconductor layer and preparing a cathode on the side of the multilayer semiconductor layer far away from the substrate, wherein the vertical projection of the anode on the substrate at least partially overlaps with the vertical projection of the P-type epitaxial layer on the substrate.

According to the semiconductor device and the preparation method thereof provided by the embodiment of the invention, the P-type epitaxial layer is additionally arranged in the semiconductor device, the vertical projection of the anode on the substrate is at least partially overlapped with the vertical projection of the P-type epitaxial layer on the substrate, and the energy band is raised through the P-type epitaxial layer, and the two-dimensional electron gas below the anode is exhausted, so that the device leakage of the semiconductor device is reduced; on the other hand, the semiconductor device does not need to etch the multilayer semiconductor layer to form the anode groove, so that etching damage does not exist, the interface state of the traditional anode groove structure is avoided, and the electric leakage of the semiconductor device is further reduced; compared with the anode groove etching process in the prior art, the P-type epitaxial layer in the embodiment of the invention has better uniformity, can improve the consistency of the forward starting voltage of the device, and can avoid the problem of poor consistency of the forward starting voltage of the semiconductor device caused by uneven etching of the anode groove.

Drawings

In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, a brief description is given below of the drawings used in describing the embodiments. It should be clear that the described figures are only views of some of the embodiments of the invention to be described, not all, and that for a person skilled in the art, other figures can be derived from these figures without inventive effort.

Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;

FIG. 2 is a schematic cross-sectional view of the semiconductor device provided in FIG. 1 along section line A-A';

fig. 3 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present invention;

FIG. 4 is a schematic cross-sectional view of the semiconductor device provided in FIG. 3 along section line B-B';

fig. 5 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present invention;

fig. 6 is a schematic cross-sectional view of the semiconductor device provided in fig. 5 along the sectional line C-C;

fig. 7 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present invention;

fig. 8 is a schematic cross-sectional view of the semiconductor device provided in fig. 7 along a sectional line D-D';

fig. 9 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present invention;

fig. 10 is a schematic cross-sectional view of the semiconductor device provided in fig. 9 along section line E-E';

fig. 11 is a schematic cross-sectional view of the semiconductor device provided in fig. 1 along section line F-F';

fig. 12 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present invention;

fig. 13 is a schematic cross-sectional view of the semiconductor device provided in fig. 12 along section line G-G';

fig. 14 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be fully described by the detailed description with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are a part of the embodiments of the present invention, not all embodiments, and all other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without inventive efforts fall within the scope of the present invention.

Fig. 1 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present invention, and fig. 2 is a schematic structural diagram of a cross section of the semiconductor device provided in fig. 1 along a section line a-a', as shown in fig. 1 and fig. 2, the semiconductor device provided in an embodiment of the present invention may include:

a substrate 10;

a multilayer semiconductor layer 20 on one side of the substrate 10;

a P-type epitaxial layer 30 positioned on a side of the multilayer semiconductor layer 20 away from the substrate 10;

an anode 41 located on the side of the P-type epitaxial layer 30 away from the multilayer semiconductor layer 20 and a cathode 42 located on the side of the multilayer semiconductor layer 20 away from the substrate, wherein a vertical projection of the anode 41 on the substrate 10 at least partially overlaps a vertical projection of the P-type epitaxial layer 30 on the substrate 10.

As shown in fig. 1 and fig. 2, the P-type epitaxial layer 30 is located on a side of the multi-layer semiconductor layer 20 away from the substrate 10, the anode 41 is located on a side of the P-type epitaxial layer 30 away from the multi-layer semiconductor layer 20, a vertical projection of the anode 41 on the substrate 10 at least partially overlaps a vertical projection of the P-type epitaxial layer 30 on the substrate 10, for example, the vertical projection of the anode 41 on the substrate 10 may completely cover the vertical projection of the P-type epitaxial layer 30 on the substrate 10. In fig. 1 and fig. 2, in order to show the P-type epitaxial layer 30 under the film layer where the anode 41 is located, the anode 41 is not completely covered on the P-type epitaxial layer 30. Since the P-type epitaxial layer 30 can raise the energy band and deplete the two-dimensional electron gas at the position corresponding to the anode 41, the device leakage of the semiconductor device can be reduced by adding the P-type epitaxial layer between the anode 41 and the multilayer semiconductor layer 20. Compared with the scheme that an anode groove is prepared in the multilayer semiconductor layer 20, an anode is formed in the anode groove, and two-dimensional electron gas below the anode is etched in the prior art, the technical scheme that the P-type epitaxial layer is additionally arranged between the anode 41 and the multilayer semiconductor layer 20 provided by the embodiment of the invention has the advantages that the multilayer semiconductor layer 20 is not required to be etched, etching damage does not exist, the interface state of the traditional anode groove structure is avoided, and the electric leakage of a semiconductor device can be further reduced. Moreover, compared with the anode groove etching process in the prior art, the P-type epitaxial layer 30 in the embodiment of the invention has better uniformity, can improve the consistency of the forward starting voltage of the device, and can avoid the problem of poor consistency of the forward starting voltage of the semiconductor device caused by uneven etching of the anode groove.

Optionally, the P-type epitaxial layer 30 may be a P-type GaN layer or a P-type AlGaN layer, and is preferably a GaN layer. Mg or Al can be doped in the GaN layer to obtain a P-type GaN layer.

Alternatively, the substrate 10 may be one or a combination of more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, silicon, or any other material capable of growing group III nitrides.

Optionally, the multilayer semiconductor layer 20 may be a semiconductor material of a III-V compound, and may also be silicon or another semiconductor material, which is not limited in this embodiment of the present invention.

In summary, by adding the P-type epitaxial layer 30 in the semiconductor device, the vertical projection of the anode 41 on the substrate 10 is at least partially overlapped with the vertical projection of the P-type epitaxial layer 30 on the substrate 10, and the energy band is raised by the P-type epitaxial layer 30, and the two-dimensional electron gas below the anode 41 is exhausted, so that the device leakage of the semiconductor device is reduced; on the other hand, the semiconductor device does not need to etch the multilayer semiconductor layer 20 to form the anode groove, so that etching damage does not exist, the interface state of the traditional anode groove structure is avoided, and the electric leakage of the semiconductor device is further reduced; moreover, compared with the anode groove etching process in the prior art, the P-type epitaxial layer 30 in the embodiment of the invention has better uniformity, can improve the consistency of the forward starting voltage of the device, and can avoid the problem of poor consistency of the forward starting voltage of the semiconductor device caused by uneven etching of the anode groove.

Optionally, the doping concentration n of the P-type epitaxial layer 30 satisfies 1 × 10¹⁹cm^-3≤n≤5×10¹⁹cm^-3The doping concentration of the P-type epitaxial layer 30 is reasonably set, so that the P-type epitaxial layer 30 can be ensured to properly raise an energy band, two-dimensional electron gas below the anode 41 is fully exhausted, and the device leakage of the semiconductor device is reduced; on the other hand, the process of doping the P-type epitaxial layer 30 can be matched with the existing doping process, and the preparation process of the P-type epitaxial layer 30 is simple.

Optionally, with continuing reference to fig. 1 and fig. 2, the semiconductor device provided in the embodiment of the present invention may further include a passivation layer 50, where the passivation layer 50 is located on a side of the multilayer semiconductor layer 20 away from the substrate 10 and located between the P-type epitaxial layer 30 and the cathode 42; along the first direction, the thickness h1 of the P-type epitaxial layer 30 meets the condition that h1 is more than or equal to 20nm and less than or equal to 70 nm; the thickness h2 of the passivation layer 50 satisfies that h2 is more than or equal to 40nm and less than or equal to 90 nm; wherein the first direction is parallel to the vertical direction of the substrate 10, as shown by the X-direction in the figure.

Illustratively, as shown in fig. 1 and fig. 2, the semiconductor device provided by the embodiment of the invention may further include a passivation layer 50, where the passivation layer 50 covers the multilayer semiconductor layer 20 between the P-type epitaxial layer 30 and the cathode 42, and is used for passivation protection of the multilayer semiconductor layer 20 and for insulating the anode 41 and the cathode 42. Optionally, the passivation layer 50 may be selected from one or more combinations of silicon nitride, aluminum nitride, silicon oxide, aluminum oxide, and the like having a passivation effect, which is not limited in the embodiment of the present invention.

Further, along the first direction, the thickness h1 of the P-type epitaxial layer 30 satisfies 20nm ≤ h1 ≤ 70 nm; the thickness h2 of the passivation layer 50 satisfies that h2 is more than or equal to 40nm and less than or equal to 90 nm. H1 may be any value or any range of values greater than or equal to 20nm and less than or equal to 70nm, such as 30nm, 40nm, 50nm, 70nm, 85nm, 30nm-50nm, or 50nm-70nm, which is not limited to the embodiments of the present invention and is not exhaustive. The thickness of rationally setting up P type epitaxial layer 30 can guarantee to reduce semiconductor device's device electric leakage through P type epitaxial layer 30 on the one hand, improves the uniformity of device forward opening voltage, and on the other hand can also realize the design of semiconductor device frivolousization. Similarly, h2 may be any value or any range of values greater than or equal to 40nm and less than or equal to 90nm, such as 50nm, 60nm, 70nm, 80nm, 40nm to 70nm, or 70nm to 90nm, which is not limited to be exhaustive by the embodiments of the present invention. By reasonably setting the thickness of the passivation layer 50, on one hand, the passivation protection effect on the multilayer semiconductor layer 20 can be realized, and on the other hand, the development trend of thinning and thinning of the semiconductor device can be realized.

Alternatively, the P-type epitaxial layer 30 and the passivation layer 50 may be disposed without a gap along the direction from the anode 41 to the cathode 42; or a certain interval exists between the P-type epitaxial layer 30 and the passivation layer 50; or the passivation layer 50 covers a portion of the P-type epitaxial layer 30. The different positional relationships between the P-type epitaxial layer 30 and the passivation layer 50 will be described in detail below.

First, a case where the P-type epitaxial layer 30 and the passivation layer 50 are provided without a space therebetween will be described.

Specifically, with continued reference to fig. 2, in the second direction, the distance L1 between the P-type epitaxial layer 30 and the passivation layer 50 satisfies that L1 is 0; wherein the second direction is parallel to the direction in which the anode 41 points towards the cathode 42, as shown in the Y-direction in fig. 2.

Illustratively, as shown in fig. 2, a distance L1 between the P-type epitaxial layer 30 and the passivation layer 50 satisfies that L1 is 0, that is, there is no separation and no overlap between the side of the P-type epitaxial layer 30 close to the cathode 42 and the side of the passivation layer 50 close to the anode 41, the device leakage of the semiconductor device is reduced by the P-type epitaxial layer 30, the consistency of the forward turn-on voltage of the device is improved, and passivation protection of the multilayer semiconductor layer 20 is achieved by the passivation layer 50.

Next, a case where a certain space is provided between the P-type epitaxial layer 30 and the passivation layer 50 in a direction from the anode 41 to the cathode 42 will be described.

FIG. 3 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present invention, and FIG. 4 is a schematic structural diagram of a cross-section of the semiconductor device provided in FIG. 3 along a section line B-B', as shown in FIGS. 3 and 4, a distance L1 between the P-type epitaxial layer 30 and the passivation layer 50 along a second direction satisfies 0.4 μm & lt L1 & lt 1 μm; wherein the second direction is parallel to the direction in which the anode 41 points toward the cathode 42, such as the Y direction shown in fig. 4; the anode 41 comprises a first anode subsection 411 located at a side of the P-type epitaxial layer 30 remote from the substrate 10 and a second anode subsection 412 located between the P-type epitaxial layer 30 and the passivation layer 50, the second anode subsection 412 forming a schottky contact with the multilayer semiconductor layer 20.

Illustratively, a certain distance exists between the P-type epitaxial layer 30 and the passivation layer 50 along the second direction (Y direction shown in the figure), so that when the anode metal is evaporated, a first anode subsection 411 is formed at a side of the P-type epitaxial layer 30 away from the substrate 10, a second anode subsection 412 is formed in a gap between the P-type epitaxial layer 30 and the passivation layer 50, the second anode subsection 412 forms a schottky contact with the multilayer semiconductor layer 20, a schottky junction is formed, and the turn-on voltage of the semiconductor device is further reduced through the schottky junction. Moreover, when a certain distance exists between the P-type epitaxial layer 30 and the passivation layer 50, the requirements on the preparation process of the P-type epitaxial layer 30 and the passivation layer 50 are low, a relative position relationship without separation and overlapping between the P-type epitaxial layer 30 and the passivation layer 50 is not required, the requirements on the preparation process of the semiconductor device are low, and the preparation process of the semiconductor device is simple.

Further, along the second direction, the distance L1 between the P-type epitaxial layer 30 and the passivation layer 50 satisfies 0.4 μm ≦ L1 ≦ 1 μm, where L1 may be any value or any range of values greater than or equal to 0.4 μm and less than or equal to 1 μm, such as 0.5 μm, 0.6 μm, 0.75 μm, 0.85 μm, 0.95 μm, 0.5 μm-0.75 μm, or 0.75 μm-1 μm, which is not limited and is not exhaustive by the embodiments of the present invention. The distance between the P-type epitaxial layer 30 and the passivation layer 50 is reasonably set, so that the starting voltage of the semiconductor device can be reduced through the schottky junction between the second anode subsection 412 and the multilayer semiconductor layer 20, and the electrical performance of the semiconductor device is improved.

Next, a case where the passivation layer 50 covers a portion of the P-type epitaxial layer 30 in a direction in which the anode 41 is directed toward the cathode 42 will be described.

FIG. 5 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present invention, and FIG. 6 is a schematic structural diagram of a cross-section of the semiconductor device provided in FIG. 5 along a section line C-C', as shown in FIG. 3 and FIG. 4, a passivation layer 50 near one side of the P-type epitaxial layer 30 along a second direction covers a portion of the P-type epitaxial layer 30, and an extension length L2 of the portion of the passivation layer 50 covering the P-type epitaxial layer 30 along the second direction satisfies 0.4 μm & lt/EN & gt L2 & lt/EN & gt 1 μm; wherein the second direction is parallel to a direction in which the anode points toward the cathode.

Illustratively, the passivation layer 50 near one side of the P-type epitaxial layer 30 covers a part of the P-type epitaxial layer 30 along the second direction (Y direction shown in the figure), so that the anode 41 above the overlapped part of the passivation layer 50 and the P-type epitaxial layer 30 can be understood as a part of the anode field plate extending towards the cathode 42, so that the electric field peak at the edge of the anode 41 near the cathode 42 can be further reduced, and the reverse bias withstand voltage of the semiconductor device can be improved. Moreover, when the passivation layer 50 close to one side of the P-type epitaxial layer 30 covers part of the P-type epitaxial layer 30, the requirements on the preparation process of the P-type epitaxial layer 30 and the passivation layer 50 are low, no separation or overlapping relative position relation is not required to be formed between the P-type epitaxial layer 30 and the passivation layer 50, the requirements on the preparation process of the semiconductor device are low, and the preparation process of the semiconductor device is simple.

Further, along the second direction, the extension length L2 of the portion of the passivation layer 50 covering the P-type epitaxial layer 30 satisfies 0.4 μm ≦ L2 ≦ 1 μm, where L2 may be any value or any range of values greater than or equal to 0.4 μm and less than or equal to 1 μm, such as 0.5 μm, 0.6 μm, 0.75 μm, 0.85 μm, 0.95 μm, 0.5 μm-0.75 μm, or 0.75 μm-1 μm, which is not limited by the embodiments of the present invention and is not exhaustive. The extension length of the part of the passivation layer 50 covering the P-type epitaxial layer 30 is reasonably set, so that the anode 41 positioned above the overlapped part of the passivation layer 50 and the P-type epitaxial layer 30 can further reduce the electric field peak value of the anode 41 close to the edge of the cathode 42, the reverse bias withstand voltage of the semiconductor device is improved, and the electrical performance of the semiconductor device is improved.

In summary, in the embodiment of the present invention, the position relationship between the P-type epitaxial layer 30 and the passivation layer 50 along the second direction is not limited, and no interval may be provided between the P-type epitaxial layer 30 and the passivation layer 50, or a certain interval may exist between the P-type epitaxial layer 30 and the passivation layer 50, or the passivation layer 50 covers a part of the P-type epitaxial layer 30, and the position relationship between the P-type epitaxial layer 30 and the passivation layer 50 may be selected according to the actual manufacturing process and the actual product requirement.

Fig. 7 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present invention, and fig. 8 is a schematic structural diagram of a cross-section of the semiconductor device provided in fig. 7 along a section line D-D', as shown in fig. 7 and 8, the semiconductor device further includes an anode field plate 60 located on a side of the passivation layer 50 away from the substrate 10, wherein the anode field plate 60 is electrically connected to the anode 41; along the first direction, the thickness h1 of the P-type epitaxial layer 30 and the thickness h2 of the passivation layer 50 meet the requirement that h2-h1 are more than or equal to 5nm and less than or equal to 60 nm; the extended length L3 of the anode field plate 60 in the second direction satisfies 0.4 μm L3 m 2 μm; wherein the second direction is parallel to the direction in which the anode 41 is directed towards the cathode 42.

Illustratively, the anode field plate 60 is electrically connected to the anode 41, and the anode field plate 60 and the anode 41 can be fabricated in the same process. Along the first direction, the thickness h1 of the P-type epitaxial layer 30 is smaller than the thickness h2 of the passivation layer 50, so that the surface of the anode 41 close to the substrate 10 side is closer to the substrate 10 than the surface of the anode field plate 60 close to the substrate 10 side, so that the electric field concentration degree at the edge of the anode 41 close to the anode field plate 60 side can be dispersed, the electric field peak value at the edge of the anode 41 close to the anode field plate 60 side is reduced, the reverse bias withstand voltage of the semiconductor device is improved, and the electrical performance of the semiconductor device is improved. Further, by forming the anode field plate 60 on the side of the passivation layer 50 far from the substrate 10, the modulation capability of the two-dimensional electron gas is enhanced by the anode field plate 60, and meanwhile, the electric field peak value at the edge of the anode 41 close to the anode field plate 60 is further reduced, and the reverse bias withstand voltage of the semiconductor device is improved.

Further, along the first direction (X direction shown in the figure), the thickness h1 of the P-type epitaxial layer 30 and the thickness h2 of the passivation layer 50 satisfy 5nm ≦ h2-h1 ≦ 60nm, wherein the difference between the thickness of the P-type epitaxial layer 30 and the thickness of the passivation layer 50 may be any value or any range of values greater than or equal to 5nm and less than or equal to 60nm, such as 10nm, 20nm, 30nm, 40nm, 50nm, 10nm-30nm, or 30nm-60nm, which is not limited and is not exhaustive in the embodiments of the present invention. The difference between the thickness of the P-type epitaxial layer 30 and the thickness of the passivation layer 50 is reasonably set, so that the surface of the anode 41 close to one side of the substrate 10 can be ensured to be closer to the substrate 10 than the surface of the anode field plate 60 close to one side of the substrate 10, the electric field gathering degree of the anode 41 close to one side edge of the anode field plate 60 can be dispersed, the electric field peak value of the anode 41 close to one side edge of the anode field plate 60 is reduced, the reverse bias withstand voltage of the semiconductor device is improved, and the electrical performance of the semiconductor device is improved.

Further, along the second direction (Y direction as shown in the figure), the extension length L3 of the anode field plate 60 satisfies 0.4 μm ≦ L3 ≦ 2 μm, where L3 may be any value or any range of values greater than or equal to 0.4 μm and less than or equal to 2 μm, such as 0.5 μm, 0.6 μm, 0.9 μm, 1.4 μm, 1.85 μm, 0.4 μm-0.95 μm, or 0.25 μm-2 μm, which is not limited by the embodiments of the present invention and is not exhaustive. The extension length of the anode field plate 60 is reasonably set, so that the modulation capability of the anode field plate 60 on two-dimensional electron gas can be ensured, the electric field peak value at the edge of the anode 41 close to the anode field plate 60 is further reduced, and the reverse bias withstand voltage of the semiconductor device is improved.

Fig. 9 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present invention, and fig. 10 is a schematic structural diagram of a cross-section of the semiconductor device provided in fig. 9 along a section line E-E', as shown in fig. 9 and 10, where the P-type epitaxial layer 30 is continuously disposed along the second direction. In a preferred embodiment, along the second direction, the P-type epitaxial layer 30 includes a plurality of first P-type epitaxial layer segments 31 arranged at intervals; the anode 41 comprises a first anode subsection 411 positioned on one side of the first P-type epitaxial layer subsection 31 far away from the substrate 10 and a third anode subsection 413 positioned between two adjacent first P-type epitaxial layer subsections 31, wherein the third anode subsection 413 forms Schottky contact with the multilayer semiconductor layer 20, and compared with a structure in which the P-type epitaxial layer 30 is continuously arranged, the arrangement of the first P-type epitaxial layer subsections at intervals can reduce the forward starting voltage of the device and improve the performance of the semiconductor device; wherein the second direction is parallel to the direction in which the anode 41 points towards the cathode 42, as indicated by the Y-direction in the figure.

Illustratively, the P-type epitaxial layer 30 may be continuously disposed along the second direction (e.g., the Y direction shown in the figures) (as shown in fig. 1-8), or may include a plurality of first P-type epitaxial layer segments 31 disposed at intervals (as shown in fig. 9 and 10), which is not limited in this embodiment of the invention. When the P-type epitaxial layer 30 includes a plurality of first P-type epitaxial layer segments 31 arranged at intervals, the anode 41 may include a first anode subsection 411 positioned on one side of the first P-type epitaxial layer segment 31 away from the substrate 10 and a third anode subsection 413 positioned between two adjacent first P-type epitaxial layer segments 31, and the third anode subsection 413 forms schottky contact with the multilayer semiconductor layer 20, so as to arrange the device structure, on one hand, the first P-type epitaxial layer segment 31 is depleted of 2DEG to reduce reverse bias leakage, on the other hand, the schottky junction between the third anode subsection 413 and the multilayer semiconductor layer 20 is used to reduce forward starting voltage and power consumption, thereby effectively improving device performance and increasing device operation stability.

Further, as shown in FIG. 10, along the second direction (Y direction as shown in the figure), the extension length L4 of the first P-type epitaxial-layer block 31 satisfies 0.1 μm L4 0.5 μm; the distance L5 between two adjacent first P-type epitaxial layer blocks 31 meets the condition that L5 is more than or equal to 0.3 mu m and less than or equal to 0.5 mu m.

Illustratively, along the second direction, the extension length L4 of the first P-type epitaxial layer segment 31 satisfies 0.1 μm L4 0.5 μm, and the distance L5 between two adjacent first P-type epitaxial layer segments 31 satisfies 0.3 μm L5 0.5 μm. L4 may be any value or any range of values greater than or equal to 0.1 μm and less than or equal to 0.5 μm, and L5 may be any value or any range of values greater than or equal to 0.3 μm and less than or equal to 0.5 μm, which are not limited and are not exhaustive in the embodiments of the present invention. The extension length of the first P-type epitaxial layer sub-block 31 and the distance between two adjacent first P-type epitaxial layer sub-blocks 31 are reasonably set, so that the first P-type epitaxial layer sub-block 31 can be further controlled to effectively exhaust 2DEG, the influence on carriers of the device can be avoided, the forward starting voltage can be reasonably controlled and reduced through the Schottky junction between the third anode sub-block 413 and the multilayer semiconductor layer 20, and the overall electrical performance of the semiconductor device can be improved.

Fig. 11 is a schematic cross-sectional structure view of the semiconductor device provided in fig. 1 along a cross-sectional line F-F ', fig. 12 is a schematic cross-sectional structure view of another semiconductor device provided in accordance with an embodiment of the present invention, and fig. 13 is a schematic cross-sectional structure view of the semiconductor device provided in fig. 12 along a cross-sectional line G-G', as shown in fig. 1, fig. 11, fig. 12 and fig. 13, wherein a P-type epitaxial layer 30 is continuously disposed along a third direction; or, along the third direction, the P-type epitaxial layer 30 includes a plurality of second P-type epitaxial layer segments 32 arranged at intervals; the anode 41 comprises a first anode subsection 411 positioned on one side of the second P-type epitaxial layer subsection 32 far away from the substrate 10 and a fourth anode subsection 414 positioned between two adjacent second P-type epitaxial layer subsections 32, and the fourth anode subsection 414 forms Schottky contact with the multilayer semiconductor layer 20, so that compared with a continuously arranged P-type epitaxial layer structure, the structure can reduce the starting voltage of the device and the power consumption; wherein the third direction is parallel to the plane of the substrate 10 and perpendicular to the direction in which the anode 41 points towards the cathode 42, as shown in the figure as the Z-direction. Illustratively, the P-type epitaxial layer 30 may be continuously disposed along the third direction (e.g., the Z direction shown in the figures) (as shown in fig. 1 and 11), or may include a plurality of second P-type epitaxial layer segments 32 disposed at intervals (as shown in fig. 12 and 13), which is not limited in this embodiment of the present invention. When the P-type epitaxial layer 30 includes a plurality of second P-type epitaxial layer segments 32 arranged at intervals, the anode 41 may include a first anode segment 411 located on one side of the second P-type epitaxial layer segment 32 away from the substrate 10 and a fourth anode segment 414 located between two adjacent second P-type epitaxial layer segments 32, the fourth anode segment 414 forms schottky contact with the multilayer semiconductor layer 20, so that the device reverse bias leakage is reduced by depletion of 2DEG by the second P-type epitaxial layer segments 32, and the forward turn-on voltage is reduced and the power consumption is reduced by a schottky junction between the fourth anode segment 414 and the multilayer semiconductor layer 20.

Further, as shown in FIG. 13, along the third direction (Z direction as shown in the figure), the extension length L6 of the second P-type epitaxial layer block 32 satisfies 0.1 μm L6 0.5 μm; the distance L7 between two adjacent second P-type epitaxial layer blocks 32 satisfies 0.3 mu m-L7-0.5 mu m.

Illustratively, along the third direction, the extension length L6 of the second P-type epitaxial layer segment 32 satisfies 0.1 μm L6 0.5 μm, and the distance L7 between two adjacent second P-type epitaxial layer segments 32 satisfies 0.3 μm L7 0.5 μm. L6 may be any value or any range of values greater than or equal to 0.1 μm and less than or equal to 0.5 μm, and L7 may be any value or any range of values greater than or equal to 0.3 μm and less than or equal to 0.5 μm, which are not limited and are not exhaustive in the embodiments of the present invention. The extension length of the second P-type epitaxial layer sub-block 32 and the distance between two adjacent second P-type epitaxial layer sub-blocks 32 are reasonably set, so that the 2DEG can be consumed by the second P-type epitaxial layer sub-blocks 32, the forward starting voltage can be reduced by the schottky junction between the fourth anode subsection 414 and the multilayer semiconductor layer 20, and the electrical performance of the semiconductor device is improved.

Alternatively, as shown with continued reference to fig. 2, 4, 6, 8, 10, 11, and 13, embodiments of the invention provide a multilayer semiconductor layer 20 that may include a nucleation layer 21 on a substrate 10; a buffer layer 22 located on a side of the nucleation layer 21 away from the substrate 10; a channel layer 23 on the buffer layer 22 on the side away from the nucleation layer 21; and a barrier layer 24 on a side of the channel layer 23 remote from the buffer layer 22.

Illustratively, the material of the nucleation layer 21 and the buffer layer 22 may be nitride, specifically GaN or AlN or other nitride, and may also be silicon or other semiconductor material. Nucleation layer 21 and buffer layer 22 may be used to match the material of substrate 10 and epitaxial channel layer 23. The material of the channel layer 23 may be GaN or InAlN, or may be silicon or other semiconductor material. Preferably, the channel layer 23 may be an unintentionally doped gallium nitride layer (UID-GaN). The barrier layer 24 is located above the channel layer 23, and the material of the barrier layer 24 can be a gallium-based compound semiconductor material or a nitrogen-based compound semiconductor material, such as InxAlyGazN1-x-y-z, wherein x is greater than or equal to 0 and less than or equal to 1, y is greater than or equal to 0 and less than or equal to 1, and z is greater than or equal to 0 and less than or equal to 1. Optionally, the channel layer 23 and the barrier layer 24 form a semiconductor heterojunction structure, a high-concentration two-dimensional electron gas is formed at an interface between the channel layer 23 and the barrier layer 24, and the channel layer 23 provides a channel for movement of the two-dimensional electron gas. Optionally, the material of the barrier layer 204 may also be silicon or other semiconductor material. Therefore, the multilayer semiconductor layer 20 provided in the embodiment of the present invention may be a semiconductor material of a III-V compound, or may be silicon or another semiconductor material, which is not limited in the embodiment of the present invention.

Based on the same inventive concept, an embodiment of the present invention further provides a method for manufacturing a semiconductor device, and as shown in fig. 14, the method for manufacturing a semiconductor device according to the embodiment of the present invention may include:

and S110, providing a substrate.

Illustratively, the substrate may be a combination of one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, silicon, or any other material capable of growing group III nitrides. The substrate can be prepared by atmospheric pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, metal organic compound vapor deposition, low pressure chemical vapor deposition, high density plasma chemical vapor deposition, ultra-high vacuum chemical vapor deposition, plasma enhanced chemical vapor deposition, catalytic chemical vapor deposition, hybrid physical chemical vapor deposition, rapid thermal chemical vapor deposition, vapor phase epitaxy, pulsed laser deposition, atomic layer epitaxy, molecular beam epitaxy, sputtering, or evaporation.

And S120, preparing a multilayer semiconductor layer on one side of the substrate.

Illustratively, the multilayer semiconductor layer is located on one side of the substrate, and the multilayer semiconductor layer may be specifically a semiconductor material of a III-V compound, and may also be silicon or another semiconductor material, which is not limited in this embodiment of the present invention.

And S130, preparing a P-type epitaxial layer on one side of the multilayer semiconductor layer far away from the substrate.

Illustratively, the P-type epitaxial layer can be obtained by epitaxial layer on the side of the multi-layer semiconductor layer far away from the substrate, and then doping or ion implantation is performed on the epitaxial layer. The epitaxial layer may be a GaN layer, and the doped or implanted ions may be Mg or Al.

S140, preparing an anode on the side, away from the multilayer semiconductor layer, of the P-type epitaxial layer, and preparing a cathode on the side, away from the substrate, of the multilayer semiconductor layer, wherein the vertical projection of the anode on the substrate at least partially overlaps the vertical projection of the P-type epitaxial layer on the substrate.

Exemplarily, an anode is prepared on one side of the P-type epitaxial layer far away from the multilayer semiconductor layer, the vertical projection of the anode on the substrate is at least partially overlapped with the vertical projection of the P-type epitaxial layer on the substrate, and the energy band is raised through the P-type epitaxial layer, and two-dimensional electron gas below the anode is exhausted, so that the device leakage of the semiconductor device is reduced; on the other hand, the preparation method of the semiconductor device does not need to etch the multilayer semiconductor layer to form the anode groove, so that no etching damage exists, the interface state of the traditional anode groove structure is avoided, and the electric leakage of the semiconductor device is further reduced; compared with the anode groove etching process in the prior art, the P-type epitaxial layer in the embodiment of the invention has better uniformity, can improve the consistency of the forward starting voltage of the device, and can avoid the problem of poor consistency of the forward starting voltage of the semiconductor device caused by uneven etching of the anode groove.

Optionally, the method for manufacturing a semiconductor device according to the embodiment of the present invention may further include manufacturing a passivation layer on a side of the multilayer semiconductor layer away from the substrate and manufacturing an anode field plate on a side of the passivation layer away from the substrate; meanwhile, the step of preparing the multi-layered semiconductor layer may include sequentially preparing a nucleation layer, a buffer layer, a channel layer, and a barrier layer. The specific process flow of the semiconductor device will be described in detail below with reference to the method of manufacturing the semiconductor device in the actual manufacturing process.

Step 1: extending an AlN nucleating layer on a Si substrate by MOCVD;

step 2: extending a GaN buffer layer on the AlN nucleating layer;

and 3, step 3: extending an unintentionally doped UID-GaN channel layer on the GaN buffer layer;

and 4, step 4: extending an AlGaN barrier layer on the UID-GaN channel layer;

and 5, step 5: extending a GaN epitaxial layer on the AlGaN barrier layer;

and 6, step 6: carrying out Mg ion doping on the GaN epitaxial layer to form a P-type GaN epitaxial layer;

and 7, step 7: manufacturing a SiO2/Ti/Ni laminated layer on the P-type GaN epitaxial layer;

and 8, step 8: coating photoresist on the SiO2/Ti/Ni laminated layer, developing a non-Schottky region, carrying out ICP etching, and etching off the SiO2/Ti/Ni laminated layer outside the Schottky region;

step 9: etching the P-type GaN epitaxial layer outside the non-Schottky region by taking the SiO2/Ti/Ni laminated layer as a mask;

step 10: removing the SiO2/Ti/Ni laminated layer, and cleaning the wafer;

and 11, step 11: depositing a SiN passivation layer on the surface of the P-type GaN epitaxial layer;

step 12: photoetching and developing an ohmic region on the surface of the wafer, etching away SiN in the region, evaporating Ti/Al/Ni/Au metal, stripping and annealing to form an ohmic contact cathode;

step 13: and photoetching and developing a Schottky region on the surface of the wafer, etching away SiN in the region, evaporating Ni/Au metal, and stripping to form a Schottky anode and an anode field plate.

In summary, according to the method for manufacturing the semiconductor device provided by the embodiment of the invention, the P-type epitaxial layer is additionally arranged in the semiconductor device, the vertical projection of the anode on the substrate is at least partially overlapped with the vertical projection of the P-type epitaxial layer on the substrate, and the energy band is raised through the P-type epitaxial layer, and the two-dimensional electron gas below the anode is exhausted, so that the device leakage of the semiconductor device is reduced; on the other hand, the semiconductor device does not need to etch the multilayer semiconductor layer to form the anode groove, so that etching damage does not exist, the interface state of the traditional anode groove structure is avoided, and the electric leakage of the semiconductor device is further reduced; compared with the anode groove etching process in the prior art, the P-type epitaxial layer in the embodiment of the invention has better uniformity, can improve the consistency of the forward starting voltage of the device, and can avoid the problem of poor consistency of the forward starting voltage of the semiconductor device caused by uneven etching of the anode groove.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.