阅读说明：本技术 一种基于cpld的数字式正弦波电路 (Digital sine wave circuit based on CPLD ) 是由 张海宝 于 2020-11-17 设计创作，主要内容包括：本发明公开了一种基于CPLD的数字式正弦波电路,包括CPLD单元、RC加权滤波电路和有源滤波电路,CPLD单元输入端接收外部基准时钟信号、外部同步信号和预设的初始相位,输出端连接RC加权滤波电路的输入端,RC加权滤波电路的输出端连接有源滤波电路的输入端。本发明所产生的正弦信号具有频率、幅值、相位、波形系数等参数高度稳定准确和波形失真度小的优点,可设置正弦波形的初始相位,接收外部同步信号,与外部主机保持一个预置的相位差。同时该电路还具有受环境温度影响小的优点,可作为单相或三相逆变器的参考基准信号,满足较宽温度范围的使用。(The invention discloses a digital sine wave circuit based on a CPLD, which comprises a CPLD unit, an RC weighted filter circuit and an active filter circuit, wherein the input end of the CPLD unit receives an external reference clock signal, an external synchronous signal and a preset initial phase, the output end of the CPLD unit is connected with the input end of the RC weighted filter circuit, and the output end of the RC weighted filter circuit is connected with the input end of the active filter circuit. The sinusoidal signal generated by the invention has the advantages of highly stable and accurate parameters such as frequency, amplitude, phase, waveform coefficient and the like and small waveform distortion degree, and can set the initial phase of the sinusoidal waveform, receive the external synchronous signal and keep a preset phase difference with an external host. Meanwhile, the circuit has the advantage of small influence of ambient temperature, can be used as a reference signal of a single-phase or three-phase inverter, and meets the use in a wider temperature range.)

1. A digital sine wave circuit based on a CPLD is characterized by comprising a CPLD unit, an RC weighted filter circuit and an active filter circuit, wherein the input end of the CPLD unit receives an external reference clock signal, an external synchronous signal and a preset initial phase, the output end of the CPLD unit is connected with the input end of the RC weighted filter circuit, and the output end of the RC weighted filter circuit is connected with the input end of the active filter circuit; the CPLD unit adjusts the phase and frequency of the output sinusoidal signal according to a preset initial phase, an input external reference clock signal and an external synchronous signal, the RC weighted filter circuit adjusts the waveform of the sinusoidal signal by adjusting the resistor connected with the output pin of the CPLD unit, so as to reduce the distortion degree of the sinusoidal waveform, and finally the waveform passes through an active filter circuit formed by an operational amplifier, so as to reduce harmonic waves and provide a good reference sinusoidal wave for the inverter.

2. The CPLD-based digital sine wave circuit according to claim 1, wherein the CPLD unit comprises a CPLD chip U1, the CPLD chip U1 is used as a sine wave control chip, monitors an external reference clock signal, an external synchronization signal and a preset initial phase setting signal which are externally input, and controls nine output ends to output high and low levels according to the three signals.

3. The CPLD-based digital sine wave circuit as claimed in claim 2, wherein nine output terminals of the CPLD chip U1 are marked as IO 5-IO 13, and each time the CPLD chip U1 receives a rising edge of an externally inputted reference clock signal, the IO 5-IO 13 perform a shift operation in the order of IO5 → IO6, IO6 → IO7, IO7 → IO8, IO8 → IO9, IO9 → IO10, IO10 → IO11, IO11 → IO12, IO12 → IO13, (! 13) → IO 5.

4. The CPLD-based digital sine wave circuit as claimed in claim 3, wherein the RC-weighted filter circuit includes nine resistors R1-R9 and a capacitor C1, nine output terminals of the CPLD chip U1 are respectively connected to one ends of resistors R1-R9, the other ends of resistors R1-R9 are connected to one end of a capacitor C1, the other end of the capacitor C1 is grounded, the resistors R1-R9 determine the waveform coefficient of the sine waveform, and the output sine waveform is changed by adjusting the resistance values of the resistors R1-R9.

5. The CPLD-based digital sine wave circuit according to claim 4, wherein the other ends of the resistors R1-R9 and one end of the capacitor C1 are simultaneously connected with one end of a capacitor C2, the other end of the capacitor C2 is connected with an active filter circuit, and the capacitor C2 plays a role in blocking DC and filters out the DC component of the sine wave on C1.

6. The CPLD-based digital sine wave circuit according to claim 5, wherein the active filter circuit comprises a second-order low-pass filter for filtering out high frequency harmonic components of the sine wave passing through the capacitor C2 and outputting a standard sine wave with lower harmonics.

7. The CPLD-based digital sine wave circuit of claim 6, wherein the second order low pass filter comprises a resistor R10, a resistor R11, a resistor R12, a resistor R13, a capacitor C3, a capacitor C4, an operational amplifier U2; one end of a resistor R10 is connected with the other end of the capacitor C2, the other end of a resistor R10 is connected with one end of a resistor R11, one end of a resistor R12 and one end of a capacitor C3, the other end of the capacitor C3 is grounded, the other end of a resistor R11 is connected with the negative input end of the operational amplifier U2, one end of the resistor R13 is grounded, the other end of the resistor R13 is connected with the positive input end of the operational amplifier U2, one end of a capacitor C4 is connected between the other end of the resistor R11 and the negative input end of the operational amplifier U2, and the other end of the capacitor C4 and the other end.

8. The CPLD-based digital sine wave circuit according to claim 7, wherein two pins are provided in the input signal of the CPLD chip U1 as a sine wave initial phase setting signal, when the two discrete quantity signals are 00, the sine wave initial phase is 0 °, when the two discrete quantity signals are 01, the sine wave initial phase is 120 °, when the two discrete quantity signals are 10, the sine wave initial phase is 240 °, and the pre-set output is performed on the RC weighting filter circuit at the CPLD output end according to the sine wave initial phase value.

9. The CPLD-based digital sine wave circuit of claim 8, wherein in said CPLD chip U1, the rising edge of each CPLD clock acquires the external synchronization signal status and stores it in a buffer variable, and when the rising edge of the next CPLD clock arrives, the external synchronization signal status in the buffer is compared with the new one, and it is determined whether a level change of 0 → 1 occurs; when the rising edge of an external synchronizing signal is received, the state of the signal is set according to the acquired sine wave initial phase, 9 paths of IO signals output to the RC weighted filter circuit are set, the external synchronizing signal is used for resetting the digital signal output to the RC weighted filter circuit by the CPLD chip U1, the preset output is performed on the RC weighted filter circuit at the output end of the CPLD according to the sine wave initial phase value after each reset, the reset frequency is the same as the frequency of the output sine wave, and the accumulated error of the phase difference between the sine wave reference signal output by the CPLD and the sine wave of an external host is prevented.

10. Use of a CPLD-based digital sine wave circuit according to any of claims 1-9 in the field of inverter technology.

Technical Field

The invention belongs to the technical field of inverters, and relates to a digital sine wave circuit based on a CPLD (complex programmable logic device), in particular to a circuit which is generated by the CPLD and used as a reference sine wave of a single-phase or three-phase inverter.

Background

At present, single-phase and three-phase inverters need to have a sinusoidal reference signal as a reference signal of output voltage, and the output voltage is modulated according to the reference signal, so that the waveform of the output voltage is close to the reference signal. The generation of the sine reference signal is realized in various modes such as a Venturi bridge circuit, a shift register circuit, a singlechip and a D/A chip. The Venturi bridge circuit is greatly influenced by temperature and is not suitable for wide-temperature environment conditions, the used devices of the shift register circuit are more, the occupied area of a circuit board is larger, and the reliability of the mode of adding the D/A chip to the singlechip is lower than that of a CPLD digital sine wave generating circuit. The digital sine wave generating circuit of the CPLD has the advantages of few devices, small temperature influence, and realization of complex functions of initial phase setting, synchronization with external input signals and the like.

Disclosure of Invention

Objects of the invention

The purpose of the invention is: the digital sine wave circuit based on the CPLD solves the problems that the traditional sine generating circuit is greatly influenced by temperature, is not suitable for use under wide-temperature environment conditions, uses more devices, occupies larger circuit board area and the like, and simultaneously aims to improve the reliability of the sine generating circuit.

(II) technical scheme

In order to solve the technical problems, the invention provides a digital sine wave circuit based on a CPLD, which comprises a CPLD unit, an RC weighted filter circuit and an active filter circuit, wherein the input end of the CPLD unit receives an external reference clock signal, an external synchronous signal and a preset initial phase, the output end of the CPLD unit is connected with the input end of the RC weighted filter circuit, and the output end of the RC weighted filter circuit is connected with the input end of the active filter circuit; the CPLD unit adjusts the phase and frequency of the output sinusoidal signal according to a preset initial phase, an input external reference clock signal and an external synchronous signal, the RC weighted filter circuit adjusts the waveform of the sinusoidal signal by adjusting the resistor connected with the output pin of the CPLD unit, so as to reduce the distortion degree of the sinusoidal waveform, and finally the waveform passes through an active filter circuit formed by an operational amplifier, so as to reduce harmonic waves and provide a good reference sinusoidal wave for the inverter.

(III) advantageous effects

The digital sine wave circuit based on the CPLD realizes a smaller area of the reference sine wave generating circuit, is suitable for being used in a wider environment temperature range, has the functions of presetting phases, synchronizing with an external host in a single period and combining into a three-phase reference sine wave, and has high practical value.

Drawings

Fig. 1 is a schematic block diagram of a digital sine wave circuit based on a CPLD of the present invention.

Fig. 2 is a circuit diagram of a digital sine wave circuit based on a CPLD.

Fig. 3 is a flow chart of a digital sine wave circuit based on a CPLD of the present invention.

Detailed Description

In order to make the objects, contents, and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.

The invention designs a digital sine wave circuit based on a CPLD (complex programmable logic device), and the circuit is shown by referring to FIG. 1 and comprises a CPLD unit, an RC (resistor-capacitor) weighting filter circuit and an active filter circuit, wherein the input end of the CPLD unit receives an external reference clock signal, an external synchronous signal and a preset initial phase, the output end of the CPLD unit is connected with the input end of the RC weighting filter circuit, and the output end of the RC weighting filter circuit is connected with the input end of the active filter circuit; the CPLD unit adjusts the phase and frequency of the output sinusoidal signal according to a preset initial phase, an input external reference clock signal and an external synchronous signal, the RC weighted filter circuit adjusts the waveform of the sinusoidal signal by adjusting the resistor connected with the output pin of the CPLD unit, so as to reduce the distortion degree of the sinusoidal waveform, and finally the waveform passes through an active filter circuit formed by an operational amplifier, so as to reduce harmonic waves and provide a good reference sinusoidal wave for the inverter.

Referring to fig. 3, the CPLD mainly implements digital sine wave output by the following steps:

1) obtaining sine wave initial phase setting signal

2) Obtaining external synchronization signal state rising edge

3) The signal is set according to the initial phase of the sine wave to output an IO signal to an RC weighted filter circuit

4) Shift operation of output IO signal according to external reference clock signal

5) Repeating the operation of the 3 rd and 4 th steps after receiving the rising edge of the external synchronous signal again

Step 1) setting two pins in an input signal of the CPLD as a sine wave initial phase setting signal according to one of the two conditions that the phase difference between any two phases of a three-phase alternating-current power supply is 120 degrees or 240 degrees, when two paths of discrete magnitude signals are 00, the sine wave initial phase is 0 degrees, when two paths of discrete magnitude signals are 01, the sine wave initial phase is 120 degrees, when two paths of discrete magnitude signals are 10, the sine wave initial phase is 240 degrees, and preset output is performed on an RC weighting filter circuit at the output end of the CPLD according to the sine wave initial phase value.

And step 2) acquiring an external synchronizing signal state on the rising edge of each CPLD clock, storing the external synchronizing signal state into a buffer variable, comparing the external synchronizing signal state in the buffer with the newly acquired external synchronizing signal state when the rising edge of the next CPLD clock arrives, and judging whether the level change of 0 → 1 occurs or not.

And 3) after receiving the rising edge of the external synchronous signal, setting the state of the signal according to the initial phase setting signal of the sine wave obtained in the step 1, and setting 9 paths of IO signals (D1-D9) output to the RC weighted filter circuit. The external synchronizing signal is used for resetting the digital signal output by the CPLD to the RC weighted filter circuit, the RC weighted filter circuit at the output end of the CPLD is preset and output according to the initial phase value of the sine wave after each reset, the reset frequency is the same as the frequency of the output sine wave, and the accumulated error of the phase difference between the sine wave reference signal output by the CPLD and the sine wave of the external host is prevented.

Step 4) performing shifting operation on 9 paths of IO signals (IO 5-IO 13) output to the RC weighted filter circuit after receiving the rising edge of the external reference clock signal, wherein the shifting sequence is IO5 → IO6, IO6 → IO7, IO7 → IO8, IO8 → IO9, IO9 → IO10, IO10 → IO11, IO11 → IO12, IO12 → IO13, (! IO13) → IO5, and performs a shift operation every time an external reference clock signal rising edge is received.

And 5) continuously carrying out shift operation according to the received external reference clock signal until the rising edge of the external synchronous signal is received again, and repeating the operations of the steps 3 and 4.

The following devices were connected as shown in fig. 2: the CPLD chip U1, as a sine wave control chip, monitors an externally input reference clock signal (IO1), a synchronization signal (IO2), and an initial phase setting signal (IO3, IO4), and controls the output high and low levels of IO5 to IO13 according to the above three signals. After receiving a rising edge of a reference clock signal input from the outside, the shift operations of IO5 to IO13 are performed once, and the shift sequence is IO5 → IO6, IO6 → IO7, IO7 → IO8, IO8 → IO9, IO9 → IO10, IO10 → IO11, IO11 → IO12, IO12 → IO13, (| IO13) → IO5, resistors R1 to R9, and a capacitor C1 form an RC weighted filter circuit, wherein the resistors R1 to R9 determine the waveform coefficients of a sinusoidal waveform, and the output sinusoidal waveform can be changed by adjusting the resistance values of R1 to R9. The capacitor C2 acts as a dc block and filters out the dc component of the sine wave at C1. The resistors R10-R13, the capacitors C3 and C4 and the operational amplifier U2 form a second-order low-pass filter, high-frequency harmonic components in the sine wave passing through the C2 are filtered, and a standard sine wave containing lower harmonics is output.

According to the technical scheme, the sinusoidal signal generated by the invention has the advantages of highly stable and accurate parameters such as frequency, amplitude, phase, waveform coefficient and the like and small waveform distortion degree, and can be used for setting the initial phase of the sinusoidal waveform, receiving the external synchronous signal and keeping a preset phase difference with an external host. Meanwhile, the circuit has the advantage of small influence of ambient temperature, can be used as a reference signal of a single-phase or three-phase inverter, and meets the use in a wider temperature range.

The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.