阅读说明：本技术 低温高品质的介电膜 (Low temperature high quality dielectric films ) 是由 E·文卡塔苏布磊曼聂 S·E·戈特海姆 P·曼纳 A·B·玛里克 于 2019-07-15 设计创作，主要内容包括：描述了沉积高密度介电膜以用于图案化应用的技术。更具体来说,提供了处理基板的方法。所述方法包括使含有前驱物的气体混合物流动到处理腔室的处理容积中,所述处理腔室具有在静电卡盘上定位的基板。将基板维持在约0.1毫托(mTorr)与约10托(Torr)之间的压力下。通过将第一RF偏压施加到静电卡盘以在基板水平处产生等离子体,而在基板上沉积介电膜。介电膜具有在约1.5至约3的范围中的折射率。(Techniques for depositing high density dielectric films for patterning applications are described. More specifically, methods of processing a substrate are provided. The method includes flowing a gas mixture containing a precursor into a processing volume of a processing chamber having a substrate positioned on an electrostatic chuck. The substrate is maintained at a pressure between about 0.1 millitorr (mTorr) and about 10Torr (Torr). A dielectric film is deposited on a substrate by applying a first RF bias to an electrostatic chuck to generate a plasma at the substrate level. The dielectric film has a refractive index in a range of about 1.5 to about 3.)

1. A method of processing a substrate, the method comprising:

flowing a gas mixture containing a precursor into a processing volume of a processing chamber having a substrate positioned on an electrostatic chuck;

maintaining the substrate at a pressure in a range of about 0.1mTorr and about 10Torr and at a temperature in a range of about-50 ℃ to about 150 ℃; and

generating a plasma at a substrate level by applying a first RF bias to the electrostatic chuck to deposit a dielectric film on the substrate, the dielectric film having a refractive index in a range of about 1.5 to about 3.

2. The method of claim 1, further comprising: applying a second RF bias to the electrostatic chuck to generate the plasma at the substrate level, wherein the second RF bias is provided at a power in a range of about 10 watts to about 3000 watts and at a frequency in a range of about 350KHz to about 100MHz, or wherein the second RF bias is provided at a power in a range of about 800 watts to about 1200 watts at a frequency of about 2 MHz.

3. The method of claim 1, wherein the first RF bias is provided at a power in a range of about 10 watts to about 3000 watts and at a frequency in a range of about 350KHz to about 100MHz, or wherein the first RF bias is provided at a power in a range of about 2500 watts to about 3000 watts at a frequency of about 13.56 MHz.

4. The method of claim 1, further comprising: applying a chucking voltage to the substrate positioned on the electrostatic chuck.

5. The method of claim 1, wherein the precursor-containing gas mixture comprises one or more precursors selected from the group consisting of: silane (SiH)₄) Triethoxy siliconAlkane (SiH (OEt)₃) Tetraethoxysilane (tetraethyl orthosilicate; si (OEt)₄Or TEOS), disilane (Si)₂H₆)、SiH(CH₃)₃Dimethylsilane (SiH)₂(CH₃)₂) Methylsilane (SiH)₃CH₃) Dichlorosilane (SiH)₂Cl₂) Silicon tetrachloride (SiCl)₄) Silicon tetrafluoride (SiF)₄) Trichlorosilane (HSiCl)₃) Methylsilane (CH)₃SiH₃) Trimethylsilane (C)₃H₁₀Si), 1,3, 3-Tetramethyldisiloxane (TMDZ), 1,3, 5-Trisilacyclopentane (TSP), (bis (tert-butylamino) silane (BTBAS), (bis (diethylamino) silane (BDEAS), tris (dimethylamino) silane (TDMAS), (Si [ n (tbu) CH ═ chn (tbu))](OEt)₂(Si-TBES)、Si[N(tBu)CH＝CHN(tBu)](H)NH₂(Si-TBAS), germane (GeH)₄) Germanium tetrachloride (GeCl)₄) Germanium tetrafluoride (GeF)₄) Tert-butylgermane (GeH (CH)₃)₃)、N₂O、O₂、NH₃、N₂、H₂、C₂H₂Or C₃H₆。

6. The method of claim 1, wherein the precursor-containing gas mixture comprises one or more diluent gases selected from the group consisting of: helium (He), argon (Ar), xenon (Xe), krypton (Kr), nitrogen (N)₂) Or hydrogen (H)₂)。

7. The method of claim 1, wherein the dielectric film comprises one or more of: silicon, silicon nitride, silicon carbide, silicon oxide, silicon oxycarbide, silicon oxycarbonitride, silicon oxynitride, titanium nitride, or a composite of oxide and nitride.

8. A method of processing a substrate, the method comprising:

flowing a gas mixture containing a precursor into a processing volume of a processing chamber having a substrate positioned on an electrostatic chuck, wherein the gas containing a precursorThe bulk mixture comprises one or more precursors selected from the group consisting of: silane (SiH)₄) Triethoxysilane (SiH (OEt)₃) Tetraethoxysilane (tetraethyl orthosilicate; si (OEt)₄Or TEOS), disilane (Si)₂H₆)、SiH(CH₃)₃Dimethylsilane (SiH)₂(CH₃)₂) Methylsilane (SiH)₃CH₃) Dichlorosilane (SiH)₂Cl₂) Silicon tetrachloride (SiCl)₄) Silicon tetrafluoride (SiF)₄) Trichlorosilane (HSiCl)₃) Methylsilane (CH)₃SiH₃) Trimethylsilane (C)₃H₁₀Si), 1,3, 3-Tetramethyldisiloxane (TMDZ), 1,3, 5-Trisilacyclopentane (TSP), (bis (tert-butylamino) silane (BTBAS), (bis (diethylamino) silane (BDEAS), tris (dimethylamino) silane (TDMAS), (Si [ n (tbu) CH ═ chn (tbu))](OEt)₂(Si-TBES)、Si[N(tBu)CH＝CHN(tBu)](H)NH₂(Si-TBAS), germane (GeH)₄) Germanium tetrachloride (GeCl)₄) Germanium tetrafluoride (GeF)₄) Tert-butylgermane (GeH (CH)₃)₃)、N₂O、O₂、NH₃、N₂、H₂、C₂H₂Or C₃H₆；

Maintaining the substrate at a pressure in a range of about 0.1mTorr to about 10 Torr; and

generating a plasma at a substrate level by applying a first RF bias and a second RF bias to the electrostatic chuck to deposit a dielectric film on the substrate, the dielectric film having a refractive index in a range of about 1.5 to about 3.

9. The method of claim 8, wherein the first RF bias is provided at a power in the range of about 2500 watts to about 3000 watts at a frequency of about 13.56 MHz.

10. The method of claim 8, wherein the second RF bias is provided at a power in the range of about 800 watts to about 1200 watts at a frequency of about 2 MHz.

11. A method of processing a substrate, the method comprising:

flowing a gas mixture containing a precursor into a processing volume of a processing chamber having a substrate positioned on an electrostatic chuck;

maintaining the processing volume at a pressure in a range of about 0.1mTorr to about 10 Torr;

generating a plasma at a substrate level by applying a first RF bias and a second RF bias to the electrostatic chuck to deposit a dielectric film on the substrate, the dielectric film having a refractive index in a range of about 1.5 to about 3;

forming a patterned photoresist layer over the dielectric film;

etching the dielectric film in a pattern corresponding to the patterned photoresist layer to provide etched portions of the dielectric film;

etching the pattern into the substrate; and

depositing a material into the etched portion of the dielectric film.

12. The method of claim 11, wherein the first RF bias is provided at a power in the range of about 10 watts to about 3000 watts at a frequency of about 350KHz to about 100 MHz.

13. The method of claim 11, wherein the second RF bias is provided at a power in a range of about 10 watts to about 3000 watts at a frequency in a range of about 350KHz to about 100 MHz.

14. The method of claim 11, wherein the precursor-containing gas mixture comprises one or more precursors selected from the group consisting of: silane (SiH)₄) Triethoxysilane (SiH (OEt)₃) Tetraethoxysilane (tetraethyl orthosilicate; si (OEt)₄Or TEOS), disilane (Si)₂H₆)、SiH(CH₃)₃Dimethylsilane (SiH)₂(CH₃)₂) Methylsilane (SiH)₃CH₃) Dichlorosilane (SiH)₂Cl₂) Silicon tetrachloride (SiCl)₄) Silicon tetrafluoride (SiF)₄) Trichlorosilane (HSiCl)₃) Methylsilane (CH)₃SiH₃) Trimethylsilane (C)₃H₁₀Si), 1,3, 3-Tetramethyldisiloxane (TMDZ), 1,3, 5-Trisilacyclopentane (TSP), (bis (tert-butylamino) silane (BTBAS), (bis (diethylamino) silane (BDEAS), tris (dimethylamino) silane (TDMAS), (Si [ n (tbu) CH ═ chn (tbu))](OEt)₂(Si-TBES)、Si[N(tBu)CH＝CHN(tBu)](H)NH₂(Si-TBAS), germane (GeH)₄) Germanium tetrachloride (GeCl)₄) Germanium tetrafluoride (GeF)₄) Tert-butylgermane (GeH (CH)₃)₃)、N₂O、O₂、NH₃、N₂、H₂、C₂H₂Or C₃H₆。

15. The method of claim 11, wherein the precursor-containing gas mixture comprises one or more diluent gases selected from the group consisting of: helium (He), argon (Ar), xenon (Xe), krypton (Kr), nitrogen (N)₂) Or hydrogen (H)₂)。

Technical Field

Embodiments of the present disclosure relate to the field of electronic component manufacturing, and in particular, to Integrated Circuit (IC) manufacturing. More specifically, embodiments of the present disclosure provide methods of depositing dielectric films that may be used for patterning applications.

Background

Integrated circuits have evolved into complex components that can include millions of transistors, capacitors, and resistors on a single wafer. The development of chip designs continues to demand faster circuitry and greater circuit density. The demand for faster circuits with greater circuit density places corresponding demands on the materials used to fabricate such integrated circuits. In particular, as the size of integrated circuit components is reduced, low resistivity conductive materials as well as low dielectric constant insulating materials must be used to obtain suitable electrical performance from such components.

The demand for greater integrated circuit density also places demands on the process sequences used in the manufacture of integrated circuit components. For example, in a process sequence using conventional lithographic techniques, an energy sensitive resist layer is formed over a material layer stack disposed on a substrate. The energy sensitive resist layer is exposed to a pattern image to form a photoresist mask. Thereafter, the mask pattern is transferred to one or more material layers of the stack using an etching process. The chemical etchant used in the etching process is selected to have a greater etch selectivity to the stacked material layers than the mask of the energy sensitive resist. That is, the chemical etchant etches one or more layers of the material stack at a much faster rate than the energy sensitive resist. The etch selectivity of the resist to one or more material layers of the stack prevents the consumption of energy sensitive resist before pattern transfer is complete.

As the pattern size decreases, the thickness of the energy sensitive resist must be correspondingly reduced in order to control the pattern resolution. Many new applications in the industry have very low thermal budgets, below 400 ℃ (e.g., cross-point memory flows). Therefore, there is a need to deposit high quality dielectric films for patterning and other applications that meet this stringent thermal budget without sacrificing film quality.

Disclosure of Invention

Apparatus and methods for fabricating integrated circuits are described. In one or more embodiments, a method of forming a film on a substrate is described. In one embodiment, a film is formed on a substrate by flowing a gas mixture containing a precursor into a processing volume of a processing chamber having a substrate positioned on an electrostatic chuck. The substrate is maintained at a pressure in a range of about 0.1 millitorr (mTorr) and about 10Torr (Torr) and at a temperature in a range of about-50 ℃ to about 150 ℃. Depositing a dielectric film on the substrate by applying a first RF bias to the electrostatic chuck to generate a plasma at the substrate level, the dielectric film having a refractive index in a range of about 1.5 to about 3.

In one or more embodiments, a method of forming a film on a substrate is described. In one embodiment, a film is formed on a substrate by flowing a gas mixture containing a precursor into a processing volume of a processing chamber having a substrate positioned on an electrostatic chuck, wherein the gas mixture containing a precursor comprises one or more precursors selected from the group consisting of: silane (SiH)₄) Triethoxysilane (SiH (OEt)₃) Tetraethoxysilane(tetraethyl orthosilicate; Si (OEt)₄Or TEOS), disilane (Si)₂H₆)、SiH(CH₃)₃Dimethylsilane (SiH)₂(CH₃)₂) Methylsilane (SiH)₃CH₃) Dichlorosilane (SiH)₂Cl₂) Silicon tetrachloride (SiCl)₄) Silicon tetrafluoride (SiF)₄) Trichlorosilane (HSiCl)₃) Methylsilane (CH)₃SiH₃) Trimethylsilane (C)₃H₁₀Si), 1,3, 3-Tetramethyldisiloxane (TMDZ), 1,3, 5-Trisilacyclopentane (TSP), (bis (tert-butylamino) silane (BTBAS), (bis (diethylamino) silane (BDEAS), tris (dimethylamino) silane (TDMAS), (Si [ n (tbu) CH ═ chn (tbu))](OEt)₂(Si-TBES)、Si[N(tBu)CH＝CHN(tBu)](H)NH₂(Si-TBAS), germane (GeH)₄) Germanium tetrachloride (GeCl)₄) Germanium tetrafluoride (GeF)₄) Tert-butylgermane (GeH (CH)₃)₃)、N₂O、O₂、NH₃、N₂、H₂、C₂H₂Or C₃H₆. The substrate is maintained at a pressure in a range of about 0.1mTorr to about 10 Torr. A dielectric film is deposited on the substrate by generating a plasma at the substrate level by applying a first RF bias and a second RF bias to the electrostatic chuck, the dielectric film having a refractive index in a range of about 1.5 to about 3.

In one or more embodiments, a method of forming a film on a substrate is described. In one embodiment, a film is formed on a substrate by flowing a gas mixture containing a precursor into a processing volume of a processing chamber having a substrate positioned on an electrostatic chuck. The process volume is maintained at a pressure in a range of about 0.1mTorr to about 10 Torr. A dielectric film is deposited on the substrate by generating a plasma at the substrate level by applying a first RF bias and a second RF bias to the electrostatic chuck, the dielectric film having a refractive index in a range of about 1.5 to about 3. A patterned photoresist layer is formed over the dielectric film. The dielectric film is etched in a pattern corresponding to the patterned photoresist layer. A pattern is etched into the substrate. A material is deposited into the etched portions of the dielectric film.

Drawings

So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments. Embodiments as described herein are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements.

FIG. 1A shows a schematic cross-sectional view of a deposition system that can be used to practice embodiments described herein;

FIG. 1B depicts a schematic cross-sectional view of another deposition system that may be used to practice embodiments described herein;

FIG. 2 depicts a schematic cross-sectional view of an electrostatic chuck that may be used in the apparatus of FIGS. 1A and 1B to practice embodiments described herein;

FIG. 3 depicts a flow diagram of a method for forming a dielectric film on a substrate in accordance with one or more embodiments; and

fig. 4A-4B depict one embodiment of a sequence for forming a dielectric film on a film stack formed on a substrate in accordance with one or more embodiments.

Detailed Description

Before describing several exemplary embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The disclosure is capable of other embodiments and of being practiced or of being carried out in various ways.

The numerous details, dimensions, angles and other features illustrated in the various figures are merely illustrative of particular embodiments. Thus, other embodiments may have other details, components, dimensions, angles, and features without departing from the spirit or scope of the disclosure. Furthermore, other embodiments of the disclosure may be practiced without several of the details described below.

As used herein, "substrate," "substrate surface," and the like refer to any substrate or material surface formed on a substrate on which processing is performed. For example, depending on the application, the substrate surface on which processing may be performed includes, but is not limited to, materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. The substrate may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate (or otherwise create or graft a target chemical moiety to impart chemical functionality), anneal, and/or bake the substrate surface. In addition to processing directly on the surface of the substrate itself, in the present disclosure, as disclosed in more detail below, any film processing steps of the disclosure may also be performed on an underlying layer formed on the substrate, and the term "substrate surface" is intended to include such an underlying layer as the context dictates. Thus, for example, in the case where a film/layer or a portion of a film/layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film/layer becomes the substrate surface. The material comprising a given substrate surface will depend on the material to be deposited, as well as the particular chemistry used.

As used in this specification and the appended claims, the terms "reactive compound," "reactive gas," "reactive species," "precursor," "process gas," and the like are used interchangeably to mean a species having a species capable of reacting with a substrate surface or a material on a substrate surface in a surface reaction (e.g., chemisorption, oxidation, reduction). For example, a first "reactive gas" may simply adsorb onto the substrate surface and be available for further chemical reaction with a second reactive gas.

As used in this specification and the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gaseous species that can react with a substrate surface.

As used herein, "chemical vapor deposition" refers to a process of simultaneously or substantially simultaneously exposing a substrate surface to a precursor and/or a co-reactant. As used herein, "substantially simultaneously" refers to a situation where co-flows or overlaps exist for a majority of the exposure of the precursors.

Plasma Enhanced Chemical Vapor Deposition (PECVD) is widely used to deposit films due to cost efficiency and film quality versatility. In a PECVD process, a hydrocarbon source (such as a vapor of a gas phase hydrocarbon or a liquid phase hydrocarbon) that has been carried in a carrier gas is introduced into a PECVD chamber. A plasma-initiated gas, typically helium, is also introduced into the chamber. A plasma is then initiated in the chamber to generate excited CH radicals. The excited CH radicals chemically bond to a surface of the substrate positioned in the chamber, thereby forming a desired amorphous carbon film thereon. The embodiments described herein with reference to PECVD processes may be performed using any suitable thin film deposition system. Any device descriptions described herein are illustrative and should not be understood or interpreted as limiting the scope of the embodiments described herein.

Many applications in the semiconductor industry have very low thermal budgets of less than 400 c, and even less than 300 c in some cases. Generally, in the PECVD process, film quality is greatly impaired at low temperatures. Embodiments described herein advantageously provide methods for depositing high quality dielectric films for patterning and other applications that meet this stringent thermal budget without sacrificing film quality.

Embodiments described herein include improved methods of making dielectric films having high density (e.g., > 1.8g/cc), high refractive index (e.g., > 1.5), and low stress (e.g., < -500 MPa). In one or more embodiments, the density and stress are dependent on the particular film being fabricated, but the films of one or more embodiments have similar or improved densities and stresses when compared to films fabricated at very high temperatures. The dielectric films fabricated according to embodiments described herein are amorphous and have higher etch selectivity, as well as very large density (e.g., > 1.8g/cc) and lower stress (< -500MPa) compared to existing patterned films. In general, the deposition processes described herein are also fully compatible with existing integration schemes for hard mask applications.

In some embodiments, the dielectric films described herein may be formed by a chemical vapor deposition (plasma enhanced and/or thermal) process using a precursor-containing gas mixture comprising one or more precursors selected from the group consisting of: silane (SiH)₄) Triethoxysilane (SiH (OEt)₃) Tetraethoxysilane (tetraethyl orthosilicate; si (OEt)₄Or TEOS), disilane (Si)₂H₆)、SiH(CH₃)₃Dimethylsilane (SiH)₂(CH₃)₂) Methylsilane (SiH)₃CH₃) Dichlorosilane (SiH)₂Cl₂) Silicon tetrachloride (SiCl)₄) Silicon tetrafluoride (SiF)₄) Trichlorosilane (HSiCl)₃) Methylsilane (CH)₃SiH₃) Trimethylsilane (C)₃H₁₀Si), 1,3, 3-Tetramethyldisiloxane (TMDZ), 1,3, 5-Trisilacyclopentane (TSP), (bis (tert-butylamino) silane (BTBAS), (bis (diethylamino) silane (BDEAS), tris (dimethylamino) silane (TDMAS), (Si [ n (tbu) CH ═ chn (tbu))](OEt)₂(Si-TBES)、Si[N(tBu)CH＝CHN(tBu)](H)NH₂(Si-TBAS), germane (GeH)₄) Germanium tetrachloride (GeCl)₄) Germanium tetrafluoride (GeF)₄) Tert-butylgermane (GeH (CH)₃)₃)、N₂O、O₂、NH₃、N₂、H₂、C₂H₂Or C₃H₆。

The deposition process may be performed at a temperature varying from about-50 ℃ to about 150 ℃, including about-50 ℃, about-45 ℃, about-40 ℃, about-35 ℃, about-30 ℃, about-25 ℃, about-20 ℃, about-15 ℃, about-10 ℃, about-5 ℃, about 0 ℃, about 5 ℃, about 10 ℃, about 15 ℃, about 20 ℃, about 25 ℃, about 30 ℃, about 35 ℃, about 40 ℃, about 45 ℃, about 50 ℃, about 55 ℃, about 60 ℃, about 65 ℃, about 70 ℃, about 75 ℃, about 80 ℃, about 85 ℃, about 90 ℃, about 95 ℃, about 100 ℃, about 105 ℃, about 110 ℃, about 115 ℃, about 120 ℃, about 125 ℃, about 130 ℃, about 135 ℃, about 140 ℃, about 145 ℃, and about 150 ℃.

The deposition process can be performed in a process volume at a pressure ranging from 0.1mTorr to 10Torr, including pressures of about 0.1mTorr, about 1mTorr, about 10mTorr, about 100mTorr, about 500mTorr, about 1Torr, about 2Torr, about 3Torr, about 4Torr, about 5Torr, about 6Torr, about 7Torr, about 8Torr, about 9Torr, and about 10 Torr.

The precursor-containing gas mixture may further comprise one or more diluent gases selected from the group consisting of: helium (He), argon (Ar), xenon (Xe), nitrogen (N)₂) Or hydrogen (H)₂). The diluent gas of some embodiments comprises a compound that is an inert gas with respect to the reactants and substrate materials.

The gas mixture containing the precursor may further include an etchant gas, such as Cl, for improving film quality₂、CF₄Or NF₃。

Plasmas (e.g., capacitively coupled plasmas) can be formed from top and bottom electrodes or side electrodes. The electrodes may be formed from a single powered electrode, dual powered electrodes, or more electrodes having multiple frequencies (such as, but not limited to, 350KHz, 2MHz, 13.56MHz, 27MHz, 40MHz, 60MHz, and 100MHz) used alternately or simultaneously in a CVD system having any or all of the reactant gases listed herein to deposit a thin film of dielectric. In some embodiments, the plasma is a Capacitively Coupled Plasma (CCP). In some embodiments, the plasma is an Inductively Coupled Plasma (ICP). In some embodiments, the plasma is a microwave plasma.

In some embodiments, the dielectric film is deposited in a chamber having a substrate pedestal maintained at 10 ℃ and a pressure maintained at 2mTorr, with a plasma generated at the wafer level by applying a bias of 2500 watts (13.56MHz) to the electrostatic chuck (i.e., direct plasma). In some embodiments, 1000 watts of additional RF power at 2MHz is also delivered to the electrostatic chuck, generating a dual-bias plasma at the wafer level.

Fig. 1A depicts a schematic illustration of a substrate processing system 132 that may be used to perform dielectric film deposition according to embodiments described herein. The substrate processing system 132 includes a process chamber 100 coupled to a gas panel 130 and a controller 110. The process chamber 100 generally includes a top wall 124, sidewalls 101, and a bottom wall 122 defining a processing volume 126. A substrate support assembly 146 is provided in the processing volume 126 of the process chamber 100. The substrate support assembly 146 generally includes an electrostatic chuck 150 supported by a stem 160. The electrostatic chuck 150 may typically be fabricated from aluminum, ceramic, or other suitable materials. The electrostatic chuck 150 may be moved in a vertical direction inside the process chamber 100 using a displacement mechanism (not shown).

A vacuum pump 102 is coupled to a port formed in the bottom of the process chamber 100. The vacuum pump 102 is used to maintain a desired gas pressure in the process chamber 100. The vacuum pump 102 also evacuates the processed gases and process byproducts from the process chamber 100.

The substrate processing system 132 may further include additional equipment for controlling the chamber pressure, such as valves (e.g., throttle and isolation valves) positioned between the process chamber 100 and the vacuum pump 102 to control the chamber pressure.

A gas distribution assembly 120 having a plurality of holes 128 is disposed on the top of the process chamber 100 above the electrostatic chuck 150. The holes 128 of the gas distribution assembly 120 are used to introduce process gases into the process chamber 100. The holes 128 may have different sizes, numbers, distributions, shapes, designs, and diameters to facilitate the flow of various process gases for different process requirements. The gas distribution assembly 120 is connected to a gas panel 130, which gas panel 130 allows various gases to be supplied to the process volume 126 during processing. A plasma is formed from the process gas mixture exiting the gas distribution assembly 120 to enhance thermal decomposition of the process gas, resulting in deposition of material on the surface 191 of the substrate 190.

The gas distribution assembly 120 and the electrostatic chuck 150 may form a pair of spaced apart electrodes in the processing volume 126. One or more RF power supplies 140 provide a bias potential to the gas distribution assembly 120 via an optional matching network 138 to facilitate generation of a plasma between the gas distribution assembly 120 and the electrostatic chuck 150. Alternatively, the RF power source 140 and optional matching network 138 may be coupled to the gas distribution assembly 120, the electrostatic chuck 150, or to both the gas distribution assembly 120 and the electrostatic chuck 150, or to an antenna (not shown) disposed outside the process chamber 100. In some embodiments, the RF power source 140 can generate power at a frequency of 350KHz, 2MHz, 13.56MHz, 27MHz, 40MHz, 60MHz, or 100 MHz. In one embodiment, between about 100 watts and about 3000 watts of RF power 140 may be provided at a frequency of about 50kHz to about 13.56 MHz. In another embodiment, the RF power source 140 may be provided at a frequency of about 50kHz to about 13.56MHz at between about 500 watts and about 1800 watts.

The controller 110 includes a Central Processing Unit (CPU)112, memory 116, and support circuits 114 for controlling process sequences and regulating gas flow from the gas panel 130. The Central Processing Unit (CPU)112 may be any form of a general purpose computer processor that can be used in an industrial environment. Software routines may be stored in the memory 116, such as random access memory, read only memory, floppy or hard disk drive, or other form of digital storage. The support circuits 114 are conventionally coupled to a Central Processing Unit (CPU)112 and may include cache, clock circuits, input/output systems, power supplies, and the like. Bidirectional communication between the controller 110 and the various components of the substrate processing system 132 is handled via several signal cables, collectively referred to as the signal bus 118, some of which are shown in fig. 1A.

Fig. 1B depicts a schematic cross-sectional view of another substrate processing system 180 that may be used to practice embodiments described herein. The substrate processing system 180 is similar to the substrate processing system 132 of fig. 1A, except that the substrate processing system 180 is configured to flow process gas from the gas panel 130 across the surface 191 of the substrate 190 via the sidewall 101. Further, the gas distribution assembly 120 depicted in FIG. 1A is replaced with an electrode 182. The electrode 182 may be configured for secondary electron generation. In one embodiment, electrode 182 is a silicon-containing electrode.

Fig. 2 depicts a schematic cross-sectional view of a substrate support assembly 146 used in the processing system of fig. 1A and 1B that may be used to practice embodiments described herein. Referring to fig. 2, the electrostatic chuck 150 may includeAn embedded heater element 170 adapted to control the temperature of a substrate 190 supported on an upper surface 192 of the electrostatic chuck 150. The electrostatic chuck 150 may be resistively heated by applying a current from the heater power supply 106 to the heater element 170. Heater power supply 106 may be coupled via RF filter 216. RF filter 216 may be used to protect heater power supply 106 from RF energy. The heater element 170 may be formed from a nickel-iron-chromium alloy (e.g.,) The nickel-chromium wire encapsulated in the sheath tube. The current supplied from the heater power supply 106 is regulated by the controller 110 to control the heat generated by the heater element 170 to maintain the substrate 190 and the electrostatic chuck 150 at a substantially constant temperature during film deposition. The supplied current may be adjusted to selectively control the temperature of the electrostatic chuck 150 between about-50 ℃ to about 150 ℃.

Referring to fig. 1A and 1B, a temperature sensor 172, such as a thermocouple, may be embedded in the electrostatic chuck 150 to monitor the temperature of the electrostatic chuck 150 in a conventional manner. The measured temperature is used by the controller 110 to control the power supplied to the heater element 170 to maintain the substrate at a desired temperature.

Referring to fig. 2, the electrostatic chuck 150 includes a chucking electrode 210, and the chucking electrode 210 may be a mesh of a conductive material. The chucking electrode 210 may be embedded in the electrostatic chuck 150. The chucking electrode 210 is coupled to a chucking power supply 212, which, when energized, the chucking power supply 212 electrostatically chucks the substrate 190 to the upper surface 192 of the electrostatic chuck 150.

The chucking electrode 210 may be configured as a monopolar electrode or a bipolar electrode, or have another suitable arrangement. The chucking electrode 210 may be coupled to a chucking power supply 212 via an RF filter 214, the chucking power supply 212 providing Direct Current (DC) power to electrostatically clamp the substrate 190 to the upper surface 192 of the electrostatic chuck 150. The RF filter 214 prevents RF power used to form plasma within the process chamber 100 from damaging electrical equipment or presenting an electrical hazard outside the chamber. The electrostatic chuck 150 may be made of a ceramic material, such as AlN or Al₂O₃. Alternatively, the electrostatic chuck 150 may be made of a polymer, such as polyimideAmines, Polyetheretherketones (PEEK), Polyaryletherketones (PAEK), and the like.

The power application system 220 is coupled to the substrate support assembly 146. Power application system 220 may include heater power supply 106, chucking power supply 212, first Radio Frequency (RF) power supply 230, and second RF power supply 240. Embodiments of the power application system 220 may additionally include a controller 110, and a sensor device 250 in communication with both the controller 110 and the first and second Radio Frequency (RF) power supplies 230, 240.

The controller 110 may also be used to control the plasma from the process gas by applying RF power from a first Radio Frequency (RF) power supply 230 and a second RF power supply 240 in order to deposit a material layer on the substrate 190.

As described above, the electrostatic chuck 150 includes a chucking electrode 210, which chucking electrode 210 may be used in one aspect to chuck the substrate 190 while also serving as the first RF electrode. The electrostatic chuck 150 can also include a second RF electrode 260 and, along with the chucking electrode 210, RF power can be applied to tune the plasma. A first Radio Frequency (RF) power source 230 may be coupled to the second RF electrode 260 and a second RF power source 240 may be coupled to the chucking electrode 210. A first matching network and a second matching network may be provided for the first Radio Frequency (RF) power supply 230 and the second RF power supply 240, respectively. The second RF electrode 260 may be a solid metal plate of conductive material as shown. Alternatively, second RF electrode 260 can be a mesh of conductive material.

The first Radio Frequency (RF) power supply 230 and the second RF power supply 240 may generate power at the same frequency or at different frequencies. In some embodiments, one or both of the first Radio Frequency (RF) power supply 230 and the second RF power supply 240 can independently generate power at a frequency in the range of about 350KHz to about 100MHz (including, but not limited to, 350KHz, 2MHz, 13.56MHz, 27MHz, 40MHz, 60MHz, or 100 MHz). In some embodiments, the first Radio Frequency (RF) power supply 230 may generate power at a frequency of 13.56MHz and the second RF power supply 240 may generate power at a frequency of 2MHz, or vice versa. The RF power from one or both of the first Radio Frequency (RF) power supply 230 and the second RF power supply 240 may be varied in order to tune the plasma. For example, the sensor device 250 may be used to monitor the Radio Frequency (RF) energy from one or both of the first RF power supply 230 and the second RF power supply 230. Data from the sensor device 250 can be communicated to the controller 110, and the controller 110 can be used to vary the power applied by the first Radio Frequency (RF) power supply 230 and the second RF power supply 240.

In general, the following exemplary deposition process parameters may be used to form the as-deposited dielectric film. The wafer temperature may vary from about-50 ℃ to about 150 ℃, including but not limited to from about 10 ℃ to about 100 ℃, or from about 10 ℃ to about 50 ℃. The chamber pressure may vary from a chamber pressure in the range of about 0.1mTorr to about 10Torr, including but not limited to from about 2mTorr to about 50mTorr, or from about 2mTorr to about 10 mTorr. The flow rate of the gas mixture containing the precursor may range from about 10sccm to about 1000sccm, including but not limited to from about 100sccm to about 200sccm, or from about 150sccm to about 200 sccm. The flow rate of the dilution gas can independently vary from about 50sccm to about 50000sccm, including but not limited to from about 50sccm to about 1000sccm, or from about 50sccm to about 100 sccm.

The dielectric film may be deposited to a thickness of aboutTo aboutA thickness in the range of, including aboutTo aboutIn the range ofTo aboutA range of, or aboutTo about The range of (1).

The deposited dielectric film may have a refractive index or n value (n (at 633 nm)) greater than about 1.5, for example, about 1.6 to about 3.0, including about 1.5, about 1.6, about 1.7, about 1.8, about 1.9, about 2.0, about 2.1, about 2.2, about 2.3, about 2.4, about 2.5, about 2.6, about 2.7, about 2.8, about 2.9, or about 3.0. In one or more embodiments, the film is silicon oxide and the refractive index is about 1.5. In yet another embodiment, the film is silicon nitride and the refractive index is about 1.9 to about 2.0. The method of one or more embodiments advantageously enables the manufacture of high quality films and low temperatures that have similar properties or are improved over films prepared by high temperature CVD or high temperature PECVD. The deposited dielectric film may have an extinction coefficient or k-value (k (at 633 nm)) greater than 0.1, for example, from about 0.2 to about 0.3, including about 0.2, about 0.21, about 0.22, about 0.23, about 0.24, about 0.25, about 0.26, about 0.27, about 0.28, about 0.29, about 0.30. The deposited dielectric film can have a stress (MPa) of less than about-300 MPa, for example, from about-600 MPa to about-300 MPa, from about-600 MPa to about-500 MPa, including about-600 MPa, about-575 MPa, about-550 MPa, about-525 MPa, about-500 MPa, about-475 MPa, about-450 MPa, about-425 MPa, about-400 MPa, about-375 MPa, about-350 MPa, about-325 MPa, or about-300 MPa.

In one or more embodiments, the dielectric film has a density greater than 1.8g/cc, including greater than 1.9g/cc, and including greater than 2.0 g/cc. In one or more embodiments, the dielectric film has a density of about 2.1 g/cc. In one or more embodiments, the dielectric film has a density in a range from about greater than 1.8g/cc to about 2.2 g/cc. In one or more embodiments, the dielectric film has a density greater than about 2.2 g/cc.

Another advantage of the method of one or more embodiments is that a lower temperature process can be used to produce dielectric films having a desired density and transparency. In general, higher substrate temperatures during deposition are process parameters used to facilitate the formation of higher density films. When the precursors and methods of one or more embodiments are used together, surprisingly the substrate temperature can be reduced during deposition, e.g., as low as about less than-40 ℃, and less than about 0 ℃, less than about 10 ℃, less than about room temperature, or less than about 22 ℃ to about 26 ℃, and still produce films of the desired density, i.e., dielectric films having a density greater than about 1.8g/cc, including greater than about 1.9g/cc, and including greater than about 2.0 g/cc. Thus, the methods of one or more embodiments may produce relatively high density films, particularly high density carbon films, with absorption coefficients as low as about 0.04.

Fig. 3 depicts a flow diagram of a method 300 for forming a dielectric film on a film stack disposed on a substrate according to one embodiment of the present disclosure. For example, a dielectric film formed on a film stack may be used as an insulating layer in the film stack.

Fig. 4A-4B show schematic cross-sectional views of a sequence for forming a dielectric film on a film stack disposed on a substrate, according to method 300. Although the method 300 is described below with reference to a dielectric layer that may be formed on a film stack for fabricating stair-like structures in the film stack for use in three-dimensional semiconductor devices, the method 300 may also be used to advantage in other device fabrication applications. Additionally, it should also be understood that the operations depicted in fig. 3 may be performed concurrently and/or in a different order than depicted in fig. 3.

The method 300 begins with operation 310: a substrate, such as substrate 400 depicted in fig. 4A, is positioned into a process chamber, such as process chamber 100 depicted in fig. 1A or 1B. The substrate 400 may be the substrate 190 depicted in fig. 1A, 1B, and 2. The substrate 400 may be positioned on an electrostatic chuck (e.g., the upper surface 192 of the electrostatic chuck 150). The substrate 400 may be a silicon-based material having a film stack 404 disposed on the substrate 400 or any suitable insulating or conductive material as desired, the substrate 400 may be used to form a structure 402, such as a stair-like structure, in the film stack 404.

As illustrated in the exemplary embodiment depicted in fig. 4A, the substrate 400 may have a substantially planar surface, a non-uniform surface, or a substantially planar surface with structures formed thereon. A film stack 404 is formed on the substrate 400. In one embodiment, the film stack 404 may be used to form a gate structure, a contact structure, or an interconnect structure in a front-end process or a back-end process. The method 300 may be performed on a film stack 404 to form a staircase-like structure therein for use in a memory structure, such as a NAND structure. In one embodiment, the substrate 400 may be a material such as crystalline silicon (e.g., Si (100) or Si (111)), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon substrates, and patterned or unpatterned substrates silicon-on-insulator (SOI), carbon doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire. The substrate 400 may have various sizes, such as 200mm, 300mm, and 450mm, or other diameter substrates, as well as rectangular or square panels. Unless otherwise mentioned, the embodiments and examples described herein are performed on a substrate having a 200mm diameter, a 300mm diameter, or a 450mm diameter substrate. In embodiments where an SOI structure is used for substrate 400, substrate 400 may include a buried dielectric layer disposed on a silicon crystalline substrate. In the embodiments depicted herein, the substrate 400 may be a crystalline silicon substrate.

In one embodiment, the film stack 404 disposed on the substrate 400 may have several vertically stacked layers. The film stack 404 may include pairs including a first layer (shown as 408) repeatedly formed in the film stack 404_a1、408_a2、408_a3、……、408_an) And a second layer (shown as 408)_b1、408_b2、408_b3、……、408_bn). The pairs include alternating first layers (shown at 408) that are repeatedly formed until a predetermined number of pairs of first and second layers are reached_a1、408_a2、408_a3、……、408_an) And a second layer (shown as 408)_b1、408_b2、408_b3、……、408_bn)。

The film stack 404 may be part of a semiconductor chip, such as a three-dimensional memory chip. Although the first layer (illustrated as 408) is illustrated in fig. 4A-4B_a1、408_a2、408_a3、……、408_an) Anda second layer (shown as 408)_b1、408_b2、408_b3、……、408_bn) Three repeating layers, but it is noted that any desired number of repeating pairs of first and second layers may be utilized as desired.

In one embodiment, the film stack 404 may be used to form a plurality of gate structures of a three-dimensional memory wafer. A first layer 408 formed in the film stack 404_a1、408_a2、408_a3、……、408_anCan be a first dielectric layer in accordance with one or more embodiments, and a second layer 408_b1、408_b2、408_b3、……、408_bnMay be a second dielectric layer in accordance with one or more embodiments. A suitable dielectric film according to one or more embodiments may be used to form the first layer 408_a1、408_a2、408_a3、……、408_anAnd/or second layer 408_b1、408_b2、408_b3、……、408_bnIncluding, but not limited to, one or more of the following: silicon, silicon nitride, silicon carbide, silicon oxide, silicon oxycarbide, silicon oxycarbonitride, silicon oxynitride, titanium nitride, or a composite of oxide and nitride (at least one or more oxide layers sandwiched between nitride layers), combinations thereof, and the like.

In some embodiments, the dielectric layer may be a high dielectric constant material having a dielectric constant greater than 4. Suitable examples of high dielectric constant materials include, but are not limited to, hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Hafnium silicon oxide (HfSiO)₂) Hafnium aluminum oxide (HfAlO), zirconium silicon oxide (ZrSiO)₂) Tantalum dioxide (TaO)₂) Aluminum oxide, aluminum-doped hafnium oxide, Bismuth Strontium Titanium (BST), and Platinum Zirconium Titanium (PZT), among others.

In one particular example, the first layer 408_a1、408_a2、408_a3、……、408_anIs a silicon oxide layer, and a second layer 408_b1、408_b2、408_b3、……、408_bnIs in the first layer 408_a1、408_a2、408_a3、……、408_anA silicon nitride layer or a polysilicon layer disposed thereon. In thatIn one embodiment, the first layer 408_a1、408_a2、408_a3、……、408_anCan be controlled to be aboutAnd aboutBetween, such as aboutAnd each second layer 408_b1、408_b2、408_b3、……、408_bnCan be controlled to be aboutAnd aboutBetween, such as about. The film stack 404 may have a thickness of aboutAnd aboutTo the total thickness of the layers. In one embodiment, the total thickness of the film stack 404 is about 3 microns to about 10 microns, and will vary as the technology progresses.

The dielectric film of one or more embodiments may be formed on any surface or any portion of the substrate 400, with or without the presence of the film stack 404 on the substrate 400.

At operation 320, a chucking voltage is applied to the electrostatic chuck to chuck the substrate 400 to the electrostatic chuck. In some embodiments in which the substrate 400 is positioned on the upper surface 192 of the electrostatic chuck 150, the upper surface 192 provides support and chucks the substrate 400 during processing. The electrostatic chuck 150 flattens the substrate 400 more tightly against the upper surface 192 to prevent backside deposition. An electrical bias is provided to the substrate 400 via the chucking electrode 210. Chucking electrode 210 may be in electronic communication with chucking power supply 212, chucking power supply 212 supplying a bias voltage to chucking electrode 210. In one embodiment, the chucking voltage is between about 10 volts and about 3000 volts. In one embodiment, the chucking voltage is between about 100 volts and about 2000 volts. In one embodiment, the chucking voltage is between about 200 volts and about 1000 volts.

During operation 320, several process parameters may be adjusted. In one embodiment suitable for processing 300mm substrates, the process pressure in the processing volume may be maintained at about 0.1mTorr to about 10Torr, including about 2mTorr to about 50mTorr, or about 5mTorr to about 20 mTorr. In one embodiment suitable for processing 300mm substrates, the processing temperature and/or substrate temperature may be maintained at about-50 ℃ to about 250 ℃, including about 0 ℃ to about 50 ℃; or from about 10 ℃ to about 20 ℃.

In one embodiment, a constant chucking voltage is applied to the substrate 400. In one embodiment, a chucking voltage may be pulsed to the electrostatic chuck 150. In some embodiments, a backside gas may be applied to the substrate 400 while a chucking voltage is applied to control the substrate temperature. The backside gas may include, but is not limited to, helium (He), argon (Ar), and the like.

At operation 330, a plasma is generated at the substrate level by applying a first RF bias to the electrostatic chuck. The plasma generated at the substrate level may be generated in a plasma region between the substrate and the electrostatic chuck. The first RF bias can be from about 10 watts and about 3000 watts at a frequency in the range from about 350KHz to about 100MHz, including but not limited to 350KHz, 2MHz, 13.56MHz, 27MHz, 40MHz, 60MHz, or 100 MHz. In one embodiment, the first RF bias is provided at a frequency of about 13.56MHz at a power between about 2500 watts and about 3000 watts. In one embodiment, the first RF bias is provided to the electrostatic chuck 150 via the second RF electrode 260. Second RF electrode 260 can be in electronic communication with a first Radio Frequency (RF) power supply 230, first RF power supply 230 supplying a bias voltage to second RF electrode 260. In one embodiment, the bias power is between about 10 watts and about 3000 watts. In one embodiment, the bias power is between about 2000 watts and about 3000 watts. In one embodiment, the bias power is between about 2500 watts and about 3000 watts. The first Radio Frequency (RF) power supply 230 may generate power at a frequency in a range from about 350KHz to about 100MHz, including but not limited to 350KHz, 2MHz, 13.56MHz, 27MHz, 40MHz, 60MHz, or 100 MHz.

In some embodiments, operation 330 further comprises applying a second RF bias to the electrostatic chuck. The second RF bias can be from about 10 watts and about 3000 watts at a frequency in the range from about 350KHz to about 100MHz, including but not limited to 350KHz, 2MHz, 13.56MHz, 27MHz, 40MHz, 60MHz, or 100 MHz. In one embodiment, the second RF bias is provided at a frequency of about 2MHz at a power of between about 800 watts and about 1200 watts. In one embodiment, a second RF bias is provided to substrate 400 via chucking electrode 210. Chucking electrode 210 may be in electronic communication with a second RF power supply 240, with second RF power supply 240 supplying a bias voltage to chucking electrode 210. In one embodiment, the bias power is between about 10 watts and about 3000 watts. In one embodiment, the bias power is between about 500 watts and about 1500 watts. In one embodiment, the bias power is between about 800 watts and about 1200 watts. The second RF power supply 240 may generate power at a frequency in a range from about 350KHz to about 100MHz, including but not limited to 350KHz, 2MHz, 13.56MHz, 27MHz, 40MHz, 60MHz, or 100 MHz. In one embodiment, the chucking voltage supplied in operation 320 is maintained during operation 330.

In some embodiments, during operation 330, a first RF bias is provided to substrate 400 via chucking electrode 210 and a second RF bias may be provided to substrate 400 via second RF electrode 260. In one embodiment, the first RF bias is about 2500 watts (13.56MHz) and the second RF bias is about 1000 watts (2 MHz).

During operation 340, a gas mixture containing a precursor is flowed into the process volume 126 to form a dielectric film on the film stack. A gas mixture containing a precursor may flow from the gas panel 130 through the gas distribution assembly 120 or through the sidewall 101 into the processing volume 126. The gas mixture containing the precursors may include one or more precursors as described herein. The gas mixture containing the precursor may further include an inert gas, a diluent gas, a nitrogen-containing gas, an etchant gas, or combinations thereof. The precursor may be a liquid or a gas, although preferred precursors will be a vapor at room temperature to simplify the hardware required for material metering, control, and delivery to the chamber. In some embodiments, the chucking voltage supplied during operation 320 is maintained during operation 340. In some embodiments, the process conditions established during operation 320 and the plasma formed during operation 330 are maintained during operation 340.

In some embodiments, the gas mixture containing the precursor further comprises one or more diluent gases. If desired, a suitable diluent gas (such as helium (He), argon (Ar), xenon (Xe), hydrogen (H)₂) Nitrogen (N)₂) Ammonia (NH)₃) Or combinations thereof, etc.) to the gas mixture. Argon (Ar), helium (He) and nitrogen (N)₂) For controlling the density and deposition rate of the dielectric film. In some cases, as discussed below, N₂And/or NH₃Can be used to control the hydrogen ratio of the dielectric film. Alternatively, no diluent gas may be used during deposition.

In some embodiments, the gas mixture containing the precursor further comprises one or more nitrogen-containing gases. For example, suitable nitrogen-containing compounds include pyridine, fatty amines, nitriles, ammonia, and the like.

In some embodiments, the gas mixture containing the precursor further comprises an inert gas. In some embodiments, an inert gas, such as argon (Ar) and/or helium (He), may be supplied into the process volume 126 along with a gas mixture containing a precursor. Other inert gases (such as nitrogen (N)₂) And Nitric Oxide (NO)) may also be used to control the density and deposition rate of the dielectric film. In addition, various other process gases may be added to the gas mixture containing the precursor to modify the properties of the dielectric film material. In one embodiment, the other process gas may be a reactive gas, such as hydrogen (H)₂) Ammonia (NH)₃) Hydrogen (H)₂) With nitrogen (N)₂) Mixtures of (a) or combinations thereof. Addition of H₂And/or NH₃Can be used to control the hydrogen ratio of the deposited dielectric film. The ratio of hydrogen present in the dielectric film provides control over layer properties, such as reflectivity.

In some embodiments, the gas mixture containing the precursor further comprises an etchant gas. Suitable etchant gases include chlorine (Cl)₂) Carbon tetrafluoride (CF)₄) Nitrogen trifluoride (NF)₃) Or a combination thereof.

In some embodiments, after forming the dielectric film 412 on the substrate during operation 340, the dielectric film 412 is exposed to hydrogen radicals. In some embodiments, dielectric film 412 is exposed to hydrogen radicals during the deposition process of operation 340. In some embodiments, hydrogen radicals are formed in the RPS and delivered to the treatment region.

In operation 350, after the dielectric film 412 is formed on the substrate, the substrate is dechucked. During operation 350, the chucking voltage is turned off. The reactive gas is turned off and optionally purged from the process chamber. In one embodiment, during operation 350, the RF power is reduced (e.g., -200W). Optionally, the controller 110 monitors the impedance change to determine whether the electrostatic charge is dissipated to ground via the RF path. Once the substrate is de-chucked from the electrostatic chuck, the remaining gas is purged from the process chamber. The process chamber is evacuated and the substrate is moved up the lift pins and transferred out of the chamber.

After forming the dielectric film 412 on the substrate, the dielectric film 412 may be used as a patterned mask in an etching process to form a three-dimensional structure, such as a staircase-like structure. The dielectric film 412 may be patterned using standard photoresist patterning techniques. A patterned photoresist (not shown) may be formed over dielectric film 412. The dielectric film 412 may be etched in a pattern corresponding to the patterned photoresist layer, which is then etched into the substrate 400. Material may be deposited into the etched portions of the dielectric film 412. The dielectric film 412 may be removed using a solution including hydrogen peroxide and sulfuric acid. An exemplary solution comprising hydrogen peroxide and sulfuric acid is known as a Piranha solution or Piranha etchant. The dielectric film 412 may also be etched using an etching chemistry containing oxygen and a halogen including, but not limited to, chlorine (Cl), fluorine (F), iodine (I), bromine (Br), and astatine (At)And (5) removing the substances. For example, the dielectric film 412 may contain Cl₂/O₂、CF₄/O₂Or Cl₂/O₂/CF₄The etch chemistry of (1) is removed. The dielectric film 412 may be removed by a Chemical Mechanical Polishing (CMP) process.

The process may be generally stored in memory as software routines that, when executed by a processor, cause the process chamber to perform the processes of the present disclosure. The software routines may also be stored and/or executed by a second processor (not shown) that is remotely located from the hardware being controlled by the processor. Some or all of the methods of the present disclosure may also be performed in hardware. Thus, the processes may be implemented in software and performed in hardware using a computer system, for example, as an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. When executed by the processor, the software routines convert the general purpose computer into a special purpose computer (controller) that controls the chamber operation such that the process is performed.

The present disclosure is now described with reference to the following examples. Before describing several exemplary embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The disclosure is capable of other embodiments and of being practiced or of being carried out in various ways.

Examples of the invention

Example 1

A low temperature, high quality silicon nitride dielectric film is produced by the steps of: flowing 30sccm SiH at a temperature of 100 ℃ and a pressure of 400mTorr₄、100sccm NH₃And N₂As process gases, 200 watts RF (13.56MHz) power was applied through the substrate pedestal (electrostatic chuck) in a CVD reactor with ar (g) and he (g) as diluent gases. The resulting dielectric film had a Refractive Index (RI) (633nm) of 1.82, which is much higher than a dielectric film formed by PECVD at the same temperature. RI is improved by adjusting power (higher) and voltage (lower). The primary and secondary RF can be any combination of 350KHz, 2MHz, 13.56MHz, 27MHz, 40MHz, 60MHz, and 100 MHz.

The use of the terms "a" and "an" and "the" and similar references in the context of describing the materials and methods discussed herein, especially in the context of the following claims, is to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., "such as") provided herein, is intended merely to better illuminate the materials and methods and does not pose a limitation on the scope unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

Reference throughout this specification to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases such as "in one or more embodiments," "in certain embodiments," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

Although the disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made in the method and apparatus of the present disclosure without departing from the spirit and scope of the disclosure. Thus, it is intended that the present disclosure encompass such modifications and changes as fall within the scope of the appended claims and equivalents thereof.