阅读说明：本技术 一种电压动态调节的方法、装置、设备和介质 (Method, device, equipment and medium for dynamically adjusting voltage ) 是由 金建广 姜开永 于 2020-06-24 设计创作，主要内容包括：本发明公开了一种电压动态调节的方法,包括：响应于开机而将CPLD上电,并通过CPLD控制电源芯片对交换芯片上电；通过CPLD检测交换芯片输出的AVS值,并过滤掉无效的AVS值；将过滤后的AVS值转化为符合PMBUS的规范要求的寄存器值,并通过PMBUS将寄存器值传输到电源芯片中控制输出电压值的寄存器,寄存器根据寄存器值获取电源芯片对交换芯片的输出电压；通过CPLD控制延时预设时间后将对交换芯片输出的复位信号配置为高电平以对交换芯片执行输出电压。本发明还公开了一种装置、设备和介质。本发明可以通过CPLD来动态调节core的电压来控制电源芯片输出电压,使交换芯片的功耗降低。(The invention discloses a method for dynamically adjusting voltage, which comprises the following steps: powering on the CPLD in response to starting up, and controlling the power chip to power on the exchange chip through the CPLD; the AVS value output by the exchange chip is detected through the CPLD, and invalid AVS values are filtered; converting the filtered AVS value into a register value meeting the standard requirement of a PMBUS, transmitting the register value to a register for controlling an output voltage value in the power chip through the PMBUS, and acquiring the output voltage of the power chip to the exchange chip by the register according to the register value; and after the CPLD is controlled to delay the preset time, the reset signal output to the exchange chip is configured to be at a high level so as to output voltage to the exchange chip. The invention also discloses a device, equipment and a medium. The invention can dynamically adjust the voltage of the core through the CPLD to control the output voltage of the power chip, so that the power consumption of the exchange chip is reduced.)

1. A method of dynamic voltage regulation, the method comprising:

powering on the CPLD in response to starting up, and controlling a power supply chip to power on the exchange chip through the CPLD;

detecting the AVS value output by the exchange chip through the CPLD, and filtering out invalid AVS values;

converting the filtered AVS value into a register value meeting the standard requirement of a PMBUS, transmitting the register value to a register for controlling an output voltage value in the power supply chip through the PMBUS, and acquiring the output voltage of the power supply chip to the exchange chip by the register according to the register value;

And after the CPLD is controlled to delay preset time, the reset signal output to the exchange chip is configured to be high level so as to execute the output voltage to the exchange chip.

2. The method of dynamic voltage adjustment of claim 1, further comprising:

and writing the AVS value into a main control module in the CPLD through a hardware description language, and converting the AVS value into the register value through the main control module.

3. The method according to claim 1, wherein the detecting, by the CPLD, the AVS value output by the switch chip and filtering out invalid AVS values further comprises:

and detecting a power supply preparation signal of the power supply chip to the output voltage of the exchange chip, and responding to the detection that the power supply preparation signal is output as powergood, and filtering the invalid AVS value by delaying preset filtering time.

4. The method of dynamic voltage adjustment of claim 1, further comprising:

and canceling the control of the PMBUS after delaying the preset time through the CPLD control.

5. An apparatus for dynamic voltage regulation, the apparatus comprising:

The power-on module is configured to power on the CPLD in response to starting up and control the power chip to power on the exchange chip through the CPLD;

the AVS value acquisition module is configured to detect the AVS value output by the switching chip through the CPLD and filter the invalid AVS value;

the output voltage acquisition module is configured to convert the filtered AVS value into a register value meeting the standard requirement of a PMBUS, transmit the register value to a register for controlling an output voltage value in the power chip through the PMBUS, and acquire the output voltage of the power chip to the switching chip according to the register value;

the output voltage execution module is configured to configure the reset signal output to the switch chip to be a high level after delaying for a preset time through the CPLD control so as to execute the output voltage to the switch chip.

6. The apparatus for voltage dynamics adjustment according to claim 5, further comprising:

the master control module writing module is configured to write the master control module in the CPLD through a hardware description language, and the AVS value is converted into the register value through the master control module.

7. The apparatus for voltage dynamic adjustment according to claim 5, wherein the AVS value obtaining module is further configured to:

and detecting a power supply preparation signal of the power supply chip to the output voltage of the exchange chip, and responding to the detection that the power supply preparation signal is output as powergood, and filtering the invalid AVS value by delaying preset filtering time.

8. The apparatus for voltage dynamics adjustment according to claim 5, further comprising:

the PMBUS control releasing module is configured to cancel control over the PMBUS after the CPLD controls to delay the preset time.

9. A computer device, comprising:

at least one processor; and

memory storing a computer program operable on the processor, wherein the processor, when executing the program, performs the method of any of claims 1-4.

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, is adapted to carry out the method of any one of claims 1 to 4.

Technical Field

The present invention relates to the field of hardware monitoring technologies, and in particular, to a method, an apparatus, a device, and a medium for dynamically adjusting a voltage.

Background

With the development of network communications, switches are the essential part of the network. At present, the bandwidth of the switch chip is larger and larger, and the frequency is higher and higher, which brings the problem of power consumption, and the smooth operation of the whole switch system is affected by the too high power consumption.

For the problem of how to reduce the power consumption of the switch, some manufacturers of the switch chips propose their own design methods for reducing the power consumption, and most of them reduce the power consumption of the switch chip by reducing the voltage.

At present, some switch manufacturers do not use the dynamic Voltage regulation function of the AVS (Adaptive Voltage Scaling) of the boston switch chip, and a Core power output chip is set to a fixed output value in the design process, which can help to reduce the power consumption of the equipment.

However, the Core voltage of the commissional switching chip is different from each chip when leaving factory, if the Core voltage is a lower limit value, the fixed value set by the switch manufacturer is higher than the actual value of the chip, and the current required by the switching chip is a fixed value, so that the total power consumption of the switch system is increased invisibly; if the fixed value set by the switch manufacturer is higher than the actual value of the chip, the chip may be damaged, and the service life of the switch is reduced; and the overall power consumption of the switch system increases, which increases the pressure on the overall heat dissipation, increases the noise of the fan, and the like.

Disclosure of Invention

In view of the above, an object of the embodiments of the present invention is to provide a method for controlling an output voltage of a power chip by dynamically adjusting a Core voltage through a CPLD (Complex programmable logic Device).

In view of the above object, the present invention provides a method for dynamically adjusting voltage, the method comprising:

powering on the CPLD in response to starting up, and controlling the power chip to power on the exchange chip through the CPLD;

the AVS value output by the exchange chip is detected through the CPLD, and invalid AVS values are filtered;

converting the filtered AVS value into a register value meeting the standard requirement of a PMBUS, transmitting the register value to a register for controlling an output voltage value in the power chip through the PMBUS, and acquiring the output voltage of the power chip to the exchange chip by the register according to the register value;

and after the CPLD is controlled to delay the preset time, the reset signal output to the exchange chip is configured to be at a high level so as to output voltage to the exchange chip.

In some embodiments of the method of dynamic voltage regulation of the present invention, the method further comprises:

and writing the AVS value into the master control module in the CPLD through a hardware description language, and converting the AVS value into a register value through the master control module.

In some embodiments of the method for dynamically adjusting voltage of the present invention, detecting the AVS value output by the switch chip through the CPLD, and filtering out invalid AVS values further includes:

and detecting a power supply preparation signal of the power supply chip to the output voltage of the exchange chip, and responding to the detection that the power supply preparation signal is output as powergood, and filtering invalid AVS values by delaying preset filtering time.

In some embodiments of the method of dynamic voltage regulation of the present invention, the method further comprises:

and the control on the PMBUS is cancelled after the CPLD is used for controlling the delay preset time.

In another aspect of the embodiments of the present invention, there is also provided a device for dynamically adjusting voltage, where the device includes:

the power-on module is configured to power on the CPLD in response to starting up and control the power chip to power on the exchange chip through the CPLD;

the AVS value acquisition module is configured to detect the AVS value output by the exchange chip through the CPLD and filter out invalid AVS values;

the output voltage acquisition module is configured to convert the filtered AVS value into a register value meeting the standard requirement of the PMBUS, transmit the register value to a register for controlling the output voltage value in the power chip through the PMBUS, and acquire the output voltage of the power chip to the exchange chip according to the register value;

And the output voltage execution module is configured to configure the reset signal output to the exchange chip into a high level after delaying the preset time through the control of the CPLD so as to execute the output voltage to the exchange chip.

In some embodiments of the voltage dynamics regulation apparatus of the present invention, the apparatus further comprises:

the main control module writing module is configured to write the main control module in the CPLD through a hardware description language, and the AVS value is converted into a register value through the main control module.

In some embodiments of the apparatus for dynamic voltage adjustment of the present invention, the AVS value obtaining module is further configured to:

and detecting a power supply preparation signal of the power supply chip to the output voltage of the exchange chip, and responding to the detection that the power supply preparation signal is output as powergood, and filtering invalid AVS values by delaying preset filtering time.

In some embodiments of the voltage dynamics regulation apparatus of the present invention, the apparatus further comprises:

and the PMBUS control releasing module is configured to cancel the control of the PMBUS after delaying the preset time through the control of the CPLD.

In another aspect of the embodiments of the present invention, there is also provided a computer device, including:

At least one processor; and

the memory stores a computer program capable of running on the processor, and the processor executes the program to execute the method for dynamically adjusting the voltage.

In another aspect of the embodiments of the present invention, a computer-readable storage medium is further provided, where a computer program is stored, and the computer program is executed by a processor to perform the foregoing method for dynamically adjusting voltage.

The invention has at least the following beneficial technical effects:

1. and dynamically adjusting the voltage value of the core of each switching chip to reduce the power consumption of the switching chip.

2. The power consumption of the exchange chip is reduced, the total power consumption of the exchanger system is reduced, the heat dissipation pressure is reduced, the rotating speed of the fan is reduced, and the noise is weakened.

3. The power consumption is reduced by dynamically adjusting the voltage of the core, the output power consumption pressure of the power supply control chip is reduced, the power consumption is reduced, and the service life of the machine is prolonged.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.

FIG. 1 shows a schematic block diagram of an embodiment of a method of dynamic voltage regulation according to the present invention;

FIG. 2 shows a schematic diagram of a system architecture of an embodiment of a method of dynamic voltage regulation according to the present invention;

fig. 3 shows a flow chart of an embodiment of a method of dynamic voltage adjustment according to the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it is understood that "first" and "second" are only used for convenience of description and should not be construed as limiting the embodiments of the present invention, and the descriptions thereof in the following embodiments are omitted.

In view of the above object, a first aspect of the embodiments of the present invention proposes an embodiment of a method for dynamic voltage adjustment. Fig. 1 shows a schematic block diagram of an embodiment of a method of dynamic voltage regulation according to the present invention. In the embodiment shown in fig. 1, the method comprises at least the following steps:

S100, responding to starting up, electrifying the CPLD, and controlling the power supply chip to electrify the exchange chip through the CPLD;

s200, detecting the AVS value output by the exchange chip through the CPLD, and filtering out invalid AVS values;

s300, converting the filtered AVS value into a register value meeting the standard requirement of a PMBUS, transmitting the register value to a register for controlling an output voltage value in the power chip through the PMBUS, and acquiring the output voltage of the power chip to the exchange chip by the register according to the register value;

and S400, configuring a reset signal output to the exchange chip into a high level to output voltage to the exchange chip after delaying the preset time through the CPLD control.

The CPLD adopts programming technologies such as CMOS EPROM, EEPROM, flash memory, SRAM and the like, thereby forming a programmable logic device with high density, high speed and low power consumption. In some embodiments of the present invention, fig. 2 is a schematic diagram illustrating a system structure of an embodiment of the method for dynamically adjusting voltage according to the present invention, and as shown in fig. 2, the CPLD is inserted into an AC (Alternating Current) overall machine to start to power up, the CPLD starts to power up, and the CPLD is the first power-up of the entire switch system. And then, the CPLD controls the switching chip to be powered on according to the time sequence, the reset signal output of the switching chip is low level, and the reset signal output is low, so that the switching chip is only powered on but is not controlled to perform other operations. The CPLD detects the AVS [7:0] value sent by the BOOTON exchange chip, filters the invalid AVS value and takes the valid AVS value. And the CPLD converts the detected effective 8-bit AVS value into a register value meeting the specification requirement of the corresponding PMBUS, and outputs the register value to a register of the power supply chip for correspondingly controlling the output voltage value. The CPLD delays for a period of time to wait for the power supply chip to be adjusted; and then the CPLD starts to perform reset on the Mactong switching chip.

According to some embodiments of the method of dynamic voltage adjustment of the present invention, the method further comprises:

and writing the AVS value into the master control module in the CPLD through a hardware description language, and converting the AVS value into a register value through the master control module.

In some embodiments of the present invention, a master module of the PMBUS is added in the CPLD, and the master module converts the AVS value that is effective after the filtering is completed into a register value that meets the specification requirement of the PMBUS.

According to some embodiments of the method for dynamically adjusting voltage of the present invention, detecting the AVS value output by the switch chip through the CPLD, and filtering out invalid AVS values further includes:

and detecting a power supply preparation signal of the power supply chip to the output voltage of the exchange chip, and responding to the detection that the power supply preparation signal is output as powergood, and filtering invalid AVS values by delaying preset filtering time.

In some embodiments of the present invention, the CPLD makes the register control Power chip output 0.8875V as the initial voltage of default output by PMBUS (Power Management Bus). And detecting whether the core displays the powergood information or not, and delaying the CPLD for 70ms until the core displays the powergood information so as to filter out invalid AVS values (the voltage output is the default output initial voltage value of 0.8875V).

According to some embodiments of the method of dynamic voltage adjustment of the present invention, the method further comprises:

and the control on the PMBUS is cancelled after the CPLD is used for controlling the delay preset time.

In some embodiments of the invention, the register value is output to a register of a power supply chip corresponding to a control voltage value, the power supply chip is controlled by the register to adjust the output voltage of the power supply, after the register value is output, the CPLD makes 30ms of delay, the PMBUS bus is idle, so that other masters (main control ends) can conveniently control the power supply, then RST (Reset, release) signals of the exchange chip are output, and the RST signals are output to high level for resetting.

In another aspect of the embodiments of the present invention, an embodiment of a device for dynamically adjusting voltage is provided.

The device includes:

the power-on module is configured to power on the CPLD in response to starting up and control the power chip to power on the exchange chip through the CPLD;

the AVS value acquisition module is configured to detect the AVS value output by the exchange chip through the CPLD and filter out invalid AVS values;

the output voltage acquisition module is configured to convert the filtered AVS value into a register value meeting the standard requirement of the PMBUS, transmit the register value to a register for controlling the output voltage value in the power chip through the PMBUS, and acquire the output voltage of the power chip to the exchange chip according to the register value;

And the output voltage execution module is configured to configure the reset signal output to the exchange chip into a high level after delaying the preset time through the control of the CPLD so as to execute the output voltage to the exchange chip.

According to some embodiments of the apparatus for dynamic voltage regulation of the present invention, the apparatus further comprises:

the main control module writing module is configured to write the main control module in the CPLD through a hardware description language, and the AVS value is converted into a register value through the main control module.

According to some embodiments of the apparatus for dynamic voltage adjustment of the present invention, the AVS value obtaining module is further configured to:

and detecting a power supply preparation signal of the power supply chip to the output voltage of the exchange chip, and responding to the detection that the power supply preparation signal is output as powergood, and filtering invalid AVS values by delaying preset filtering time.

According to some embodiments of the apparatus for dynamic voltage regulation of the present invention, the apparatus further comprises:

and the PMBUS control releasing module is configured to cancel the control of the PMBUS after delaying the preset time through the control of the CPLD.

In view of the above object, another aspect of the embodiments of the present invention further provides a computer device, including: at least one processor; and a memory storing a computer program operable on the processor, the processor executing the program to perform the aforementioned method of voltage dynamic adjustment.

In another aspect of the embodiments of the present invention, a computer-readable storage medium is further provided, where a computer program is stored, and the computer program is executed by a processor to perform the foregoing method for dynamically adjusting voltage.

Likewise, it will be appreciated by a person skilled in the art that all embodiments, features and advantages set forth above for the method of dynamic voltage regulation according to the present invention apply equally well to the device, the computer apparatus and the medium according to the present invention. For the sake of brevity of the present disclosure, no repeated explanation is provided herein.

It should be particularly noted that the steps in the embodiments of the method, apparatus, device and medium for voltage dynamic adjustment described above can be mutually intersected, replaced, added and deleted, so that these methods, apparatus, devices and media for voltage dynamic adjustment, which are reasonably transformed by permutation and combination, should also belong to the scope of the present invention, and should not limit the scope of the present invention to the embodiments.

Finally, it should be noted that, as one of ordinary skill in the art can appreciate that all or part of the processes of the methods of the above embodiments can be implemented by a computer program to instruct related hardware, and the program of the method for dynamically adjusting voltage can be stored in a computer readable storage medium, and when executed, the program can include the processes of the embodiments of the methods as described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.

Furthermore, the methods disclosed according to embodiments of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. Which when executed by a processor performs the above-described functions defined in the methods disclosed in embodiments of the invention.

Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.

Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.

The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.

The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.