阅读说明：本技术 用于识别电路缺陷并用于避免调节器中的过电压的电路 (Circuit for identifying circuit defects and for avoiding overvoltages in a regulator ) 是由 H·巴拉苏布拉马尼亚姆 于 2018-11-23 设计创作，主要内容包括：描述一种用于识别电路缺陷和/或用于避免调节器中的过电压的电路,该电路包括功率调节器电路和过电压抑制电路,该功率调节器电路具有第一晶体管(MOS<Sub>PWR</Sub>)、包括运算放大器(OTA<Sub>PWR</Sub>)以及第一参考电压源(V<Sub>REF1</Sub>)的调节环路和反馈电阻(R<Sub>1</Sub>、R<Sub>2</Sub>、R<Sub>3</Sub>),该过电压抑制电路具有第二晶体管(MOS<Sub>PROT</Sub>)、包括运算放大器(OTA<Sub>PROT</Sub>)以及参考电压源(V<Sub>RFF2</Sub>)的调节环路和反馈电阻(R<Sub>4</Sub>、R<Sub>5</Sub>、R<Sub>6</Sub>),其中,功率调节器电路设置为用于为过电压抑制电路提供电压(V<Sub>DD_PWR</Sub>),过电压抑制电路设置为用于提供受保护的电压(V<Sub>DD_PROT</Sub>)。(A circuit for identifying circuit defects and/or for avoiding overvoltages in a regulator is described, the circuit comprising a power regulator circuit having a first transistor (MOS) and an overvoltage suppression circuit PWR ) Comprising an operational amplifier (OTA) PWR ) And a first reference voltage source (V) REF1 ) Regulation loop and feedback resistance (R) 1 、R 2 、R 3 ) The overvoltage suppression circuit has a second transistor (MOS) PROT ) Comprising an operational amplifier (OTA) PROT ) Andreference voltage source (V) RFF2 ) Regulation loop and feedback resistance (R) 4 、R 5 、R 6 ) Wherein the power regulator circuit is arranged to provide a voltage (V) to the overvoltage suppression circuit DD_PWR ) The overvoltage suppression circuit is arranged to provide a protected voltage (V) DD_PROT )。)

1. A circuit for identifying circuit defects and/or for avoiding overvoltages in a regulator, the circuit comprising:

-a power regulator circuit having a first transistor (MOS)_PWR) Comprising an operational amplifier (OTA)_PWR) And a first reference voltage source (V)_REF1) Regulation loop, feedback resistance (R)₁，R₂，R₃)；

-an overvoltage suppression circuit having a second transistor (MOS)_PROT) Comprising an operational amplifier (OTA)_PROT) And a reference voltage source (V)_REF2) Regulation loop, feedback resistance (R)₄，R₅，R₆)；

Wherein the power regulator circuit is arranged to provide a voltage (V) to the overvoltage suppression circuit_{DD_PWR}) The overvoltage suppression circuit is arranged to provide a protected voltage (V)_{DD_PROT})。

2. The circuit of claim 1, further comprising a third transistor (MOS)_OV) A gate connecting terminal of the third transistor and the second transistor (MOS)_PROT) And the third transistor is arranged to confine the third transistor (MOS)_OV) The source connection terminal of (a).

3. The circuit of claim 2, wherein at the second stageThree transistors (MOS)_OV) The source electrode connecting end is connected with a first Comparator (COMP)_OV) The first comparator being arranged for passing a limited voltage (V)_OV) And the second reference voltage source (V)_REF2) Are compared to detect overvoltages.

4. A circuit according to claim 3, wherein said first Comparator (COMP) arranged to detect an overvoltage_OV) Is arranged to output a binary value (FLAG) representing an overvoltage_OV)。

5. Circuit according to any of claims 1 to 4, further comprising a second Comparator (COMP) for comparing the first and second signals_UV) A circuit for detecting an undervoltage of said power regulator, said second comparator being coupled to said second reference voltage source (V)_REF2) With a protected voltage (V) provided by_{DD_PROT}) The voltage (V) thus obtained_UV) A comparison is made.

6. Circuit according to claim 5, wherein said second Comparator (COMP) arranged for detecting under-voltage_UV) Is arranged to output a binary value (FLAG) representing an under-voltage_UV)。

7. Circuit according to any of claims 1 to 4, further comprising means for comparing by means of two Comparators (COMP) _UV1，COMP_UV2) A circuit for detecting an undervoltage of the power regulator, wherein provision is made for the first reference voltage source or the second reference voltage source (Vref)_REF1，V_REF2) And a protected voltage (V) provided by means of said voltage_{DD_PROT}) The voltage (V) thus obtained_UV) A comparison is made.

8. Circuit according to claim 7, wherein said two Comparators (COMP)_UV1，COMP_UV2) Is arranged to useAt the output of a binary value (FLAG) representing the undervoltage_UV1，FLAG_UV2)。

9. Circuit according to claim 8, wherein a logical AND gate (AND) is provided for the binary value (FLAG) that will reflect the under-voltage_UV1，FLAG_UV2) And (4) associating.

10. Circuit according to any of claims 1 to 4, further comprising a circuit for detecting defects in the reference source causing over-voltage of the power regulator or under-voltage of the protection regulator, comprising an under-voltage identification Comparator (COMP) with a switchable reference source_UV)。

11. The circuit according to any of claims 1 to 10, further comprising a digital part (DT) at which the protected voltage (V) is provided_{DD_PROT})。

12. Circuit according to claim 11, wherein the digital part (DT) has a receiver for receiving a binary value (FLAG) _oV，FLAG_UV) And for transmitting binary values (BIST)_PWR，BIST_oV，EN_LOAD，EN₁，EN₂，EN₃) To the output terminal of (a).

13. The circuit according to any of claims 1 to 12, wherein the external battery voltage (V) is used_BATT) To the first reference voltage source (V)_REF1) The second reference voltage source (V)_REF2) The power regulator circuit and the overvoltage suppression circuit supply power.

Technical Field

The invention relates to a circuit for identifying circuit defects and/or for avoiding overvoltages in a regulator, comprising a power regulator circuit and an overvoltage suppression circuit, wherein the power regulator circuit is provided for supplying a voltage to the overvoltage suppression circuit, and the overvoltage suppression circuit is provided for supplying a protected voltage.

Background

Different methods are known from the prior art, by means of which overvoltages in the circuit can be detected.

For example, US 7,576,964B 2 discloses an overvoltage protection circuit for MOS transistors and switching circuits of consumers, which are connected in series between a first current supply means and a second current supply means. The overvoltage protection circuit comprises a control signal circuit, a dynamic clamping circuit, a control switch and an overvoltage detection circuit.

Furthermore, an overvoltage protection circuit is known from US 9,007,737B 2, which comprises a resistor divider, a reference voltage supply unit, a comparator and an inverter, wherein the inverter comprises a series-parallel combination of first to third semiconductor switching elements which are operated by the output of the comparator. Here, the first semiconductor switching element and the second semiconductor switching element or the third semiconductor switching element are operated by receiving an output signal of the comparator, and the external voltage is output when the external voltage is within a range of a voltage required by the internal switching circuit. In this way, the external voltage flows to the ground and thus the voltage applied to the internal circuit is made 0 volt, so that the internal switching circuit is protected from the external overvoltage.

Furthermore, the publication "Low drop regulator with overvoltage protection and reset function for automatic environment" of the Institute of Electrical and Electronics Engineers (IEEE) describes how the bipolar high voltage process enables the integration of the following voltage regulators: the voltage regulator can operate with minimal voltage drop and can withstand positive and negative overvoltages up to 80 volts. The fully surface-protected PNP transistor on the power side enables a large range of uses, which is required in particular for automotive and industrial applications. The so-called "Zener-Zap-Trimm" reference enables the reset logic to be turned on and off accurately without adjustable or highly accurate external components.

In the above method, overvoltage events are avoided or detected by: the destruction of the output side MOS transistor is prevented in the case of using an overvoltage detection circuit and a clamp circuit, thereby turning off the output side MOS transistor and referring the output side voltage to ground or turning off the output side power PNP transistor.

It is assumed in each of the methods that the output terminal MOS/PNP transistor does not have a defect such as a short circuit between the drain and the source or a short circuit between the collector and the emitter. Such defects may result in the external battery voltage causing damage to the on-board circuitry and the load or the consumer occurring directly at the load or at the consumer without any regulation. This is important in the automotive field, since the battery voltage is nominally 14 volts but can rise in the case of a load deposition (latablegrung).

Disclosure of Invention

According to the invention, a circuit for identifying circuit defects and/or for avoiding overvoltages in a regulator is provided, the circuit comprising a power regulator circuit having a first transistor, a regulation loop comprising an operational amplifier and a first reference voltage source, a feedback resistor, and an overvoltage suppression circuit having a second transistor, a regulation loop comprising an operational amplifier and a reference voltage source, a feedback resistor, wherein the power regulator circuit is arranged for providing a voltage to the overvoltage suppression circuit, the overvoltage suppression circuit being arranged for providing a protected voltage.

THE ADVANTAGES OF THE PRESENT INVENTION

The invention makes it possible to detect defects not only in different partial circuits of the regulator, but also in the output MOS transistor itself. Each defect in the partial circuit and the output MOS transistor may cause an over-voltage event or an under-voltage event that causes malfunction or destruction of the chip.

Furthermore, the invention makes it possible not only to detect overvoltage events, but also to limit these overvoltage events so that digital logic circuits and load circuits operating in the range from 2.7V to 3.6V can function as specified. This enables the digital logic circuit to take corresponding measures, for example measures for controlled shutdown. The voltage suppression circuit limits the voltage over the maximum operating range of the power-on circuit so that the power-on circuit functions well even in the presence of defects, such as a drain-source short of a power transistor. This is particularly useful for applications in the automotive field, where uncontrolled switching off may lead to undesired behavior.

Advantageously, the circuit further comprises a third transistor, the gate connection of which is connected to the source connection of the second transistor of the overvoltage suppression circuit and which is provided for limiting overvoltages at the source connection of the third transistor. According to the invention, it is thereby achieved that a voltage value of more than 3.6 volts at the drain connection of the third transistor becomes impermissible at the source connection.

According to a particular embodiment of the circuit, the source connection of the third transistor is connected to the input of a comparator: the comparator is arranged to detect the overvoltage by comparing the limited voltage with a voltage of a second reference voltage source. In this way, a binary output signal that indicates the presence of an overvoltage and can be further processed can be generated.

Preferably, the first comparator arranged to detect overvoltages is arranged to output a binary value indicative of an overvoltage. This makes it possible to identify defects in the second reference voltage source which lead to a lower target value, despite the second comparator and the protection regulator using the same second reference voltage source, by the first comparator.

In an advantageous embodiment, the circuit further comprises a circuit for detecting an undervoltage of the power regulator by means of a second comparator, which compares the voltage of the second reference voltage source with a voltage obtained by the provided protected voltage. A binary output signal indicating the presence of an under-voltage can thus be generated which can be further processed.

In a particular embodiment of the invention, the comparator provided for detecting an undervoltage is provided here for outputting a binary value representing the undervoltage. It is thereby possible to achieve that the predefined voltage value is not undershot, so that digital logic circuits and load circuits operating in the range of 2.7 volts to 3.6 volts can function as intended.

According to an alternative embodiment of the invention, the circuit further comprises a circuit for detecting an undervoltage of the power regulator by means of two comparators, wherein a voltage obtained by the voltage of the first or second reference voltage source is compared with a voltage obtained by means of the supplied protected voltage. This makes it possible to clearly distinguish between an overvoltage in the voltage supplied by the power regulator circuit and an undervoltage in the protected voltage supplied.

Advantageously, the two comparators are here provided for outputting a binary value representing the undervoltage. According to a preferred embodiment of the invention, a logical and gate is also provided for associating a binary value reflecting an undervoltage. In this way, the output value is additionally set to 1 if the voltage supplied by the power regulator circuit is significantly below the predefined value, so that a fault in the second reference voltage source can be detected.

According to another alternative embodiment of the invention, the circuit further comprises an under-voltage discrimination comparator with a switchable reference source for detecting defects in the reference source that cause power regulator over-voltages or protect regulator under-voltages. This makes it possible to clearly distinguish between an overvoltage or undervoltage due to a fault in the regulator and a fault in the reference voltage.

Preferably, the circuit according to the invention comprises a digital part at which the protected voltage is provided. By means of such a digital part, certain components of the circuit (for example power regulators and/or comparators) can be electrically excited, in particular.

According to a further advantageous variant of the invention, the digital part has an input for receiving binary values and an output for transmitting binary values. By transmitting the binary value, for example, a controlled shutdown of the load circuit can be carried out on the basis of the received binary value in order to avoid damage to the circuit and/or damage to the load circuit or to the load circuit of the circuit.

According to the invention, provision can also be made for the first reference voltage source, the second reference voltage source, the power regulator circuit and the overvoltage suppression circuit to be supplied with external battery voltage.

Advantageous embodiments of the invention are specified in the dependent claims and described in the description.

Drawings

Embodiments of the invention are further elucidated on the basis of the figures and the following description. The figures show:

FIG. 1 shows a circuit for detecting defects and for over-voltage suppression according to the present invention;

FIG. 2 illustrates in a flow chart the changes in values implemented during the BIST stage corresponding to a circuit according to the present invention;

FIG. 3 shows another embodiment of a circuit according to the present invention that enables V due to a defect in the reference voltage_{DD_PWR}Overvoltage and V in_{DD_PROT}To make a clear distinction between undervoltages in (1);

fig. 4 shows an embodiment of a circuit according to the invention which, in contrast to the embodiment known from fig. 3, requires only one under-voltage comparator;

fig. 5 shows an alternative embodiment of the circuit according to the invention implementing the off mode/standby mode.

Detailed Description

Fig. 1 shows a circuit according to the invention for detecting defects and for overvoltage suppression of high-voltage BCD (Bipolar), CMOS and DMOS) semiconductor processes, which circuit is suitable for use in the automotive field. The circuit can also be adapted to other semiconductor processes.

From the battery at a voltage V_BATTThe regulator is powered. The power regulator comprises a high-voltage transistor MOS_PWRRegulation loop and high-ohmic feedback resistor R₁、R₂And R₃The regulation loop comprising an operational amplifier OTA_PWRAnd an undervoltage bandgap reference voltage V as a reference voltage source_REF1. The power regulator supplies a voltage V to the over-voltage suppression circuit_{DD_PWR}。

The overvoltage suppression circuit comprises a high-voltage protection transistor MOS_PROTRegulation loop and high-ohmic feedback resistor R₄、R₅And R₆The regulation loop comprising an operational amplifier OTA_PROTAnd an undervoltage bandgap reference voltage V as a reference voltage source_REF2. Overvoltage suppression circuit to protect voltage V_{DD_PROT}To the digital logic circuit represented by the digital part DT and to the LOAD loop LOAD, CP.

From voltage V_{DD_PROT}The power supply charge pump CP is at V_BATTOperational amplifier OTA at lower voltage_PWRAnd OTA_PROTProviding a higher voltage V_CPMaking the transistor MOS_PWRAnd MOS_PROTThe voltage on the drain and source connections of (a) is limited only by its on-resistance and load current, and not by the regulated voltage on its gate.

For a better understanding of the circuit according to the invention, the following interrelationships are given:

(1)R₂＝R₁*2085/1215

(2)R₃＝R₁*300/1215

(3)R₅＝R₄*288/1215

(4)R₆＝R₄*1897/1215

(5)R₈＝R₇*4670/1215

(6)R₉＝R₇*55/1215

(7)V_{DD_PWR}＝V_REF1*(3300+(BIST_PWR*300))/1215

(8a)V_{DD_PROT}＝V_{DD_PWR}for V_{DD_PWR}＜3.4V

(8b)V_{DD_PROT}＝V_REF23400/1215 for V_{DD_PWR}≥3.4V

(9)V_UV＝V_{DD_PROT}*1503/3400

(10)V_OV＝(V_DDPWR+V_{DD_PROT})/(2+(4670/(1215+(BIST_OV*55))))

(11a)FLAG_UV1 for V _UV＜V_REF2

(11b)FLAG_UVFor V equal to 0_UV≥V_REF2

(12a)FLAG_OVFor V equal to 0_OV＜V_REF2

(12b)FLAG_OV1 for V_OV≥V_REF2

It is assumed herein that: parameter V_BATTNominal value of 14 volts, parameter V representing the voltage at the output of the charge pump_CPIs greater than 7V and is used as the undervoltage band-gap reference voltage V of the reference voltage_REF1And V_REF2Are respectively 1.215V, regulated voltage V_{DD_PWR}Nominal value of 3.3 volts, by BIST_PWRRegulated voltage V_{DD_PWR}Nominal value of 3.6 volts, regulated voltage V_{DD_PROT}Is 3.4 volts. In addition, to activate FLAG_UV，V_{DD_PROT}Must be less than 2.75 volts. To activate FLAG_OVAverage value ((V)_{DD_PWR}+V_{DD_PROT}) /2) must be greater than 3.55 volts and to enable BIST_OVFLAG in (1)_OVAverage value ((V)_{DD_PWR}+V_{DD_PROT}) /2) must be greater than 3.45 volts. For digital logic circuits DT and loadsThe operating voltage of the loop is in the range of 2.7 volts to 3.6 volts.

In this context, the comparator COMP_UVAnd a reference voltage V_REF2The undervoltage of the regulator is identified by: if the voltage V is_{DD_PROT}Below its 2.75 volt threshold, FLAG will be asserted_UVSet to a value of 1. By comparator COMP_OVAnd a reference voltage V_REF2The overvoltage of the regulator is detected by: if V_OVVoltage greater than V_REF2Reference voltage, then FLAG_OVSet to a value of 1. When the voltage V is_{DD_PWR}Above 3.6 volts, the transistor MOS _OVThe limit is applied to comparator COMP_OVThe maximum voltage at the positive input terminal. The digital logic circuit and load loop function properly at supply voltages between 2.7 volts and 3.6 volts.

In normal operation, i.e. if no defect is present, the protection regulator allows a total regulated voltage V of 3.3 volts_{DD_PWR}And (4) passing. This is because the protection regulator will protect the voltage V_{DD_PROT}Adjusted to a higher value of 3.4 volts. Thus, the transistor MOS_PROTIn normal operation, it functions as a so-called source follower, which leads to a voltage V_{DD_PROT}Voltage V equal to 3.3 volts_{DD_PWR}. Due to the voltage V_OVLess than COMP_OVThreshold value V_REF2Therefore, FLAG is not used in normal operation_OVSet to a value of 1.

The invention provides a reference voltage V_REF1And V_REF2Internal defect, voltage V_{DD_PWR}And V_{DD_PROT}Of the regulating path of the MOS transistor at the defect output end_PWRAnd MOS_PROTFull coverage of internal defects. If there is a defect, V_{DD_PWR}、V_{DD_PROT}、V_REF1And V_REF2Changes in value of and results in activation of FLAG_UVOr FLAG_OV。FLAG_UVOr FLAG_OVThe setting of the value of (b) is then used to cause the load loop to be controlled shut down to avoid damage.

The means for detecting defects in each of these partial circuits is further described below based on fig. 1.

V_REF1A defect in the voltage source of the reference voltage may result in the value of the voltage being higher or lower than the nominal value of 1.215 volts. If V _REF1The reference voltage is less than the nominal value of 1.215V, so that the voltage V_{DD_PWR}And V_{DD_PROT}Less than 2.75 volts, then through comparator COMP_UVFLAG is added_UVSet to a value of 1, the comparator uses an independent second reference voltage V_REF2. If V_REF1The reference voltage is above the nominal value of 1.215 volts, such that the voltage V_{DD_PWR}Higher than 3.7 volts and protecting the regulator from coupling the output V_{DD_PROT}Adjust to 3.4 volts, then FLAG_OVIs set to the value 1 because of the average value ((V)_DDPWR+V_{DD_PROT}) /2) greater than 3.55 volts and therefore voltage V_OVGreater than at comparator COMP_OVIn the set threshold value V_REF2。

Regulating path V_{DD_PWR}Any defect (e.g. feedback resistance R)₁、R₂、R₃MOS transistor_PWRDefect in (d) will cause a voltage V_{DD_PWR}Above or below the nominal value of 3.3 volts. If a defect in the regulation loop causes the voltage V_{DD_PWR}Deviates from the nominal value of 3.3 volts to become less than 2.75 volts, FLAG will be applied_UVSet to a value of 1 to indicate power regulator undervoltage. If a defect in the regulation loop (e.g. transistor MOS)_PWRDrain-source short) causes the voltage V to be applied_{DD_PWR}Deviates upward by a value of 3.3 volts and becomes greater than 3.7 volts, FLAG will be applied_OVSet to a value of 1 to indicate an overvoltage in the power regulator.

V_REF2Defects in the reference voltage may result in V_REF2Is higher or lower than the nominal value of 1.215 volts. If V_REF2A value less than a nominal value of 1.215 volts, so that the protective regulator will output V _{DD_PROT}Adjusted to be less than V_{DD_PWR}The value of (1) is in the transistor MOS_PROTGenerating a differential voltage. If the difference is large enough, comparator COMP_OVFLAG is added_OVIs set to 1 to thereby display V_REF2There may be a defect in the reference voltage. Based on the above nominal values and equations (1) through (12b), FLAG may be generated_OVIs arranged atV is a value of 1_REF2The value of the reference voltage is calculated at 1.084 volts, and the voltage V_{DD_PROT}The corresponding voltage drop of (3.033) volts. Thus, by applying FLAG_OVIs set to 1 to show V_REF2A voltage value defect that lowers its target value by 0.131 volts or more. The advantage of the proposed overvoltage monitoring scheme is that despite comparator COMP_UVUsing the same reference voltage V as the protection regulator_REF2But may be determined by comparator COMP_OVBy FLAG_OVValue of (3) identifies V_REF2Defects in the reference voltage that result in a lower target value. In this case, FLAG_OVThe setting of the value of (A) does not necessarily mean that an overvoltage is present, but indicates that V is present_REF2Resulting voltage V in a reference voltage_{DD_PROT}Below voltage V_{DD_PWR}To a problem of (a). If it must be at V_{DD_PWR}Overvoltage and V in_{DD_PROT}To make a clear distinction between under-voltages in (b), the embodiments described later in connection with fig. 3 and 4 may be used. If V_REF2A value above the target value of 1.215 volts, the protection regulator attempts to regulate the voltage V _{DD_PROT}Adjusted to a higher value. However, since the input of the protection regulator is limited by the power regulator, V_{DD_PROT}Is maintained at 3.3 volts, and thus voltage V_UVThe value of (a) is not changed. However, the voltage V_REF2Higher value of (b) causes comparator COMP_UVFLAG is added_UVIs set to 1 because of V_REF2Value above its threshold voltage V_UV. Based on the above nominal values and equations (1) through (12b), FLAG may result_UVV set to value 1_REF2The increase is calculated at 1.458 volts. Thus, by applying FLAG_UVSetting to a value of 1 to display V_REF2The target value of which is increased by 0.243 volt. In this case, FLAG_UVThe setting of the value of (A) does not necessarily mean that there is an undervoltage, but rather indicates that V is present_REF2Resulting voltage V in a reference voltage_UVBelow the reference voltage V_REF2To a problem of (a).

Regulating path V_{DD_PROT}Each defect (e.g. feedback resistance R)₄、R₅、R₆MOS transistor_PROTDefect in (d) will cause a voltage V_{DD_PROT}Is adjusted to a value below or above the nominal value of 3.4 volts. If a defect in the regulation loop results in a voltage V_{DD_PROT}Deviates downward from the nominal value of 3.4 volts and becomes below 2.75 volts, FLAG is turned off_UVSet to a value of 1 to indicate at a voltage V_{DD_PROT}There is a fault in the regulation path of (2). If a defect in the regulation loop (e.g. transistor MOS) _PROTDrain-source short) causes a voltage V_{DD_PROT}Up to 3.4 volts from nominal and adjusted to a higher value of 3.5 volts or more, then In the BIST (build-In Self-Test) phase, FLAG_OVThe behavior of the value of (a) will show the defect. The BIST stage is performed after the regulator is turned on and before the load loop is activated. If a fault exists, the activation of the load loop and all circuits are locked out until the fault is cleared. During the BIST stage, to the output voltage V_{DD_PWR}Power regulator and comparator COMP_OVExcited so as to be FLAG_OVResulting in a determined output mode. If the mode changes, it indicates that V is_{DD_PROT}There is a defect in the adjustment path of (2). In normal operation, i.e. if no defects are present, the digital section DT is passed through the Signal BIST_PWREnergizing the power regulator so that the voltage V_{DD_PWR}Up to 3.6 volts. Protecting the regulator from the voltage V_{DD_PROT}Is regulated to 3.4 volts below voltage V_REF2Voltage V of reference value of_OVBlocking comparator COMP_OVFLAG is added_OVIs set to 1. The digital part DT is then passed through the output signal BIST_OVFor over-voltage comparator COMP_OVThe activation takes place such that the comparison threshold of the overvoltage comparator changes. Thereby turning FLAG _OVIs set to a value of 1 because V_OVThe voltage is now higher than the reference voltage V_REF2. Thus, if no defect is present, FLAG_OVThe expected output mode during the BIST stage is a value of 0, then a value of 1. However, if path V is adjusted_{DD_PROT}With the defect that this adjustment path is adjusted to a value higher than the nominal value, with 3.5 volts, during the BIST phase-when the digital part DT pass signal BIST_PWRWhen the protective regulator is excited-V_{DD_PROT}Will rise to 3.5 volts and thus the voltage V_OVBecomes greater than a reference voltage V_REF2Thereby causing comparator COMP_OVFLAG is added_oVSet to a value of 1. Thus, FLAG in the presence of a defect in the regulation loop_OVThe output mode of (1) is a value of 1 and then again a value of 1. In contrast, in the case of no defects, the first value 0 is followed by the second value 1. In fact, when the voltage V is_{DD_PWR}Faults in the regulation loop are also identified in the BIST stage when biased downward off the nominal value of 3.4 volts and regulated to a smaller value of 3.3 volts or less. In this case, FLAG in the case of a defect in the regulation loop_OVThe output mode of (1) is a value of 0 and then again a value of 0.

The same applies to the transistor MOS_PWR、MOS_PROTAt a voltage V in a neutral or regulation loop _{DD_PWR}Or a reference voltage V_REF1And V_REF2The aspect is a drawback. In fact, only when V_{DD_PWR}Regulator and V_{DD_PROT}Regulator and reference voltage V_REF1And V_REF2Operating within its limits, the BIST stage can only pass. Based on the above nominal values and equations (1) to (12b), if the voltage V is_{DD_PWR}Or V_{DD_PROT}Deviates from its nominal value by about + -0.1 volt or if the reference voltage V is_REF1Or V_REF2Is about 0.034 volts from its nominal value, a fault is generated in the BIST stage. FLAG if one of the voltage or the reference voltage deviates upward_OVThe value 1 is generated in the BIST stage and then again the value 1. FLAG if the voltage deviates downward_OVThe value 0 is generated during the BIST stage and then reset to the value 0.

In fig. 2, the flow illustrated with reference to fig. 1 of the circuit according to the invention is shown graphically in terms of the corresponding waveforms with and without defects in the regulating path during the BIST phase. Here, for the parameter V_BATT、V_REF1、V_REF2、V_{DD_PWR}、V_{DD_PROT}And V_OVIn voltsCorresponding voltage value is set, and for parameter FLAG_UV、FLAG_OV、BIST_PWRAnd BIST_OVLogical values or binary values 0 and 1 may be used. As described above, in the parameter FLAG_OVThe first sequence of values 0 and 1 in the curve of variation (c) indicates the presence of defect-free V_{DD_PROT}A regulation loop. Conversely, the parameter FLAG _OVThe sequence of values 1 and 1 or 0 and 0 shown next allows identification of the sequence at V_{DD_PROT}There are drawbacks in the regulation loop.

Fig. 3 shows an embodiment of a circuit according to the invention, which enables a voltage at V to be set_{DD_PWR}Overvoltage and V in_{DD_PROT}Is clearly distinguished from the undervoltage in (b). The circuit additionally comprises two dual voltage detection comparators COMP_UV1And COMP_UV2The two dual voltage identification comparators are at a reference voltage V_REF1And V_REF2And (4) working. In this embodiment, if the voltage V is_{DD_PROT}Significantly below 2.75 volts, FLAG_UVIs at the reference voltage V due to the intermediate connected logical AND gate AND_REF1Comparator COMP working on_UV2Additionally set to 1. In this way, by using FLAG_UVAnd FLAG_OVSetting to a value of 1 identifies V_REF2A fault in the reference voltage.

In fig. 4, an embodiment of the circuit according to the invention is shown, which, in contrast to fig. 3, has only an undervoltage detection comparator COMP_UVThe undervoltage detection comparator has a switchable reference voltage in order to be able to distinguish unambiguously between an overvoltage/undervoltage due to a fault in the regulator and a fault in the reference voltage. When FLAG is turned off_OVHaving a value of 0, COMP_UVUsing a reference voltage V _REF2(ii) a When FLAG is turned off_OVHaving a value of 1, COMP_UVUsing a reference voltage V_REF1. In this embodiment, since the reference voltage V_REF2When the voltage V is small_{DD_PROT}FLAG at significantly less than 2.75 volts_UVDue to conversion to V_REF1The reference voltage is additionally set to 1. In this way, by using FLAG_UVAnd FLAG_OVIdentifying V by setting to a value of 1_RFF2A fault in the reference voltage. Similarly, if the reference voltage V_REF1Deviation to a value above 1.5 volts due to defects is at V_{DD_PWR}There is an overvoltage. Protecting the regulator from the voltage V_{DD_PWR}Limited to 3.4 volts and thus V is limited_UVLimited to 1.5 volts. Due to overvoltage, COMP_OVFLAG is added_OVSet to value 1 and thus COMP_UVFrom V to V_REF2Conversion to V_REF1. However, the voltage V_REF1Higher value of (b) causes comparator COMP_UVFLAG is added_UVIs set to 1 because of V_REF1Value above its threshold voltage V_UV. Thus, by applying FLAG_UVAnd FLAG_OVSetting to a value of 1 to display V_REF1The target value of which is increased by 0.285 v.

Fig. 5 shows an alternative embodiment of a circuit according to the invention, which enables an off mode in which a binary signal EN can be used₃Turn-off overvoltage identification comparator COMP_OVAnd can be assisted by a binary signal EN ₁Turn off the protection regulator and pass EN₂Passively regulated protection transistor MOS_PROTSo that the voltage does not exceed the maximum operating voltage of 3.6 volts. This can be achieved by using a zener-clamp diode Z with a resistor R having a positive temperature coefficient_TKPAnd R having a negative temperature coefficient_TKNAnd MOS_PROT2Is implemented by a parallel combination of the threshold voltages of the transistors of (a). From the resistance R_TKP、R_TKNFormed resistor divider and transistor threshold voltage MOS_PROT2In-process generation protection transistor MOS_PROT2Such that the gate voltage appears as a protection transistor MOS_PROTIs similar to the threshold voltage of the first transistor. This results in a passive gate clamp voltage that is stable with respect to temperature, which can clamp voltage V_{DD_PROT}Limited to a maximum of 3.6 volts. In this embodiment, the external enable signal EN may be received by the digital part DT₀Time-on overvoltage detection logic circuit and protection switchA section loop, which switches the entire Application Specific Integrated Circuit (ASIC) from an off/standby mode to an active mode. Instead of a high-ohmic resistor divider (R7, R8, R9), the transistor MOS can be replaced by a resistor_PROTIs provided with a differential voltage detector on the drain and source to detect the transistor MOS _PROTThe voltage drop over. The same principle can also be matched for regulators with other transistor types (e.g. PMOS or BJT).