阅读说明：本技术 缓存存储器操作的协调 (Coordination of cache memory operations ) 是由 B·施泰因马赫尔-布罗 于 2019-03-27 设计创作，主要内容包括：本发明涉及一种用于协调由一致性共享存储系统的处理器设备执行的指令序列的方法。一条指令被执行并使所述处理器设备将存储器线的副本填充到处理器高速缓存中。基于检测到指示关于所述存储器线的跨所述共享存储系统的一致性传播未被确认的第一标志信息,所述处理器设备对所述存储器线进行标记。基于检测到指示关于所述存储器线的跨所述共享存储系统的所述一致性传播已确认的第二标志信息,所述处理器设备对所述存储器线进行清除标记。基于执行存储器屏障指令,在标记所述存储器线的同时阻止所述存储器屏障指令的执行完成。(The present invention relates to a method for coordinating sequences of instructions executed by processor devices of a coherent shared memory system. An instruction is executed and causes the processor device to fill a copy of a memory line into a processor cache. The processor device marks the memory line based on detecting first flag information indicating that coherency propagation across the shared memory system with respect to the memory line is not confirmed. The processor device clears the memory line based on detecting second flag information indicating that the coherency propagation across the shared memory system with respect to the memory line is confirmed. Based on executing a memory barrier instruction, execution of the memory barrier instruction is prevented from completing while the memory line is marked.)

1. A method for coordinating an instruction sequence comprising a plurality of instructions for execution by a processor device of a coherent shared memory system, wherein the processor device is operatively connected with a processor cache memory, the method comprising:

executing, by the processor device, instructions of a sequence of instructions, wherein execution of the instructions causes the processor device to populate the processor cache memory with a copy of a memory line of main memory of the shared memory system;

marking, by the processor device, the respective memory lines based on detecting that first flag information indicating memory coherency propagation across the shared storage system with respect to the population of the copies of the memory lines is not confirmed;

clearing, by the processor device, a flag for the respective memory line based on detecting that second flag information indicating memory coherency propagation across the shared storage system with respect to the population of the copy of the memory line is confirmed;

based on a memory barrier instruction executing the sequence of instructions, the processor device prevents completion of execution of the memory barrier instruction while marking the memory line.

2. The method of claim 1, wherein completion of execution of the memory barrier instruction is prevented until all memory lines previously marked by the processor device are marked clear.

3. The method of claim 1, wherein the marking of the memory line comprises adding an identifier of the memory line to a cache of the processor device, and wherein the flush marking of the marked memory line comprises removing the identifier of the memory line from the cache of the processor.

4. The method of claim 3, wherein the identifiers of the marked memory lines stored in the cache comprise memory addresses of the respective memory lines in the main memory.

5. The method of claim 3, wherein completion of execution of the memory barrier instruction is prevented until the buffer of the processor device is empty.

6. The method of claim 1, wherein the memory coherence of the shared memory system is implemented using a coherence directory.

7. The method of claim 6, wherein at least one of the first and the second flag information is provided by a message received by the processor device from the coherence directory.

8. The method of claim 6, wherein at least one of the first and the second flag information is provided by a message sent by the processor device to the coherence directory.

9. The method of claim 1, wherein memory coherency of the shared storage system is achieved using broadcasting.

10. The method of claim 1, wherein the instruction that causes the processor device to fill the copy of the memory line to the processor cache memory is an instruction that specifies a write access to the respective memory line.

11. The method of claim 1, wherein the memory coherency propagation across the shared memory system comprises: invalidating other copies of the memory line used by remote processor cache memories of other processor devices of the shared memory system.

12. The method of claim 1, wherein a message related to the modification of the contents of the processor cache memory and processed by the processor device comprises a coherency propagation field, wherein the coherency propagation field comprises one of: indicating marker information that is not confirmed with respect to memory coherency propagation across the shared storage system of the modification; flag information indicating that propagation of memory coherency across the shared memory system with respect to the modification has been confirmed, or flag information indicating that neither a marking operation nor a clearing marking operation is required.

13. A processor device of a coherent shared memory system, wherein the processor device is operatively connected with a processor cache memory and is configured to coordinate execution of an instruction sequence comprising a plurality of instructions, the coordination comprising:

executing instructions of a sequence of instructions, wherein execution of the instructions causes the processor device to populate the processor cache memory with a copy of a memory line of main memory of the shared memory system;

marking, by the processor device, the respective memory lines based on detecting that flag information indicating memory coherency propagation across the shared storage system with respect to the population of the copies of the memory lines is not confirmed;

clearing, by the processor device, a flag for the respective memory line based on detecting that flag information indicating memory coherency propagation across the shared storage system with respect to the population of the copy of the memory line is confirmed;

based on a memory barrier instruction executing the sequence of instructions, preventing completion of execution of the memory barrier instruction while marking the memory line.

14. The processor apparatus of claim 13, wherein execution of the memory barrier instruction is prevented from completing until all memory lines previously marked by the processor device are marked clear.

15. The processor device of claim 13, wherein the processor device comprises a cache to register memory lines, copies of the memory lines are populated to the processor cache memory, and memory coherency propagation across the shared memory system with respect to the population of the respective copies is not confirmed for the memory lines, wherein the marking of the memory lines comprises adding an identifier of the memory lines to the cache of the processor device, and wherein the clearing of the marked memory lines comprises deleting the identifier of the memory lines from the cache of the processor.

16. The processor device of claim 15, wherein the identifiers of the marked memory lines stored in the buffer comprise memory addresses of the respective memory lines in the main memory.

17. The processor device of claim 15, wherein completion of execution of the memory barrier instruction is prevented until the buffer of the processor apparatus is empty.

18. A method for managing a coherence directory that implements memory coherence for a shared memory system, the method comprising:

Maintaining, by the coherency directory, flag information for a memory line allocated to main memory of the shared storage system, wherein a processor device of the shared storage system has initiated a fill of a copy of the memory line to a processor cache memory operatively connected to the processor device, the flag information indicating whether a memory coherency propagation across the shared storage system regarding the fill of the copy of the memory line has been determined;

sending the flag information to the processor device by the coherence directory included in a message;

sending the message to the processor device through the coherence directory.

19. The method of claim 18, wherein the coherency directory initiates the maintenance of the tag information assigned to the memory line based on determining that the contents of a remote processor cache memory of another processor device of the shared storage system need to be modified in order to propagate memory coherency with respect to populating the copy of the memory line to the remote cache memory.

20. The method of claim 19, wherein the coherency directory sends a request to the remote processor cache memory to request modification of contents of the remote processor cache memory for propagation of the memory coherency with respect to the population of the copy of the memory line to the remote processor cache memory.

21. The method of claim 20, wherein the modification requested by the coherency directory comprises invalidating another copy of the memory line included by the remote processor cache memory.

22. The method of claim 19, wherein a coherency directory includes a register to keep track of the content revisions of the processor caches of the other processor devices of the shared memory system based on the propagation of the memory coherency across the shared memory system with respect to the population of the copy of the memory line.

23. The method of claim 22, wherein when a store coherency propagation across the shared memory system with respect to the population of the copy of the memory line is confirmed, the register includes a coherency propagation notification indicator that identifies a processor cache memory of a processor device of the shared memory system that is to be notified by the coherency directory.

24. A coherence directory to implement memory coherence for a shared memory system, the coherence directory configured to:

Maintaining flag information for a memory line allocated to main memory of the shared storage system, wherein a processor device of the shared storage system has initiated a population of a copy of the memory line to a processor cache memory operatively connected to the processor device, the flag information indicating whether a memory coherency propagation across the shared storage system regarding the population of the copy of the memory line has been determined;

including the flag information in a message;

sending the message to the processor device.

25. A coherent shared memory system comprising a coherence directory implementing memory coherence of the shared memory system, a main memory, and a processor device operably connected to a processor cache memory, the processor device configured to coordinate execution of a sequence of instructions comprising a plurality of instructions, the coordination comprising:

executing instructions of a sequence of instructions, wherein execution of the instructions causes the processor device to populate the processor cache memory with a copy of a memory line of main memory of the shared memory system;

marking, by the processor device, the respective memory lines based on detecting that flag information indicating memory coherency propagation across the shared storage system with respect to the population of the copies of the memory lines is not confirmed;

Clearing, by the processor device, a flag for the respective memory line based on detecting that flag information indicating memory coherency propagation across the shared storage system with respect to the population of the copy of the memory line is confirmed;

based on a memory barrier instruction executing the sequence of instructions, preventing completion of execution of the memory barrier instruction while marking the memory line;

and the coherency directory is configured to maintain the flag information allocated to the memory line of the main memory based on initiating the population of the copy of the memory line, the flag information indicating whether the memory coherency propagation across the shared storage system regarding the population of the copy of the memory line is determined, wherein the maintaining comprises:

first including flag information indicating that propagation of the memory coherency across the shared storage system with respect to the population of the copy of the memory line is not confirmed as a first message;

sending the first message to the processor device;

obtaining a confirmation based on the propagation, updating the flag information and including the updated flag information indicating that the populated, consistent propagation of the memory across the shared storage system with respect to the copy of the stored message is confirmed as a second message;

Sending the second message to the processor device.