阅读说明：本技术 一种上管镶嵌式微型多功能开关 (Upper tube embedded type miniature multifunctional switch ) 是由 赵文全 于 2020-08-07 设计创作，主要内容包括：本发明涉及电动自行车技术领域,具体地说是一种上管镶嵌式微型多功能开关。一种上管镶嵌式微型多功能开关,其特征在于：位于车架上管的一端上部嵌设有开关固定座,开关固定座内嵌设有下盖,下盖的上端通过超声波焊接连接上盖,上盖与下盖之间设有按键控制模块；位于车架上管内设有开关线束,开关线束通过线路贯穿开关固定座及下盖与按键控制模块连接；按键控制模块上设有主控逻辑电路、按键和灯板电路、主板供电电路、CAN通讯电路。同现有技术相比,将其开关控制模块做成集成式的结构,并且开关的上盖、下盖及开关固定座做成镶嵌式的,一套多功能的开关全部镶嵌在电动自行车的管路中,提高了电动自行车的整体性能。(The invention relates to the technical field of electric bicycles, in particular to an upper tube embedded type miniature multifunctional switch. The utility model provides a miniature multi-functional switch of upper tube mosaic which characterized in that: a switch fixing seat is embedded in the upper part of one end of the upper frame tube, a lower cover is embedded in the switch fixing seat, the upper end of the lower cover is connected with the upper cover through ultrasonic welding, and a key control module is arranged between the upper cover and the lower cover; a switch wire harness is arranged in the upper pipe of the frame and is connected with the key control module through a circuit penetrating through the switch fixing seat and the lower cover; the key control module is provided with a main control logic circuit, a key and lamp panel circuit, a mainboard power supply circuit and a CAN communication circuit. Compared with the prior art, the switch control module is made into an integrated structure, the upper cover, the lower cover and the switch fixing seat of the switch are made into an embedded type, and a set of multifunctional switches are all embedded in a pipeline of the electric bicycle, so that the overall performance of the electric bicycle is improved.)

1. The utility model provides a miniature multi-functional switch of upper tube mosaic, includes upper cover, lower cover, switch fixing base, frame upper tube, its characterized in that: a switch fixing seat (4) is embedded at the upper part of one end of the upper frame tube (6), a lower cover (3) is embedded in the switch fixing seat (4), the upper end of the lower cover (3) is connected with the upper cover (1) through ultrasonic welding, and a key control module (2) is arranged between the upper cover (1) and the lower cover (3); a switch wiring harness (5) is arranged in the upper frame tube (6), and the switch wiring harness (5) is connected with the key control module (2) through a circuit penetrating switch fixing seat (4) and the lower cover (3); the key control module (2) is provided with a master control logic circuit, a key and lamp panel circuit, a mainboard power supply circuit and a CAN communication circuit.

2. The upper tube embedded type micro multifunctional switch as claimed in claim 1, wherein: the upper cover (1) is of a long strip structure, the upper end of the upper cover (1) is provided with a ring-shaped lamp strip (1-1), and the inner side of the ring-shaped lamp strip (1-1) is sequentially provided with a key (1-2), an indicator lamp (1-3) and another key (1-4) from left to right.

3. The upper tube embedded type micro multifunctional switch as claimed in claim 1, wherein: the front side and the rear side of the lower cover (3) are respectively provided with a buckle (3-1), the front side and the rear side of the switch fixing seat (4) are respectively provided with a clamping groove (4-1), and the lower cover (3) is connected with the clamping groove (4-1) of the switch fixing seat (4) through the buckle (3-1).

4. The upper tube embedded type micro multifunctional switch as claimed in claim 1, wherein: the frame upper pipe (6) is of a long strip structure, and the cross section of the frame upper pipe (6) is of a triangular hollow structure.

5. The upper tube embedded type micro multifunctional switch as claimed in claim 1, wherein: the main control logic circuit comprises a first chip (U1A), a second chip (U1B), a first connecting terminal (J1), a second connecting terminal (P2) and a third connecting terminal (P3), wherein the type of the first chip (U1A) is MCU (APM32F103TBU6), the type of the second chip (U1B) is MCU (APM32F103TBU6), a No. 2 port of the first chip (U1A) and one end of a first capacitor (C1) are combined and connected with one end of a crystal oscillator (Y1), a No. 3 port of the first chip (U1A) and one end of a second capacitor (C2) are combined and connected with the other end of the crystal oscillator (Y1), and the other ends of the first capacitor (C1) and the second capacitor (C2) are combined and grounded; the No. 35 port of the chip I (U1A) is connected with one end of a resistor I (R9), and the other end of the resistor I (R9) is grounded; the No. 4 port of the first chip (U1A) is respectively connected with the No. 5 port of the second connecting terminal (P2), one end of a second resistor (R2) and one end of a third capacitor (C4), and the other end of the third capacitor (C4) is grounded; the other end of the second resistor (R2) is connected with the port 1 of the second connecting terminal (P2) and the port 3 of the first connecting terminal (J1); a No. 7 port of a chip I (U1A) is connected with one end of a resistor III (R8), the other end of the resistor III (R8) is respectively connected with one end of a resistor IV (R4) and a drain electrode of a power tube I (Q1), the other end of the resistor IV (R4) is respectively connected with a No. 1 port of a connecting terminal II (P2) and a No. 3 port of a connecting terminal I (J1), a gate of the power tube I (Q1) is respectively connected with one end of a capacitor IV (C10), a cathode of a voltage stabilizing diode I (ZD 1), a resistor V (R16) and one end of a resistor VI (R10), a source of the power tube I (Q1), the other end of the capacitor IV (C10), an anode of the voltage stabilizing diode I (ZD 1) and the other end of the resistor V (R16) are combined to be grounded; the other end of the resistor six (R10) is connected with one end of the resistor seven (R5), the other end of the resistor seven (R5) is connected with the cathode of the diode I (D3), and the anode of the diode I (D3) is connected with the No. 5 port of the connecting terminal I (J1); the No. 8 port of the first chip (U1A) is connected with one end of a resistor eight (R34), the No. 33 port of the first chip (U1A) is respectively connected with the No. 3 port of a connecting terminal three (P3) and one end of a resistor nine (R3), the No. 34 port of the first chip (U1A) is respectively connected with the No. 2 port of the connecting terminal three (P3) and one end of a resistor ten (R1), and the other ends of the resistor eight (R34), the resistor nine (R3) and the resistor ten (R1) are respectively connected with the No. 1 port of a connecting terminal two (P2) and the No. 3 port of the connecting terminal one (J1); a port 23 of the first chip (U1A) is connected with a port 9 of the first connecting terminal (J1) and one end of a resistor eleven (R14), a port 24 of the first chip (U1A) is connected with a port 8 of the first connecting terminal (J1) and one end of a resistor twelve (R12), and the other ends of the resistor eleven (R14) and the resistor twelve (R12) are connected with a port 1 of the second connecting terminal (P2) and a port 3 of the first connecting terminal (J1) in a combined manner; the No. 3 port of the connecting terminal III (P3) is grounded; no. 25 port of the first chip (U1A) is connected with No. 2 port of the second connecting terminal (P2), No. 28 port of the first chip (U1A) is connected with No. 3 port of the second connecting terminal (P2), and No. 4 port of the second connecting terminal (P2) is grounded; the 20 th port of the chip I (U1A) is connected with one end of a resistor thirteen (R17), the other end of the resistor thirteen (R17) is respectively connected with one end of a resistor fourteen (R28) and the gate pole of a power tube II (Q4), the drain electrode of the power tube II (Q4) is connected with the 2 nd port of a wiring terminal I (J1), and the source electrode of the power tube II (Q4) and the other end of the resistor fourteen (R28) are combined and grounded; a port 17 of the chip I (U1A) is connected with a port 6 of the connection terminal I (J1), a port 10 of the chip I (U1A) is connected with a port 15 of the connection terminal I (J1), a port 11 of the chip I (U1A) is connected with a port 14 of the connection terminal I (J1), a port 12 of the chip I (U1A) is connected with a port 13 of the connection terminal I (J1), a port 13 of the chip I (U1A) is connected with a port 12 of the connection terminal I (J1), a port 14 of the chip I (U1A) is connected with a port 11 of the connection terminal I (J1), a port 15 of the chip I (U1A) is connected with a port 10 of the connection terminal I (J1), a port 16 of the connection terminal I (U1A) is connected with a port 7 of the connection terminal I (J1), a port 8 of the chip I (U1A) is connected with a port 1 of the connection terminal I (J6854), and a port 1 is grounded;

ports No. 6, No. 19, No. 27 and No. 1 of a chip II (U1B) are combined and connected with one end of a capacitor five (C15), a capacitor six (C14), a capacitor seven (C13), a capacitor eight (C12) and a capacitor nine (C11) respectively, ports No. 5, No. 18, No. 26 and No. 36 of the chip II (U1B) are combined and connected with the other end of the capacitor five (C15), the capacitor six (C14), the capacitor seven (C13), the capacitor eight (C12) and the capacitor nine (C11) respectively, one end of the capacitor five (C15), the capacitor six (C14), the capacitor seven (C13), the capacitor eight (C12) and the capacitor nine (C11) is combined and connected with a port No. 1 of a connecting terminal II (P2) and a port No. 3 of a connecting terminal I (J1), and the other end of the capacitor five (C15), the capacitor six (C14), the capacitor seven (C13), the capacitor eight (C8253) and the other end of the capacitor 11).

6. The upper tube embedded type micro multifunctional switch as claimed in claim 1, wherein: the key and lamp panel circuit comprises a connecting terminal four (J3) and a connecting terminal five (J5), wherein the port 1 of the connecting terminal four (J3) is connected with one end of a switch I (SW 1), and the other end of the switch I (SW 1) is connected with the port 6 of the connecting terminal four (J3); the No. 7 port of the terminal IV (J3) is connected with one end of a resistor fifteen (R24), the other end of the resistor fifteen (R24) is respectively connected with one end of a switch II (SW 2), one end of a capacitor ten (C22) and the No. 12 port of a terminal V (J5), and the other ends of the switch II (SW 2) and the capacitor ten (C22) are grounded in a combined mode; the 10 port of the connecting terminal five (J5) and the 9 port of the connecting terminal five (J5) are combined and connected with the cathode of the first bicolor light-emitting diode (LED 1), the anode of the first bicolor light-emitting diode (LED 1) is respectively connected with one end of a resistor sixteen (R25) and one end of a resistor seventeen (R26), the 6 port of the connecting terminal five (J5) and the 5 port of the connecting terminal five (J5) are combined and connected with the cathode of the second bicolor light-emitting diode (LED 2), the anode of the second bicolor light-emitting diode (LED 2) is respectively connected with one end of a resistor eighteen (R27) and one end of a resistor nineteen (R29), the 4 port of the connecting terminal five (J5) and the 3 port of the connecting terminal five (J5) are combined and connected with the cathode of the third bicolor light-emitting diode (LED 3), the anode of the third bicolor light-emitting diode (LED 3) is respectively connected with one end of a resistor twenty (R6) and one end of a resistor twenty-one (R31), and the anode of the connecting terminal five connecting The cathode of the (LED 4), the anode of the bicolor light emitting diode four (LED 4) are respectively connected with one end of a resistor twenty-two (R32) and one end of a resistor twenty-three (R33), the other ends of a resistor sixteen (R25), a resistor seventeen (R26), a resistor eighteen (R27), a resistor nineteen (R29), a resistor twenty (R30), a resistor twenty-one (R31), a resistor twenty-two (R32) and a resistor twenty-three (R33) are connected with one end of a resistor twenty-four (R39) and a port 13 of a connecting terminal five (J5), a port 3 of the connecting terminal four (J3) is connected with one end of a resistor twenty-five (R38), the other ends of the resistor twenty-four (R39) and the resistor twenty-five (R38) are respectively connected with one end of a resistor twenty-six (R23), a resistor twenty-seven (R35), a resistor twenty-eight (R36), a resistor nineteen (R37), a resistor thirty (R40) and one end of a resistor thirty-one end of a, The other ends of the twenty-seventh resistor (R35), the twenty-eighth resistor (R36), the twenty-ninth resistor (R37), the thirty-first resistor (R41) and the thirty-first resistor (R41) are respectively connected with the anodes of the light emitting diode five (LED 5), the light emitting diode six (LED 6), the light emitting diode seven (LED 7), the light emitting diode eight (LED 8), the light emitting diode nine (LED 9) and the light emitting diode ten (LED 10), the cathodes of the light emitting diode five (LED 5), the light emitting diode six (LED 6), the light emitting diode seven (LED 7), the light emitting diode eight (LED 8), the light emitting diode nine (LED 9) and the light emitting diode ten (LED 10) are combined and connected with the 14-th port of the connecting terminal five (J5), the 15-th port of the connecting terminal five (J5) is connected with the 2-th port and the 8-th port of the connecting terminal four (J3), the 11-th port of the five (J5) is connected with, the No. 7 port of the terminal five (J5) is connected with the No. 4 port of the terminal four (J3), and the No. 8 port of the terminal five (J5) is connected with the No. 5 port of the terminal four (J3).

7. The upper tube embedded type micro multifunctional switch as claimed in claim 1, wherein: the mainboard power supply circuit comprises a chip III (U3), a chip IV (U4), a wiring terminal VI (P4) and a wiring terminal VII (J2), wherein the model of the chip III (U3) is LDO (HT7533-1), the model of the chip IV (U4) is LDO (HT7550-1), the port 1 of the wiring terminal VI (P4) is respectively connected with the anodes of a diode II (D1) and a diode III (D2), the cathodes of the diode II (D1) and the diode III (D2) are respectively connected with one ends of a resistor thirty-two (R18) and a resistor thirty-three (R19), the other end of the resistor thirty-two (R18) is connected with the port 1 of the wiring terminal VII (J2), the other end of the resistor thirty-three (R19) is respectively connected with one end of a triode I (Q5), one end of a resistor thirty-four (R20) and one end of a resistor thirty-five (R21), and the other end of the resistor 85Q 20 is connected with a collector of a triode 3, the other end of the resistor thirty-five (R21) is connected with the base of the triode II (Q3) and the cathode of the zener diode II (ZD 3), the emitter of the triode II (Q3) is connected with the base of the triode I (Q5), the emitter of the triode I (Q5) is respectively connected with the cathode of the zener diode III (ZD 2), the port 2 of the chip III (U3), the port 2 of the chip IV (U4) and one end of the capacitor eleven (C18), the port 3 of the chip IV (U4) is respectively connected with the port 3 of the connecting terminal seven (J2), the port twelve (C16) and one end of the capacitor thirteen (C17), the anode of the zener diode II (ZD 3), the anode of the zener diode III (2), the port 1 of the chip IV (U4), the capacitor eleven (C18), the twelve (C16) and the other end of the capacitor thirteen (C17) are merged and grounded;

the No. 2 port of the chip III (U3) is connected with one end of a capacitor fourteen (C21), the No. 3 port of the chip III (U3) is respectively connected with the No. 7 port of a connecting terminal seven (J2), one end of a capacitor fifteen (C19) and one end of a capacitor sixteen (C20), and the No. 1 port of the chip III (U3), the other end of the capacitor fourteen (C21), the other end of the capacitor fifteen (C19) and the other end of the capacitor sixteen (C20) are combined and grounded;

the No. 4 port of the six wiring terminal (P4) is connected with the No. 6 port of the seven wiring terminal (J2), the No. 6 port and the No. 7 port of the six wiring terminal (P4) are merged and grounded, the No. 5 port of the six wiring terminal (P4) is respectively connected with one end of a resistor thirty-six (R36) and grounded, and the other end of the resistor thirty-six (R36) is respectively connected with the No. 2 port, the No. 8 port and grounded of the seven wiring terminal (J2).

8. The upper tube embedded type micro multifunctional switch as claimed in claim 1, wherein: the CAN communication circuit comprises a chip five (U2), the model of the chip five (U2) is a CAN communication chip (TJA1057T), the port 1 of the chip five (U2) is connected with the port 5 of the connecting terminal seven (J2), the port 4 of the chip five (U2) is connected with the port 4 of the connecting terminal seven (J2), the port 2 of the chip five (U2) is grounded, the port 3 of the chip five (U2) is respectively connected with the port 3 of the connecting terminal seven (J2), one end of a capacitor seventeen (C5), one end of a capacitor eighteen (C6) and one end of a capacitor nineteen (C7), and the other ends of the capacitor seventeen (C5), the capacitor eighteen (C6) and the capacitor nineteen (C7) are grounded in a combined mode; the No. 8 port of the chip five (U2) is grounded; a No. 7 port of the chip five (U2) is respectively connected with one ends of a resistor thirty-seven (R7) and a resistor thirty-eight (R11), and the other end of the resistor thirty-eight (R11) is respectively connected with one end of a capacitor twenty (C9), one end of a bicolor breakdown diode I (FD 1) and a No. 2 port of a connecting terminal six (P4); the No. 6 port of the chip five (U2) is respectively connected with one ends of a resistor thirty-nine (R15) and a resistor forty (R13), and the other end of the resistor forty (R13) is respectively connected with one end of a capacitor twenty-one (C8), one end of a two-color breakdown diode two (FD 2) and the No. 3 port of a connecting terminal six (P4); the other ends of the first bicolor breakdown diode (FD 1), the second bicolor breakdown diode (FD 2), the twenty capacitor (C9) and the twenty-one capacitor (C8) are grounded in a combined mode; the other ends of the resistor thirty-seven (R7) and the resistor thirty-nine (R15) are connected with one end of the capacitor twenty-two (C3), and the other end of the capacitor twenty-two (C3) is grounded.

Technical Field

The invention relates to the technical field of electric bicycles, in particular to an upper tube embedded type miniature multifunctional switch.

Background

The traditional electric bicycle can only be driven by a lithium battery pack installed in part of pipelines, the control aspect of the traditional electric bicycle is simpler, due to the limitation of pipeline space, excessive functions cannot be added on the switch of the traditional electric bicycle, the manufactured electric bicycle can only achieve the efficiency of a simple lamp switch, if a customer wants further functions, no way is available, and the electric bicycle cannot attract a large number of customers in terms of the functions.

Disclosure of Invention

The invention provides an upper tube embedded type micro multifunctional switch, which overcomes the defects of the prior art, wherein a switch control module is made into an integrated structure, an upper cover, a lower cover and a switch fixing seat of the switch are made into an embedded type, a set of multifunctional switches are all embedded in a pipeline of an electric bicycle, and a plurality of functions are added on the basis of attractive appearance, so that the overall performance of the electric bicycle is improved.

For realizing above-mentioned purpose, design a miniature multi-functional switch of upper tube mosaic type, including upper cover, lower cover, switch fixing base, frame top tube, its characterized in that: a switch fixing seat is embedded in the upper part of one end of the upper frame tube, a lower cover is embedded in the switch fixing seat, the upper end of the lower cover is connected with the upper cover through ultrasonic welding, and a key control module is arranged between the upper cover and the lower cover; a switch wire harness is arranged in the upper pipe of the frame and is connected with the key control module through a circuit penetrating through the switch fixing seat and the lower cover; the key control module is provided with a master control logic circuit, a key and lamp panel circuit, a mainboard power supply circuit and a CAN communication circuit.

The upper cover is of a long strip-shaped structure, the annular lamp strip is arranged at the upper end of the upper cover, and the inner side of the annular lamp strip is sequentially provided with a key, an indicator light and another key from left to right.

The front side and the rear side of the lower cover are respectively provided with a buckle, the front side and the rear side of the switch fixing seat are respectively provided with a clamping groove, and the lower cover is connected with the clamping grooves of the switch fixing seat through the buckles.

The frame upper tube is of a long strip-shaped structure, and the cross section of the frame upper tube is of a triangular hollow structure.

The main control logic circuit comprises a first chip, a second chip, a first wiring terminal, a second wiring terminal and a third wiring terminal, wherein the type of the first chip is MCU (APM32F103TBU6), the type of the second chip is MCU (APM32F103TBU6), a port 2 of the first chip and one end of a first capacitor are combined and connected with one end of a crystal oscillator, a port 3 of the first chip and one end of the second capacitor are combined and connected with the other end of the crystal oscillator, and the other ends of the first capacitor and the second capacitor are combined and grounded; the No. 35 port of the first chip is connected with one end of a first resistor, and the other end of the first resistor is grounded; the No. 4 port of the first chip is connected with the No. 5 port of the second wiring terminal, the second resistor and one end of the third capacitor respectively, and the other end of the third capacitor is grounded; the other end of the second resistor is connected with the port 1 of the second connecting terminal and the port 3 of the first connecting terminal; the No. 7 port of the first chip is connected with one end of a third resistor, the other end of the third resistor is respectively connected with one end of a fourth resistor and the drain electrode of the first power tube, the other end of the fourth resistor is respectively connected with the No. 1 port of a second connecting terminal and the No. 3 port of the first connecting terminal, the gate pole of the first power tube is respectively connected with one end of the fourth capacitor, the cathode of the first voltage stabilizing diode, the fifth resistor and one end of the sixth resistor, and the source electrode of the first power tube, the other end of the fourth capacitor, the anode of the first voltage stabilizing diode and the other end of the fifth; the other end of the resistor six is connected with one end of the resistor seven, the other end of the resistor seven is connected with the cathode of the diode I, and the anode of the diode I is connected with the No. 5 port of the wiring terminal I; the No. 8 port of the first chip is connected with one end of the eighth resistor, the No. 33 port of the first chip is respectively connected with the No. 3 port of the third connecting terminal and one end of the ninth resistor, the No. 34 port of the first chip is respectively connected with the No. 2 port of the third connecting terminal and one end of the tenth resistor, and the other ends of the eighth resistor, the ninth resistor and the tenth resistor are combined and respectively connected with the No. 1 port of the second connecting terminal and the No. 3 port of the first connecting terminal; the No. 23 port of the first chip is connected with the No. 9 port of the first connecting terminal and one end of the first resistor, the No. 24 port of the first chip is connected with the No. 8 port of the first connecting terminal and one end of the twelfth resistor, and the other ends of the eleventh resistor and the twelfth resistor are connected with the No. 1 port of the second connecting terminal and the No. 3 port of the first connecting terminal in a combined mode; the No. 3 port of the wiring terminal III is grounded; the 25 th port of the first chip is connected with the 2 nd port of the second connecting terminal, the 28 th port of the first chip is connected with the 3 rd port of the second connecting terminal, and the 4 th port of the second connecting terminal is grounded; the No. 20 port of the chip I is connected with one end of a resistor thirteen, the other end of the resistor thirteen is respectively connected with one end of a resistor fourteen and a gate pole of a power tube II, a drain electrode of the power tube II is connected with the No. 2 port of a wiring terminal I, and a source electrode of the power tube II and the other end of the resistor fourteen are merged and grounded; the port 17 of the first chip is connected with the port 6 of the first connecting terminal, the port 10 of the first chip is connected with the port 15 of the first connecting terminal, the port 11 of the first chip is connected with the port 14 of the first connecting terminal, the port 12 of the first chip is connected with the port 13 of the first connecting terminal, the port 13 of the first chip is connected with the port 12 of the first connecting terminal, the port 14 of the first chip is connected with the port 11 of the first connecting terminal, the port 15 of the first chip is connected with the port 10 of the first connecting terminal, the port 16 of the first chip is connected with the port 7 of the first connecting terminal, the port 8 of the first chip is connected with the port 4 of the first connecting terminal, and the port 1 of the first connecting terminal is grounded; the ports No. 6, No. 19, No. 27 and No. 1 of the chip II are combined and respectively connected with one ends of the capacitor five, the capacitor six, the capacitor seven, the capacitor eight and the capacitor nine, the ports No. 5, No. 18, No. 26 and No. 36 of the chip II are combined and respectively connected with the other ends of the capacitor five, the capacitor six, the capacitor seven, the capacitor eight and the capacitor nine, one ends of the capacitor five, the capacitor six, the capacitor seven, the capacitor eight and the capacitor nine are combined and connected with the port No. 1 of the connecting terminal two and the port No. 3 of the connecting terminal one, and the other ends of the capacitor five, the capacitor six, the capacitor seven, the capacitor eight and the.

The button and lamp panel circuit comprises a fourth wiring terminal and a fifth wiring terminal, wherein the port 1 of the fourth wiring terminal is connected with one end of the first switch, and the other end of the first switch is connected with the port 6 of the fourth wiring terminal; the No. 7 port of the connecting terminal IV is connected with one end of a resistor fifteen, the other end of the resistor fifteen is respectively connected with one end of a switch II, one end of a capacitor ten and the No. 12 port of the connecting terminal V, and the other ends of the switch II and the capacitor ten are combined and grounded; the No. 10 port of the connecting terminal five and the No. 9 port of the connecting terminal five are connected with the cathode of the first bicolor light-emitting diode in a combining way, the anode of the first bicolor light-emitting diode is respectively connected with one end of a resistor sixteen and one end of a resistor seventeen, the No. 6 port of the connecting terminal five and the No. 5 port of the connecting terminal five are connected with the cathode of the second bicolor light-emitting diode in a combining way, the anode of the second bicolor light-emitting diode is respectively connected with one end of a resistor eighteen and one end of a resistor nineteen, the No. 4 port of the connecting terminal five and the No. 3 port of the connecting terminal five are connected with the cathode of the third bicolor light-emitting diode in a combining way, the anode of the third bicolor light-emitting diode is respectively connected with one end of a resistor twenty and one, the other ends of the resistor sixteen, the resistor seventeen, the resistor eighteen, the resistor nineteen, the resistor twenty-one, and the resistor twenty-three are combined and connected with one end of the resistor twenty-four and a port 13 of the connecting terminal five, the port four 3 of the connecting terminal is connected with one end of the resistor twenty-five, the other ends of the resistor twenty-four and the resistor twenty-five are respectively connected with one ends of the resistor twenty-six, the resistor twenty-seven, the resistor twenty-eighteen, the resistor twenty-nine, the resistor thirty and the resistor thirty-five, the other ends of the resistor twenty-six, the resistor twenty-seven, the resistor twenty-eighteen, the resistor twenty-nine, the resistor thirty and the resistor thirty-five are respectively connected with anodes of the light emitting diode five, the light emitting diode six, the light emitting diode seven, the light emitting diode eight, the light, The cathodes of the nine light-emitting diodes and the ten light-emitting diodes are combined and connected with the 14 th port of the five wiring terminal, the 15 th port of the five wiring terminal is connected with the 2 nd port and the 8 th port of the four wiring terminal, the 11 th port of the five wiring terminal is connected with the 6 th port of the four wiring terminal, the 7 th port of the five wiring terminal is connected with the 4 th port of the four wiring terminal, and the 8 th port of the five wiring terminal is connected with the 5 th port of the four wiring terminal.

The mainboard power supply circuit comprises a chip III, a chip IV, a wiring terminal VI and a wiring terminal VII, wherein the model of the chip III is LDO (HT7533-1), the model of the chip IV is LDO (HT7550-1), the port 1 of the wiring terminal VI is respectively connected with the anodes of a diode II and a diode III, the cathodes of the diode II and the diode III are respectively connected with one ends of a resistor thirty-two and a resistor thirty-three, the other end of the resistor thirty-two is connected with the port 1 of the wiring terminal VII, the other end of the resistor thirty-three is respectively connected with the collector of a triode I, one end of a resistor thirty-four and one end of a resistor thirty-five, the other end of the resistor thirty-four is connected with the collector of a triode II, the other end of the resistor thirty-five is connected with the base of the triode II and the cathode of a voltage stabilizing diode II, the emitter, The port 2 of the chip III, the port 2 of the chip IV and one end of the capacitor eleven are connected, the port 3 of the chip IV is respectively connected with the port 3 of the wiring terminal VII, one end of the capacitor twelve and one end of the capacitor thirteen, and the anode of the voltage stabilizing diode II, the anode of the voltage stabilizing diode III, the port 1 of the chip IV, the other end of the capacitor eleven and the other end of the capacitor thirteen are merged and grounded; the port 2 of the chip III is connected with one end of the capacitor fourteen, the port 3 of the chip III is respectively connected with the port 7 of the wiring terminal seven, the capacitor fifteen and one end of the capacitor sixteen, and the port 1 of the chip III, the capacitor fourteen, the capacitor fifteen and the other end of the capacitor sixteen are combined and grounded; no. 4 port of the sixth wiring terminal is connected with No. 6 port of the seventh wiring terminal, the No. 6 port and the No. 7 port of the sixth wiring terminal are merged and grounded, the No. 5 port of the sixth wiring terminal is respectively connected with one end of a resistor thirty-six and grounded, and the other end of the resistor thirty-six is respectively connected with the No. 2 port, the No. 8 port of the seventh wiring terminal and grounded.

The CAN communication circuit comprises a fifth chip, wherein the model of the fifth chip is a CAN communication chip (TJA1057T), a port 1 of the fifth chip is connected with a port 5 of a connecting terminal seven, a port 4 of the fifth chip is connected with a port 4 of the connecting terminal seven, a port 2 of the fifth chip is grounded, a port 3 of the fifth chip is respectively connected with a port 3 of the connecting terminal seven, a capacitor seventeen, a capacitor eighteen and one end of a capacitor nineteen, and the other ends of the capacitor seventeen, the capacitor eighteen and the capacitor nineteen are grounded in a combined mode; the No. 8 port of the chip five is grounded; the No. 7 port of the chip five is respectively connected with one end of a resistor thirty-seven and one end of a resistor thirty-eight, and the other end of the resistor thirty-eight is respectively connected with one end of a capacitor twenty, one end of a bicolor breakdown diode I and the No. 2 port of a wiring terminal six; the No. 6 port of the chip five is respectively connected with one end of a resistor thirty-nine and one end of a resistor forty, and the other end of the resistor forty is respectively connected with one end of a capacitor twenty-one, one end of a two-color breakdown diode two and the No. 3 port of a wiring terminal six; the other ends of the first bicolor breakdown diode, the second bicolor breakdown diode, the twenty capacitor and the twenty-one capacitor are combined and grounded; and the other ends of the thirty-seven and thirty-nine resistors are combined and connected with one end of the twenty-two capacitor, and the other end of the twenty-two capacitor is grounded.

Compared with the prior art, the upper tube embedded type miniature multifunctional switch is provided, the switch control module is made into an integrated structure, the upper cover, the lower cover and the switch fixing seat of the switch are made into an embedded type, a set of multifunctional switch is completely embedded in a pipeline of an electric bicycle, multiple functions are added on the basis of attractive appearance, and the overall performance of the electric bicycle is improved.

Drawings

FIG. 1 is a schematic view of the structure of the present invention.

Fig. 2 is a schematic structural view of the upper cover.

Fig. 3 is a schematic structural view of the lower cover.

Fig. 4 is a schematic structural view of the switch holder.

FIG. 5 is a schematic diagram of a main control logic circuit in the key control module according to the present invention.

Fig. 6 is a schematic diagram of circuits of a key and a lamp panel in the key control module according to the present invention.

Fig. 7 is a schematic diagram of a motherboard power supply circuit in the key control module according to the present invention.

Fig. 8 is a schematic diagram of a CAN communication circuit in the key control module according to the present invention.

Referring to fig. 1 to 4, 1 is an upper cover, 1-1 is a ring-shaped lamp strip, 1-2 is a key, 1-3 is an indicator light, 1-4 is another key, 2 is a key control module, 3 is a lower cover, 3-1 is a buckle, 4 is a switch fixing seat, 4-1 is a clamping groove, 5 is a switch wiring harness, and 6 is an upper frame tube.

Detailed Description

The invention is further illustrated below with reference to the accompanying drawings.

As shown in fig. 1 to 8, a switch fixing seat 4 is embedded in the upper portion of one end of an upper tube 6 of a frame, a lower cover 3 is embedded in the switch fixing seat 4, the upper end of the lower cover 3 is connected to an upper cover 1 through ultrasonic welding, and a key control module 2 is arranged between the upper cover 1 and the lower cover 3; a switch wiring harness 5 is arranged in the upper frame pipe 6, and the switch wiring harness 5 penetrates through the switch fixing seat 4 and the lower cover 3 through a circuit to be connected with the key control module 2; the key control module 2 is provided with a main control logic circuit, a key and lamp panel circuit, a mainboard power supply circuit and a CAN communication circuit.

The upper cover 1 is of a long strip-shaped structure, the annular lamp strip 1-1 is arranged at the upper end of the upper cover 1, and the key 1-2, the indicator lamp 1-3 and the other key 1-4 are sequentially arranged on the inner side of the annular lamp strip 1-1 from left to right.

The front side and the rear side of the lower cover 3 are respectively provided with a buckle 3-1, the front side and the rear side of the switch fixing seat 4 are respectively provided with a clamping groove 4-1, and the lower cover 3 is connected with the clamping groove 4-1 of the switch fixing seat 4 through the buckle 3-1.

The upper frame tube 6 is of a long strip structure, and the cross section of the upper frame tube 6 is of a triangular hollow structure.

The master control logic circuit comprises a first chip U1A, a second chip U1B, a first connecting terminal J1, a second connecting terminal P2 and a third connecting terminal P3, wherein the type of the first chip U1A is MCU (APM32F103TBU6), the type of the second chip U1B is MCU (APM32F103TBU6), a No. 2 port of the first chip U1A and one end of a first capacitor C1 are combined and connected with one end of a crystal oscillator Y1, a No. 3 port of the first chip U1A and one end of a second capacitor C2 are combined and connected with the other end of the crystal oscillator Y1, and the other ends of the first capacitor C1 and the second capacitor C2 are combined and grounded; the No. 35 port of the first chip U1A is connected with one end of a first resistor R9, and the other end of the first resistor R9 is grounded; the No. 4 port of the first chip U1A is respectively connected with the No. 5 port of the second connecting terminal P2, the second resistor R2 and one end of the third capacitor C4, and the other end of the third capacitor C4 is grounded; the other end of the second resistor R2 is connected with the port No. 1 of the second connecting terminal P2 and the port No. 3 of the first connecting terminal J1; a No. 7 port of a first chip U1A is connected with one end of a resistor three R8, the other end of the resistor three R8 is connected with one end of a resistor four R4 and a drain electrode of a power tube one Q1, the other end of a resistor four R4 is connected with a No. 1 port of a connecting terminal two P2 and a No. 3 port of a connecting terminal one J1, a gate electrode of the power tube one Q1 is connected with one end of a capacitor four C10, a cathode of a zener diode one ZD1, a resistor five R16 and one end of a resistor six R10, a source electrode of the power tube one Q1, the other end of the capacitor four C10, an anode of the zener diode one ZD1 and the other end of the resistor five R16 are grounded; the other end of the six R10 resistor is connected with one end of the seven R5 resistor, the other end of the seven R5 resistor is connected with the cathode of the first diode D3, and the anode of the first diode D3 is connected with the No. 5 port of the first connecting terminal J1; the No. 8 port of the first chip U1A is connected with one end of a resistor eight R34, the No. 33 port of the first chip U1A is respectively connected with the No. 3 port of a connecting terminal three P3 and one end of a resistor nine R3, the No. 34 port of the first chip U1A is respectively connected with the No. 2 port of a connecting terminal three P3 and one end of a resistor ten R1, and the other ends of the resistor eight R34, the resistor nine R3 and the resistor ten R1 are respectively connected with the No. 1 port of a connecting terminal two P2 and the No. 3 port of a connecting terminal one J1 in a combined mode; the No. 23 port of the first chip U1A is connected with the No. 9 port of the first connecting terminal J1 and one end of a resistor eleven R14 respectively, the No. 24 port of the first chip U1A is connected with the No. 8 port of the first connecting terminal J1 and one end of a resistor twelve R12 respectively, and the other ends of the resistor eleven R14 and the resistor twelve R12 are connected with the No. 1 port of the second connecting terminal P2 and the No. 3 port of the first connecting terminal J1 in a combined mode; the No. 3 port of the connecting terminal three P3 is grounded; the No. 25 port of the first chip U1A is connected with the No. 2 port of the second connecting terminal P2, the No. 28 port of the first chip U1A is connected with the No. 3 port of the second connecting terminal P2, and the No. 4 port of the second connecting terminal P2 is grounded; the No. 20 port of the first chip U1A is connected with one end of a resistor thirteen R17, the other end of the resistor thirteen R17 is respectively connected with one end of a resistor fourteen R28 and the gate of a power tube two Q4, the drain electrode of the power tube two Q4 is connected with the No. 2 port of a wiring terminal I J1, and the source of the power tube two Q4 and the other end of the resistor fourteen R28 are combined and grounded; a port 17 of the first chip U1A is connected with a port 6 of the first connecting terminal J1, a port 10 of the first chip U1A is connected with a port 15 of the first connecting terminal J1, a port 11 of the first chip U1A is connected with a port 14 of the first connecting terminal J1, a port 12 of the first chip U1A is connected with a port 13 of the first connecting terminal J1, a port 13 of the first chip U1A is connected with a port 12 of the first connecting terminal J1, a port 14 of the first chip U1A is connected with a port 11 of the first connecting terminal J1, a port 15 of the first chip U1A is connected with a port 10 of the first connecting terminal J1, a port 16 of the first chip U1A is connected with a port 7 of the first connecting terminal J1, a port 8 of the first chip U1A is connected with a port 4 of the first connecting terminal J1, and a port 1 of the first J1 is grounded; ports No. 6, 19, 27 and 1 of the second chip U1B are combined and respectively connected with one end of a capacitor five C15, a capacitor six C14, a capacitor seven C13, a capacitor eight C12 and a capacitor nine C11, ports No. 5, 18, 26 and 36 of the second chip U1B are combined and respectively connected with the other ends of a capacitor five C15, a capacitor six C14, a capacitor seven C13, a capacitor eight C12 and a capacitor nine C11, one ends of a capacitor five C15, a capacitor six C14, a capacitor seven C13, a capacitor eight C12 and a capacitor nine C11 are combined and connected with a port No. 1 of the second connecting terminal P2 and a port No. 3 of the first connecting terminal J1, and the other ends of a capacitor five C15, a capacitor six C14, a capacitor seven C13, a capacitor eight C12 and a capacitor nine C11 are combined and grounded.

The key and lamp panel circuit comprises a connecting terminal four J3 and a connecting terminal five J5, wherein the port 1 of the connecting terminal four J3 is connected with one end of a switch one SW1, and the other end of the switch one SW1 is connected with the port 6 of the connecting terminal four J3; the No. 7 port of the connection terminal four J3 is connected with one end of a resistor fifteen R24, the other end of the resistor fifteen R24 is respectively connected with one end of a switch two SW2, one end of a capacitor ten C22 and the No. 12 port of the connection terminal five J5, and the other ends of the switch two SW2 and the capacitor ten C22 are combined and grounded; the 10 port of the connecting terminal five J5 and the 9 port of the connecting terminal five J5 are connected with the cathode of the first bicolor LED1 in a combined manner, the anode of the first bicolor LED1 is connected with one end of the resistors sixteen R25 and seventeen R26 respectively, the 6 port of the connecting terminal five J5 and the 5 port of the connecting terminal five J5 are connected with the cathode of the second bicolor LED2 in a combined manner, the anode of the second bicolor LED2 is connected with one end of the resistors eighteen R27 and nineteen R29 respectively, the 4 port of the connecting terminal five J5 and the 3 port of the connecting terminal five J5 are connected with the cathode of the third bicolor LED3 in a combined manner, the anode of the third bicolor LED3 is connected with one end of the resistors twenty R30 and one end of the resistor twenty-one R31 respectively, the 2 port of the connecting terminal five J5 and the 1 port of the fifth J5 are connected with the cathode of the fourth LED4 of the bicolor LED, the anode of the fourth LED 828653 and the twelve R8653, the other ends of the resistor sixteen R25, the resistor seventeen R26, the resistor eighteen R27, the resistor nineteen R29, the resistor twenty-one R29, the resistor twenty-two R29 and the resistor twenty-three R29 are connected with one end of the resistor twenty-four R29 and a port 13 of the connecting terminal fifty J29 in a combined manner, the port of the connecting terminal forty J29 is connected with one end of the resistor twenty-five R29, the other ends of the resistor twenty-four R29 and the resistor twenty-five R29 are respectively connected with one end of the resistor twenty-six R29, the resistor twenty-seven R29, the resistor twenty-nine R29, the resistor thirty-nine R29 and the resistor thirty-one end of the resistor thirty-one R29, the other ends of the resistor twenty-six R29, the resistor twenty-seven R29, the resistor thirty R29, the LED anode of the LED 29 and the LED 29, the cathodes of the five light-emitting diodes 5, the six light-emitting diodes 6, the seven light-emitting diodes 7, the eight light-emitting diodes 8, the nine light-emitting diodes 9 and the ten light-emitting diodes 10 are combined and connected with the 14 th port of the five connecting terminal J5, the 15 th port of the five connecting terminal J5 is connected with the 2 nd port and the 8 th port of the four connecting terminal J3, the 11 th port of the five connecting terminal J5 is connected with the 6 th port of the four connecting terminal J3, the 7 th port of the five connecting terminal J5 is connected with the 4 th port of the four connecting terminal J3, and the 8 th port of the five connecting terminal J5 is connected with the 5 th port of the four connecting terminal J46.

The mainboard power supply circuit comprises a chip three U3, a chip four U4, a connection terminal six P4 and a connection terminal seven J2, wherein the model of the chip three U3 is LDO (HT7533-1), the model of the chip four U4 is LDO (HT7550-1), the port 1 of the connection terminal six P4 is respectively connected with the anodes of a diode two D1 and a diode three D2, the cathodes of a diode two D1 and a diode three D2 are respectively connected with one end of a resistor thirty-two R18 and a resistor thirty-three R19, the other end of the resistor thirty-two R18 is connected with the port 1 of a connection terminal seven J2, the other end of the resistor thirty-three R19 is respectively connected with the collector of a triode one Q5, one end of a resistor thirty-four R20 and one end of a resistor thirty-five R21, the other end of the resistor thirty-four R20 is connected with the collector of a triode two Q3, the other end of the base of the triode two Q21 is connected with the emitter of a triode 21 and the cathode of a triode 21, an emitter of the triode I Q5 is respectively connected with a cathode of a zener diode three ZD2, a port 2 of a chip three U3, a port 2 of a chip four U4 and one end of a capacitor eleven C18, a port 3 of a chip four U4 is respectively connected with a port 3 of a connecting terminal seven J2, one end of a capacitor twelve C16 and one end of a capacitor thirteen C17, and the other ends of an anode of a zener diode two ZD3, an anode of the zener diode three ZD2, a port 1 of a chip four U4, a capacitor eleven C18, a capacitor twelve C16 and a capacitor thirteen C17 are grounded in a combined mode;

the No. 2 port of the chip three U3 is connected with one end of a capacitor fourteen C21, the No. 3 port of the chip three U3 is respectively connected with the No. 7 port of a connecting terminal seven J2, one end of a capacitor fifteen C19 and one end of a capacitor sixteen C20, and the other ends of the No. 1 port of the chip three U3, the other end of the capacitor fourteen C21, the other end of the capacitor fifteen C19 and the other end of the capacitor sixteen C20 are combined and grounded; no. 4 port of the connecting terminal six P4 is connected with No. 6 port of the connecting terminal seven J2, No. 6 port and No. 7 port of the connecting terminal six P4 are merged and grounded, No. 5 port of the connecting terminal six P4 is connected with one end of a resistor thirty-six R36 and grounded respectively, and the other end of the resistor thirty-six R36 is connected with No. 2 port, No. 8 port and grounded of the connecting terminal seven J2 respectively.

The CAN communication circuit comprises a five-chip U2, the five-chip U2 is a CAN communication chip (TJA1057T), a port 1 of the five-chip U2 is connected with a port 5 of a connecting terminal seven J2, a port 4 of the five-chip U2 is connected with a port 4 of a connecting terminal seven J2, a port 2 of the five-chip U2 is grounded, a port 3 of the five-chip U2 is respectively connected with a port 3 of a connecting terminal seven J2, a capacitor seventeen C5, a capacitor eighteen C6 and one end of a capacitor nineteen C7, and the other ends of the capacitor seventeen C5, the capacitor eighteen C6 and the capacitor nineteen C7 are grounded in a combined mode; the No. 8 port of the five chip U2 is grounded; a No. 7 port of the chip five U2 is respectively connected with one ends of a resistor thirty-seven R7 and a resistor thirty-eight R11, and the other end of the resistor thirty-eight R11 is respectively connected with one end of a capacitor twenty C9, one end of a two-color breakdown diode one FD1 and a No. 2 port of a wiring terminal six P4; a No. 6 port of the chip five U2 is respectively connected with one end of a resistor thirty-nine R15 and one end of a resistor forty R13, and the other end of the resistor forty R13 is respectively connected with one end of a capacitor twenty-one C8, one end of a two-color breakdown diode two FD2 and a No. 3 port of a wiring terminal six P4; the other ends of the first two-color breakdown diode FD1, the second two-color breakdown diode FD2, the capacitor twenty C9 and the capacitor twenty-one C8 are grounded in a combined mode; the other ends of the resistor thirty-seven R7 and the resistor thirty-nine R15 are connected with one end of the capacitor twenty-two C3, and the other end of the capacitor twenty-two C3 is grounded.

1. The main logic circuit part is described in a function mode: the key detection is mainly responsible for, drive lamp plate shows electric quantity information, communicates with the BMS.

2. Partial function description of the key and lamp panel circuit: the button is responsible for giving logic circuit part input signal, and the lamp plate is responsible for showing the current electric quantity of battery package. I.e. one blue light represents 25%; two blue lamps represent 50%; three blue lamps represent 75%; four blue lamps represent 25%.

And 6 blue background lights are also arranged, and when the battery pack is in a normal working state, the blue background lights are normally on.

3. Partial functional description of the main board power supply circuit: the power supply circuit mainly comprises a 3.3V power supply and a 5.0V power supply, wherein the 3.3V power supply supplies power to the MCU, and the 5.0V power supply supplies power to the CAN communication circuit.

Functional description of part of the CAN communication circuit: the CAN communication circuit is mainly responsible for communication between the MCU in the circuit and the MCU in the battery pack.

And 6 blue background lights are also arranged, and when the battery pack is in a normal working state, the blue background lights are normally on.

5. Description of the logical function: after pressing ON/OFF button 1S for a long time, the ON/OFF button gives switch board MCU and BMS board MCU a signal simultaneously, BMS board MCU detects and can get into the mode after the button, the MCU of switch board can pass through U3 simultaneously, U4 obtains the power and then begins work, at first can carry out the self-checking to lamp (LED1-4) lamp, turn OFF lamp (LED1-4) after the self-checking, light (LED5-10) backlight simultaneously, then MCU can communicate with the MCU in the battery package through U2, obtain current electric quantity information, touch ON/OFF button once more this moment, lamp plate (LED1-4) can show current battery package electric quantity, extinguish after 5S, the backlight is normally bright this moment, the operating condition presses 3S and then gets into the low-power consumption mode, all lamps extinguish.