阅读说明：本技术 一种降低寄生电容的mos电容及优化方法 (MOS capacitor capable of reducing parasitic capacitance and optimization method ) 是由 刘新宁 潘家驹 于 2020-06-15 设计创作，主要内容包括：本发明提供了一种降低寄生电容的MOS电容和降低MOS电容寄生电容的优化方法,在MOS电容N-阱接触与偏置电压Vbias之间接入一高阻抗Z,使N-阱到P-衬底之间较小的电容等效串联入寄生电容(主要为沟道至N-阱之间的电容),从而降低MOS电容的总寄生电容,解决了MOS电容在开关电容等应用场景中寄生过大的问题。通过本发明提供的技术方案,MOS电容的寄生因子由10％-20％减小至1％-2％,降低了MOS电容的寄生电容,增加了MOS电容的有效电容密度。采用这种优化后的MOS电容能够节省电路面积,降低成本,提高电路性能。对于具体的开关电容转换器来说,能够提高电路的转换效率。(The invention provides an MOS capacitor for reducing parasitic capacitance and an optimization method for reducing the parasitic capacitance of the MOS capacitor, wherein a high impedance Z is connected between an N-well contact of the MOS capacitor and a bias voltage Vbias, so that a smaller capacitor between an N-well and a P-substrate is equivalently connected in series with the parasitic capacitance (mainly the capacitor between a channel and the N-well), thereby reducing the total parasitic capacitance of the MOS capacitor and solving the problem of overlarge parasitic of the MOS capacitor in application scenes such as a switch capacitor and the like. By the technical scheme provided by the invention, the parasitic factor of the MOS capacitor is reduced to 1-2% from 10-20%, the parasitic capacitance of the MOS capacitor is reduced, and the effective capacitance density of the MOS capacitor is increased. The MOS capacitor after being optimized can save the circuit area, reduce the cost and improve the circuit performance. For a specific switched capacitor converter, the conversion efficiency of the circuit can be improved.)

1. A MOS capacitor for reducing parasitic capacitance, comprising a P-type substrate, an N-well formed in the P-type substrate, a P + diffusion region formed in the P-type substrate, and an N + diffusion region formed in the N-well, wherein the P + diffusion region is connected to the lowest potential, the N + diffusion region is used as an N-well contact and is connected with a bias voltage, characterized in that: a high impedance module is connected between the N-well contact and the bias voltage, so that a smaller capacitor between the N-well and the P-type substrate is equivalently connected in series into a parasitic capacitor.

2. The MOS capacitor with reduced parasitic capacitance of claim 1, wherein: the MOS capacitor is a common capacitor and also comprises two P + diffusion regions formed in the N-well, an insulating layer covering the N-well and a polycrystalline silicon layer covering the insulating layer; the two P + diffusion regions are led out and connected to serve as anodes of the MOS capacitors, the grid electrodes are led out of the polycrystalline silicon layer and serve as cathodes of the MOS capacitors, a first parasitic capacitance is formed between the channels and the N-well, and a second parasitic capacitance is formed between the N-well and the P-type substrate.

3. The MOS capacitor with reduced parasitic capacitance of claim 1, wherein: the MOS capacitor is an accumulation type MOS capacitor and also comprises a P-well formed in an N-well, two P + diffusion regions formed in the P-well, an insulating layer covering the P-well and a polycrystalline silicon layer covering the insulating layer, wherein the two P + diffusion regions are led out and connected to serve as an anode of the MOS capacitor, a grid is led out from the polycrystalline silicon layer and serves as a cathode of the MOS capacitor, a first parasitic capacitor is arranged between the P-well and the N-well, and a second parasitic capacitor is arranged between the N-well and a P type substrate.

4. The MOS capacitor with reduced parasitic capacitance of claim 1, wherein: the MOS capacitor is an inverted MOS capacitor and further comprises a P-well formed in the N-well, two N + diffusion regions and a P + doping region formed in the P-well, an insulating layer covering the P-well and a polycrystalline silicon layer covering the insulating layer, the two N + diffusion regions and the P + doping region are led out and connected to serve as an anode of the MOS capacitor, a grid is led out of the polycrystalline silicon layer and serves as a cathode of the MOS capacitor, a first parasitic capacitor is arranged between the P-well and the N-well, and a second parasitic capacitor is arranged between the N-well and the P-type substrate.

5. The MOS capacitor with reduced parasitic capacitance of any one of claims 1-4, wherein: the high impedance module is a high impedance element or a high impedance circuit.

6. The MOS capacitor with reduced parasitic capacitance of claim 5, wherein: the high impedance element is a large resistance or a small capacitance.

7. The MOS capacitor with reduced parasitic capacitance of claim 5, wherein: the high impedance circuit comprises MOS tubes connected in a face-to-face diode fashion.

8. The MOS capacitor with reduced parasitic capacitance of claim 7, wherein: the high impedance circuit comprises a first PMOS tube and a second PMOS tube, wherein the source electrode of the first PMOS tube is connected with bias voltage, the grid electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the second PMOS tube is connected with the drain electrode of the second PMOS tube, and the source electrode of the first PMOS tube is connected with the N-well contact of the MOS capacitor.

9. The MOS capacitor with reduced parasitic capacitance of claim 1, wherein: the equivalent series-connected parasitic capacitance is the capacitance between the channel and the N-well.

10. An optimization method for reducing parasitic capacitance of a MOS capacitor is characterized by comprising the following steps:

a high impedance module is connected between the contact of the MOS capacitor N-well and the bias voltage, so that the smaller capacitance between the N-well and the P-substrate is equivalently connected in series with the parasitic capacitance.

Technical Field

The invention belongs to the technical field of electronic circuits, relates to a capacitor technology, and particularly relates to an MOS capacitor for reducing parasitic capacitance and an optimization method for reducing the parasitic capacitance of the MOS capacitor.

Background

The MOS capacitor mainly comprises a gate oxide capacitor inside the MOS tube and a depletion region capacitor formed between the gate and the substrate, thereby having high capacitance density of 4-12fF/um². The process flow for manufacturing the MOS capacitor is consistent with that of the common MOSFET, no extra mask layer is needed, and the manufacturing cost is the lowest. However, due to the influence of the manufacturing process, a large parasitic capacitance exists between the lower plate of the MOS capacitor and the substrate,the scale factor alpha is as high as 10% -20%, which also severely restricts the application space of the MOS capacitor.

Such MOS capacitors are used in various analog circuits, such as fly capacitors in switched capacitors DC-DC. A 2:1 series-parallel topology common in switched-capacitor converter circuits is given in fig. 1 (a). The operation principle and the influence of parasitic capacitance on the operation of the circuit will be briefly explained. In the charging phase, i.e., PE-a, the power supply charges the output terminal through the flying capacitor C1 under CLKA as shown in fig. 1 (b); during the discharging phase, i.e., PE-B, the charge accumulated in flying capacitor C1 will be discharged to the output terminal under CLKB, as shown in fig. 1 (C). Due to the existence of the parasitic capacitor Cbp, in a charging state, a power supply needs to transfer charges to the Cbp at the same time; in the discharge state, the charge accumulated by Cbp is directly discharged to the ground without being transferred to the output terminal, so Cbp wastes the charge from the power supply, resulting in a decrease in conversion efficiency. In an actual circuit simulation test, if the existing MOS capacitor is used as a flying capacitor, the conversion efficiency of the switched capacitor converter is limited due to an excessive parasitic factor.

Disclosure of Invention

In order to solve the problems, the invention provides an MOS capacitor for reducing parasitic capacitance and an optimization method for reducing the parasitic capacitance of the MOS capacitor, wherein a high impedance Z is connected between the contact of an N-well of the MOS capacitor and a bias voltage Vbias, so that a smaller capacitor between the N-well and a P-substrate is equivalently connected in series with the parasitic capacitance (mainly the capacitor between a channel and the N-well), thereby reducing the total parasitic capacitance of the MOS capacitor and solving the problem that the MOS capacitor is too large in application scenes such as a switch capacitor and the like.

In order to achieve the purpose, the invention provides the following technical scheme:

a MOS capacitor for reducing parasitic capacitance comprises a P-type substrate, an N-well formed in the P-type substrate, a P + diffusion region formed in the P-type substrate, and an N + diffusion region formed in the N-well, wherein the P + diffusion region is connected to the lowest potential, the N + diffusion region is used as an N-well contact and is connected with a bias voltage, a high-impedance module is connected between the N-well contact and the bias voltage, and a smaller capacitor between the N-well and the P-type substrate is equivalently connected in series into the parasitic capacitance.

Furthermore, the MOS capacitor is a common capacitor, and also comprises two P + diffusion regions formed in an N-well, an insulating layer covering the N-well, and a polysilicon layer covering the insulating layer; the two P + diffusion regions are led out and connected to serve as anodes of the MOS capacitors, the grid electrodes are led out of the polycrystalline silicon layer and serve as cathodes of the MOS capacitors, a first parasitic capacitance is formed between the channels and the N-well, and a second parasitic capacitance is formed between the N-well and the P-type substrate.

Furthermore, the MOS capacitor is an accumulation type MOS capacitor, and further comprises a P-well formed in the N-well, two P + diffusion regions formed in the P-well, an insulating layer covering the P-well, and a polycrystalline silicon layer covering the insulating layer, wherein the two P + diffusion regions are led out and connected to serve as an anode of the MOS capacitor, a grid is led out from the polycrystalline silicon layer and serves as a cathode of the MOS capacitor, a first parasitic capacitor is arranged between the P-well and the N-well, and a second parasitic capacitor is arranged between the N-well and the P-type substrate.

Furthermore, the MOS capacitor is an inverse MOS capacitor and also comprises a P-well formed in the N-well, two N + diffusion regions and a P + doping region formed in the P-well, an insulating layer covering the P-well and a polycrystalline silicon layer covering the insulating layer, wherein the two N + diffusion regions and the P + doping region are led out and connected to serve as an anode of the MOS capacitor, a grid is led out from the polycrystalline silicon layer and serves as a cathode of the MOS capacitor, a first parasitic capacitor is arranged between the P-well and the N-well, and a second parasitic capacitor is arranged between the N-well and the P-type substrate.

Further, the high impedance module is a high impedance element or a high impedance circuit.

Further, the high impedance element is a resistor or a capacitor.

Further, the high impedance circuit comprises MOS tubes connected in a face-to-face diode manner.

Further, the high impedance circuit comprises a first PMOS tube and a second PMOS tube, wherein a source electrode of the first PMOS tube is connected with a bias voltage, a grid electrode of the first PMOS tube is connected with a drain electrode of the second PMOS tube, the grid electrode of the second PMOS tube is connected with the drain electrode, and a source electrode of the first PMOS tube is connected with an N-well contact of the MOS capacitor.

Further, the equivalent series parasitic capacitance is the capacitance between the channel and the N-well.

An optimization method for reducing parasitic capacitance of MOS capacitor includes the following steps:

a high impedance module is connected between the contact of the MOS capacitor N-well and the bias voltage, so that the smaller capacitance between the N-well and the P-substrate is equivalently connected in series with the parasitic capacitance.

Further, the high impedance module is a high impedance element or a high impedance circuit.

Compared with the prior art, the invention has the following advantages and beneficial effects:

by the technical scheme provided by the invention, the parasitic factor of the MOS capacitor is reduced to 1-2% from 10-20%, the parasitic capacitance of the MOS capacitor is reduced, and the effective capacitance density of the MOS capacitor is increased. The MOS capacitor after being optimized can save the circuit area, reduce the cost and improve the circuit performance. For example, for a specific switched capacitor converter, the conversion efficiency of the circuit can be improved. The method is suitable for any scene of using the MOS capacitor.

Drawings

FIG. 1 is a schematic diagram of parasitic capacitance of a switched capacitor DC-DC2:1 topology.

Fig. 2 is a general schematic diagram of a MOS capacitor structure for reducing parasitic capacitance according to the present invention.

Fig. 3 is a schematic diagram of an equivalent of an original MOS capacitor parasitic capacitance and a MOS capacitor parasitic capacitance after an optimization scheme is adopted, where (a) is a schematic diagram of an equivalent of an original MOS capacitor parasitic capacitance, and (b) is a schematic diagram of an equivalent of an MOS capacitor parasitic capacitance after an optimization scheme is adopted.

Fig. 4 is a schematic diagram of an accumulation type capacitor structure adopting the optimization scheme of the invention.

Fig. 5 is a schematic diagram of an inversion-type capacitor structure adopting the optimization scheme of the invention.

Fig. 6 is a circuit structure diagram of the embodiment of the present invention in which a resistor is used as an optimization scheme.

Fig. 7 is a circuit structure diagram of the embodiment of the present invention in which a capacitor is used as an optimization scheme.

Fig. 8 is a circuit structure diagram and an equivalent schematic diagram of a high impedance circuit formed by MOS transistors as an optimization scheme in an embodiment of the present invention, where (a) is the circuit structure diagram, and (b) is the equivalent schematic diagram.

Detailed Description

The technical solutions provided by the present invention will be described in detail below with reference to specific examples, and it should be understood that the following specific embodiments are only illustrative of the present invention and are not intended to limit the scope of the present invention.

As shown in FIG. 2, the invention switches in a high impedance Z1 between the MOS capacitor N-well contact and the bias voltage Vbias, so that the smaller capacitance between the N-well and the P-substrate is equivalent to the series connection of the parasitic capacitance (mainly the capacitance between the channel and the N-well), thereby reducing the total parasitic capacitance.

Taking a general MOS capacitor as an example, the MOS capacitor structure for reducing the parasitic capacitance specifically includes: the N-well is formed in the P-type substrate, two P + diffusion regions are formed in the N-well and are led out to be connected to serve as an MOS capacitor anode Vtop, an N + diffusion region is formed in the N-well to serve as an N-well contact and is connected to a bias voltage Vbias, high impedance Z1 is connected between the N-well contact and the bias voltage Vbias, an insulating layer covers the N-well, a polycrystalline silicon layer covers the insulating layer, a grid is led out from the polycrystalline silicon layer and serves as a cathode Vbias of the MOS capacitor, a first parasitic capacitor C1 is a capacitor between a channel and the N-well, and a second parasitic capacitor C2 is a capacitor between the N-well and the P-type substrate.

As shown in fig. 3(a), before the optimization scheme provided by the present invention is not adopted, the equivalent parasitic capacitance of the MOS capacitor is the first parasitic capacitance C1 between the channel and the N-well, i.e., Cp — C1; after the optimization scheme provided by the present invention is adopted, as shown in fig. 3(b), under an ac condition, due to the access of a large impedance, a path from the bottom of C1 to Vbias is equivalent to an open circuit, in this case, C2 and C1 are equivalently connected in series, and then the equivalent parasitic capacitance is the value of series connection between C1 and C2, that is, Cp-C1-C2/(C1 + C2). Generally, the parasitic capacitance C2 between the N-well and the P-substrate is much smaller than the parasitic capacitance C1 between the channel and the N-well, i.e. C1>10C2, so the equivalent parasitic capacitance Cp after the C1 and the C2 are connected in series will be reduced, and the parasitic ratio of the MOS capacitance is reduced from 10% -20% to 1% -2%, thereby increasing the effective capacitance density of the MOS capacitance and making the MOS capacitance suitable for more scenes. For example, the PMOS capacitor under the TSMC28nmCMOS process is adopted for simulation verification: when the capacitance is 100pF, C1 is 12.6pF and C2 is 1.2 pF. Before the optimization scheme provided by the invention is not adopted, Cp-C1-12.6 pF and the parasitic factor is 12.6%; after the optimization scheme is adopted, due to the fact that C1 and C2 are equivalently connected in series, Cp is reduced to 1.1pF, and the parasitic factor is also reduced to 1.1%.

The MOS capacitor to which the present invention is applied may be an accumulation type capacitor. As shown in fig. 4, the structure is specifically as follows: the N-well is formed in the N-well and used as an N-well contact and connected with a bias voltage Vbias, high impedance Z1 is connected between the N-well contact and the bias voltage Vbias, the P-well is formed in the N-well, two P + diffusion regions are formed in the P-well and led out and connected to serve as an MOS capacitor anode Vtop, an insulating layer covers the P-well, a polycrystalline silicon layer covers the insulating layer, a grid is led out from the polycrystalline silicon layer and used as a MOS capacitor cathode Vbottom, a first parasitic capacitor C1 is a capacitor from the P-well to the N-well, and a second parasitic capacitor C2 is a capacitor from the N-well to the P-well.

The MOS capacitor to which the present invention is applied may be an inversion type capacitor. As shown in fig. 5, the structure is specifically as follows: the N-well is formed in the N-well and used as N-well contact and connected with a bias voltage Vbias, high-impedance Z1 is connected between the N-well contact and the bias voltage Vbias, the P-well is formed in the N-well, two N + diffusion regions and a P + doping region are formed in the P-well and led out and connected to serve as a MOS capacitor anode Vtop, an insulating layer covers the P-well, a polycrystalline silicon layer covers the insulating layer, a grid is led out from the polycrystalline silicon layer and used as a cathode Vbottom of the MOS capacitor, a first parasitic capacitor C1 is a capacitor between the P-well and the N-well, and a second parasitic capacitor C2 is a capacitor between the N-well and the P-type substrate.

The high impedance of the switch-in may be a large resistor as shown in fig. 6, or may be a small capacitor as shown in fig. 7,

the high impedance connected by the embodiment of the invention can be various circuit structures with high impedance, such as a circuit structure in which MOS tubes are connected in a face-to-face diode mode. As shown in fig. 8(a), the series connection of MOS transistors connected in the form of face-to-face diodes can provide a large equivalent impedance. The structure is as follows: the source electrode of the first PMOS tube is connected with a bias voltage Vbias, the grid electrode of the first PMOS tube is connected with the drain electrode and the drain electrode of the second PMOS tube, the grid electrode of the second PMOS tube is connected with the drain electrode, and the source electrode of the second PMOS tube is connected with the N-well contact of the MOS capacitor. The principle is as shown in 8(b), and the PMOS tubes are connected into a diode form and are connected in a back-to-face connection mode, so that one PMOS tube cannot be conducted from one end to the other end of the circuit structure, and therefore the circuit structure has high equivalent impedance. In the actual simulation test, compared with the use of a large resistor, the circuit structure has the same effect of reducing the parasitic capacitance of the MOS capacitor, and the area consumption is far less than that of the MOS capacitor, so that the circuit structure is a better choice in the conventional high-impedance circuit structure.

Fig. 6-8 are examples of a general MOS capacitor, and a large resistor, a small capacitor or other circuit structures with high impedance can also be applied to the accumulation-type capacitor and the inversion-type capacitor.

The embodiment of the invention is suitable for circuit scenes using MOS capacitors at will, such as switched capacitor DC-DC, and the circuit conversion efficiency can be improved by using the embodiment of the invention as a flying capacitor.

The technical means disclosed in the invention scheme are not limited to the technical means disclosed in the above embodiments, but also include the technical scheme formed by any combination of the above technical features. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and such improvements and modifications are also considered to be within the scope of the present invention.