阅读说明：本技术 具有降低的传输延迟的脉宽调制 (Pulse width modulation with reduced transmission delay ) 是由 D·哈默施密特 于 2021-03-31 设计创作，主要内容包括：本公开的各实施例涉及具有降低的传输延迟的脉宽调制。脉宽调制(PWM)输出级包括：数据源,被配置为生成数据信号；以及脉宽调制器,被配置为在多个采样时间处对数据信号进行采样,并且基于对应于多个采样时间的多个数据样本生成PWM信号。PWM信号包括具有第一时长的第一阶段和第二时长的第二阶段的PWM周期。脉宽调制器被配置为：在第一阶段之前的第一采样时间处对第一数据样本进行采样；基于第一数据样本设置PWM周期的第一时长和第二时长,在第二阶段期间的第二采样时间处对第二数据样本进行采样；并且基于第二数据样本调整第一PWM周期的第二时长。(Embodiments of the present disclosure relate to pulse width modulation with reduced transmission delay. A Pulse Width Modulation (PWM) output stage comprising: a data source configured to generate a data signal; and a pulse width modulator configured to sample the data signal at a plurality of sampling times and generate a PWM signal based on a plurality of data samples corresponding to the plurality of sampling times. The PWM signal includes a PWM cycle having a first phase of a first duration and a second phase of a second duration. The pulse width modulator is configured to: sampling a first data sample at a first sampling time prior to a first phase; setting a first duration and a second duration of the PWM cycle based on the first data sample, sampling the second data sample at a second sampling time during the second phase; and adjusting a second duration of the first PWM period based on the second data sample.)

1. A pulse width modulation, PWM, output stage comprising:

a data source configured to generate a data signal; and

a pulse width modulator configured to sample the data signal at a plurality of sampling times and generate a PWM signal based on a plurality of data samples corresponding to the plurality of sampling times,

wherein the PWM signal comprises a plurality of PWM cycles, each PWM cycle comprising a first phase of a first duration and a second phase of a second duration,

wherein the first duration and the second duration are variable,

wherein the plurality of PWM periods includes a first PWM period, an

Wherein the pulse width modulator is configured to: sampling a first data sample at a first sampling time prior to the first phase of the first PWM cycle; setting the first duration and the second duration of the first PWM cycle based on a first data value of the first data sample, sampling a second data sample at a second sampling time during the second phase of the first PWM cycle; and adjusting the second duration of the first PWM period based on a second data value of the second data sample.

2. The PWM output stage according to claim 1, wherein the second data value is represented by a ratio of the first duration of the first PWM period to a sum of the first duration of the first PWM period plus the adjusted second duration of the first PWM period.

3. The PWM output stage according to claim 1, wherein:

an initial PWM period of the first PWM cycle is equal to a sum of the first duration and the second duration of the first PWM cycle, an

The adjusted PWM time period of the first PWM cycle is equal to a sum of the first duration of the first PWM cycle and the adjusted second duration.

4. The PWM output stage according to claim 1, wherein the pulse width modulator is further configured to:

comparing the first data value to a predetermined threshold,

under a first condition that the first data value is greater than the predetermined threshold, setting the PWM signal to a first state during the first phase of the first PWM cycle, and setting the PWM signal to a second state during the second phase of the first PWM cycle, wherein the first state is a high state or a low state, and wherein the second state is a state opposite to the first state, and

setting the PWM signal to the second state during the first phase of the first PWM cycle and setting the PWM signal to the first state during the second phase of the first PWM cycle under a second condition that the first data value is less than the predetermined threshold.

5. The PWM output stage of claim 4, wherein the pulse width modulator is further configured to normalize the plurality of data samples.

6. The PWM output stage according to claim 1, wherein the pulse width modulator is further configured to set the second sampling time at a predetermined time between an end of the first duration and an end of the second duration of the first PWM period.

7. The PWM output stage of claim 4, wherein the pulse width modulator is further configured to:

sampling a third data sample at a third sampling time during the first phase of the first PWM cycle, an

Adjusting the first duration of the first PWM cycle based on a third data value of the third data sample.

8. The PWM output stage according to claim 7, wherein:

an initial PWM period of the first PWM cycle is equal to a sum of the first duration and the second duration of the first PWM cycle, an

The adjusted PWM time period of the first PWM cycle is equal to a sum of the adjusted first duration and the adjusted second duration of the first PWM cycle.

9. The PWM output stage of claim 7, wherein the pulse width modulator is further configured to:

calculating estimated data samples based on the first data samples and the third data samples, an

Adjusting the first duration of the first PWM cycle based on a data value of the estimated data sample.

10. A PWM output stage according to claim 9, wherein the estimated data sample is a predicted data value of the second data sample to be taken at the second sampling time.

11. The PWM output stage according to claim 1, wherein the pulse width modulator is further configured to:

sampling a third data sample at a third sampling time during the first phase of the first PWM cycle, an

Adjusting the first duration of the first PWM cycle based on a third data value of the third data sample.

12. The PWM output stage according to claim 1, wherein a total PWM period of each PWM cycle of the plurality of PWM cycles is variable.

13. The PWM output stage according to claim 1, wherein:

the plurality of PWM periods includes a second PWM period that is adjacent to and before the first PWM period, an

The pulse width modulator is configured to obtain the first data sample during the second phase of the second PWM cycle.

14. A pulse width modulation, PWM, method comprising:

generating a data signal;

sampling the data signal at a plurality of sampling times; and

generating a PWM signal based on a plurality of data samples corresponding to the plurality of sampling times,

wherein the PWM signal comprises a plurality of PWM cycles, each PWM cycle comprising a first phase of a first duration and a second phase of a second duration,

wherein the first duration and the second duration are variable,

wherein the plurality of PWM periods includes a first PWM period,

wherein sampling the data signal at the plurality of sampling times comprises:

sampling a first data sample at a first sampling time prior to the first phase of the first PWM cycle, and

sampling a second data sample at a second sampling time during the second phase of the first PWM cycle, an

Wherein generating the PWM signal comprises:

setting the first and second durations of the first PWM cycle based on a first data value of the first data sample, an

Adjusting the second duration of the first PWM cycle based on a second data value of the second data sample.

15. The PWM method according to claim 14, wherein the second data value is represented by a ratio of the first duration of the first PWM period to a sum of the first duration of the first PWM period plus the adjusted second duration of the first PWM period.

16. The PWM method according to claim 14, wherein:

an initial PWM period of the first PWM cycle is equal to a sum of the first duration and the second duration of the first PWM cycle, an

The adjusted PWM time period of the first PWM cycle is equal to a sum of the first duration of the first PWM cycle and the adjusted second duration.

17. The PWM method according to claim 14, wherein generating the PWM signal further comprises:

comparing the first data value to a predetermined threshold;

under a first condition that the first data value is greater than the predetermined threshold, setting the PWM signal to a first state during the first phase of the first PWM cycle, and setting the PWM signal to a second state during the second phase of the first PWM cycle, wherein the first state is a high state or a low state, and wherein the second state is an opposite state to the first state; and is

Setting the PWM signal to the second state during the first phase of the first PWM cycle and setting the PWM signal to the first state during the second phase of the first PWM cycle under a second condition that the first data value is less than the predetermined threshold.

18. The PWM method according to claim 17, wherein generating the PWM signal further comprises normalizing the plurality of data samples.

19. The PWM method of claim 14, wherein sampling the data signal at the plurality of sampling times further comprises: setting the second sampling time at a predetermined time between an end of the first duration and an end of the second duration of the first PWM cycle.

20. The PWM method according to claim 17, wherein:

sampling the data signal at the plurality of sampling times further comprises: sampling a third data sample at a third sampling time during the first phase of the first PWM cycle, an

Generating the PWM signal further includes: adjusting the first duration of the first PWM cycle based on a third data value of the third data sample.

21. The PWM method according to claim 20, wherein:

an initial PWM period of the first PWM cycle is equal to a sum of the first duration and the second duration of the first PWM cycle, an

The adjusted second PWM time period of the first PWM cycle is equal to a sum of the adjusted first duration and the adjusted second duration of the first PWM cycle.

22. The PWM method according to claim 20, wherein generating the PWM signal further comprises:

calculating estimated data samples based on the first data samples and the third data samples; and

adjusting the first duration of the first PWM cycle based on a data value of the estimated data sample.

23. A PWM method according to claim 22, wherein the estimated data sample is a predicted data value of the second data sample to be taken at the second sampling time.

24. The PWM method according to claim 14, wherein:

sampling the data signal at the plurality of sampling times further comprises: sampling a third data sample at a third sampling time during the first phase of the first PWM cycle, an

Generating the PWM signal further includes: adjusting the first duration of the first PWM cycle based on a third data value of the third data sample.

25. The PWM method according to claim 14, further comprising:

varying a total PWM period of each of the plurality of PWM cycles.

26. The PWM method according to claim 14, wherein:

the plurality of PWM periods includes a second PWM period that is adjacent to and before the first PWM period, an

The first sampling time occurs during the second phase of the second PWM cycle.

Technical Field

The present disclosure relates generally to pulse width modulators and to methods for Pulse Width Modulation (PWM).

Background

Many applications for Pulse Width Modulation (PWM) include voltage regulation, power level control, and motor control, to name a few. Each PWM period (i.e., transmission cycle) includes a high time for a first portion of the PWM period followed by a low time for a second portion of the PWM period, and vice versa. The duration of the first and second portions is regulated by a pulse width modulator, which is typically a PWM circuit or processor.

Due to its simplicity, PWM is widely used to transmit sensor data. However, it has a serious disadvantage that it takes a long time to transmit a single value. This delay problem grows exponentially with the required resolution of the data transmission. The reception of data is significantly delayed with respect to the sampling time. This delay places a limit on the speed achievable by the control loop using the sensor data.

Therefore, it may be desirable to develop a pulse width modulator and PWM method that reduces transmission delay.

Disclosure of Invention

One or more embodiments provide a Pulse Width Modulation (PWM) output stage, comprising: a data source configured to generate a data signal; and a pulse width modulator configured to sample the data signal at a plurality of sampling times and generate a PWM signal based on a plurality of data samples corresponding to the plurality of sampling times. The PWM signal includes a plurality of PWM cycles, each PWM cycle including a first phase of a first duration and a second phase of a second duration. The first duration and the second duration are variable. The plurality of PWM periods includes a first PWM period. The pulse width modulator is configured to: sampling a first data sample at a first sampling time prior to a first phase of a first PWM period; setting a first duration and a second duration of a first PWM cycle based on a first data value of a first data sample, sampling a second data sample at a second sampling time during a second phase of the first PWM cycle; and adjusting a second duration of the first PWM period based on a second data value of the second data sample.

One or more embodiments provide a PWM method including: generating a data signal; sampling a data signal at a plurality of sampling times; and generating a PWM signal based on a plurality of data samples corresponding to the plurality of sample times, wherein the PWM signal comprises a plurality of PWM periods, each PWM period comprising a first phase of a first duration and a second phase of a second duration, wherein the first duration and the second duration are variable, wherein the plurality of PWM periods comprises the first PWM period. Sampling the data signal at a plurality of sampling times comprises: the first data sample is sampled at a first sampling time prior to a first phase of a first PWM period and the second data sample is sampled at a second sampling time during a second phase of the first PWM period. Generating the PWM signal includes: the first and second durations of the first PWM period are set based on a first data value of the first data sample, and the second duration of the first PWM period is adjusted based on a second data value of the second data sample.

Drawings

Embodiments are described herein with reference to the drawings.

FIG. 1A is a schematic block diagram of a system using a pulse width modulator in accordance with one or more embodiments;

FIG. 1B is a schematic block diagram of another system using a pulse width modulator in accordance with one or more embodiments;

FIG. 2 is a signal diagram of a PWM signal for a PWM transmission period in accordance with one or more embodiments;

FIG. 3 is a signal diagram of two possible PWM signals for a PWM transmission period using two data samples in accordance with one or more embodiments; and

fig. 4 is a signal diagram of two possible PWM signals for a PWM transmission period using three data samples in accordance with one or more embodiments.

Detailed Description

In the following, details are set forth to provide a more thorough explanation of the exemplary embodiments. It will be apparent, however, to one skilled in the art that the embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form or in schematic form, rather than in detail, in order to avoid obscuring the embodiments. In addition, the features of the different embodiments described below may be combined with each other, unless specifically noted otherwise.

Further, in the following description, the same or similar elements or elements having the same or similar functions are denoted by the same or similar reference numerals. Since the same or functionally equivalent elements in the drawings are given the same reference numerals, a repetitive description of the elements having the same reference numerals may be omitted. Accordingly, the descriptions provided for elements having the same or similar reference numbers may be interchanged with one another.

In this regard, directional terminology, such as "top," "bottom," "below … …," "above … …," "front," "back," "leading," "trailing," etc., may be used with reference to the orientation of the figure(s) being described. Because portions of the embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims. The following detailed description is, therefore, not to be taken in a limiting sense.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements (e.g., "between … …" and "directly between … …", "adjacent" and "directly adjacent", etc.) should be interpreted in a similar manner.

In the embodiments described herein or shown in the drawings, any direct electrical connection or coupling, i.e., any connection or coupling without additional intermediate elements, may also be achieved through an indirect connection or coupling (i.e., a connection or coupling with one or more additional intermediate elements), and vice versa, for example, as long as the general purpose of the connection or coupling is essentially maintained to transmit a certain signal or transmit certain information. Features from different embodiments may be combined to form further embodiments. For example, unless indicated to the contrary, variations or modifications described with respect to one of the embodiments may also be applicable to the other embodiments.

The term "substantially" may be used herein to account for small manufacturing tolerances (e.g., within 5%) that are considered acceptable in the industry without departing from aspects of the embodiments described herein.

A sensor may refer to a component that converts a physical quantity to be measured into an electrical signal (e.g., a current signal or a voltage signal). For example, the physical quantity may be a current or a voltage at a shunt resistor in a single shunt resistor system.

The signal processing circuitry and/or signal conditioning circuitry may receive one or more signals from one or more components and perform signal conditioning or processing thereon. As used herein, signal conditioning refers to manipulating a signal in a manner such that the signal meets the requirements for the next stage of further processing. Signal conditioning may include conversion from analog to digital (e.g., via an analog-to-digital converter), amplification, filtering, conversion, biasing, range matching, isolation, and any other processes needed to make the signal suitable for processing after conditioning.

Thus, the signal processing circuit may comprise an analog-to-digital converter (ADC) which converts analog signals from one or more sensor elements into digital signals. The signal processing circuit may also include a Digital Signal Processor (DSP) that performs some processing on the digital signal.

Fig. 1A is a schematic block diagram of a system 100 using a pulse width modulator in accordance with one or more embodiments. The system comprises: a data source 10, a Pulse Width Modulator (PWM)12, an RC circuit 14, and an analog output Aout. The data source 10 may be a sensor configured to generate a sensor signal (i.e., a data signal) in response to measuring a physical quantity, such as temperature, pressure, magnetic field, voltage, current, etc. The pulse width modulator 12 includes an input Din that receives the sensor signal. The pulse width modulator 12 samples the sensor signal received at the input Din at predetermined intervals and generates a PWM signal based on the received data. In particular, as will be described in further detail below, each PWM period of the PWM signal corresponds to two or more data samples.

The RC circuit 14 is a Low Pass Filter (LPF) that converts the PWM signal into an analog signal. In this way, the analog signal is output from the RC circuit 14 via the analog output Aout. The analog signal is an average signal representing an average of a plurality of PWM periods or cycles.

The pulse width modulator 12 may be used to transmit data from the sensors to a microcontroller (not shown) of an Electronic Control Unit (ECU). In this case it can also be used to replace analog signals that are extremely sensitive to electromagnetic interference (EMI), thus requiring bulky and expensive linear output drivers. The PWM signal is transmitted in binary coding using a pulse width modulator 12 and can be converted to an analog signal using an RC circuit 14 on the receive side. The pulse width modulator 12 drives the switching of the PWM signal to power or ground, thus requiring only minimal chip area compared to a linear output stage for analog signals. Thus, the system 100 may be an output stage of a communication interface.

Fig. 1B is a schematic block diagram of a system 200 using a pulse width modulator in accordance with one or more embodiments. System 200 may include an inverter control unit 20, a power inverter 21, and a motor 22. The inverter control unit 20 functions as a motor control unit for controlling the motor 22. The power inverter 21 may include a transistor bridge configured to provide three-phase power by providing three-phase voltages to drive the motor 22, for example. The inverter control unit 20 includes: a motor control circuit 24 (such as a microcontroller implementing a motor control algorithm); and a pulse width modulator 26, the pulse width modulator 26 transmitting the PWM control signal to the gate driver, the gate driver controlling the switching array of the transistor bridge.

In this case, the motor control circuit 24 is a data source that generates a data signal in accordance with a motor control algorithm and receives the data signal at an input Din of the pulse width modulator 26. The pulse width modulator 26 samples the data signal received at the input Din at predetermined intervals and generates a PWM control signal based on the received data. In particular, as will be described in further detail below, each PWM period of the PWM control signal corresponds to two or more data samples. Thus, the system 200 may be an output stage used in power applications.

Note that since the smoothing is done by the mechanical inertia of the motor 22, a low-pass filter that smoothes the switching current signal is not required.

According to an embodiment, a second sampling time is introduced immediately before the end of each PWM period, and the time of the PWM period is allowed to be modified to represent the actual value of the measured signal at that second sampling time. In other words, although two or more data samples need to be taken for each PWM period or transmission cycle, the data content of the PWM period represents the most recent of those samples, since the duration or length of each PWM period is variable (i.e., updated) according to the most recent data sample.

According to the method, a first data sample is acquired or captured by the pulse width modulator 12, 26 at the beginning of the PWM period to set an initial high time and an initial low time of the PWM pulse. Additionally, a second data sample is taken during the PWM period (i.e., before the end of the same PWM period) to modify the later arriving one of the high or low times of the PWM pulse. Thus, the length of the second phase of the PWM signal is updated based on the new second data sample, which is taken just before the end of the duration of the initial PWM signal established by the first data sample. This has the effect of modifying the overall PWM data content and the time of the PWM period of the PWM pulse.

Fig. 2 is a signal diagram of a PWM transmission period of a PWM signal in accordance with one or more embodiments. The PWM transmission cycle or PWM period includes two parts: a first stage followed by a second stage. The first phase is defined by a high time or a low time during which the PWM is a logic high value or a logic low value, respectively. The second phase is defined by a low time or a high time, the value of the second phase being complementary to the value of the first phase. For fig. 2, the following variables are defined:

d1: an initial data sample;

ts 1: the sampling time of the initial data sample D1;

tp 1: an initial PWM time period;

th 1: initial high time based on D1 and Tp 1;

tl 1: initial low times based on D1 and Tp 1;

d2: a second data sample;

ts 2: the sampling time of the second data sample D2;

tl 2: low time of update based on D2; and

tp 2: updated PWM periods based on Th1 and Tl 2.

It should also be noted that the signal range for the following example is normalized to [ -1,1 ]. However, it will be appreciated that a different normalization range may be used, or no normalization at all may be used. Under this normalization scheme, the initial PWM period is equal to 1 (i.e., Tp1 is equal to 1). It will be further appreciated that it is also possible to start with a low time initially and then transition to a high time, and embodiments are not limited to starting with a high time or a low time.

It should also be noted that PWM signals such as in the data transmission system shown in fig. 1A cannot allow the high and low periods to extend to the entire PWM cycle length, as this would result in the receiver not being able to detect edges for distinguishing between data values. Thus, in this case, the high and low periods are generated between smaller limits (such as between 5% and 95% of the total PWM period) to provide detectable edges between PWM cycles. Thus, the allowable value for the initial high time or the initial low time may be limited to a range of set values that is less than the entire range of values for the PWM period. For example, the entire normalized range of PWM periods may be between-1 and 1 (inclusive), and the range of allowable values for the initial high or low times may be between-0.9 and 0.9 (inclusive). Thus, the initial data sample D1 may be sampled before the PWM cycle start point or after the PWM cycle start point but before the first phase start point. This is not the case for motor control (e.g., Permanent Magnet Synchronous Machine (PMSM)), where the first and second phases may extend to 0 or 100% of the total PWM cycle length.

Thus, at a first sampling time Ts1 prior to the first phase of the corresponding PWM transmission period, the data value D1 is sampled by the pulse width modulator 12, 26, and the pulse width modulator 12, 26 calculates an initial high time Th1 relative to a time Tp1 of the initial period based on the data value D1. For example, the pulse width modulators 12, 26 may calculate the initial high time Th1 with respect to the time Tp1 of the initial period based on the data value D1 using equation 1:

naturally, it can be concluded that the initial low time Tl1 with respect to the time Tp1 of the initial period can also be determined according to equation 2:

tl1 Tp1-Th1 equation 2

As a result of the initial calculation, the PWM signal transitions high at the beginning of the corresponding PWM transmission period and remains high for a calculated time Th 1. After the high time Th1 ends, the PWM signal returns low.

A second data sample D2 of the data signal is acquired by the pulse width modulator 12, 26 at a sampling time Ts2 at a defined time during the initial low time Tl1 and at a time before the end of time Tp1 of the initial period of the ongoing current PWM transmission cycle. The pulse width modulators 12, 26 use the value of the second data sample to adjust the initial low time Tl1, and thus the time Tp1 of the initial period of the current PWM transmission cycle during its transmission. In other words, the pulse width modulators 12, 26 update the initial low time Tl1 to an updated low time Tl2 based on the value of the second data sample D2, and update the initial PWM period Tp1 to an updated PWM period Tp 2. As a result, the second data sample D2 is represented by the ratio of the previously transmitted high time Th1 to the time Tp2 of a new adaptation period, which new adaptation period time Tp2 is the sum of the elapsed high time Th1 and the adjusted low time Tl 2. For example, the updated low time Tl2 and the updated PWM time period Tp2 may be calculated using equations 3 and 4:

tp2 Th1+ TI2 equation 4

As a result, a single PWM transfer period is used to transfer the latest of the two data samples D1 and D2, with the data sample D1 being sampled prior to the PWM transfer period and the data sample D2 being sampled during the PWM transfer period. Once the PWM signal is updated based on the data sample D2, the first data sample D1 will be overwritten. Thus, the final value conveyed by the PWM transmission period represents the data sample D2.

Example 1 provided below provides one possible result when the pulse width modulator 12, 26 applies the PWM transmission method to the initial calculation of the start of a PWM transmission based on the initial sample D1.

D1-0.9 Tp 1-1 the time of the initial period,

th 1-0.95 initial high time,

tl1 Tp1-Th1 Tl1 0.05 initial Low time.

Before the end of the PWM transmission, the calculation is updated with a new sample D2: d2 ═ 0.8. Since the high state has been transmitted, the low time is updated to Tl 2:

tl2 is 0.106 updated low time,

tp2 Th1+ Tl2 Tp2 time 1.056 for the updated period.

This is a good result, since the time of the period can only be increased by 5.6%, which is feasible to obtain the second sample time just before the end of the PWM period. However, a possible disadvantage of the applied method is that for very short high times the time of the period has to be changed considerably, which greatly affects the sampling rate. Therefore, the PWM transmission method can be further adjusted according to the following method.

Fig. 3 is a signal diagram of two possible PWM signals for a PWM transmission period in accordance with one or more embodiments. In particular, FIG. 3 includes top and bottom views for normalized data ranging from-1 to +1, the top view showing the case where the data value of the initial data sample D1 is a positive value, and the bottom view showing the case where the data value of the initial data sample D1 is a negative value.

In a suitable PWM transmission method, the PWM signal is transmitted first with a longer state. This means that for a positive data value of D1 (high state longer), the high state is transmitted first in the PWM transmission period, followed by the low state. Alternatively, for a negative data value of D1 requiring a longer low state, the PWM transmission period starts with the low state followed by the high state.

Thus, the pulse width modulators 12, 26 sample the first data sample D1 at an initial sampling time Ts1 and compare the data value of the first data sample D1 to zero or some other predetermined threshold. Under a first condition that the data value of the first data sample D1 is greater than a predetermined threshold, the pulse width modulator 12, 26 selects a high state for the first phase of the PWM transmission period. Under a second condition where the data value of the first data sample D1 is less than the predetermined threshold, the pulse width modulator 12, 26 selects a low state for the first phase of the PWM transmission period.

When the first condition is met, the pulse width modulator 12, 26 samples the second data sample D2 during the second phase of the PWM transmission period at Ts2 (i.e., during the low state) and adjusts the duration of the low state according to the data value of the second data sample D2. In this case, equations 1-4 may be applied as described above.

When the second condition is met, the pulse width modulator 12, 26 samples the second data sample D2 during the second phase of the PWM transmission period at Ts2 (i.e., during the high state) and adjusts the duration of the high state according to the data value of the second data sample D2. In this case, equations 1 and 2 may be applied to calculate the initial values of Th1 and Tl 1. However, the updated values of Th2 and Tp2 may be calculated using additional equations 5 and 6:

tp 2-Th 2+ Tl1 equation 6

As a result, a single PWM transmission period is used to transmit the second data sample D2, where the data sample D1 is used to set the initial value of the PWM signal for the PWM transmission period, and the data sample D2 is sampled during the PWM transmission period and used to set the final value of the PWM signal. The data sample D1 may be acquired during the previous PWM period near the beginning of the next PWM period corresponding to D2. Alternatively, the data samples D1 may be taken between consecutive or adjacent PWM periods (i.e., between a previous PWM period and a next PWM period). Alternatively, data samples D1 may be taken during their corresponding PWM transmission period but prior to the first phase of the PWM transmission period. In the latter case, there may be some buffer period between the start of the corresponding PWM transmission period and the first phase (i.e., before the first transition edge).

Example 2 provided below provides one possible result when the pulse width modulator 12, 26 applies the appropriate PWM transmission method to the initial calculation of the start of the PWM transmission based on the initial sample D1.

D1-0.9 Tp 1-1 time of the initial period

Initial high time 0.05 Th1

Tl1 Tp1-Th1 Tl1 0.95 initial Low time

Since the data value of D1 is less than the predetermined threshold, the PWM transmission starts in a low state according to Tl 1. The pulse width modulator 12, 26 then updates the calculation with the new data sample D2 before the end of the PWM transmission: d2 ═ 0.8. Since the low state has been transmitted, the high state time is updated to Th2

Low time of update 0.106 Th2 ═ h

Time of the time period of the update of Tp 2-Th 2+ Tl1 Tp 2-1.056

Since the order of the high-order section and the low-order section is changed, the high-order section requires only a small expansion, and the time Tp2 of the final period is increased by 5.6% with respect to the time Tp1 of the initial period.

Further, the pulse width modulators 12, 26 may be configured to acquire a third data sample, D3, at the sampling time, T3, in order to adjust the duration of the first phase of the PWM transmission period. For example, fig. 4 is a signal diagram of two possible PWM signals for a PWM transmission period in accordance with one or more embodiments. In particular, fig. 4 includes a top view showing a case where the data value of the initial data sample D1 is a positive value and a bottom view showing a case where the data value of the initial data sample D1 is a negative value. The pulse width modulators 12, 26 use the data samples D1 and D2 in a similar manner as described above, but also use the third data sample D3 to adjust the duration of the first phase of the PWM transmission period.

When the first phase duration is modified according to the third data sample D3, the complete set of durations Tl1, Th1 will be covered by Tl3, Th3 using equation 1 and equation 2, with Tl1 replaced by Tl3 and Th1 replaced by Th 3. The sum Tp3 of Tl3 and Th3 will remain equal to the initial time period Tp 1. The calculation of the duration of the second phase need not be performed since it is covered anyway afterwards. Due to the equality of Tp1 and Tp3, the sampling time Ts2 for the last sample D2 may remain the same and need not change. Since the time periods Tp1 and Tp3 are equal, a change in the first-stage time length based on D3 results in an equal but opposite change in the second-stage time length. Then, the next modification based on the data sample D2 at Ts2 will again change the second duration according to the previous equation of replacing only Tx1 (i.e., Tl1 and Th1) with Tx3 (i.e., Tl3 and Th 3). The second adjustment must change the length of the time period Tp2 because the first time period has already been transmitted and cannot compensate for the total length of the time period.

Therefore, the total period length of the PWM transmission period may be initially set based on D1 and then adjusted based on D2. The first phase is set first based on D1 and then updated based on D3. The second phase is initially set based on D1, then adjusted first based on D3 and then second based on D2 due to the adjustment to the first phase. The total period length is adjusted based on D2 only.

The sequence of operations may include: sample D1 at Ts 1; determining whether to start the first phase of the PWM transmission cycle in a high state or a low state based on a comparison of the sample D1 with zero or some other predetermined threshold; calculating initial period lengths of the first and second phases based on D1; starting a PWM transmission period according to the determined starting state and the determined initial first-stage and second-stage duration; sampling D3 at Ts3 during the first phase of the PWM transmission period; updating the initial duration of the first stage based on D3 via the adjustment; sampling D2 at Ts2 during the second phase of the PWM transmission period; the initial duration of the second phase is updated based on D2 via the adjustment.

Alternatively, the pulse width modulators 12, 26 may use the values of the data samples D1 and D3 to calculate estimated data samples D2est, the estimated data samples D2est representing the predicted value of the data sample D2 taken at Ts 2. The pulse width modulators 12, 26 may adjust the initial duration of the first phase of the current PWM period using the estimated value of the data sample D2est rather than based solely on the data sample D3. For an oversampled signal this must be the case if the analogue signal has to be reconstructed by low pass filtering the PWM sequence, which will significantly reduce the required updates for the duration of the second PWM signal state.

The pulse width modulators 12, 26 may calculate the estimated data samples D2est using a linear predictor model using equations 7 and 8. In the case where the sampling times Ts1, Ts3, and Ts2 are not equidistant, equation 7 may be used. In the case where the sampling times Ts1, Ts3, and Ts2 are equidistant, equation 8 may be used.

D2 est-2 × D3-D1 equation 8

The data sample D2 taken by the pulse width modulator 12, 26 at the sample time Ts2 then overwrites the estimated data sample D2est and the pulse width modulator 12, 26 uses the data sample D2 to adjust the initial duration of the second phase of the current PWM period.

Therefore, the total period length of the PWM transmission period may be initially set based on D1 and then adjusted based on D2. While keeping Tp1 constant, the estimated data samples D2est are used to cover the initial values of Th1 and Tl1 — much like the process described above for D3. Therefore, the first phase is initially set based on D1 and then updated based on D2 est. The second phase is initially set based on D1, then adjusted first based on D2est due to the adjustments made to the first phase, and then adjusted next based on D2 est. The total period length is adjusted based on D2 only.

The sequence of operations may include: sample D1 at Ts 1; determining whether to start the first phase of the PWM transmission cycle in a high state or a low state based on a comparison of the sample D1 with zero or some other predetermined threshold; calculating initial period lengths of the first and second phases based on D1; starting a PWM transmission period according to the determined starting state and the determined initial first-stage and second-stage duration; sampling D3 at Ts3 during the first phase of the PWM transmission period; calculating estimated data samples D2est based on samples D1 and D3; updating an initial duration of the first stage based on the D2est via the adjustment; sampling D2 at Ts2 during the second phase of the PWM transmission period; the initial duration of the second phase is updated based on D2 via the adjustment.

Updating the initial duration of the first phase based on D3 alone or on D2est will help to keep subsequent adjustments to the second phase, which will eventually be as small as possible based on the measured value of D2, thereby reducing transmission delays. The smaller the maximum change in duration of the second phase, the closer the second sample is to the end of the PWM period, and thus the delay is minimized.

An additional advantage of the disclosed embodiments is that the period length of the PWM cycle is not constant and thus the peak of the spectral distribution at 1/Tp1 is reduced by spectral spreading, where Tp is the initial PWM period time.

As described with reference to fig. 1A and 1B, respectively, although not limited thereto, the disclosed embodiments may be used in systems including linear sensors with PWM interfaces for simulation of analog signals, as well as in motor bridge drivers for Permanent Magnet Synchronous Machines (PMSM).

While various embodiments have been described, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the disclosure. Accordingly, the invention is not to be restricted except in light of the attached claims and their equivalents. In regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a "means") used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention.

Furthermore, the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate example embodiment. Although each claim may stand on its own as an independent example embodiment, it is noted that although a dependent claim may refer in the claims to a specific combination with one or more other claims, other example embodiments may also include combinations of the subject matter of the dependent claims with each other dependent or independent claim. Such combinations are presented herein unless indicated otherwise. Furthermore, it is intended that features of a claim are also included in any other independent claim, even if this claim is not directly dependent on the independent claim.

It is further noted that the methods disclosed in the specification or claims may be implemented by an apparatus having means for performing each of the individual acts of the methods.

Further, it should be understood that the disclosure of multiple acts or functions disclosed in the specification or claims may not be construed as to be within a particular order. Thus, the disclosure of multiple acts or functions will not limit them to a particular order unless such acts or functions are not interchangeable for technical reasons. Further, in some embodiments, a single action may include or may be broken down into multiple sub-actions. Unless expressly excluded, such sub-acts may be included within and be part of the disclosure of the single act.

Embodiments provided herein may be implemented in hardware or software, depending on certain implementation requirements. The implementation can be performed using a digital storage medium (e.g. a floppy disk, a DVD, a blu-ray, a CD, a RAM, a ROM, a PROM, an EPROM, an EEPROM or a flash memory) having electronically readable control signals stored thereon, which cooperate (or are capable of cooperating) with a programmable computer system such that the respective method is performed. Accordingly, the digital storage medium may be computer-readable.

The instructions may be executed by one or more processors, such as one or more Central Processing Units (CPUs), Digital Signal Processors (DSPs), general purpose microprocessors, Application Specific Integrated Circuits (ASICs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Thus, as used herein, the term "processor" refers to any of the foregoing structures or any other structure suitable for implementation of the techniques described herein. In addition, in some aspects, the functions described herein may be provided within dedicated hardware and/or software modules. Also, the techniques may be fully implemented in one or more circuits or logic elements.

Thus, the techniques described in this disclosure may be implemented, at least in part, in hardware, software, firmware, or any combination thereof. For example, various aspects of the described techniques may be implemented within one or more processors, including one or more microprocessors, DSPs, ASICs, or any other equivalent integrated or discrete logic circuitry, as well as any combinations of such components.

The control unit, including hardware, may also perform one or more of the techniques described in this disclosure. Such hardware, software, and firmware may be implemented within the same device or within separate devices to support the various techniques described in this disclosure. The software may be stored on a non-transitory computer readable medium such that the non-transitory computer readable medium comprises program code or program algorithms stored thereon which, when executed, cause a computer program to perform the steps of the method.

Although various exemplary embodiments have been disclosed, it will be apparent to those skilled in the art that various changes and modifications can be made which will achieve some of the advantages of the concepts disclosed herein without departing from the spirit and scope of the invention. It is obvious to those skilled in the art that other components having the same function may be appropriately replaced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. It should be mentioned that even in features not explicitly mentioned, features explained with reference to a particular figure can be combined with features of other figures. Such modifications to the general inventive concept are intended to be covered by the appended claims and their legal equivalents.