阅读说明：本技术 触发器电路、控制电路及芯片 (Trigger circuit, control circuit and chip ) 是由 张琼 石瑞恺 于 2020-04-03 设计创作，主要内容包括：本发明实施例提供一种触发器电路、控制电路及芯片,包括脉冲触发器和时钟产生单元,脉冲触发器包括延时单元、第一锁存器、第二锁存器和比较单元,其中,延时单元与第一锁存器连接,比较单元分别与第一锁存器和第二锁存器连接,第一锁存器和第二锁存器连接,时钟产生单元分别与第一锁存器和第二锁存器连接；时钟产生单元用于,在触发器电路的模式为功能模式时,控制第一锁存器处于锁存状态；比较单元用于,在触发器电路的模式为时序检测模式时,根据第一锁存器和第二锁存器的输出确定时序检测结果,从而降低了触发器电路的功耗。(The embodiment of the invention provides a trigger circuit, a control circuit and a chip, which comprise a pulse trigger and a clock generation unit, wherein the pulse trigger comprises a delay unit, a first latch, a second latch and a comparison unit, wherein the delay unit is connected with the first latch, the comparison unit is respectively connected with the first latch and the second latch, the first latch and the second latch are connected, and the clock generation unit is respectively connected with the first latch and the second latch; the clock generation unit is used for controlling the first latch to be in a latch state when the mode of the trigger circuit is a functional mode; the comparison unit is used for determining a timing detection result according to the output of the first latch and the second latch when the mode of the trigger circuit is a timing detection mode, so that the power consumption of the trigger circuit is reduced.)

1. A flip-flop circuit comprising a pulse flip-flop and a clock generation unit, said pulse flip-flop comprising a delay unit, a first latch, a second latch and a comparison unit, wherein,

the delay unit is connected with the first latch, the comparison unit is respectively connected with the first latch and the second latch, the first latch and the second latch are connected, and the clock generation unit is respectively connected with the first latch and the second latch;

the clock generation unit is used for controlling the first latch to be in a latch state when the mode of the trigger circuit is a functional mode;

the comparison unit is used for determining a timing detection result according to the output of the first latch and the second latch when the mode of the trigger circuit is a timing detection mode.

2. The circuit of claim 1, wherein the clock generation unit comprises a clock gating unit and a pulse generator, wherein,

the clock gating unit is connected with the pulse generator;

the clock gating unit is connected with the first latch and the second latch respectively.

3. The circuit of claim 2, wherein the clock gating cell comprises an OR gate, a third latch, a first selection cell, and an AND gate, wherein,

the input end of the OR gate is used for receiving a detection control signal and a scanning enabling signal, and the output end of the OR gate is connected with the data input end of the third latch;

the clock input end of the third latch is used for receiving a square wave clock signal through a NOT gate;

the input end of the first selection unit is connected with the pulse generator and is used for receiving the square wave clock signal;

the input end of the AND gate is respectively connected with the output end of the third latch and the output end of the first selection unit, and the output end of the AND gate is respectively connected with the first latch and the second latch.

4. The circuit of any of claims 1-3, wherein the pulse flip-flop further comprises a first input selection unit, wherein,

the input end of the first input selection unit is connected with the output end of the delay unit, the first input selection unit is further used for receiving a scanning signal and a scanning enabling signal, and the input end of the delay unit is further used for receiving a data signal;

the output end of the first input selection unit is connected with the data input end of the first latch.

5. The circuit according to any of claims 1-3, wherein the pulse flip-flop further comprises a second input selection unit,

the input end of the second input selection unit is connected with the output end of the first latch, and the second input selection unit is also used for receiving a data signal and a scanning enabling signal;

and the output end of the second input selection unit is connected with the data input end of the second latch.

6. The circuit according to any of claims 1-3, wherein the pulse flip-flop further comprises a first clock selection unit, wherein,

the input end of the first clock selection unit is connected with the clock generation unit, and the first clock selection unit is also used for receiving a scanning enabling signal;

the output end of the first clock selection unit is connected with the clock input end of the first latch.

7. The circuit of any of claims 1-3, wherein the pulse flip-flop further comprises a second clock select unit, wherein,

the input end of the second clock selection unit is connected with the clock generation unit, and the second clock selection unit is also used for receiving a scanning enabling signal;

and the output end of the second clock selection unit is connected with the clock input end of the second latch.

8. A circuit according to any one of claims 1-3, wherein the delay element comprises N inverters connected in series, where N is an even number greater than 0.

9. A control circuit comprising M timing paths, a signal processing module and a conditioning module, each timing path comprising the flip-flop circuit of any one of claims 1-8, M being an integer greater than or equal to 1, wherein,

m trigger circuits in the M time sequence paths are respectively connected with the signal processing module, and the signal processing module is connected with the adjusting module;

the adjusting module is respectively connected with the M time sequence paths.

10. The control circuit of claim 9, wherein the regulating module comprises a voltage regulating unit and/or a frequency regulating unit.

11. A chip comprising the flip-flop circuit of any one of claims 1 to 10.

Technical Field

The embodiment of the invention relates to the technical field of circuits, in particular to a trigger circuit, a control circuit and a chip.

Background

Currently, to ensure the normal operation of a flip-flop circuit, the flip-flop circuit generally has a plurality of modes (e.g., a functional mode, a scan mode, a timing detection mode, etc.). In the functional mode, the flip-flop circuit is used to complete the corresponding function, and in the non-functional mode, the flip-flop circuit can be tested.

In order for a flip-flop circuit to have a scan mode and a timing detection mode, it is generally necessary to add logic cells in the flip-flop, for example, when the flip-flop circuit has multiple modes (e.g., a functional mode, a scan mode, a timing detection mode, etc.), the logic cells included in the flip-flop are generally more than the logic cells included when the flip-flop has only a functional mode. When the flip-flop is in the functional mode, the logic units in the flip-flop circuit all need to consume power, and when the flip-flop circuit includes more logic units, the power consumption of the flip-flop circuit is higher.

Disclosure of Invention

The embodiment of the invention provides a trigger circuit, a control circuit and a chip, which reduce the power consumption of the trigger circuit.

In a first aspect, an embodiment of the present invention provides a flip-flop circuit, including a pulse flip-flop and a clock generation unit, where the pulse flip-flop includes a delay unit, a first latch, a second latch, and a comparison unit,

the delay unit is connected with the first latch, the comparison unit is respectively connected with the first latch and the second latch, the first latch and the second latch are connected, and the clock generation unit is respectively connected with the first latch and the second latch;

the clock generation unit is used for controlling the first latch to be in a latch state when the mode of the trigger circuit is a functional mode;

the comparison unit is used for determining a timing detection result according to the output of the first latch and the second latch when the mode of the trigger circuit is a timing detection mode.

In a possible embodiment, the clock generation unit comprises a clock gating unit and a pulse generator, wherein,

the clock gating unit is connected with the pulse generator;

the clock gating unit is connected with the first latch and the second latch respectively.

In one possible embodiment, the clock gating unit comprises an or gate, a third latch, a first selection unit and an and gate, wherein,

the input end of the OR gate is used for receiving a detection control signal and a scanning enabling signal, and the output end of the OR gate is connected with the data input end of the third latch;

the clock input end of the third latch is used for receiving a square wave clock signal through a NOT gate;

the input end of the first selection unit is connected with the pulse generator and is used for receiving the square wave clock signal;

the input end of the AND gate is respectively connected with the output end of the third latch and the output end of the first selection unit, and the output end of the AND gate is respectively connected with the first latch and the second latch.

In a possible embodiment, the pulse trigger further comprises a first input selection unit, wherein,

the input end of the first input selection unit is connected with the output end of the delay unit, the first input selection unit is further used for receiving a scanning signal and a scanning enabling signal, and the input end of the delay unit is further used for receiving a data signal;

the output end of the first input selection unit is connected with the data input end of the first latch.

In one possible embodiment, the pulse trigger further comprises a second input selection unit,

the input end of the second input selection unit is connected with the output end of the first latch, and the second input selection unit is also used for receiving a data signal and a scanning enabling signal;

and the output end of the second input selection unit is connected with the data input end of the second latch.

In a possible embodiment, the pulse flip-flop further comprises a first clock selection unit, wherein,

the input end of the first clock selection unit is connected with the clock generation unit, and the first clock selection unit is also used for receiving a scanning enabling signal;

the output end of the first clock selection unit is connected with the clock input end of the first latch.

In a possible embodiment, the pulse flip-flop 10 further comprises a second clock selection unit, wherein,

the input end of the second clock selection unit is connected with the clock generation unit, and the second clock selection unit is also used for receiving a scanning enabling signal;

and the output end of the second clock selection unit is connected with the clock input end of the second latch.

In a possible implementation, the delay unit includes N inverters connected in sequence, where N is an even number greater than 0.

In a second aspect, an embodiment of the present invention provides a control circuit, including M timing paths, a signal processing module, and an adjusting module, where each timing path includes the flip-flop circuit described in any one of the first aspects, M is an integer greater than or equal to 1,

m trigger circuits in the M time sequence paths are respectively connected with the signal processing module, and the signal processing module is connected with the adjusting module;

the adjusting module is respectively connected with the M time sequence paths.

In one possible embodiment, the control module comprises a voltage control unit and/or a frequency control unit.

In a third aspect, an embodiment of the present application provides a chip, including the flip-flop circuit described in any one of the first aspects.

The embodiment of the invention provides a trigger circuit and a control circuit, which comprise a pulse trigger and a clock generation unit, wherein the pulse trigger comprises a delay unit, a first latch, a second latch and a comparison unit, the delay unit is connected with the first latch, the comparison unit is respectively connected with the first latch and the second latch, the first latch and the second latch are connected, and the clock generation unit is respectively connected with the first latch and the second latch; the comparison unit is used for determining a time sequence detection result according to the output of the first latch and the second latch when the mode of the trigger circuit is a time sequence detection mode, and the clock generation unit is used for controlling the first latch to be in a latch state when the mode of the trigger circuit is a functional mode, so that the first latch can be prevented from being inverted, and the power consumption of the trigger circuit is further reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a flip-flop circuit according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of another flip-flop circuit according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a clock generation unit according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a pulse trigger according to an embodiment of the present invention;

FIG. 5 is a timing diagram of a scan mode according to an embodiment of the present invention;

FIG. 6 is a timing diagram of the timing detection mode according to the embodiment of the present invention;

FIG. 7 is a timing diagram of functional modes according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of a control circuit according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of another control circuit according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of a timing path according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

For ease of understanding, the concepts to which this application relates will first be described.

A latch: is a pulse level sensitive memory cell circuit. When the latch signal input to the latch is an active signal, the output of the latch changes as the input of the latch changes. When the latch signal input to the latch is an invalid signal, the output of the latch is held in the previous state, and the output of the latch does not change with the change of the input of the latch. The valid signal may be 0 or 1, for example, if the latch is sensitive to low, the valid signal is 0, and if the latch is sensitive to high, the valid signal is 1.

A trigger: is a memory cell circuit sensitive to edges. The flip-flop may be controlled by a clock signal, the output of the flip-flop changing with changes in the input of the flip-flop at the arrival of a transition edge (rising edge or falling edge) of the clock signal, and the output of the flip-flop remaining unchanged for the rest of the time (non-transition edge). Namely, the flip-flop only stores the input at the jumping edge of the clock signal, and the anti-interference capability is strong. A flip-flop may correspond to a cascade of two different level sensitive latches.

A pulse latch: refers to a latch that uses a clock signal as a latch signal. The pulse generator generates a short pulse signal near the rising or falling edge of the clock signal, the short pulse signal is used as a latch signal of the latch to latch data, the pulse latch is sensitive to the level of the latch signal, and the transparent time window of the pulse latch is very short, so that the anti-jamming capability of the circuit is enhanced.

In the flip-flop circuit shown in the present application, the clock generation unit is included, and in the functional mode, the clock generation unit can control power consumption of a part of logic units in the flip-flop circuit through the generated clock information, so as to save power consumption of the flip-flop circuit.

The technical means shown in the present application will be described in detail below with reference to specific examples. It should be noted that the following embodiments may be combined with each other, and the description of the same or similar contents in different embodiments is not repeated.

Fig. 1 is a schematic structural diagram of a flip-flop circuit according to an embodiment of the present invention. Referring to fig. 1, the flip-flop circuit includes a pulse flip-flop 10 and a clock generation unit 20, the pulse flip-flop 10 includes a delay unit 11, a first latch 12, a second latch 13, and a comparison unit 14, wherein the delay unit 11 is connected to the first latch 12, the comparison unit 14 is connected to the first latch 12 and the second latch 13, the first latch 12 and the second latch 13 are connected, and the clock generation unit is connected to the first latch 12 and the second latch 13, respectively.

The clock generation unit 20 is configured to control the operating mode of the flip-flop to be a functional mode, a timing detection mode, or a scan mode, and control the first latch 12 to be in a latch state when the mode of the flip-flop circuit is the functional mode; the comparison unit 14 is configured to determine a timing detection result according to outputs of the first latch 12 and the second latch 13 when the mode of the flip-flop circuit is the timing detection mode.

Optionally, the delay unit 11 is configured to perform delay processing on the signal.

Alternatively, the delay unit 11 may include a plurality of logic units. For example, the delay unit 11 includes N inverters connected in series, N being an even number greater than 0. N may be 2, 4, 6, and the like, and in an actual application process, the size of N may be set according to actual needs, which is not specifically limited in the embodiment of the present invention.

Optionally, the comparing unit 14 is configured to compare whether the outputs of the first latch 12 and the second latch 13 are the same. For example, the comparison unit 14 may output a low level when the outputs of the first and second latches 12 and 13 are the same, and the comparison unit 14 may output a high level when the outputs of the first and second latches 12 and 13 are different.

Optionally, the first latch 12 and the second latch 13 are connected, and when the clock signals of the first latch 12 and the second latch 13 are in opposite phases, the first latch 12 and the second latch 13 form the master-slave flip-flop 10 under the action of the inverted clock signals.

In this application, the modes of the flip-flop circuit may include a functional mode, a scan mode, and a timing detection mode. In the functional mode, the flip-flop circuit is used to implement the corresponding memory function. In the scan mode, the test circuit is used for testing the logic unit of the trigger circuit. And in the time sequence detection mode, the method is used for detecting the time sequence of the critical path.

Next, the operation of the flip-flop circuit will be described.

In the scan mode, a scan signal may be input to the first latch 12 through a scan input terminal (not shown in the figure), and an output of the first latch 12 serves as an input of the second latch 13. The clock generation unit inputs the clock signals of inverted phases to the first latch 12 and the second latch 13, so that the first latch 12 and the second latch 13 constitute a master-slave flip-flop circuit.

In the timing detection mode, a data signal may be input to the first latch 12 and a data signal may be input to the second latch 13 through the delay unit 11. The clock generation unit inputs the same clock signal to the first latch 12 and the second latch 13, so that the first latch 12 can be used as a shadow latch of the second latch 13 to monitor the timing of the second latch 13. For example, the comparing unit 14 may determine whether the outputs of the first latch 12 and the second latch 13 are the same, and if the outputs are the same, it indicates that the critical path is not detected, and if the outputs are not the same, it indicates that the critical path is detected. The critical path is the path with the largest time delay in the circuit.

In the functional mode, a data signal is input to the second latch 13. The clock generation unit inputs an invalid signal to the first latch 12 so that the first latch 12 is in a latched state. The clock generation unit inputs a pulse clock signal to the second latch 13 so that the second latch 13 realizes the function of a pulse latch. In this mode, since the clock generation unit can control the first latch 12 to be in the latch state, the first latch 12 is prevented from being flipped, thereby saving power consumption of the circuit.

The embodiment of the invention provides a trigger circuit, which comprises a pulse trigger 10 and a clock generation unit 20, wherein the pulse trigger 10 comprises a delay unit 11, a first latch 12, a second latch 13 and a comparison unit 14, the delay unit 11 is connected with the first latch 12, the comparison unit 14 is respectively connected with the first latch 12 and the second latch 13, the first latch 12 is connected with the second latch 13, and the clock generation unit is respectively connected with the first latch 12 and the second latch 13; the comparing unit 14 is configured to determine a timing detection result according to outputs of the first latch 12 and the second latch 13 when the mode of the flip-flop circuit is the timing detection mode, and the clock generating unit 20 is configured to control the first latch 12 to be in a latch state when the mode of the flip-flop circuit is the functional mode, so that the first latch 12 is prevented from being flipped, and power consumption of the circuit is further reduced.

Based on any of the above embodiments, the structure of the flip-flop circuit shown in fig. 1 will be described in further detail with reference to fig. 2.

Fig. 2 is a schematic structural diagram of another flip-flop circuit according to an embodiment of the present invention. Referring to fig. 2, the flip-flop circuit includes a first input selection unit 15, a second input selection unit 16, and a clock selection unit.

Referring to fig. 2, an input terminal of the first input selecting unit 15 is connected to an output terminal of the delay unit 11, the first input selecting unit 15 is further configured to receive a scan signal and a scan enable signal, and an input terminal of the delay unit 11 is configured to receive a data signal.

Referring to fig. 2, an input terminal of the second input selecting unit 16 is connected to the output terminal of the first latch 12, the second input selecting unit 16 is further configured to receive a data signal and a scan enable signal, and an output terminal of the second input selecting unit 16 is connected to a data input terminal of the second latch 13.

Referring to fig. 2, the clock selection unit is connected to the clock generation unit, the clock generation unit may receive a detection enable signal, a scan enable signal and a square wave clock signal, and generate a clock signal according to the received signals, the clock signal may be any one of a functional clock signal (FCLK), a scan clock Signal (SCLK) and a monitor clock signal (MCLK), and the clock selection unit may transmit corresponding clock signals to the first latch 12 and the second latch 13 according to the received signals generated by the clock generation unit.

In practical application, when the flip-flop circuits are in different modes, the detection enable signal and the scan enable signal input to the clock generation unit are also different, and correspondingly, the clock selection unit outputs different clock signals to the first latch 12 and the second latch 13; when the modes of the flip-flop circuit are different, the scan enable signals input to the first input selecting unit 15 and the second input selecting unit 16 are also different, so that the input/output of the first input selecting unit 15 and the second input selecting unit 16 are also different, and the flip-flop circuit is further caused to operate in different modes.

In addition to any of the above embodiments, the following describes a structure of the clock generation unit with reference to fig. 3.

Fig. 3 is a schematic structural diagram of a clock generation unit according to an embodiment of the present invention. Referring to fig. 3, the clock generation unit 20 includes a clock gating unit 21 and a pulse generator 22, wherein the clock gating unit 21 is connected to the pulse generator 22; the clock gating unit 21 is connected to the first latch 12 and the second latch 13, respectively (not shown in fig. 3).

Referring to fig. 3, the clock gating unit 21 includes an OR gate OR, an input terminal of which is configured to receive a detection control signal AND a scan enable signal, a third latch 211, a first selection unit 212, AND an AND gate AND, an output terminal of which is connected to a data input terminal of the third latch 211; the clock input terminal of the third latch 211 is configured to receive a square wave clock signal through the not gate; the input of the first selection unit 212 is connected to the pulse generator 22 and is configured to receive a square wave clock signal; the input terminals of the AND gate AND are connected to the output terminal of the third latch 211 AND the output terminal of the first selection unit 212, respectively, AND the output terminals of the AND gate AND are connected to the first latch 12 AND the second latch 13, respectively.

The inputs to the clock generation unit 20 include: monitoring a control signal (ME), a scan enable Signal (SE) and a common clock square wave clock signal (CLK). The outputs of the clock generation unit 20 include a functional clock signal (FCLK), a scan clock Signal (SCLK), and a monitoring clock signal (MCLK).

The square wave clock signal (CLK) is input to the pulse generator 22, and the output of the pulse generator 22 is the functional clock signal (FCLK). When the scan enable Signal (SE) is at a high level, the functional clock signal (FCLK) output by the pulse generator 22 is at a low level when the signal received by the pulse generator 22 through the not gate is at a low level.

The inputs of the first selection unit 212 include: a square wave clock signal (CLK) and a functional clock signal (FCLK) output by the pulse generator 22. The output of the first selection unit 212 is different according to the scan enable Signal (SE). For example, when the scan enable Signal (SE) is at a high level, the output of the first selection unit 212 is a square wave clock signal (CLK). When the scan enable Signal (SE) is low, the output of the first selection unit 212 is the functional clock signal (FCLK).

The inputs to OR gate OR include: a monitor control signal (ME) and a scan enable Signal (SE), and an output of the OR gate OR is high when one of the monitor control signal (ME) and the scan enable Signal (SE) is high.

The third latch 211 is a low-level sensitive latch, and when the clock signal (CLK) is low, the output of the third latch 211 changes with the input, and at other times, the third latch 211 maintains a latched state.

The inputs to the AND gate AND include: the output of the third latch 211 and the output of the first selection unit 212. The output of the AND gate AND is either the scan clock Signal (SCLK) or the monitor clock signal (MCLK).

In addition to any of the above embodiments, the structure of the pulse trigger 10 will be described below with reference to fig. 4. Fig. 4 is a schematic structural diagram of a pulse trigger according to an embodiment of the present invention.

Referring to fig. 4, the pulse flip-flop 10 circuit further includes a first input selecting unit 15 and a second input selecting unit 16, wherein an input end of the first input selecting unit 15 is connected to an output end of the delay unit 11, the first input selecting unit 15 is further configured to receive a scan signal, and an input end of the delay unit 11 is further configured to receive a data signal; the output of the first input selection unit 15 is connected to the data input of the first latch 12; the input end of the second input selection unit 16 is connected with the output end of the first latch 12, and the second input selection unit 16 is also used for receiving a data signal; the output of the second input selection unit 16 is connected to the data input of the second latch 13. The first input selection unit 15 and the second input selection unit 16 are also respectively used for receiving scan enable signals.

Referring to fig. 4, the circuit of the pulse flip-flop 10 further includes a first clock selecting unit 17 and a second clock selecting unit 18, wherein an input terminal of the first clock selecting unit 17 is connected to the clock generating unit 20; the output of the first clock selection unit 17 is connected to the clock input of the first latch 12; the input end of the second clock selection unit 18 is connected with the clock generation unit 20; the output of the second clock selection unit 18 is connected to the clock input of the second latch 13. The first clock selection unit 17 and the second clock selection unit 18 are also respectively configured to receive scan enable signals. Alternatively, the first clock selecting unit 17 may receive the scan clock Signal (SCLK) of the clock generating unit 20 through the inverse delay 19.

Optionally, the inputs of the pulse trigger 10 circuit may include: a functional clock signal (FCLK), a scan clock Signal (SCLK), a monitor clock signal (MCLK), a data signal (D), a scan Signal (SI), and a scan enable Signal (SE). The input and output of the pulse trigger 10 circuit may include: a data output signal (Q) and a misprediction signal (FAIL).

The input of the delay unit 11 is a data signal (D), and the output of the delay unit 11 is a delayed data signal (D').

The input of the first input selection unit 15 includes: the delay unit 11 outputs a delay data signal (D') and a scanning Signal (SI). The output of the first input selection unit 15 is different according to the scan enable Signal (SE). For example, when the scan enable Signal (SE) is high, the output (DA) of the first input selecting unit 15 is the scan Signal (SI), and when the scan enable Signal (SE) is low, the output (DA) of the first input selecting unit 15 is the delayed data signal (D').

The inputs of the second input selection unit 16 include: a data signal (D) and an output (QA) of the first latch 12. The output of the second input selection unit 16 is different according to the scan enable Signal (SE). For example, when the scan enable Signal (SE) is at a high level, the output (DB) of the second input selecting unit 16 is the output (QA) of the first latch 12, and when the scan enable Signal (SE) is at a low level, the output (DB) of the second input selecting unit 16 is the data signal (D).

The inputs of the first clock selection unit 17 include the monitoring clock signal (MCLK) and the inverse signal (-SCLK) of the scanning clock Signal (SCLK). The output of the first clock selection unit 17 is different according to the scan enable Signal (SE). For example, when the scan enable Signal (SE) is at a high level, the output of the first clock selecting unit 17 is an inverted Signal (SCLK) of the scan clock Signal (SCLK), and when the scan enable Signal (SE) is at a low level, the output of the first clock selecting unit 17 is the monitor clock signal (MCLK).

The inputs of the second clock selection unit 18 include a scan clock Signal (SCLK) and a functional clock signal (FCLK). The output of the second clock selection unit 18 is different according to the scan enable Signal (SE). For example, when the scan enable Signal (SE) is high, the output of the second clock selecting unit 18 is the scan clock Signal (SCLK), and when the scan enable Signal (SE) is low, the output of the second clock selecting unit 18 is the functional clock signal (FCLK).

The first latch 12 has different outputs from the first latch 12 according to its clock control signal (CLKA), which is an output of the first clock selection unit 17, and may be an inverted Signal (SCLK) of the scan clock Signal (SCLK) or may be the monitor clock signal (MCLK). When the clock control signal (CLKA) of the first latch 12 is at a high level, the first latch 12 outputs a signal QA according to its input (DA), and at other times, the first latch 12 maintains a latched state.

The second latch 13 has different outputs according to its clock control signal (CLKB), and the clock control signal (CLKB) of the second latch 13 is the output of the second clock selection unit 18, which may be the scan clock Signal (SCLK) or the functional clock signal (FCLK). When the clock control signal (CLKB) of the second latch 13 is high, the second latch 13 outputs the signal Q according to its input (DB), and at other times, the first latch 12 maintains the latched state.

The input of comparing section 14 includes an output (QA) of first latch 12 and an output (Q) of second latch 13, and comparing section 14 compares QA and Q with each other, and if they are the same, output FAIL of comparing section 14 is at a low level, and if they are not the same, output FAIL of comparing section 14 is at a high level.

The operation of the flip-flop circuit will be described with reference to fig. 3 to 4.

In the scan mode, the scan enable Signal (SE) is at a high level, and the functional clock signal (FCLK) output by the pulse generator 22 is at a low level. The output of the first selection unit 212 is a square wave clock signal (CLK), which is output from the AND gate AND.

Since the scan enable Signal (SE) is high, the output (DA) of the first input selection unit 15 is the scan Signal (SI), that is, the input of the first latch 12 is the scan Signal (SI). The output (DB) of the second input selection unit 16 is the output (QA) of the first latch 12, i.e., the input of the second latch 13 is the output (QA) of the first latch 12.

Since the scan enable Signal (SE) is high, the output of the first clock selecting unit 17 is an inverted Signal (SCLK) of the scan clock Signal (SCLK). The output of the second clock selection unit 18 is the scan clock Signal (SCLK).

As can be seen from the above, in the scan mode, the input of the first latch 12 is the scan signal, the output of the second latch 13 is the input of the second latch 13, and the clock signal of the first latch 12 and the clock signal of the second latch 13 are opposite in phase, so that the first latch 12 and the second latch 13 constitute a master-slave flip-flop circuit.

Next, the timing relationship in the scan mode will be described with reference to fig. 5.

Fig. 5 is a timing diagram of the scan mode according to the embodiment of the present invention. Referring to fig. 5, in the scan mode, the scan enable Signal (SE) is high, and the monitor control signal (ME) and the data signal (D) are disabled for the flip-flop circuit. The output (QA) of the first latch 12 and the output (Q) of the second latch 13 vary following the variation of the scan Signal (SI).

In the timing detection mode, the scan enable Signal (SE) is low, and the monitor control signal (ME) is high. The functional clock signal (FCLK) output from the pulse generator 22 is a pulse signal. The output of the first selection unit 212 is a functional clock signal (FCLK). The AND gate AND logically AND-operates the functional clock signal (FCLK) AND the output of the third latch 211, AND the output monitoring clock signal (MCLK) is a pulse clock signal.

Since the scan enable Signal (SE) is low, the output (DA) of the first input selection unit 15 is the delayed data signal (D '), i.e., the input of the first latch 12 is the delayed data signal (D'). The output (DB) of the second input selection unit 16 is the data signal (D), i.e. the input of the second latch 13 is the data signal (D).

Since the scan enable Signal (SE) is at a low level, the output of the first clock selection unit 17 is the monitoring clock signal (MCLK). The output of the second clock selection unit 18 is a functional clock signal (FCLK), wherein the monitoring clock signal (MCLK) and the functional clock signal (FCLK) are both pulse clock signals.

As can be seen from the above, in the timing detection mode, the input of the first latch 12 is the delayed data signal (D'), the input of the second latch 13 is the data signal (D), and the clock signal of the first latch 12 is the same as the clock signal of the second latch 13, so that the first latch 12 can be used as a shadow latch of the second latch 13 to monitor the timing of the second latch 13.

Next, the timing relationship in the timing detection mode will be described with reference to fig. 6.

Fig. 6 is a timing diagram of the timing detection mode according to the embodiment of the present invention. Referring to fig. 6, in the timing detection mode, the scan enable Signal (SE) is at a low level and the monitor control signal (ME) is at a high level. The scan Signal (SI) is inactive for the flip-flop circuit.

Let the propagation delay of the delay unit 11 be T_delayThe setup time of the data terminal of the latch (first latch 12, second latch 13 and third latch 211) is T_setupThe delay time from the data signal (D) to the falling edge of the pulse clock signal CLK, which is FCLK output from the pulse generating unit, is T_d. When T is_d-T_delay≥T_setupBoth the first latch 12 and the second latch 13 may sample the transition to the data input and the misprediction signal (FAIL) is inactive, i.e. the critical path is not monitored.

Please refer to (1) area, T in fig. 6_d1Is the delay from the data signal (D) to the falling edge of the pulse clock signal (CLK) in the region (1) of FIG. 6, and satisfies T_d-T_delay≥T_setupTherefore, the misprediction signal (FAIL) is low, indicating that no critical path is being detected.

Referring to the (2) region in FIG. 6, Td2 is the delay from the data signal (D) to the pulse clock signal (CLK) of the (2) region in FIG. 6, T_d-T_delay<T_setupThe second latch 13 can capture a transition at the data input while the first latch 12 cannot capture a transition at the data input, and therefore the misprediction signal (FAIL) is high indicating that the critical path is detected.

As can be seen from the above description, T_delayMonitoring the window time for the critical path, i.e. when the path timing falls on T of the frequency_delayWhen the range is within, the circuit can monitor the range.

In the functional mode, the scan enable Signal (SE) is at a low level, AND the monitor enable signal (ME) is at a low level, so that the output of the third latch 211 is at a low level, AND the monitor clock signal (MCLK) or the scan clock Signal (SCLK) of the output of the AND gate AND is at a low level. Since the scan enable Signal (SE) is low, the pulse generator 22 outputs the pulse clock signal (FCLK).

Since the scan enable Signal (SE) is low, the output (DA) of the first input selection unit 15 is the delayed data signal (D '), i.e., the input of the first latch 12 is the delayed data signal (D'). The output (DB) of the second input selection unit 16 is the data signal (D), i.e. the input of the second latch 13 is the data signal (D).

Since the scan enable Signal (SE) is at a low level, the output of the first clock selection unit 17 is the monitoring clock signal (MCLK). The output of the second clock selection unit 18 is a functional clock signal (FCLK), wherein the monitoring clock signal (MCLK) is at a low level and the functional clock signal (FCLK) is a pulse clock signal.

As described above, in the functional mode, an invalid signal is input to the first latch 12, so that the first latch 12 is in a latched state. A pulse clock signal is input to the second latch 13 so that the second latch 13 realizes the function of a pulse latch. In this mode, since the clock generation unit can control the first latch 12 to be in the latch state, the first latch 12 is prevented from being flipped, thereby saving power consumption of the circuit.

Next, the timing relationship in the functional mode will be described with reference to fig. 7.

Fig. 7 is a timing diagram of the functional modes according to the embodiment of the present invention. Referring to fig. 7, in the functional mode, the scan enable Signal (SE) is low, and the monitor control signal (ME) is low. The scan Signal (SI) is disabled for the flip-flop circuit and the misprediction signal (FAIL) is disabled. The output (Q) of the second latch 13 changes following the change of the data signal (D).

Fig. 8 is a schematic structural diagram of a control circuit according to an embodiment of the present invention. Referring to fig. 8, the control circuit 30 includes M timing paths 31, a signal processing module 32, and an adjusting module 33, where each timing path 31 includes a flip-flop circuit 10, the adjusting module includes a voltage adjusting unit and/or a frequency adjusting unit, and M is an integer greater than or equal to 1. M trigger circuits in the M time sequence paths are respectively connected with a signal processing module, and the signal processing module is connected with a regulating module; the adjusting modules are respectively connected with the M time sequence paths.

In practical application, each flip-flop circuit may detect a critical path in its corresponding timing path and send a false prediction signal (FAIL) to the signal processing module. If one of the misprediction signals received by the signal processing module is at a high level, the signal processing module sends a total misprediction signal (Pre-Error) at the high level to the adjusting module.

Alternatively, the operating voltage of the circuit may be controlled by the voltage regulating unit, for example, the voltage may be raised, after the regulating module receives the high level total Error prediction signal (Pre-Error). Alternatively, the frequency adjustment unit may adjust the frequency, for example, the frequency may be decreased.

After the adjustment module performs the voltage adjustment or the frequency adjustment, a reset signal may be generated to cause the signal processing module to reset the total Error prediction signal (Pre-Error) to a low level to cause the system to enter a new monitoring cycle.

Fig. 9 is a schematic structural diagram of another control circuit according to an embodiment of the present invention. In addition to the embodiment shown in fig. 8, referring to fig. 9, the control circuit 20 further includes a control module 24 and a power supply 25. The control module is respectively connected with the signal processing module, the frequency adjusting unit and the voltage adjusting unit, and the voltage adjusting unit is also connected with the power supply.

Optionally, after the control module receives the high-level total Error prediction signal (Pre-Error) sent by the signal processing module, the control module may send an adjustment instruction to the voltage adjustment module to enable the voltage adjustment module to adjust the output voltage of the power supply, or the control module may send an adjustment instruction to the frequency adjustment module to enable the frequency adjustment module to perform frequency adjustment.

Fig. 10 is a schematic structural diagram of a timing path according to an embodiment of the present invention. Referring to fig. 10, the timing path includes memory devices, combinational logic, critical path and flip-flop circuits, etc. For example, the flip-flop at the end of the critical path may be replaced with the flip-flop circuit in the present application, resulting in the above-mentioned timing path. Fig. 10 illustrates the configuration of the timing path by way of example only, and does not limit the configuration of the timing path.

The embodiment of the present application further provides a chip including the flip-flop circuit described in any of the above embodiments.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the embodiments of the present invention, and are not limited thereto; although embodiments of the present invention have been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the embodiments of the present invention.