阅读说明：本技术 检测装置 (Detection device ) 是由 田中仁 多田正浩 中村卓 水桥比吕志 后藤词贵 加藤博文 于 2019-02-05 设计创作，主要内容包括：具有：衬底；有机材料层,其设在衬底的上侧且至少设在与检测区域重叠的位置；在与衬底垂直的方向上设在衬底与有机材料层之间的多个检测电极；在多个检测电极的每一个设置的第一开关元件；与第一开关元件连接且在第一方向上延伸的多条栅极线；与第一开关元件连接且在与第一方向交叉的第二方向上延伸的多个信号线；以及驱动电路,其经由多条栅极线将基于规定的代码针对多条栅极线的每一条被规定了电位的栅极驱动信号向多个第一开关元件分别供给。(Comprising: a substrate; an organic material layer provided on an upper side of the substrate and at least at a position overlapping the detection region; a plurality of detection electrodes provided between the substrate and the organic material layer in a direction perpendicular to the substrate; a first switching element provided at each of the plurality of detection electrodes; a plurality of gate lines connected to the first switching elements and extending in a first direction; a plurality of signal lines connected to the first switching elements and extending in a second direction intersecting the first direction; and a drive circuit that supplies, to the plurality of first switching elements, gate drive signals, each of which has a predetermined potential for each of the plurality of gate lines based on a predetermined code, via the plurality of gate lines.)

1. A detection device, having:

a substrate;

an organic material layer provided on an upper side of the substrate and at least at a position overlapping with the detection region;

a plurality of detection electrodes provided between the substrate and the organic material layer in a direction perpendicular to the substrate;

a first switching element provided at each of the plurality of detection electrodes;

a plurality of gate lines connected to the first switching elements and extending in a first direction;

a plurality of signal lines connected to the first switching elements and extending in a second direction intersecting the first direction; and

and a drive circuit configured to supply a gate drive signal, a potential of which is defined for each of the plurality of gate lines based on a predetermined code, to each of the plurality of first switching elements via the plurality of gate lines.

2. The detection apparatus according to claim 1,

a first detection electrode block including a plurality of the detection electrodes arranged in a first direction is connected to the drive circuit via the common gate line.

3. The detection apparatus according to claim 1 or 2,

having a code generation circuit that generates a selection signal having a prescribed phase for each of the gate lines based on a prescribed code,

the drive circuit generates the gate drive signal based on the selection signal.

4. The detection apparatus according to claim 3,

the substrate has a detection region provided with a plurality of the detection electrodes, and a frame region outside the detection region,

the driving circuit is disposed in the frame region of the substrate and includes the code generating circuit.

5. The detection apparatus according to claim 3,

having a control substrate different from the substrate,

the code generation circuit is arranged on the control substrate.

6. The detection apparatus according to any one of claims 1 to 5,

comprising:

an analog front-end circuit that receives signals output from a plurality of the detection electrodes; and

a signal line selection circuit provided on the substrate,

the signal line selection circuit connects the signal line to be detected among the plurality of signal lines and the analog front-end circuit based on a predetermined code.

7. The detection apparatus according to claim 6,

a second detection electrode block including a plurality of the detection electrodes arranged in the second direction is connected to the signal line selection circuit via the common signal line.

8. The detection apparatus according to any one of claims 1 to 7,

the first switching element and a second switching element different from the first switching element are provided in each of the plurality of detection electrodes,

supplying the same gate drive signal from the drive circuit to the first switching element and the second switching element via the common gate line,

the first switching element connects the detection electrode as a detection object and the signal line,

the second switching element connects the detection electrode that is not the object of detection and a reference signal line,

the reference signal line supplies a reference signal having a fixed potential to the detection electrode of the non-detection object.

9. The detection apparatus according to claim 8,

the reference signal line is provided between two of the detection electrodes adjacent in the first direction,

the two detection electrodes adjacent to each other in the first direction are connected to the common reference signal line via the second switching elements provided to the two detection electrodes, respectively.

10. The detection apparatus according to any one of claims 1 to 9,

the detection electrode is provided with a plurality of driving electrodes arranged at the same layer with the plurality of detection electrodes.

11. The detection apparatus according to any one of claims 1 to 9,

the organic electroluminescent device includes a driving electrode facing the plurality of detection electrodes with the organic material layer interposed therebetween.

12. The detection apparatus according to claim 10 or 11,

the detection electrode is an anode, and the driving electrode is a cathode.

13. The detection apparatus according to claim 10 or 11,

the detection electrode is a cathode, the driving electrode is an anode,

the signal line is connected with an inverter circuit which inverts and outputs a current flowing to the signal line.

14. The detection apparatus according to claim 11,

having a connection terminal provided in a frame region of the substrate,

an opening is provided in a position of the organic material layer overlapping the connection terminal,

the driving electrode is connected to the connection terminal via the opening.

15. The detection apparatus according to any one of claims 1 to 14,

the signal output from the detection electrode varies in accordance with the amount of light irradiated to the organic material layer.

16. The detection apparatus according to any one of claims 1 to 14,

the signal output from the detection electrode changes in accordance with the temperature of the organic material layer.

Technical Field

The present invention relates to a detection device.

Background

In recent years, a detection device in which a plurality of sensors using an organic material are provided on a flexible substrate has been known (for example, see patent document 1). Such a sensor changes a signal output from the detection electrode according to a predetermined physical quantity such as the light amount of light irradiated to the organic material or the temperature.

Disclosure of Invention

A sensor using an organic material may have a weak change in an output signal with respect to input light, heat, or the like. In this case, the area of each sensor needs to be increased, and it is difficult to achieve high accuracy. In addition, when the change in the output signal is weak, it may be difficult to separate the output signals among the plurality of sensors.

The invention aims to provide a detection device capable of improving detection performance.

A detection device according to one aspect of the present invention includes: a substrate; an organic material layer provided on an upper side of the substrate and at least at a position overlapping with the detection region; a plurality of detection electrodes provided between the substrate and the organic material layer in a direction perpendicular to the substrate; a first switching element provided at each of the plurality of detection electrodes; a plurality of gate lines connected to the first switching elements and extending in a first direction; a plurality of signal lines connected to the first switching elements and extending in a second direction intersecting the first direction; and a drive circuit configured to supply a gate drive signal, a potential of which is determined for each of the plurality of gate lines based on a predetermined code, to each of the plurality of first switching elements via the plurality of gate lines.

Drawings

Fig. 1 is a plan view showing a detection device of a first embodiment.

Fig. 2 is a block diagram showing a configuration example of the detection device of the first embodiment.

Fig. 3 is a plan view schematically showing a back plate provided in the inspection apparatus.

Fig. 4 is a plan view schematically showing an organic sensor layer included in the detection device.

Fig. 5 is a sectional view taken along line V-V of fig. 3 and 4.

Fig. 6 is a sectional view taken along line VI-VI' of fig. 3 and 4.

Fig. 7 is a circuit diagram showing a drive circuit for one detection electrode.

Fig. 8 is a circuit diagram showing an AFE.

Fig. 9 is a timing waveform diagram showing an example of the operation of the AFE.

Fig. 10 is a circuit diagram showing the arrangement of the detection electrodes.

Fig. 11 is an explanatory diagram for explaining an operation example of code division selective driving by the gate line driving circuit.

Fig. 12 is an explanatory diagram for explaining an operation example of code division selection driving by the signal line selection circuit.

Fig. 13 is a table showing an example of the detection operation by the gate line driving circuit and the signal line selection circuit from the first period to the third period.

Fig. 14 is a table showing an example of the detection operation by the gate line driving circuit and the signal line selection circuit from the fourth period to the seventh period.

Fig. 15 is a block diagram showing a configuration example of the sensor section, the gate line driving circuit, and the signal line selection circuit.

Fig. 16 is a block diagram of a gate line driving circuit.

Fig. 17 is a timing waveform diagram showing various control signals output from the control signal generation circuit.

Fig. 18 is a circuit diagram showing an example of the first code generation circuit.

Fig. 19 is a table showing the relationship of the first control signal and the first section selection signal.

Fig. 20 is a circuit diagram showing an example of the second code generation circuit.

Fig. 21 is a table showing the relationship of the second control signal and the inverted control signal with the second section selection signal.

Fig. 22 is a circuit diagram showing an example of the third code generation circuit.

Fig. 23 is a diagram showing an example of a mode code generated by the third code generation circuit when the inverted control signal is a high-level voltage.

Fig. 24 is a diagram showing an example of a mode code generated by the third code generation circuit when the inverted control signal is a low-level voltage.

Fig. 25 is a table showing the relationship of the first control signal, the second control signal, and the inverted control signal.

Fig. 26 is a circuit diagram showing a signal line selection circuit.

Fig. 27 is a plan view showing a relationship among the detection electrode, the first switching element, and the second switching element.

Fig. 28 is a cross-sectional view showing a schematic cross-sectional structure of the first switching element.

Fig. 29 is a plan view showing a detection device of the second embodiment.

Fig. 30 is a block diagram showing a configuration example of a sensor section, a gate line driving circuit, and a signal line selection circuit according to the second embodiment.

Fig. 31 is a timing waveform diagram showing an example of the operation of the detection device according to the second embodiment.

Fig. 32 is a circuit diagram showing an AFE and an inverter circuit according to the third embodiment.

Fig. 33 is a plan view showing a detection device of the fourth embodiment.

Fig. 34 is a circuit diagram showing a driving circuit for one detection region.

Fig. 35 is a circuit diagram showing a reset circuit.

Fig. 36 is a cross-sectional view showing a schematic cross-sectional structure of the detection device of the fifth embodiment.

Fig. 37 is a plan view schematically showing a detection device of the fifth embodiment.

Fig. 38 is a plan view showing the relationship of the detection electrode, the drive electrode, the eighth switching element, and the ninth switching element.

Fig. 39 is a plan view showing an enlarged area C4 of fig. 38.

Detailed Description

Modes (embodiments) for carrying out the invention will be described in detail with reference to the drawings. The present invention is not limited to the contents described in the following embodiments. The components described below include components that can be easily conceived by those skilled in the art and substantially the same components. The following constituent elements can be appropriately combined. The present disclosure is merely an example, and it is needless to say that appropriate modifications for keeping the gist of the present invention, which are easily conceivable by those skilled in the art, are included in the scope of the present invention. In addition, in order to make the description more clear, the drawings may schematically show the width, thickness, shape, and the like of each part as compared with the actual form, but the drawings are merely examples and do not limit the explanation of the present invention. In the present specification and the drawings, the same elements as those described with respect to the already-appearing figures are denoted by the same reference numerals, and detailed description thereof may be omitted as appropriate.

(first embodiment)

Fig. 1 is a plan view showing a detection device of a first embodiment. Fig. 2 is a block diagram showing a configuration example of the detection device of the first embodiment. As shown in fig. 1 and 2, the detection device 1 includes a sensor section 10, a gate line drive circuit 15, and a signal line selection circuit 16.

As shown in fig. 1, the control board 101 is electrically connected to the sensor unit 10 via the flexible printed board 71. The flexible printed board 71 is provided with an analog Front end circuit (hereinafter referred to as afe (analog Front end)48, the control substrate 101 is provided with a control circuit 102 and a power supply circuit 103, the control circuit 102 is, for example, an FPGA (Field Programmable Gate Array), the control circuit 102 supplies control signals to the sensor section 10, the Gate line drive circuit 15, and the signal line selection circuit 16 to control a detection operation, and the power supply circuit 103 supplies voltage signals such as a power supply voltage VDD to the sensor section 10 and the Gate line drive circuit 15.

As shown in fig. 2, the detection device 1 further includes a detection control unit 11 and a detection unit 40. A part or all of the functions of the detection control unit 11 are included in the control circuit 102. In addition, a part or all of the functions of the detection unit 40 other than the AFE48 are included in the control circuit 102.

The sensor portion 10 is a photosensor having an organic material layer 31 (see fig. 5). The organic material layer 31 included in the sensor portion 10 changes its characteristics (for example, voltage-current characteristics or resistance value) according to the light irradiated thereto. The sensor section 10 outputs a signal corresponding to the amount of light irradiated to the signal line selection circuit 16. The sensor unit 10 is driven by Code Division selective driving (hereinafter, referred to as CDM (Code Division Multiplexing)), and detects the first gate drive signal VGH and the second gate drive signal VGL supplied from the gate line drive circuit 15 in accordance therewith. That is, the plurality of detection electrodes 24 are simultaneously selected by the operation of the gate line driving circuit 15 (see fig. 5).

The detection controller 11 is a circuit that supplies control signals to the gate line driver circuit 15, the signal line selection circuit 16, and the detector 40, respectively, and controls the operations of these components. The detection control section 11 includes a driving section 11a and a clock signal output section 11 b. The driving section 11a supplies the power supply voltage VDD to the gate line driving circuit 15. The detection control section 11 supplies various control signals Vctrl to the gate line drive circuit 15 based on the clock signal of the clock signal output section 11 b.

The gate line driving circuit 15 is a circuit that simultaneously selects a plurality of gate lines GCL (see fig. 7) based on various control signals Vctrl. The gate line driving circuit 15 supplies the first gate driving signal VGH or the second gate driving signal VGL to the selected plurality of gate lines GCL. Thereby, the gate line driving circuit 15 selects the plurality of detection electrodes 24 connected to the gate line GCL. The sensor unit 10 can realize CDM driving by changing the state of selection of the detection electrode 24 by the gate line driving circuit 15.

The signal line selection circuit 16 is a switch circuit that simultaneously selects a plurality of signal lines SGL (see fig. 7). The signal line selection circuit 16 performs CDM driving based on the signal line selection signal Vhsel supplied from the detection control unit 11. Thereby, the signal line selection circuit 16 selects the plurality of detection electrodes 24 connected to the signal line SGL. The signal line selection circuit 16 outputs the first output signal Svh (1) and the second output signal Svh (2) to the detection unit 40. The first output signal Svh (1) and the second output signal Svh (2) are signals that integrate the detection signals of the selected plurality of detection electrodes 24.

The detector 40 is a circuit that detects a predetermined physical quantity based on the control signal supplied from the detection controller 11, the first output signal Svh (1), and the second output signal Svh (2) during CDM driving. The detection unit 40 includes an AFE48, a signal processing unit 44, a coordinate extraction unit 45, a storage unit 46, and a detection timing control unit 47. The detection timing control unit 47 controls the AFE48, the signal processing unit 44, and the coordinate extraction unit 45 to operate in synchronization with each other based on the control signal supplied from the detection control unit 11. In the following description, the first output signal Svh (1) and the second output signal Svh (2) are simply indicated as the output signal Svh, unless it is necessary to distinguish between them.

The AFE48 is a signal processing circuit having at least the functions of the detection signal amplification section 42 and the a/D conversion section 43. The detection signal amplification unit 42 amplifies the output signal Svh. The a/D converter 43 converts the analog signal output from the detection signal amplifier 42 into a digital signal.

The signal processing unit 44 is a logic circuit that detects a predetermined physical quantity input to the sensor unit 10 based on the output signal of the AFE 48. The signal processing unit 44 receives the first output signal Svh (1) and the second output signal Svh (2) via the signal line selection circuit 16, and calculates the third output signal Svh (3). The signal processing unit 44 receives the calculated third output signal Svh (3), and performs decoding processing based on a predetermined code. The signal processing unit 44 can also perform processing for extracting a signal (absolute value | Δ V |) of a difference between decoded signals. The signal processing unit 44 can detect the amount of light applied to the sensor unit 10 by comparing the absolute value | Δ V | with a predetermined threshold voltage.

The storage unit 46 temporarily stores the calculated third output signal Svh (3). The storage unit 46 may be, for example, a RAM (Random Access Memory) or a register circuit.

The coordinate extraction unit 45 calculates sensor coordinates based on the difference signal of the decoded signal, and outputs the obtained sensor coordinates as the sensor output Vo. The coordinate extraction unit 45 may output the decoded signal as the sensor output Vo without calculating the sensor coordinates.

Next, the detailed configuration of the detection device 1 will be described. Fig. 3 is a plan view schematically showing a back plate provided in the inspection apparatus. Fig. 4 is a plan view schematically showing an organic sensor layer included in the detection device. Fig. 5 is a sectional view taken along line V-V of fig. 3 and 4. Fig. 6 is a sectional view taken along line VI-VI' of fig. 3 and 4.

As shown in fig. 5, the detection device 1 has a back plate 2 and an organic sensor layer 3. The organic sensor layer 3 is disposed opposite to the direction perpendicular to the surface of the back plate 2. The back plate 2 is a drive circuit board for driving the sensor for each predetermined detection area.

The backplate 2 comprises a substrate 21, a TFT layer 22, an insulating layer 23 and a detection electrode 24. The substrate 21 is a glass substrate having light-transmitting properties capable of transmitting visible light. Alternatively, the substrate 21 may be a light-transmitting resin substrate or a resin film made of a resin such as polyimide. The TFT layer 22 is provided on the substrate 21. The TFT layer 22 is provided with circuits such as the gate line driver circuit 15 and the signal line selection circuit 16. In addition, the TFT layer 22 is provided with various wirings such as a first switching element Tr and a second switching element xTr (see fig. 10) of a TFT (Thin Film Transistor), a gate line GCL, and a signal line SGL (see fig. 10).

The detection electrodes 24 are arranged in a matrix on the upper side of the substrate 21. The detection electrode 24 is provided between the substrate 21 and the organic material layer 31 of the organic sensor layer 3. For the detection electrode 24, a light-transmitting conductive material such as ITO (Indium Tin Oxide) is used. An insulating layer 23 is provided between the detection electrode 24 and the TFT layer 22. The insulating layer 23 is an inorganic insulating layer. As the insulating layer 23, for example, silicon oxide (SiO) is used₂) And the like, and nitrides such as silicon nitride (SiN). The flexible printed board 71 is connected to the frame area GA of the substrate 21. The detection electrode 24 is electrically connected to the flexible printed circuit board 71 via the signal line SGL and the signal line selection circuit 16.

In the description of the detection apparatus 1, the direction from the substrate 21 toward the organic sensor layer 3 in the direction perpendicular to the surface of the substrate 21 will be referred to as "upper side". The direction from the organic sensor layer 3 toward the substrate 21 is referred to as "lower side". In addition, "plan view" represents a case of being viewed from a direction perpendicular to the surface of the substrate 21.

The organic sensor layer 3 includes an organic material layer 31, a drive electrode 32, and a protective layer 33. The organic material layer 31 is provided on the plurality of detection electrodes 24. The organic material layer 31 is formed of an organic material whose characteristics (e.g., voltage-current characteristics and resistance value) change in response to light irradiated thereto. As the organic material layer 31, for example, a low-molecular organic material C can be used₆₀(Fullerene), PCBM (Phenyl C61 methyl butyrate: Phenyl C61-butyl acid methyl ester), CuPc (copper phthalocyanine: Copperphthalocyanine), F₁₆CuPc (copper phthalocyanine fluoride), rubrene (rubrene: 5,6,11, 12-tetraphenyltrecene), PDI (derivative of Perylene), and the like. The organic material layer 31 can be formed by vapor deposition (Dry Process) using these low-molecular organic materials. In this case, the organic material layer 31 may be CuPc or F, for example₁₆Laminated film of CuPc, or rubrene and C₆₀The laminated film of (3). The organic material layer 31 can also be formed by a coating type (Wet Process). In this case, the organic material layer 31 is formed by using the above-mentioned low molecular compoundA material composed of a combination of an organic material and a polymer organic material. Examples of the polymer organic material include P3HT (poly (3-hexylthiophene)), F8BT (F8-alt-benzodiazepine: 9, 9-dioctylfluorene-benzothiadiazole), and the like. The organic material layer 31 may be a film in which P3HT and PCBM are mixed or a film in which F8BT and PDI are mixed.

The drive electrode 32 is provided to face the plurality of detection electrodes 24 with the organic material layer 31 interposed therebetween in a direction perpendicular to the surface of the substrate 21. An organic material layer 31 is provided between the drive electrode 32 and the detection electrode 24. The drive electrode 32 is in contact with the upper surface of the organic material layer 31, and the detection electrode 24 is in contact with the lower surface of the organic material layer 31. As the drive electrode 32, for example, a metal material such as silver (Ag) or aluminum (Al) is used. Alternatively, the drive electrode 32 may be an alloy material containing at least 1 or more of these metal materials. The protective layer 33 is provided to cover the drive electrode 32. The protective layer 33 is a passivation film and is provided to protect the driving electrode 32 and the organic material layer 31.

As shown in fig. 3, a plurality of detection electrodes 24 are provided in a matrix in the detection area AA of the substrate 21. In other words, the plurality of detection electrodes 24 are arranged in the first direction Dx and in the second direction Dy. Here, the detection area AA is an area where the detection device 1 performs detection. The frame area GA is an area outside the detection area AA.

The first direction Dx is one of directions in a plane parallel to the substrate 21, for example, a direction parallel to the gate line GCL (see fig. 10). The second direction Dy is one of the directions in a plane parallel to the substrate 21, and is a direction orthogonal to the first direction Dx. The second direction Dy may intersect the first direction Dx, instead of being orthogonal to the first direction Dx.

Various circuits such as the gate line driver circuit 15 and the signal line selection circuit 16 are provided in the frame area GA of the substrate 21. The gate line driving circuit 15 is disposed on a side of the frame area GA along the second direction Dy. The signal line selection circuit 16 is provided on the side of the frame area GA along the first direction Dx. The signal line selection circuit 16 is provided between the detection area AA and the flexible printed board 71.

In addition, a plurality of terminals 25 and a driving electrode connection terminal 29 are provided in the frame area GA of the substrate 21. The flexible printed board 71 is connected to the plurality of terminals 25. The driving electrode connection terminal 29 is a terminal for supplying a driving signal VDD _ ORG (see fig. 15) to the driving electrode 32. The driving electrode connection terminal 29 is connected to the flexible printed circuit board 71. Thereby, the driving signal VDD _ ORG is supplied from the control board 101 (see fig. 1) to the driving electrode connection terminal 29.

As shown in fig. 4, the organic material layer 31, the driving electrode 32, and the protective layer 33 are disposed to overlap each other at the outer circumferential position of the frame area GA. In other words, the organic material layer 31 and the driving electrode 32 are provided at least in a region overlapping the detection region AA shown in fig. 3. Thus, the organic material layer 31 and the drive electrode 32 are provided across the plurality of detection electrodes 24, and have portions overlapping with the plurality of detection electrodes 24 and portions not overlapping with the plurality of detection electrodes 24. The organic material layer 31 is formed by coating such as inkjet printing. In the present embodiment, the organic material layer 31 is a high-resistance material, and the interval between adjacent detection electrodes 24 is sufficiently large with respect to the thickness of the organic material layer 31. Therefore, a current in the vertical direction flows between the drive electrode 32 and each of the detection electrodes 24, and a current flowing between the adjacent detection electrodes 24 is suppressed. Thereby, the plurality of detection electrodes 24 function as individual sensors.

Concave portions 3a are provided on the outer peripheries of the organic material layer 31, the drive electrode 32, and the protective layer 33 so as to be recessed inward. The recess 3a is provided at a position overlapping the plurality of terminals 25. Thereby, the plurality of terminals 25 are exposed from the organic material layer 31, the driving electrodes 32, and the protective layer 33, and are connected to the flexible printed circuit 71.

In addition, the organic material layer 31 is provided with an opening 31a at a position overlapping with the driving electrode connection terminal 29. As shown in fig. 6, the driving electrode connection terminal 29 is provided on the substrate 21 via an insulating layer 25A. The driving electrode connection terminal 29 and the signal line SGL are provided on the same layer. The hard coat layer 25B and the insulating layer 23 are provided on the insulating layer 25A. The hard coat layer 25B and the insulating layer 23 have openings 25Ba and 23a at positions overlapping the driving electrode connection terminals 29. The opening 31a of the organic material layer 31 is provided at a position overlapping the openings 25Ba, 23 a.

The connection electrode 34 is provided at a position of the organic material layer 31 overlapping the opening 31 a. Thereby, the connection electrode 34 is in contact with the driving electrode connection terminal 29. The drive electrode 32 and the protective layer 33 are also provided at positions overlapping the openings 31 a. According to this structure, the driving electrode 32 is electrically connected to the driving electrode connection terminal 29 via the opening 31 a. The drive signal VDD _ ORG is supplied from the control board 101 (see fig. 1) to the drive electrodes 32 via the flexible printed board 71 and the drive electrode connection terminals 29.

Next, the detection operation of the detection device 1 will be described. Fig. 7 is a circuit diagram showing a drive circuit for one detection electrode. Fig. 8 is a circuit diagram showing an AFE. Fig. 9 is a timing waveform diagram showing an example of the operation of the AFE.

As shown in fig. 7, wiring lines such as the detection electrode 24, the first switching element Tr, the second switching element xTr, the signal line SGL, the gate line GCL, and the reference signal line COM are formed on the rear plate 2 (see fig. 5). The first switching element Tr and the second switching element xTr are provided corresponding to the detection electrodes 24, respectively. The signal line SGL is a wiring for outputting the detection signal of each detection electrode 24 to the AFE48 via the signal line selection circuit 16 (see fig. 3). The gate line GCL is a wiring for supplying a first gate driving signal VGH and a second gate driving signal VGL for driving the first switching element Tr and the second switching element xTr. The reference signal line COM is a wiring for supplying a reference signal Vcom (see fig. 15) to the detection electrode 24.

The first switching element Tr is formed of a thin film transistor, and in this example, is formed of an n-channel MOS (Metal oxide semiconductor) TFT. The second switching element xTr is formed of a p-channel MOS TFT in this example. That is, when the same first gate drive signal VGH is supplied, the first switching element Tr is turned on, and the second switching element xTr is turned off. When the same second gate drive signal VGL is supplied, the first switching element Tr is turned off and the second switching element xTr is turned on. Further, the first gate driving signal VGH is a voltage signal having a higher potential than the second gate driving signal VGL.

The first switching element Tr has a source connected to the signal line SGL, a gate connected to the gate line GCL, and a drain connected to the detection electrode 24, as one detection electrode 24. The second switching element xTr has a drain connected to the reference signal line COM, a gate connected to the gate line GCL, and a source connected to the detection electrode 24. As shown in fig. 7, the organic material layer 31 is equivalently represented as a diode element. In the present embodiment, the detection electrode 24 is an anode, and the drive electrode 32 is a cathode.

When the gate line drive circuit 15 supplies the first gate drive signal VGH to the gate line GCL, the first switching element Tr is turned on. The first switching element Tr connects the detection electrode 24 and the signal line SGL. Thereby, the detection electrode 24 is selected as the detection target. When the driving signal VDD _ ORG is supplied to the driving electrode 32, a predetermined current Ifh flows through the organic material layer 31. The current Ifh changes based on the change in the characteristics of the organic material layer 31 corresponding to the irradiated light. The plurality of detection electrodes 24 output the current Ifh from the organic material layer 31 to the signal line SGL as an output signal Svh. On the other hand, the second switching element xTr is turned off by the first gate driving signal VGH. Therefore, the current Idh flowing from the detection electrode 24 to the reference signal line COM is suppressed. In this manner, the sensor unit 10 changes the signal (current Ifh) output from the detection electrode 24 according to the amount of light irradiated to the organic material layer 31. Thereby, the detection device 1 can detect light.

When the gate line drive circuit 15x supplies the second gate drive signal VGL to the gate line GCL, the first switching element Tr is turned off. This suppresses the current Idl flowing from the detection electrode 24 to the signal line SGL, and the detection electrode 24 becomes a non-detection target. On the other hand, the second switching element xTr is turned on. The second switching element xTr connects the detection electrode 24 and the reference signal line COM. Therefore, a current Ifl flows from the detection electrode 24 to the reference signal line COM. The reference signal Vcom is supplied from the control substrate 101 to the reference signal line COM. The reference signal Vcom is a voltage signal having a fixed potential. The reference signal Vcom can be, for example, a ground potential. This suppresses variation in the potential of the detection electrode 24 that is not the object of detection.

As a material of the semiconductor layers of the first switching element Tr and the second switching element xTr, polysilicon or an oxide semiconductor is used. For the semiconductor layer, Low Temperature Polysilicon (LTPS) is used, for example. The first switching element Tr and the second switching element xTr using low-temperature polysilicon can be manufactured at a process temperature of 600 ℃. Therefore, circuits such as the gate line driving circuit 15 and the signal line selection circuit 16 can be formed over the same substrate as the first switching element Tr and the second switching element xTr. The detection device 1 has a first switching element Tr and a second switching element xTr. Therefore, when one of the first switching element Tr and the second switching element xTr is turned on, the other is turned off, and leakage current can be suppressed.

As shown in fig. 8, the AFE48 has an amplifier 481, a capacitor Cf, a first switch SW1, and a second switch SW 2. In fig. 8, the second switching element xTr and the reference signal line COM are not shown. The first switch SW1 is a switch for controlling the detection timing based on a control signal from the detection control unit 11 (see fig. 2). The second switch SW2 is a switch for resetting the AFE48 based on a control signal from the detection controller 11 (see fig. 2).

As shown in fig. 8, a current Ifh flows from the detection electrode 24 to the signal line SGL. AFE48 converts variations in current Ifh into variations in voltage. The obtained voltage value is then integrated and output as the sensor output Vo. The signal processing unit 44 (see fig. 2) can detect the amount of light irradiated to the sensor unit 10 by comparing the amplitude (| Δ V |) of the output signal Svh with a predetermined threshold voltage.

As shown in fig. 9, in the non-detection period toff, the first switch SW1 is turned off, and the AFE48 is disconnected from the signal line SGL. In the non-detection period toff, the second switch SW2 is turned on. Thereby, the AFE48 is reset, and the output signal Svh becomes equal in potential to the ground potential GND.

In the detection period ton, the first switch SW1 is turned on, and the AFE48 is connected to the signal line SGL. In the detection period ton, the second switch SW2 is turned off. This causes the charge to move to the capacitor Cf, and the amplitude (| Δ V |) of the sensor output Vo increases. The detection device 1 can detect light by repeating the non-detection period toff and the detection period ton at a predetermined frequency.

Next, the circuit configuration of the plurality of detection electrodes 24 will be described. Fig. 10 is a circuit diagram showing the arrangement of the detection electrodes. In fig. 10 and the like, for convenience of explanation, the detection electrodes 24 arranged in 4 rows and 4 columns in a matrix are exemplified, but not limited thereto. For example, a plurality of detection electrodes 24 are arranged in 256 rows and 256 columns. Fig. 10 shows four gate lines GCL (1), GCL (2), GCL (3), GCL (4), two reference signal lines COM (1), COM (2), and four signal lines SGL (1), SGL (2), SGL (3), SGL (4). In the following description, when it is not necessary to describe the gate lines GCL (1), GCL (2), GCL (3), and GCL (4) separately, they are only indicated as gate lines GCL. Similarly, the reference signal line COM and the signal line SGL may be illustrated.

The plurality of gate lines GCL and the plurality of signal lines SGL are arranged to cross. The plurality of gate lines GCL and the plurality of reference signal lines COM are arranged to intersect. The gate lines GCL, the signal lines SGL, and the reference signal lines COM are divided into a matrix. The detection electrode 24 is disposed in a region surrounded by the gate line GCL, the signal line SGL, and the reference signal line COM. The one partitioned areas each function as a sensor.

Here, the plurality of detection electrodes 24 arranged in the first direction Dx are set as a first detection electrode block BKx. The first detection electrode blocks BKx (1), BKx (2), BKx (3), BKx (4) are arranged in the second direction Dy. The plurality of first switching elements Tr and the plurality of second switching elements xTr provided in the first detection electrode block BKx (1) are connected to a common gate line GCL (1). The plurality of first switching elements Tr and the plurality of second switching elements xTr provided in the first detection electrode block BKx (2) are connected to the common gate line GCL (2). The same applies to the first detection electrode block BKx (3) and the first detection electrode block BKx (4). The gate lines GCL (1), GCL (2), GCL (3), and GCL (4) are connected to a gate line driving circuit 15, respectively.

The signal line SGL is provided for each of the detection electrodes 24 arranged in the first direction Dx. Here, the plurality of detection electrodes 24 arranged in the second direction Dy along the signal line SGL are set as the second detection electrode block BKy. The second sensing electrode blocks BKy (1), BKy (2), BKy (3), BKy (4) are arranged in the first direction Dx. The plurality of first switching elements Tr provided in the second detection electrode block BKy (1) are connected to the common signal line SGL (1). The plurality of first switching elements Tr provided in the second detection electrode block BKy (2) are connected to the common signal line SGL (2). The same applies to the second detection electrode blocks BKy (3), BKy (4). That is, the signal line SGL is provided for each of the second detection electrode blocks BKy. The signal lines SGL (1), SGL (2), SGL (3), and SGL (4) are connected to the signal line selection circuit 16, respectively. The reference signal line COM is provided between the detection electrodes 24 adjacent in the first direction Dx. The detection electrodes 24 adjacent to each other with the reference signal line COM interposed therebetween are connected to the common reference signal line COM via the second switching elements xTr provided respectively.

The gate line driving circuit 15 supplies the first gate driving signal VGH and the second gate driving signal VGL, which have predetermined potentials for the respective gate lines GCL, to the respective gate lines GCL based on a predetermined code. Thus, the gate line driving circuit 15 selects 1 or 2 or more gate lines GCL from the plurality of gate lines GCL based on a predetermined code and drives the selected gate lines GCL. The gate line drive circuit 15 applies a first gate drive signal VGH to the gate of the first switching element Tr via the selected gate line GCL. Thus, 1 or 2 or more first detection electrode blocks BKx are selected as detection targets and connected to the signal line SGL. In addition, the gate line drive circuit 15 applies the second gate drive signal VGL to the gate of the second switching element xTr via the gate line GCL that is not the detection object. Thus, 1 or 2 or more first detection electrode blocks BKx are selected as non-detection targets and connected to the reference signal line COM.

The signal line selection circuit 16 selects 1 or 2 or more signal lines SGL from the plurality of signal lines SGL based on a predetermined code and drives them. The signal line selection circuit 16 connects the selected signal line SGL to one output signal line Lout. Thus, the plurality of second detection electrode blocks BKy are connected to the AFE48 via one output signal line Lout.

Fig. 11 is an explanatory diagram for explaining an operation example of code division selective driving by the gate line driving circuit. In fig. 11, for convenience of explanation, an example of operation of CDM driving is shown for a second detection electrode block BKy having four detection electrodes 24. In fig. 11, the detection electrode 24 to be detected is shown with diagonal lines. In fig. 11, the gate line GCL, the gate line drive circuit 15, the first switching element Tr, and the like are not shown.

Each detection electrode 24 of the second detection electrode block BKy can be connected to the common signal line SGL by the operation of the first switching element Tr. Here, the signal value output from each detection electrode 24 is set as the signal value Si_q(q is 0, 1, 2, 3). The gate line drive circuit 15 selects 1 or a plurality of the detection electrodes 24 based on a predetermined code in the detection electrodes 24 of the second detection electrode block BKy. The signal value Si of the selected detection electrode 24_qThe integrated signal value is taken as the output signal Sv via the signal line SGL_p(p is 0, 1, 2, 3) and outputs. Output signal Sv_pThe following formula (1) is used. I.e. the output signal Sv_pUsing the signal values Si output from the plurality of detection electrodes 24 as detection objects in one second detection electrode block BKy_qIs expressed as a sum of.

[ mathematical formula 1 ]

The signal value Si is used here_qThe signal values are corresponding to the detection electrodes 24 of the first detection electrode blocks BKx (1), BKx (2), BKx (3), BKx (4). Signal value Si_qIs a signal value output according to light irradiated to the organic material layer 31. Output signal Sv_pThe signal value Si of the detection electrode 24 selected based on a predetermined code in the second detection electrode block BKy as the output signal of the second detection electrode block BKy_qA value obtained by performing an operation. The predetermined code is defined by, for example, a square matrix H of the following expression (2). The predetermined code is a code of a square matrix, for example, a hadamard matrix, which has "1" or "-1" or "0" as an element and is orthogonal to each other on the basis of two arbitrary different rows.

[ mathematical formula 2 ]

The number of times of the square matrix H becomes the number of detection electrodes 24 included in the second detection electrode block BKy, that is, the number 4 of the four first detection electrode blocks BKx. In the present embodiment, the second detection electrode block BKy including four detection electrodes 24 is described, but the present invention is not limited thereto, and the number of detection electrodes 24 included in the second detection electrode block BKy may be two, three, or five or more. In this case, the number of times of the square matrix H is also changed depending on the number of the detection electrodes 24.

In the first period ta1 and the first period ta1x shown in fig. 11, the gate line drive circuit 15 supplies the first gate drive signal VGH and the second gate drive signal VGL to each gate line GCL in accordance with the selection signal corresponding to the first row of the square matrix H. Thereby, the detection electrode 24 to be detected is selected. In the second period ta2 and the third period ta3, the detection electrodes 24 are selected in accordance with the selection signal corresponding to the second row of the square matrix H. In the fourth period ta4 and the fifth period ta5, the detection electrode 24 is selected in accordance with the selection signal corresponding to the third row of the square matrix H. In the fourth period ta4 and the fifth period ta5, the detection electrode 24 is selected by the selection signal corresponding to the fourth row of the square matrix H.

Specifically, in the first period ta1, the gate line drive circuit 15 supplies the first gate drive signal VGH having a predetermined potential corresponding to the element "1" in the first row of the square matrix H to each gate line GCL. The first switching element Tr is turned on by the first gate driving signal VGH, and the four detection electrodes 24 are connected to the common signal line SGL. Thereby, four detection electrodes 24 are selected as the first detection target. The detection electrode 24 of the first detection object outputs the first output signal Sv via the signal line SGL₀(1) Output to AFE 48. First output signal Sv₀(1) The signals are integrated with the detection signals of the four detection electrodes 24.

Next, in the first period ta1x, since the element "-1" in the first row of the square matrix H does not exist, the detection electrode 24 is not selected as the second detection target corresponding to the element "-1". Gate line driving circuit 15 for detecting the direction of each electrodeThe gate line GCL corresponding to 24 supplies the second gate driving signal VGL. Thus, the second output signal Sv₀(2) Becomes 0. The signal processing section 44 outputs the first output signal Sv in accordance with the first output signal Sv₀(1) And the second output signal Sv₀(2) Calculates the third output signal Sv₀(3)＝Sv₀(1)-Sv₀(1)。

Next, in the second period ta2, the gate line driving circuit 15 supplies the first gate driving signal VGH having a predetermined potential corresponding to the element "1" in the second row of the square matrix H to each gate line GCL. Thus, the two detection electrodes 24 belonging to the first detection electrode blocks BKx (1), BKx (3) are selected as the first detection target. The detection electrode 24 of the first detection object outputs the first output signal Sv via the signal line SGL₁(1) Output to AFE 48.

Next, in the third period ta3, the gate line driving circuit 15 supplies the first gate driving signal VGH having a predetermined potential corresponding to the element "-1" in the second row of the square matrix H to each gate line GCL. Thus, the two detection electrodes 24 belonging to the first detection electrode blocks BKx (2), BKx (4) are selected as the second detection target. The detection electrode 24 of the second detection object outputs the second output signal Sv via the signal line SGL₁(2) Output to AFE 48. The signal processing section 44 outputs the first output signal Sv in accordance with the first output signal Sv₁(1) And the second output signal Sv₁(2) Calculates the third output signal Sv₁(3)＝Sv₁(1)-Sv₁(2)。

Similarly, in the fourth period ta4, the gate line driving circuit 15 selects the first detection target corresponding to the element "1" in the third row of the square matrix H. In the fifth period ta5, the gate line driving circuit 15 selects the second detection target corresponding to the element "-1" in the third row of the square matrix H. In the sixth period ta6, the gate line driving circuit 15 selects the first detection target corresponding to the element "1" in the fourth row of the square matrix H. In the seventh period ta7, the gate line driving circuit 15 selects the second detection target corresponding to the element "-1" in the fourth row of the square matrix H.

Thus, the signal processing unit 44 performs processing on the four fourth signalsThree output signal Sv₀(3)、Sv₁(3)、Sv₂(3)、Sv₃(3) And (6) performing operation. Then, the signal processing section 44 outputs the four third output signals Sv₀(3)、Sv₁(3)、Sv₂(3)、Sv₃(3) And multiplying by a square matrix H for decoding. Thus, the detection device 1 obtains a signal strength 4 times without increasing the voltage value of the driving voltage VDD _ ORG. In addition, the detection device 1 can enhance the signal intensity without increasing the area of the detection electrode 24. Therefore, the detection device 1 can perform highly accurate light detection. In addition, the third output signal Sv_p(3) According to the first output signal Sv_p(1) And the second output signal Sv_p(2) The difference of (a) is obtained. Therefore, even when noise enters from the outside or when the characteristics of the organic material layer 31 fluctuate due to the influence of the measurement environment, the noise component of the first output signal Shp (1) and the noise component of the second output signal Shp (2) can be canceled. This improves the detection reliability of the detection device 1.

Fig. 12 is an explanatory diagram for explaining an operation example of code division selection driving by the signal line selection circuit. In fig. 12, for ease of explanation, an example of CDM driving operation is shown for a first detection electrode block BKx having four detection electrodes 24.

The signal line selection circuit 16 connects the plurality of signal lines SGL to the common output signal line Lout based on a predetermined code. Thus, the signal line selection circuit 16 selects 1 or a plurality of detection electrodes 24 based on a predetermined code in the first detection electrode block BKx. Here, the signal value output from each detection electrode 24 is set as the signal value Si_q. The selected signal value Si of the detection electrode 24 is set to be the same as the formula (1)_qThe integrated signal value is output as the output signal Shp via the output signal line Lout. That is, the output signal Shp is obtained by using the signal value Si output from the plurality of detection electrodes 24 in one first detection electrode block BKx_qIs shown as a sum.

The predetermined code is defined by, for example, the square matrix H of the above equation (2). The predetermined code may be, for example, a code based on a hadamard matrix, or may be another square matrix.

As shown in fig. 12, in the first partial period tb1, four detection electrodes 24 are selected as the first detection target corresponding to the element "1" in the first row of the square matrix H. Specifically, the signal line selection circuit 16 connects the four signal lines SGL corresponding to the element "1" in the first row of the square matrix H to the common output signal line Lout by the operation of the third switch SW 3. Thus, the detection electrode 24 to be detected applies the first output signal Sh to the common output signal line Lout₀(1) Output to AFE 48. First output signal Sh₀(1) The signals are integrated with the detection signals of the four detection electrodes 24.

Next, in the first partial period tb1x, since the element "-1" in the first row of the square matrix H does not exist, the signal line selection circuit 16 disconnects the four signal lines SGL from the common output signal line Lout by the operation of the third switch SW 3. That is, the detection electrode 24 is not selected as the second detection object corresponding to the element "-1". Thus, the second output signal Sh₀(2) Becomes 0. The signal processing section 44 outputs the first output signal Sh₀(1) And the second output signal Sh₀(2) To calculate the third output signal Sh₀(3)＝Sh₀(1)-Sh₀(1)。

Next, in the second partial period tb2, the signal line selection circuit 16 connects the signal line SGL corresponding to the element "1" in the second row of the square matrix H to the common output signal line Lout by the operation of the third switch SW 3. Thus, the two detection electrodes 24 belonging to the second detection electrode blocks BKy (1), BKy (3) are selected as the first detection target. The detection electrode 24 of the first detection object outputs the first output signal Sh via the output signal line Lout₁(1) Output to AFE 48.

Next, in the third partial period tb3, the signal line selection circuit 16 connects the signal line SGL corresponding to the element "-1" in the second row of the square matrix H to the common output signal line Lout by the operation of the third switch SW 3. Thus, the two detection electrodes 24 belonging to the second detection electrode blocks BKy (2), BKy (4) are selected as the second detection target. Examination of the second detection objectThe sensing electrode 24 outputs the second output signal Sh via the output signal line Lout₁(2) Output to AFE 48. The signal processing section 44 outputs the first output signal Sh₁(1) And the second output signal Sh₁(2) To calculate the third output signal Sh₁(3)＝Sh₁(1)-Sh₁(2)。

Similarly, in the fourth partial period tb4, the first detection target corresponding to the element "1" in the third row of the square matrix H is selected by the signal line selection circuit 16. In the fifth partial period tb5, the second detection target corresponding to the element "-1" in the third row of the square matrix H is selected by the signal line selection circuit 16. In the sixth partial period tb6, the first detection target corresponding to the element "1" in the fourth row of the square matrix H is selected by the signal line selection circuit 16. In the seventh part period tb7, the second detection object corresponding to the element "-1" in the fourth row of the square matrix H is selected by the signal line selection circuit 16.

Thus, the signal processing unit 44 outputs the four third output signals Sh₀(3)、Sh₁(3)、Sh₂(3)、Sh₃(3) And (6) performing operation. Then, the signal processing section 44 outputs the four third output signals Sh₀(3)、Sh₁(3)、Sh₂(3)、Sh₃(3) And multiplying by a square matrix H for decoding. Thus, the detection device 1 obtains a signal strength 4 times higher without increasing the voltage value of the driving voltage VDD _ ORG.

The CDM driving by the gate line driving circuit 15 shown in fig. 11 and the CDM driving by the signal line selecting circuit 16 shown in fig. 12 can be performed in an appropriate combination. Fig. 13 is a table showing an example of the detection operation by the gate line driving circuit and the signal line selection circuit from the first period to the third period. Fig. 14 is a table showing an example of the detection operation by the gate line driving circuit and the signal line selection circuit from the fourth period to the seventh period.

In fig. 13, the first gate driving signal VGH and the second gate driving signal VGL supplied to the gate lines GCL (1), GCL (2), GCL (3), and GCL (4) are shown for each of the first period ta1, the second period ta2, and the third period ta 3. In fig. 13, the AFE48 or the reference signal VR to which the second detection electrode block BKy (1), BKy (2), BKy (3), BKy (4) is connected is shown for each period from the first part period tb1 to the seventh part period tb 7. Fig. 14 likewise also shows the AFE48 or the reference signal VR for the fourth period ta4 to the seventh period ta 7.

As shown in fig. 13 and 14, the first to seventh partial periods tb1 to tb7 are provided corresponding to the first to seventh periods ta1 to ta7, respectively. The order of the periods may be changed as appropriate.

As shown in fig. 13 and 14, the gate line driving circuit 15 supplies the first gate driving signal VGH and the second gate driving signal VGL, whose potentials are determined based on the predetermined code shown in equation (2), to each gate line GCL. Specifically, in the first period ta1, the gate line driving circuit 15 supplies the first gate driving signal VGH to all the gate lines GCL (1), GCL (2), GCL (3), and GCL (4) corresponding to the element "1" in the first row of equation (2). Further, since the element "-1" in the first row of the square matrix H does not exist, the first period ta1x shown in fig. 11 can be omitted. In the second period ta2, the gate line driving circuit 15 supplies the first gate driving signal VGH to the gate lines GCL (1) and GCL (3) corresponding to the element "1" in the second row of equation (2). In the second period ta2, the gate line driving circuit 15 supplies the second gate drive signal VGL to the gate lines GCL (2) and GCL (4) in correspondence with the element "-1" in the second row of equation (2).

Similarly, in the third period ta3 to the seventh period ta7, the gate line driving circuit 15 supplies the first gate driving signal VGH and the second gate driving signal VGL corresponding to each element of the formula (2) to the gate line GCL. Thus, the detection electrode 24 of the first detection target and the detection electrode 24 of the second detection target are selected in different combinations for each period.

As shown in fig. 13 and 14, the signal line selection circuit 16 connects the signal line SGL corresponding to the predetermined code shown in equation (2) to one output signal line Lout. Thereby, the signal line selection circuit 16 selects the second detection electrode block BKy. Specifically, in the first part period tb1, the signal line selection circuit 16 selects all of the second detection electrode blocks BKy (1), BKy (2), BKy (3), BKy (4) corresponding to the element "1" of the first row of expression (2). The second detection electrode blocks BKy (1), BKy (2), BKy (3), BKy (4) are connected to the AFE48 via an output signal line Lout. In this case, the detection electrode 24 of the first detection object or the second detection object selected by the gate line drive circuit 15 among the second detection electrode blocks BKy (1), BKy (2), BKy (3), BKy (4) is connected to the output signal line Lout.

Thereby, the first output signal Svh is outputted from the second detection electrode blocks BKy (1), BKy (2), BKy (3), BKy (4)₀(1) Output to AFE 48. Here, the first output signal Svh₀(1) The signals of the detection electrodes 24 to be the first detection target among the plurality of second detection electrode blocks BKy (1), BKy (2), BKy (3), BKy (4) are integrated. Additionally, second output signal Svh₀(0) The signals of the detection electrodes 24 to be detected are integrated among the plurality of second detection electrode blocks BKy (1), BKy (2), BKy (3), BKy (4). In addition, since the element "-1" is not present in the first row of equation (2), the first part period tb1x shown in fig. 12 can be omitted. The signal processing section 44 acquires the first output signal Svh of the first part period tb1₀(1) As a third output signal Svh₀(3)。

In the second part period tb2, the signal line selection circuit 16 selects the second detection electrode blocks BKy (1), BKy (3) corresponding to the element "1" of the second row of expression (2). The second detection electrode blocks BKy (1), BKy (3) are connected to the AFE48 via an output signal line Lout. Thereby, the first output signal Svh is outputted from the second detection electrode blocks BKy (1), BKy (3)₁(1) Output to AFE 48. In this case, the detection electrode 24 selected as the first detection object or the second detection object by the gate line drive circuit 15 in the second detection electrode blocks BKy (1), BKy (3) is connected to the output signal line Lout. On the other hand, the reference signal VR is supplied to the unselected second detection electrode blocks BKy (2) and BKy (4).

In the third part period tb3, the signal line selection circuit 16 selects the second detection electrode block BKy (2), BKy (4) corresponding to the element "-1" of the second row of equation (2). Second detection electrodeThe blocks BKy (2), BKy (4) are connected to the AFE48 via the output signal line Lout. Thereby, the second output signal Svh is outputted from the second detection electrode blocks BKy (2), BKy (4)₁(2) (refer to fig. 12) to the AFE 48. In this case, the detection electrode 24 selected as the first detection object or the second detection object by the gate line drive circuit 15 in the second detection electrode blocks BKy (2), BKy (4) is connected to the output signal line Lout. On the other hand, the reference signal VR is supplied to the unselected second detection electrode blocks BKy (1) and BKy (3). The signal processing section 44 outputs the first output signal Svh according to the second part period tb2₁(1) And a second output signal Svh of tb3 during the third part₁(2) Calculates the third output signal Svh₁(3)。

Similarly, the signal line selection circuit 16 selects the second detection electrode block BKy based on the predetermined code of equation (2) in the fourth part period tb4 to the seventh part period tb 7. Thus, the signal processing section 44 acquires four third output signals Svh during the first part period tb1 to the seventh part period tb7₀(3)、Svh₁(3)、Svh₂(3)、Svh₃(3). In addition, the signal processing unit 44 obtains four third output signals Svh during the first period ta1 to the seventh period ta7, as in the example shown in fig. 11₀(3)、Svh₁(3)、Svh₂(3)、Svh₃(3). That is, the signal processing unit 44 acquires 16 third output signals Svh (3) in total. Then, the signal processing unit 44 decodes the third output signal Svh (3), thereby calculating a decoded signal for each detection electrode 24. Thus, the detection device 1 can be CDM-driven by the gate line drive circuit 15 and the signal line selection circuit 16.

As shown in fig. 3, the detection electrode 24 and the signal line selection circuit 16 are provided on the substrate 21. Then, the plurality of detection electrodes 24 are connected to one AFE48 via the output signal line Lout. Thus, even when the number of detection electrodes 24 is increased, the number of AFEs 48 can be reduced. In addition, the number of wirings connecting the substrate 21 and the AFE48 can be suppressed.

Next, the detailed configuration of the gate line driving circuit 15 will be described. Fig. 15 is a block diagram showing a configuration example of the sensor section, the gate line driving circuit, and the signal line selection circuit. Fig. 16 is a block diagram of a gate line driving circuit.

As shown in fig. 15, a sensor portion 10, a gate line driver circuit 15, and a signal line selection circuit 16 are provided over a substrate 21. The substrate 21 is provided with a control signal generation circuit 17, inverters 153 and 154, and a protection circuit 155.

The protection circuit 155 includes a protection resistance element or a protection diode. Various signals supplied from the control substrate 101 (see fig. 1) are supplied to the control signal generation circuit 17, the gate line drive circuit 15, and the signal line selection circuit 16 via the protection circuit 155. Further, the output signal line Lout of the signal line selection circuit 16 is connected to the AFE48 without passing through the protection diode of the protection circuit 155. This can suppress a decrease in the signal intensity output from the sensor unit 10.

The inverter 153 receives the reset signal RST from the control substrate 101, and outputs the inverted reset signal xRST to the control signal generation circuit 17. The inverted reset signal xRST is a voltage signal that inverts the reset signal RST. The inverter 154 receives the clock signal CLK from the control board 101 and outputs an inverted clock signal xCLK to the control signal generation circuit 17. The inverted clock signal xCLK is a voltage signal that inverts the clock signal CLK.

The control signal generation circuit 17 generates various control signals based on the reset signal RST, the clock signal CLK, the ground potential GND and the power supply voltage VDD supplied from the external control substrate 101. The control signal generation circuit 17 supplies various control signals to the gate line drive circuit 15.

Fig. 17 is a timing waveform diagram showing various control signals output from the control signal generation circuit. As shown in fig. 17, the control signal generation circuit 17 outputs an inverted control signal Vs, first control signals Va1, Va2, Va3, and second control signals Vb1, Vb2, Vb 3. The inverted control signal Vs is supplied to the inverted input terminal S of the second code generation circuit 13. The first control signals Va1, Va2, Va3 are supplied to the first input terminals a1, a2, A3 of the first code generating circuit 12, respectively. The second control signals Vb1, Vb2, and Vb3 are supplied to the second input terminals B1, B2, and B3 of the second code generation circuit 13, respectively.

As shown in fig. 17, the frequency of the second control signal Vb3 is 1/2 of the frequency of the inverted control signal Vs. The frequency of the second control signal Vb2 is 1/2 the frequency of the second control signal Vb 3. Similarly, the control signal generation circuit 17 outputs the second control signal Vb1 and the first control signals Va3, Va2, and Va1, respectively.

As shown in fig. 15 and 16, the gate line driving circuit 15 includes a first code generation circuit 12, a second code generation circuit 13, a third code generation circuit 14, a buffer circuit 151, and a level shifter 152. That is, the first code generation circuit 12, the second code generation circuit 13, the third code generation circuit 14, the buffer circuit 151, and the level shifter 152 are provided in the frame area GA of the substrate 21. In fig. 16, the buffer circuit 151 and the level shifter 152 are not shown.

The first code generation circuit 12, the second code generation circuit 13, and the third code generation circuit 14 are decoder circuits. The first code generation circuit 12 generates a first partial selection signal Vd (see fig. 18 and 19) based on the first control signals Va1, Va2, and Va3, and supplies the first partial selection signal Vd to the third code generation circuit 14. The second code generation circuit 13 generates the second partial selection signal Vf (see fig. 20 and 21) based on the second control signals Vb1, Vb2, and Vb3, and supplies the second partial selection signal Vf to the third code generation circuit 14. The third code generation circuit 14 is, for example, an exclusive or (XOR) circuit. The third code generation circuit 14 generates a first selection signal Vc based on the first partial selection signal Vd and the second partial selection signal Vf, and supplies a signal based on the first selection signal Vc to the gate line GCL.

As shown in fig. 16, the first code generation circuit 12 has first input terminals a1, a2, A3, a terminal to which the power supply voltage VDD is input, and a plurality of output terminals Ya1, Ya2, … …, Ya 8. In the present embodiment, the number of the output terminals Ya1, Ya2, … …, Ya8 of the first code generating circuit 12 is 8. First control signals Va1, Va2, Va3 are input from the control signal generation circuit 17 to the first input terminals a1, a2, A3. The first code generating circuit 12 is a circuit that generates the first section selection signal Vd based on the first control signals Va1, Va2, Va 3. The first code generation circuit 12 outputs the first partial selection signal Vd to the first selection signal lines LSa1, LSa2, … …, and LSa8 from the output terminals Ya1, Ya2, … …, and Ya 8. The first partial selection signal Vd is a signal whose phase is defined for each of the plurality of gate lines GCL.

The second code generation circuit 13 has second input terminals B1, B2, B3, an inverting input terminal S, and a plurality of output terminals Yb1, Yb2, … …, Yb 8. In the present embodiment, the number of output terminals Yb1, Yb2, … …, Yb8 of the second code generation circuit 13 is 8. Second control signals Vb1, Vb2, and Vb3 are input from the control signal generation circuit 17 to the second input terminals B1, B2, and B3. In addition, the inverted control signal Vs is input from the control signal generation circuit 17 to the second code generation circuit 13. The second code generation circuit 13 is a circuit that generates the second partial selection signal Vf based on the second control signals Vb1, Vb2, Vb3 and the inverted control signal Vs. The inversion control signal Vs is a signal that inverts the elements "1" and "-1" of the prescribed code. The second code generation circuit 13 outputs the second partial selection signal Vf to the second selection signal lines LSb1, LSb2, … …, and LSb8 from the output terminals Yb1, Yb2, … …, and Yb 8. The second partial selection signal Vf is a signal whose phase is defined for each drive signal supply line block BKL.

As shown in fig. 15, the level shifter 152 is provided between the first code generation circuit 12 and the second code generation circuit 13 and the third code generation circuit 14. The level shifter 152 is a circuit that changes the voltage (amplitude) of an input signal and outputs the changed signal. Specifically, the level shifter 152 receives the first section selection signal Vd from the first code generation circuit 12 and temporarily holds it. In addition, the level shifter 152 receives the second section selection signal Vf from the second code generation circuit 13 and temporarily holds it. The level shifter 152 changes the voltage level of the first selection signal Vc by the power supply voltages VDD and VSS supplied from the control board 101. The amplitudes of the first partial selection signal Vd and the second partial selection signal Vf are increased and output to the third code generation circuit 14. The level shifter 152 may be provided on the output side of the third code generation circuit 14.

As shown in fig. 16, a plurality of gate lines GCL (1), GCL (2), … …, GCL (n) are arranged. The gate lines GCL are provided corresponding to the first detection electrode blocks BKx (see fig. 10). The number of the gate lines GCL is 64 (n-64). The gate lines GCL are connected to driving signal supply lines Ld1, Ld2, … …, and Ldn (n is 64), respectively. The drive signal supply line section blocks sBKL1, sBKL2, … …, sBKL7, sBKL8 include 8 drive signal supply lines Ld, respectively.

The first selection signal lines LSa1, LSa2, … …, and LSa8 are connected to 1 drive signal supply line Ld for each drive signal supply line segment block sBKL, respectively. Thus, the first selection signal lines LSa1, LSa2, … …, and LSa8 are connected in parallel to the plurality of drive signal supply line segment blocks sBKL1, sBKL2, … …, sBKL7, and sBKL 8. The first selection signal lines LSa1, LSa2, … …, and LSa8 are connected to different drive signal supply lines Ld. In other words, the plurality of drive signal supply lines Ld included in one drive signal supply line segment block sBKL are connected to the first selection signal lines LSa1, LSa2, … …, and LSa8, respectively. For example, the drive signal supply lines Ld1, Ld2, Ld … …, and Ld8 included in the drive signal supply line segment sBKL1 are connected to the first selection signal lines LSa1, LSa2, Ld … …, and LSa8, respectively. The same applies to the drive signal supply line segment blocks sBKL2, … …, sBKL7, and sBKL 8.

The third code generation circuits 14-1, 14-2, … …, 14-7, and 14-8 are provided corresponding to the drive signal supply line section blocks sBKL1, sBKL2, … …, sBKL7, and sBKL8, respectively. The second selection signal lines LSb1, LSb2, … …, and LSb8 are connected to the third code generation circuits 14-1, 14-2, … …, and 14-8, respectively. In other words, the second selection signal lines LSb1, LSb2, … …, and LSb8 are connected to the driving signal supply line section blocks sBKL1, sBKL2, … …, and sBKL8, respectively. One third code generation circuit 14 is connected to a plurality of first selection signal lines LSa and one second selection signal line LSb. In the present embodiment, the plurality of first selection signal lines LSa and the plurality of second selection signal lines LSb intersect the driving signal supply line Ld in a plan view.

The plurality of third code generation circuits 14 generate the first selection signal Vc based on the first partial selection signal Vd and the second partial selection signal Vf, and supply the first selection signal Vc to the buffer circuit 151 (see fig. 15).

As shown in fig. 15, the buffer circuit 151 temporarily holds the first selection signal Vc supplied from the third code generating circuit 14. Then, the buffer circuit 151 supplies the first gate driving signal VGH and the second gate driving signal VGL corresponding to the first selection signal Vc to the plurality of selected gate lines GCL substantially simultaneously.

Next, the operations of the first code generation circuit 12, the second code generation circuit 13, and the third code generation circuit 14 will be described. Fig. 18 is a circuit diagram showing an example of the first code generation circuit. Fig. 19 is a table showing the relationship of the first control signal and the first section selection signal. As shown in fig. 18, the first code generation circuit 12 includes a plurality of exclusive or circuits 51-1, 51-2, … …, 51-7. One of the first control signals Va1, Va2 and Va3, the power supply voltage VDD or an output signal from the other XOR circuit 51 are input to the XOR circuits 51-1, 51-2, … … and 51-7. The exclusive-or circuits 51-1, 51-2, … …, and 51-7 output the exclusive-or values of the input signals to the first selection signal lines LSa2, … …, and LSa8 as the first partial selection signals Vd2, Vd3, … …, and Vd 8. In addition, the same signal as the power supply voltage VDD is output to the first selection signal line LSa1 as the first partial selection signal Vd 1.

The first code generation circuit 12 generates the first partial selection signals Vd1, Vd2, … …, and Vd8 corresponding to the first control signals Va1, Va2, and Va3 and the power supply voltage VDD in accordance with the true rational value table shown in fig. 19. In fig. 19, "1" is assigned when each signal is a high-level voltage, and "0" is assigned when each signal is a low-level voltage. Thus, the first code generation circuit 12 outputs the first partial selection signals Vd1, Vd2, … …, and Vd8, the phases of which are determined based on a predetermined code, to the respective drive signal supply line block sBKL. For example, the predetermined code is defined by a square matrix of the following equation (3). The number of times of the square matrix becomes 8, which is the number of output terminals Ya1, Ya2, … …, Ya8 of the first code generating circuit 12.

[ mathematical formula 3 ]

The first code generation circuit 12 outputs the first partial selection signals Vd1, Vd2, … …, and Vd8 for each of the periods tc1, tc2, … …, and tc 8. In each of the periods tc1, tc2, … …, and tc8, the combination patterns of ON (high level voltage) and OFF (low level voltage) of the first section selection signals Vd1, Vd2, … …, and Vd8 are different. The ON/OFF combination patterns of the first partial selection signals Vd1, Vd2, … …, and Vd8 are 8 in number, which is the same as the number of the output terminals Ya1, Ya2, … …, and Ya 8.

Fig. 20 is a circuit diagram showing an example of the second code generation circuit. Fig. 21 is a table showing the relationship of the second control signal and the inverted control signal with the second section selection signal. As shown in fig. 20, the second code generation circuit 13 includes a plurality of exclusive or circuits 52-1, 52-2, … …, 52-7 and an inverter 53. The inverter 53 is a circuit that generates a voltage signal second part selection signal Vf1 that inverts the inversion control signal Vs. The inverter 53 outputs the second partial selection signal Vf1 to the second selection signal line LSb 1. That is, the inverter 53 outputs a low-level voltage signal when the inverted control signal Vs is a high-level voltage, and outputs a high-level voltage signal when the inverted control signal Vs is a low-level voltage.

One of the second control signals Vb1, Vb2 and Vb3, and the output signal from the inverter 53 or the output signal from the other exclusive or circuit 52 are input to the exclusive or circuits 52-1, 52-2, … … and 52-7. The inverted control signal Vs and the second control signals Vb1, Vb2, Vb3 are output signals from the control signal generating circuit 17 shown in fig. 15. The exclusive or circuits 52-1, 52-2, … …, 52-7 output the exclusive or value of the input signals to the second selection signal lines LSb2, LSb3, … …, LSb8 as the second partial selection signals Vf2, Vf3, … …, Vf8, respectively. The inverter 53 is not necessarily required, and the second code generation circuit 13 may output the inverted control signal Vs as the second partial selection signal Vf 1.

The second code generation circuit 13 generates the second partial selection signal Vf corresponding to the second control signals Vb1, Vb2, Vb3 and the inverted control signal Vs according to the true rational value table shown in fig. 21. Thus, the second code generation circuit 13 outputs the second partial selection signals Vf1, Vf2, … …, and Vf8, the phases of which are determined based on the predetermined code, to the drive signal supply line block sBKL for each of the periods td1, td2, … …, and td 16. For example, the prescribed code is defined by a square matrix of equation (2). In the case where the inverted control signal Vs is OFF ("0"), second partial selection signals Vf1, Vf2, … …, Vf8 corresponding to element "1" of the square matrix are generated. In the case where the inverted control signal Vs is ON ("1"), second partial selection signals Vf1, Vf2, … …, Vf8 corresponding to the element "-1" of the square matrix are generated.

The second code generation circuit 13 outputs the second partial selection signals Vf1, Vf2, … …, Vf8 from the output terminals Yb1, Yb2, … …, Yb8 for each of the periods td1, td2, … …, td 16. The ON and OFF combination patterns of the second section selection signals Vf1, Vf2, … …, Vf8 in the respective periods td1, td2, … …, td16 are different from each other.

Here, the second code generation circuit 13 includes a combination pattern of inverting the ON and OFF of the second partial selection signals Vf1, Vf2, … … and Vf8 because the inverted control signal Vs is input. Specifically, the reverse phase control signal Vs is OFF during the periods td1, td3, td5, td7, td9, td11, td13, and td15, and ON during the periods td2, td4, td6, td8, td10, td12, td14, and td 16. For example, the period td1 and the period td2 are combined patterns for inverting ON and OFF of the second section selection signals Vf1, Vf2, … …, and Vf8, respectively. Therefore, the ON and OFF combination patterns of the second section selection signals Vf1, Vf2, … …, Vf8 become 16, which is twice the number of the output terminals Yb1, Yb2, … …, Yb 8.

Fig. 22 is a circuit diagram showing an example of the third code generation circuit. Fig. 23 is a diagram showing an example of a mode code generated by the third code generation circuit when the inverted control signal is a high-level voltage. Fig. 24 is a diagram showing an example of a mode code generated by the third code generation circuit when the inverted control signal is a low-level voltage. Fig. 25 is a table showing the relationship of the first control signal, the second control signal, and the inverted control signal.

Fig. 22 shows the third code generating circuit 14-1 of the driving signal supply line section block sBKL1 provided in the plurality of driving signal supply line section blocks sBKL. As shown in fig. 22, the third code generation circuit 14-1 includes a plurality of exclusive or circuits 54 (exclusive or circuits 54-1, 54-2, … …, 54-8). First section selection signals Vd1, Vd2, … … and Vd8 are inputted from the first code generation circuit 12 to the exclusive or circuits 54-1, 54-2, … … and 54-8, respectively. In addition, the second partial selection signal Vf1 is input from the second code generation circuit 13 to the exclusive or circuits 54-1, 54-2, … …, 54-8, respectively. The exclusive or circuits 54-1, 54-2, … …, 54-8 exclusive or the first part selection signals Vd1, Vd2, … …, Vd8 and the second part selection signal Vf 1. The values calculated by the exclusive-or circuits 54-1, 54-2, … …, and 54-8 are supplied as the first selection signal Vc to the gate lines GCL (1), GCL (2), … …, and GCL (8) via the drive signal supply lines Ld1, Ld2, … …, and Ld 8.

Similarly, the third code generation circuits 14-2, 14-3, … …, and 14-8 shown in fig. 16 perform an exclusive or operation on the first partial selection signals Vd1, Vd2, … …, and Vd8 and the second partial selection signals Vf2, Vf3, … …, and Vf8 that are input thereto.

As shown in fig. 19, the number of combinations of the first section selection signals Vd is 8. As shown in fig. 21, in the combination pattern of the second partial selection signals Vf, the inverted control signals Vs are 8 signals each having 0 and 1, and 16 signals in total. Therefore, as shown in fig. 23, the number of times of the pattern code (predetermined code) of the first partial selection signal Vd generated by the third code generation circuit 14 becomes 8 × 8 or 64 when the inversion control signal Vs is 1. Similarly, as shown in fig. 24, the number of times of the pattern code of the first partial selection signal Vd generated by the third code generation circuit 14 becomes 8 × 8 or 64 when the inversion control signal Vs is 0. The pattern code shown in fig. 24 is obtained by inverting "0" and "1" of the pattern code shown in fig. 23.

The first code generation circuit 12, the second code generation circuit 13, and the third code generation circuit 14 generate the first selection signal Vc corresponding to the mode code shown in fig. 23 and 24 in accordance with the truth value table shown in fig. 25. The gate line driving circuit 15 generates a high-level voltage signal as the first selection signal Vc corresponding to the element "1" of the pattern code. The gate line driving circuit 15 generates a low-level voltage signal as the first selection signal Vc corresponding to the element "0" of the pattern code. Thereby, the first gate driving signal VGH is supplied to the gate line GCL corresponding to the element "1" of the pattern code, and the second gate driving signal VGL is supplied to the gate line GCL corresponding to the element "0" of the pattern code.

As shown in fig. 25, a period in which the inverted control signal Vs is 1 and a period in which the inverted control signal Vs is 0 are alternately executed. Therefore, the interval of the detection time of the first output signal Svh (1) and the second output signal Svh (2) becomes short. Therefore, even when a noise component enters from the outside, the noise component is removed by calculating the difference between the first output signal Svh (1) and the second output signal Svh (2). Therefore, the detection device 1 can improve the detection accuracy.

Further, the order of combining the first partial selection signals Vd and the second partial selection signals Vf is not limited to the order shown in fig. 25. For example, after the period in which the inverted control signal Vs becomes 1 is continuously executed a plurality of times, the period in which the inverted control signal Vs becomes 0 may be continuously executed a plurality of times.

As described above, the detection device 1 of the present embodiment includes: a substrate 21; an organic material layer 31 provided on the upper side of the substrate 21 and detecting a predetermined physical quantity; a plurality of detection electrodes 24 provided between the substrate 21 and the organic material layer 31 in a direction perpendicular to the substrate 21; a first switching element Tr provided at each of the plurality of detection electrodes 24; a plurality of gate lines GCL connected to the first switching elements Tr and extending in the first direction Dx; a plurality of signal lines SGL connected to the first switching element Tr and extending in a second direction Dy intersecting the first direction Dx; and a drive circuit (gate line drive circuit 15). The gate line drive circuit 15 supplies the gate drive signals (the first gate drive signal VGH and the second gate drive signal VGL) whose potentials are determined based on a predetermined code to the plurality of first switching elements Tr via the plurality of gate lines GCL, respectively.

Thus, the gate line driving circuit 15 performs CDM driving in the first detection electrode block BKx (see fig. 10). Therefore, even when the value of the current flowing from the organic material layer 31 to the detection electrode 24 is weak in accordance with the irradiated light, the detection accuracy can be improved. Further, according to the present embodiment, for example, compared to a case where the first selection signal Vc is supplied to all the gate lines GCL by a shift register or the like, delay of the signal can be suppressed, and detection accuracy can be improved.

In this embodiment, the gate line driver circuit 15 and the control signal generator circuit 17 are provided over the substrate 21. Therefore, the number of terminals for connecting the substrate 21 and the control board 101 can be reduced. Thus, the detection device 1 can suppress the circuit scale of the gate line drive circuit 15, and can reduce the manufacturing cost.

In the present embodiment, the third code generation circuit 14 may perform an exclusive nor (Xnor) operation on the first partial selection signal Vd and the second partial selection signal Vf. Alternatively, the circuit may perform an operation substantially equivalent to an exclusive or nor logic operation. The configurations of the first code generation circuit 12 and the second code generation circuit 13 may be similarly changed as appropriate.

Next, the signal line selection circuit 16 is explained. Fig. 26 is a circuit diagram showing a signal line selection circuit. In fig. 26, 12 signal lines SGL from the signal line SGL (1) to the signal line SGL (12) are shown. The signal line selection circuit 16 includes a third switching element Tra, a fourth switching element Trax, a reference signal supply line Lr0, a third selection signal line Lr1, Lr2, … …, Lr6, and an output signal line Lout.

One output signal line Lout is provided corresponding to the signal line SGL (1) to the signal line SGL (6). One output signal line Lout is provided corresponding to the signal line SGL (7) to the signal line SGL (12). The output signal lines Lout are connected to the AFEs 48, respectively. The signal line selection circuit 16 connects a signal line SGL selected from the plurality of signal lines SGL to the AFE48 based on the signal line selection signal Vhsel. Thereby, the signal line selection circuit 16 selects the detection electrode 24 (second detection electrode block BKy) to be detected.

The signal line selection signal Vhsel is output from, for example, a code generation circuit (not shown) similar to the second code generation circuit 13 shown in fig. 20. The code generation circuit that generates the signal line selection signal Vhsel may also be included in the signal line selection circuit 16. In this case, the code generation circuit is provided over the substrate 21 in the same manner as the signal line selection circuit 16. The signal line selection circuit 16 may have a configuration without a code generation circuit. In this case, the code generation circuit is provided in the external control board 101, and the external control board 101 can output the signal line selection signal Vhsel.

The signal line selection signal Vhsel is a voltage signal whose phase is specified for each signal line SGL based on a specified code. The prescribed code is defined by a square matrix of equation (3). In the example shown in fig. 26, the 6 signal line selection signals Vhsel1, Vhsel2, … …, and Vhsel6 are supplied to the third selection signal lines Lr1, Lr2, … …, and Lr6, respectively. The signal line selection signals Vhsel1, Vhsel2, … …, and Vhsel6 are generated based on arbitrary 6 elements included in 8 elements of each row of equation (3), for example. The signal line selection signals Vhsel1, Vhsel2, … …, and Vhsel6 are supplied to the third switching element Tra and the fourth switching element Trax via the third selection signal lines Lr1, Lr2, … …, and Lr 6.

The third switching element Tra and the fourth switching element Trax are connected to each signal line SGL. When the same signal line selection signal Vhsel is supplied to the third switching element Tra and the fourth switching element Trax, the third switching element Tra and the fourth switching element Trax operate to turn on and off in opposite directions. That is, when the third switching element Tra is turned on, the fourth switching element Trax is turned off. When the third switching element Tra is turned off, the fourth switching element Trax is turned on.

The connection state of the signal line SGL and the output signal line Lout is switched by the operations of the third switching element Tra and the fourth switching element Trax. When the third switching element Tra is turned on, the signal line SGL is connected to the output signal line Lout, and when the fourth switching element Trax is turned on, the signal line SGL is connected to the reference signal supply line Lr 0.

When the signal line selection signal Vhsel is supplied to the high-level voltage signal corresponding to the element "1" of the expression (3), the third switching element Tra is turned on. Further, when the signal line selection signal Vhsel is supplied to the low-level voltage signal corresponding to the element "-1" of the equation (3), the fourth switching element Trax is turned on. Thus, in the same manner as the CDM driving operation example shown in fig. 12, the second detection electrode block BKy connected to the signal line SGL is selected based on a predetermined code.

Specifically, when a plurality of signal lines SGL corresponding to the element "1" of expression (3) are selected, the selected signal line SGL is connected to the common output signal line Lout. The first output signal Sh (1) of the second detection electrode block BKy connected to the selected signal line SGL is output from the output signal line Lout to the AFE 48. The non-selected signal line SGL is connected to the reference signal supply line Lr0 and supplies the reference signal VR. Thereby, capacitive coupling between the selected detection electrodes 24 and the non-selected detection electrodes 24 is suppressed. Therefore, detection errors and a reduction in detection sensitivity can be suppressed.

When a plurality of signal lines SGL corresponding to the element "-1" of equation (3) are selected, the selected signal line SGL is connected to the output signal line Lout. The second output signal Sh (2) of the second detection electrode block BKy connected to each of the selected signal lines SGL is output from the output signal line Lout. The non-selected signal line SGL is connected to the reference signal supply line Lr0 and supplies the reference signal VR. The signal processing unit 44 calculates a difference value between the first output signal Sh (1) and the second output signal Sh (2) and calculates the third output signal Sh (3). The signal processing unit 44 can calculate a decoded signal for each of the second detection electrode blocks BKy by decoding the third output signal Sh (3).

Next, a configuration example of the first switching element Tr and the second switching element xTr will be described. Fig. 27 is a plan view showing a relationship among the detection electrode, the first switching element, and the second switching element. Fig. 28 is a cross-sectional view showing a schematic cross-sectional structure of the first switching element. In fig. 27, the detection electrode 24 is shown by a two-dot chain line for easy observation of the drawing.

As shown in fig. 27, the first switching element Tr has a semiconductor layer 61, a source electrode 62, a drain electrode 63, and a gate electrode 64. The material used for the semiconductor layer 61 is, for example, low-temperature polysilicon. The semiconductor layer 61 is disposed along the second direction Dy and intersects the gate line GCL in a plan view. A portion of the gate line GCL overlapping the semiconductor layer 61 functions as a gate electrode 64. In addition, a channel region is formed in a portion of the semiconductor layer 61 overlapping the gate line GCL. One end of the semiconductor layer 61 is connected to the source electrode 62 via a connection hole H1. The other end of the semiconductor layer 61 is connected to the drain electrode 63 via the connection hole H2.

The source electrode 62 is electrically connected to the signal line SGL. The drain electrode 63 is electrically connected to the connection portion 68. The connection portion 68 is connected to the detection electrode 24 via a connection hole H5. The gate electrode 64 is electrically connected to the gate line GCL. According to such a configuration, the first switching element Tr can switch connection and disconnection between the detection electrode 24 and the signal line SGL.

The second switching element xTr has a semiconductor layer 61a, a source electrode 62a, a drain electrode 63a, and a gate electrode 64 a. The semiconductor layer 61a is provided along the second direction Dy, and intersects the gate electrode 64a in a plan view. A channel region is formed in a portion of the semiconductor layer 61a which overlaps with the gate electrode 64 a. One end of the semiconductor layer 61a is connected to the source electrode 62a via a connection hole H4. The other end of the semiconductor layer 61a is connected to the drain electrode 63a via a connection hole H3.

The source electrode 62a is electrically connected to the connection portion 68. That is, the source electrode 62a of the second switching element xTr and the drain electrode 63 of the first switching element Tr are connected to the detection electrode 24 via the common connection portion 68. The drain electrode 63a is electrically connected to the reference signal line COM. The gate electrode 64a is connected to the gate line GCL. In other words, the gate line GCL functions as both the gate electrode 64 of the first switching element Tr and the gate electrode 64a of the second switching element xTr. With this configuration, the second switching element xTr can switch the connection and disconnection between the detection electrode 24 and the reference signal line COM.

In the detection electrodes 24 adjacent in the second direction Dy, the first switching elements Tr provided in the respective detection electrodes 24 have a line-symmetric structure with the reference line C1 as a symmetry axis. Similarly, the second switching element xTr has a line-symmetric structure with the reference line C1 as the axis of symmetry. Here, the reference line C1 is an imaginary line along the first direction Dx passing between the detection electrodes 24 adjacent in the second direction Dy. In addition, the gate line GCL is provided to overlap the detection electrode 24. The gate line GCL is also arranged at a position line-symmetrical about the reference line C1. Between the gate lines GCL adjacent in the second direction Dy, the first switching elements Tr corresponding to the respective detection electrodes 24 are disposed adjacent in the second direction Dy. In the present embodiment, the relative positions of the gate lines GCL with respect to the detection electrodes 24 in the second direction Dy are different among the detection electrodes 24 adjacent in the second direction Dy.

In the detection electrodes 24 adjacent to each other in the first direction Dx, the first switching elements Tr provided in the respective detection electrodes 24 have a line-symmetric structure about the reference line C2 as a symmetry axis. Similarly, the second switching element xTr has a line-symmetric structure with the reference line C2 as the axis of symmetry. Here, the reference line C2 is an imaginary line along the second direction Dy passing between the detection electrodes 24 adjacent in the first direction Dx. The reference line C2 is a line overlapping the reference signal line COM. In the detection electrodes 24 adjacent to each other in the first direction Dx, the second switching element xTr provided in each detection electrode 24 is connected to the common reference signal line COM. Therefore, the number of reference signal lines COM can be reduced by half as compared with the case where the reference signal lines COM are provided for the detection electrodes 24 and the second switching elements xTr arranged in the first direction Dx. This allows the detection device 1 to increase the opening area of the detection area AA, thereby improving detection performance. Here, the opening area is an area of a region where transmission of light is not blocked by various wirings such as the signal line SGL, the first switching element Tr, the second switching element xTr, and the like.

The signal line SGL overlaps the detection electrode 24. The signal line SGL is also disposed at a position that is line-symmetric about the reference line C2. Between the signal lines SGL adjacent in the first direction Dx, the first switching elements Tr corresponding to the respective detection electrodes 24 are disposed adjacent to the first direction Dx. Between the signal lines SGL adjacent in the first direction Dx, the second switching elements xTr corresponding to the respective detection electrodes 24 are also provided adjacent in the first direction Dx. In the present embodiment, the relative position of the signal line SGL with respect to each detection electrode 24 in the first direction Dx is different among the detection electrodes 24 adjacent in the first direction Dx.

As shown in fig. 28, a light-shielding layer 65, a semiconductor layer 61, a gate electrode 64, a source electrode 62, a drain electrode 63, and a detection electrode 24 are provided in this order on one surface of a substrate 21. The first switching element Tr has a so-called top gate configuration. That is, the semiconductor layer 61 is provided between the substrate 21 and the gate electrode 64 in a direction perpendicular to the substrate 21.

The light-shielding layer 65 is provided on one surface (upper surface) of the substrate 21 via the first insulating layer 25A-1. The light-shielding layer 65 overlaps with at least the channel region of the semiconductor layer 61. The light-shielding layer 65 is made of a metal material such as molybdenum (Mo), tungsten (W), aluminum (Al), titanium (Ti), or silver (Ag). Thus, the light-shielding layer 65 can shield light applied to the semiconductor layer 61 from the other surface (lower surface) of the substrate 21. Thereby, the first switching element Tr can suppress a leakage current. The detection device 1 can detect light irradiated from the other surface of the substrate 21 well.

The second insulating layer 25A-2 is provided on the first insulating layer 25A-1 so as to cover the light shielding layer 65. The semiconductor layer 61 is provided on the second insulating layer 25A-2. A third insulating layer 25A-3 is provided on the semiconductor layer 61. A gate electrode 64 is provided on the third insulating layer 25A-3. The gate electrode 64 and the gate line GCL (see fig. 27) are provided in the same layer. A fourth insulating layer 25A-4 is provided as a gate insulating layer on the gate electrode 64.

A source electrode 62 and a drain electrode 63 are provided on the fourth insulating layer 25A-4. The source electrode 62 and the drain electrode 63 are provided in the same layer as the signal line SGL (see fig. 27). The source electrode 62 is connected to the semiconductor layer 61 through a connection hole H1 provided in the third insulating layer 25A-3 and the fourth insulating layer 25A-4. Similarly, the drain electrode 63 is connected to the semiconductor layer 61 through a connection hole H2 provided in the third insulating layer 25A-3 and the fourth insulating layer 25A-4.

The detection electrode 24 is provided on the source electrode 62 and the drain electrode 63 via the hard coat layer 25B and the insulating layer 23. An organic material layer 31 and a drive electrode 32 are provided on the detection electrode 24. In fig. 28, the protective layer 33 (see fig. 5) is not shown. According to such a stacked configuration, the first switching element Tr can switch connection and disconnection between the detection electrode 24 and the signal line SGL. The second switching element xTr also has the same laminated structure as the first switching element Tr. The semiconductor layer 61a, the source electrode 62a, the drain electrode 63a, and the gate electrode 64a of the second switching element xTr are provided in the same layer as the semiconductor layer 61, the source electrode 62, the drain electrode 63, and the gate electrode 64 of the first switching element Tr, respectively.

(second embodiment)

Fig. 29 is a plan view showing a detection device of the second embodiment. Fig. 30 is a block diagram showing a configuration example of a sensor section, a gate line driving circuit, and a signal line selection circuit according to the second embodiment. Fig. 31 is a timing waveform diagram showing an example of the operation of the detection device according to the second embodiment.

In the detection device 1A of the present embodiment, the gate line driving circuit 15A does not include the first code generating circuit 12, the second code generating circuit 13, and the third code generating circuit 14. In the present embodiment, a code generation circuit is provided on the control board 101. For example, the control circuit 102 has a function of a code generation circuit, and generates the first selection signal Vc whose phase is determined based on a predetermined code. The control circuit 102 supplies the first selection signal Vc to the gate line drive circuit 15A via the wiring LA.

As shown in fig. 30, the gate line drive circuit 15A includes a shift register 18, a latch circuit 19, and a buffer circuit 151. The shift register 18 operates based on a reset signal RST, a clock signal CKV, and a start signal STV supplied from the control substrate 101. The shift register 18 has shift signal output circuits corresponding to the plurality of gate lines GCL, respectively. The shift register 18 sequentially outputs a shift signal to the latch circuit 19 for each of the plurality of gate lines GCL.

As shown in fig. 31, when the reset signal RST is ON (high level voltage), the shift register 18 resets the plurality of shift signal output circuits. Then, the shift register 18 starts operating based on the start signal STV. The shift signal output circuit is based onThe clock signal CKV sequentially outputs the shift signals to the latch circuit 19. Each pulse of the clock signal CKV corresponds to the gate lines GCL (1), GCL (2), … …, and GCL (n). Period t of clock signal CKV_CKVThe time required for detection can be appropriately changed. The timing of supplying the clock signal CKV is, for example, the period t after the rise of the start signal STV _CKV1/4 (t)_CKV/4) The time point of (a).

As shown in fig. 30, the latch circuit 19 operates based on the shift signal from the shift register 18, the inverted reset signal xRST, the first selection signal Vc, the control signal OE, and the inverted control signal xOE. The inverted reset signal xRST is a signal obtained by inverting the reset signal RST with the inverter 153A. The inversion control signal xOE is a signal obtained by inverting the control signal OE through the inverter 154A. The control signal OE is a signal for controlling the signal output from the latch circuit 19 to the buffer circuit 151.

As shown in fig. 31, the latch circuit 19 sequentially holds the first selection signal Vc in accordance with the shift signal from the shift register 18. The first selection signal Vc is a signal in which a potential is defined for each gate line of the gate lines GCL based on a pattern code (predetermined code) shown in fig. 23, for example.

When the control signal OE is ON, the latch circuit 19 outputs the first selection signal Vc to the buffer circuit 151. The buffer circuit 151 changes the voltage level of the first selection signal Vc in accordance with the power supply voltages VDD, VSS. Thus, the buffer circuit 151 outputs the first gate drive signal VGH and the second gate drive signal VGL corresponding to the first selection signal Vc to the sensor portion 10.

When the control signal OE is ON, the control board 101 sequentially supplies the signal line selection signals Vhsel (1), Vhsel (2), … …, and Vhsel (6) to the signal line selection circuit 16. The signal line selection signals Vhsel (1), Vhsel (2), … …, and Vhsel (6) are signals corresponding to each row of the square matrix represented by equation (3). Thereby, the signal line selection circuit 16 performs CDM driving as in the first embodiment.

As shown in fig. 31, during a period t in which the signal line selection signal Vhsel is ON_{ASW_width}Inside, connectSelected signal lines SGL and AFE 48. During a period in which the signal line selection signal Vhsel is OFF (low-level voltage), the signal line SGL and the AFE48 are disconnected. In addition, the period t_{ASW_shift}The control signal OE is a period from the rising timing to the time when the signal line selection signal Vhsel is ON. Period t_{ASW_delay}The period is a period from the falling timing of the signal line selection signal Vhsel to the rising timing of the next signal line selection signal Vhsel. Period t_{ASW_width}Period t_{ASW_delay}Etc. can be appropriately changed according to the time required for detection.

After all the signal line selection signals Vhsel (1), Vhsel (2), … …, and Vhsel (6) are supplied to the signal line selection circuit 16, the gate line drive circuit 15A supplies the first gate drive signal VGH and the second gate drive signal VGL based on the next first selection signal Vc to the sensor section 10. The first selection signal Vc in this case is a signal in which a potential is defined for each gate line GCL based on a pattern code (predetermined code) shown in fig. 24, for example.

Note that the timing waveform diagram shown in fig. 31 is merely an example. For example, the shift register 18 and the latch circuit 19 may perform an operation of holding the next first selection signal Vc during a period after the control signal OE is turned OFF and during a period when the plurality of signal line selection signals Vhsel are supplied to the signal line selection circuit 16.

(third embodiment)

Fig. 32 is a circuit diagram showing an AFE and an inverter circuit according to the third embodiment. In this embodiment, the configurations of the detection electrode 24, the drive electrode 32, the first switching element Tr, the second switching element xTr, the gate line drive circuit 15, the signal line selection circuit 16, and the like are the same as those of the first embodiment described above, and detailed description thereof is omitted. In the present embodiment, the detection electrode 24 is a cathode, and the drive electrode 32 (see fig. 5) is an anode. That is, the direction of the flow of the current Ifh is opposite to that of the first embodiment. Therefore, an inverter circuit 49 is provided between the signal line SGL and the amplifier 481. Note that, although the inverter circuit 49 is disposed in the AFE48 in fig. 32, it may be provided on the substrate 21 side.

The inverter circuit 49 inverts the current Ifh flowing through the signal line SGL and outputs the inverted current to the amplifier 481. The inverter circuit 49 is a so-called current mirror circuit. The inverter circuit 49 has a fifth switching element Trb1 and a sixth switching element Trb 2. The fifth switching element Trb1 and the sixth switching element Trb2 are formed of, for example, p-channel MOS TFTs.

The gate of the fifth switching element Trb1 and the gate of the sixth switching element Trb2 are electrically connected to a common signal line SGL via a first switch SW 1. The source of the fifth switching element Trb1 is electrically connected to the signal line SGL via the first switch SW 1. A common power supply voltage VDD is supplied to the drain of the fifth switching element Trb1 and the drain of the sixth switching element Trb 2. The source of the sixth switching element Trb2 is connected to the input of the amplifier 481 of the AFE 48.

With this configuration, the direction of the current Ifh is inverted by the inverter circuit 49, and a current having the same magnitude as the current Ifh flows to the amplifier 481 of the AFE 48. The AFE48 operates in the same manner as the first embodiment. Thus, even when the detection electrode 24 is a cathode and the drive electrode 32 is an anode, the AFE48 can detect the current Ifh output from the detection electrode 24 from the irradiated light.

(fourth embodiment)

Fig. 33 is a plan view showing a detection device of the fourth embodiment. Fig. 34 is a circuit diagram showing a driving circuit for one detection region. As shown in fig. 33, the detection device 1B has a sensor section 10, a gate line drive circuit 15A, and a reset circuit 16A. The sensor unit 10 of the present embodiment is a temperature sensor for detecting temperature. The gate line driving circuit 15A supplies the first gate driving signal VGH and the second gate driving signal VGL to the gate lines GCL based on the first selection signal Vc supplied from the control circuit 102, as in the second embodiment. The reset circuit 16A is a circuit that resets the signal lines SGL and the input portion of the AFE 48. That is, in the present embodiment, the signal line selection circuit 16 is not provided. The detection device 1B performs CDM driving only by the gate line drive circuit 15A. In the present embodiment, the configurations of the detection electrode 24, the drive electrode 32, the first switching element Tr, the second switching element xTr, and the like are the same as those of the first embodiment described above, and detailed description thereof is omitted.

As shown in fig. 34, in the detection device 1B of the present embodiment, the sensor portion 10 is a temperature sensor having an organic material layer 31A. The organic material layer 31A changes characteristics (e.g., resistance value) according to temperature. In fig. 34, the organic material layer 31A is shown equivalently as a resistance element. Thereby, the sensor unit 10 outputs a detection signal corresponding to the temperature to the AFE 48. As the organic material layer 31A, for example, the same material as that of the first embodiment can be used.

As shown in fig. 34, the circuit configurations of the detection electrode 24, the first switching element Tr, the second switching element xTr, the signal line SGL, the gate line GCL, the reference signal line COM, and the like are the same as those of the first embodiment. When the gate line drive circuit 15A supplies the first gate drive signal VGH to the gate line GCL, the first switching element Tr is turned on. Thereby, the detection electrode 24 is selected as the detection target. A current Ifh corresponding to the temperature flows from the detection electrode 24 to the signal line SGL. On the other hand, the second switching element xTr is turned off. Therefore, the current Idh flowing from the detection electrode 24 to the reference signal line COM is suppressed. In this manner, the sensor unit 10 changes the signal (current Ifh) output from the detection electrode 24 in accordance with the temperature of the organic material layer 31A. Thereby, the detection device 1B can detect the temperature.

When the gate line drive circuit 15A supplies the second gate drive signal VGL to the gate line GCL, the first switching element Tr is turned off. This suppresses the current Idl flowing from the detection electrode 24 to the signal line SGL, and the detection electrode 24 becomes a non-detection target. On the other hand, the second switching element xTr is turned on. Therefore, a current Ifl flows from the detection electrode 24 to the reference signal line COM. The reference signal Vcom is supplied from the control substrate 101 to the reference signal line COM. This suppresses variation in the potential of the detection electrode 24 that is not the object of detection.

Fig. 35 is a circuit diagram showing a reset circuit. As shown in fig. 35, the reset circuit 16A includes a plurality of seventh switching elements Trc, a reference signal supply line LB1, and a reset signal supply line LB 2. In the present embodiment, each of the plurality of signal lines SGL is connected to the AFE 48. That is, CDM driving of the signal line SGL is not performed, and the output signal of the detection electrode 24 is output to the AFE48 via the signal line SGL.

A plurality of seventh switching elements Trc are provided for each signal line SGL. The seventh switching elements Trc are formed of, for example, p-channel MOS TFTs. The gate of the seventh switching element Trc is connected to a common reset signal supply line LB 2. The source of the seventh switching element Trc is connected to a common reference signal supply line LB 1. The drains of the seventh switching elements Trc are connected to the signal lines SGL, respectively.

When the reset signal Vreset is a high-level voltage, the reference signal supply line LB1 and the signal line SGL are disconnected. That is, the detection signal of the detection electrode 24 is output to the AFE48 via the signal line SGL. When the reset signal Vreset is a low-level voltage, the reference signal supply line LB1 and the signal line SGL are connected. In the present embodiment, all the signal lines SGL are simultaneously connected to the reference signal supply line LB 1. Thus, the reference signal VR is supplied to the input portions of the signal line SGL and the AFE 48. This resets the input portions of the signal line SGL and AFE 48.

The reset signal Vreset of the high-level voltage is supplied to the reset signal supply line LB2 at a timing after the control signal OE shown in fig. 31 is supplied. In other words, after the first selection signal Vc is sequentially held by the latch circuit 19, a period in which the reset signal Vreset of the high-level voltage is supplied becomes a detection period.

(fifth embodiment)

Fig. 36 is a cross-sectional view showing a schematic cross-sectional structure of the detection device of the fifth embodiment. Fig. 37 is a plan view schematically showing a detection device of the fifth embodiment. Fig. 38 is a plan view showing the relationship of the detection electrode, the drive electrode, the eighth switching element, and the ninth switching element. Fig. 39 is a plan view showing an enlarged area C4 of fig. 38.

The detection device 1C of the present embodiment is a temperature sensor as in the fourth embodiment. As shown in fig. 36, the backplate 2 includes a substrate 21, a TFT layer 22, an insulating layer 23, a detection electrode 24A, and a drive electrode 32A. The TFT layer 22 is provided with circuits such as a gate line driver circuit 15A and a reset circuit 16A (see fig. 34 and 35). In addition, the TFT layer 22 is provided with various wirings such as an eighth switching element Trd, a ninth switching element xTrd (see fig. 38), a gate line GCL, and a signal line SGL (see fig. 7). In the present embodiment, the detection electrode 24A and the drive electrode 32A are provided on the same insulating layer 23. In other words, the drive electrode 32A and the detection electrode 24A are disposed adjacent to each other on the same layer. The detection electrode 24A and the drive electrode 32A are made of a light-transmitting conductive material such as ITO. Further, not limited to this, a metal material such as silver (Ag) or aluminum (Al) may be used for the drive electrode 32A.

The organic sensor layer 3 has an organic material layer 31 and a protective layer 33. The organic material layer 31 is provided on the plurality of detection electrodes 24A and the plurality of drive electrodes 32A. The organic material layer 31 has a resistance component between the adjacent detection electrode 24A and drive electrode 32A.

As shown in fig. 37, the plurality of partial detection regions SAA are arranged in a matrix shape in the entire detection region AA. The partial detection region SAA includes the organic material layer 31, a plurality of detection electrodes 24A, and a plurality of driving electrodes 32A. The organic material layer 31 is provided separately in a matrix for each partial detection area SAA. The organic material layer 31 is patterned by, for example, photolithography.

The plurality of detection electrodes 24A and the plurality of drive electrodes 32A are alternately arranged in the second direction Dy. In addition, the plurality of detection electrodes 24A and the plurality of drive electrodes 32A are arranged in the first direction Dx, respectively. The partial detection area SAA includes two detection electrodes 24A, and two drive electrodes 32A. In other words, two detection electrodes 24A and two drive electrodes 32A are provided so as to overlap one organic material layer 31. Note that fig. 37 is merely an example, and three or more detection electrodes 24A and three or more drive electrodes 32A may be provided in one partial detection region SAA.

Fig. 38 shows two partial detection regions SAA adjacent in the first direction Dx. In fig. 38, the organic material layer 31 is not shown for the sake of convenience in view of the drawings. As shown in fig. 38, the two partial detection regions SAA have a line-symmetric structure with the reference line C3 as a symmetry axis. Here, the reference line C3 is an imaginary line passing between the partial detection regions SAA adjacent in the first direction Dx and extending along the second direction Dy. In the following description, the partial detection area SAA on the left side sandwiching the reference line C3 will be described.

As shown in fig. 38, two detection electrodes 24A, two drive electrodes 32A, an eighth switching element Trd, and a ninth switching element xTrd are provided in the partial detection region SAA. The detection electrode 24A and the drive electrode 32A are each rectangular in shape having a long side in the first direction Dx. In addition, the detection electrodes 24A and the drive electrodes 32A are alternately arranged in the second direction Dy. A resistance component is formed between the detection electrode 24A and the drive electrode 32A adjacent in the second direction Dy through the organic material layer 31.

One ends of the two detection electrodes 24A are connected to the common eighth switching element Trd via connection holes HC1 and HC3, respectively. One ends of the two detection electrodes 24A are connected to the common signal line SGL by the operation of the eighth switching element Trd. The other ends of the two detection electrodes 24A are connected to a common ninth switching element xTrd via connection holes HC2 and HC4, respectively. The other ends of the two detection electrodes 24A are connected to the common reference signal line COM by the operation of the ninth switching element xTrd. Similarly, the plurality of detection electrodes 24A belonging to the plurality of partial detection regions SAA arranged in the second direction Dy are connected to the common signal line SGL and to the common reference signal line COM.

The eighth switching element Trd is formed of an n-channel MOS TFT in this example. The ninth switching element xTrd is formed of a p-channel MOS TFT in this example.

Fig. 39 shows a connection portion of one end of the detection electrode 24A and the eighth switching element Trd. The eighth switching element Trd has a semiconductor layer 61b, a source electrode 62b, a drain electrode 63b, and a gate electrode 64 b.

The gate electrode 64b is connected to the gate line GCL and disposed along the second direction Dy. In the present embodiment, the gate line GCL is provided corresponding to the partial detection regions SAA arranged in the second direction Dy. The gate electrode 64b is disposed adjacent to the signal line SGL. The semiconductor layer 61b is provided to overlap with the gate electrode 64 b. The width of the semiconductor layer 61b in the first direction Dx is larger than the width of the gate electrode 64b in the first direction Dx. One end (left end) of the semiconductor layer 61b is connected to the drain electrode 63b via a plurality of connection holes HC 6. The other end (right end) of the semiconductor layer 61b is connected to the source electrode 62b via a plurality of connection holes HC 5.

The drain electrode 63b and the source electrode 62b each extend in the second direction Dy. The width in the second direction Dy of the drain electrode 63b and the width in the second direction Dy of the source electrode 62b are larger than the width in the second direction Dy of the detection electrode 24A. The plurality of connection holes HC6 and the plurality of connection holes HC5 are aligned in the extending direction of the drain electrode 63b and the source electrode 62b, respectively.

The connection portion 63ba of the drain electrode 63b is connected to the detection electrode 24A via a plurality of connection holes HC 1. The source electrode 62b is connected to the signal line SGL. In other words, a part of the signal line SGL functions as the source electrode 62 b. Further, the plurality of detection electrodes 24A belonging to the same partial detection region SAA (see fig. 38) are connected to the drain electrode 63 b.

The eighth switching element Trd is connected between the layers via the plurality of connection holes HC1, the plurality of connection holes HC5, and the plurality of connection holes HC 6. Therefore, the connection resistance of the eighth switching element Trd can be suppressed. This enables the detection device 1C to improve detection performance. The ninth switching element xTrd has the same configuration, and detailed description thereof is omitted.

As shown in fig. 38, the other ends (right ends) of the two drive electrodes 32A are connected to a common drive signal supply line Lvd via connection holes HC7 and HC8, respectively. One ends (left ends) of the two drive electrodes 32A are connected to other wirings and the like. The driving signal supply line Lvd passes through between the partial detection regions SAA adjacent in the first direction Dx and is disposed along the second direction Dy. The driving signal supply line Lvd is a wiring for supplying the driving signal VDD _ ORG (see fig. 34) to the driving electrode 32A. In the adjacent partial detection regions SAA with the drive signal supply line Lvd interposed therebetween, a plurality of (for example, four or more) drive electrodes 32A are connected to the common drive signal supply line Lvd.

In the present embodiment, CDM driving by the gate line driving circuit 15A is also performed. The gate line driving circuit 15A supplies the first gate driving signal VGH and the second gate driving signal VGL, the potentials of which are determined based on a predetermined code, to each gate line GCL. Thereby, the detection electrodes 24A belonging to the plurality of partial detection regions SAA selected as the detection target are connected to the signal line SGL. The detection electrode 24A of the plurality of partial detection regions SAA which are not the object of detection is connected to the reference signal line COM. The signal processing unit 44 can decode a plurality of output signals, and can calculate a decoded signal for each partial detection area SAA.

The preferred embodiments of the present invention have been described above, but the present invention is not limited to such embodiments. The disclosure of the embodiments is merely an example, and various modifications can be made without departing from the scope of the invention. It is needless to say that appropriate modifications are made within the scope of the present invention without departing from the gist of the present invention.

For example, the gate line driving circuit 15A does not have a code generation circuit in the detection device 1B according to the fourth embodiment and the detection device 1C according to the fifth embodiment, but is not limited thereto. The detection devices 1B and 1C may include a gate line driving circuit 15 having a code generation circuit, as in the first embodiment. The detection devices 1B and 1C may also include a signal line selection circuit 16, as in the first embodiment.

Description of the reference numerals

1. 1A, 1B, 1C detection device

2 backboard

3 organic sensor layer

10 sensor part

11 detection control part

12 first code generation circuit

13 second code generation circuit

14 third code generation circuit

15 gate line driving circuit

16 signal line selection circuit

16A reset circuit

17 control signal generating circuit

21 substrate

22 TFT layer

24 detection electrode

29 drive electrode connection terminal

31 organic material layer

31a opening

32 drive electrode

33 protective layer

40 detection part

48 AFE

49 inverter circuit

101 control substrate

AA detection area

BKx first detecting electrode block

BKy second detecting electrode block

COM reference signal line

GA frame region

GCL gate line

LB1 reference signal supply line

LB2 reset signal supply line

Lout output signal line

SGL signal line

Tr first switching element

xTr second switch element

Vc first selection signal

VDD _ ORG drive signal

VGH first gate drive signal

VGL second gate drive signal.