阅读说明：本技术 一种高线性度cmos太赫兹探测器前端电路 (High-linearity CMOS terahertz detector front-end circuit ) 是由 吴旭 郭晓燚 李连鸣 何龙 于 2020-07-16 设计创作，主要内容包括：本发明公开了一种高线性度CMOS太赫兹探测器前端电路,其中包括一个偏置电路、一个检测电路、一个电流镜电路和一个平方根运算电路。其中偏置电路的作用是为检测电路晶体管的栅极提供偏置电压；检测电路的作用是检测输入端太赫兹信号的幅度信息；电流镜电路的作用是将这个低频检波信号中的电流信息进行拷贝并送入平方根运算电路；平方根运算电路将拷贝得到的低频检波信号进行线性化处理,最终输出与斩波调制同频率的近似方波的输出信号。本发明使用栅极与天线相连的检测晶体管直接对太赫兹信号进行检测,并对检测信号进行线性化处理,首次实现了室温下太赫兹信号电压幅度的线性探测。(The invention discloses a front-end circuit of a high-linearity CMOS terahertz detector, which comprises a biasing circuit, a detection circuit, a current mirror circuit and a square root operation circuit. The bias circuit is used for providing bias voltage for the grid electrode of the transistor of the detection circuit; the detection circuit is used for detecting amplitude information of the terahertz signal at the input end; the current mirror circuit is used for copying the current information in the low-frequency detection signal and sending the current information to the square root operation circuit; the square root operation circuit carries out linearization processing on the copied low-frequency detection signal and finally outputs an output signal which is approximately square wave and has the same frequency as the chopping modulation. According to the invention, the detection transistor with the grid connected with the antenna is used for directly detecting the terahertz signal, and the detection signal is subjected to linearization processing, so that the linear detection of the voltage amplitude of the terahertz signal at room temperature is realized for the first time.)

1. A front-end circuit of a high-linearity CMOS terahertz detector is characterized by comprising a biasing circuit, a detection circuit, a current mirror circuit and a square root operation circuit, wherein the biasing circuit is used for providing a biasing voltage for a grid electrode of a transistor of the detection circuit; the detection circuit is used for detecting amplitude information of the terahertz signal at the input end, specifically, the terahertz signal subjected to chopper modulation is received by an antenna and then is sent to a grid of an input transistor of the detection circuit, the terahertz signal is processed by the detection circuit to obtain a low-frequency detection signal which has the same frequency as the chopper modulation and contains envelope information, and the low-frequency detection signal contains the amplitude information of the terahertz signal at the input end; the current mirror circuit is used for copying current information in the low-frequency detection signal and sending the current information to the square root operation circuit; the square root operation circuit carries out linearization processing on the copied low-frequency detection signal and finally outputs an output signal which is approximately square wave and has the same frequency as the chopping modulation.

2. The high linearity CMOS terahertz detector front-end circuit according to claim 1, wherein the bias circuit comprises a transistor M6 and a resistor R, the source of the transistor M6 is grounded, the gate and the drain of the transistor are both connected with a first bias voltage, one end of the resistor R is connected with the gate of a detection transistor M1 of the detection circuit, and the other end of the resistor R is connected with the first bias voltage.

3. The high-linearity CMOS terahertz detector front-end circuit according to claim 1, wherein the detection circuit comprises a detection transistor M1, an N-type cascode transistor M2, a P-type cascode transistor M3 and a capacitor C, wherein a gate of the detection transistor M1 is connected to one end of a resistor R in the bias circuit and is directly connected to an antenna, the chopped terahertz signal is received by the antenna and is sent to a gate of the detection transistor M1, a source of the detection transistor M1 is grounded, a drain of the detection transistor M1 is connected to a source of the N-type cascode transistor M2, and a drain of the N-type cascode transistor M2 is connected to a drain of the P-type cascode transistor M3 and is grounded through the capacitor C; the grid electrode of the N-type cascode transistor M2 is connected with a second bias voltage, the grid electrode of the P-type cascode transistor M3 is connected with a third bias voltage, and the source electrode of the P-type cascode transistor M3 is connected with the input end of the current mirror circuit.

4. The high-linearity CMOS terahertz detector front-end circuit according to claim 1, wherein the current mirror circuit comprises a first PMOS transistor M4 and a second PMOS transistor M5, a gate of the first PMOS transistor M4 is connected with a gate of the second PMOS transistor M5, a source of the first PMOS transistor M4 and a source of the second PMOS transistor M5 are both connected with a power supply, a drain and a gate of the first PMOS transistor M4 are both connected with a source of a P-type cascode transistor M3 in the detection circuit, and a drain of the second PMOS transistor M5 is connected with the ground through a first current source A1 and with an input end of the square root operation circuit.

5. The high linearity CMOS terahertz detector front-end circuit of claim 1, wherein the square root arithmetic circuit comprises but is not limited to a transconductance linear loop of BJT transistors.

6. The front-end circuit of the high-linearity CMOS terahertz detector according to claim 1, wherein a square root operation circuit is formed by four BJT transistors to form a transconductance linear loop, so that nonlinear operation between current quantities is realized; specifically, the power supply comprises a first BJT transistor T1, a second BJT transistor T2, a third BJT transistor T3, a fourth BJT transistor T4 and a second current source A2, wherein the emitter of the first BJT transistor T1 is grounded, the collector of the first BJT transistor T1 is connected with the base of the second BJT transistor T2, and the first BJT transistor T1 is used as an input end and receives an input current signal i_XA base connected to the emitter of a second BJT transistor T2; the emitter of the second BJT transistor T2 is connected to one end of the second current source A2, the base is connected to the base of the third BJT transistor T3, and the collector is connected to VDD; the collector of the third BJT transistor T3 is used as an output terminal for outputting a current signal i_oAn emitter connected to the collector and base of a fourth BJT transistor T4, and an emitter of the fourth BJT transistor T4 connected to ground; one terminal of the second current source a2 is connected to the emitter of the second BJT transistor T2, and the other terminal is connected to ground.

7. The high linearity CMOS terahertz detector front-end circuit of claim 6, wherein an input current signal i of a square root operation circuit_XAnd output current signal i_oHave the following relationship between:

wherein i_YIs the current of a second current source A2, will i_YSet to a determined value, i.e. effecting a current i_XThe square root operation of (1), the calculation result is the output current signal i_o。

8. An array front-end circuit comprising one or more pixels arranged in a matrix having rows and columns, the array front-end circuit further comprising at least one high linearity CMOS terahertz detector front-end circuit of any one of claims 1 to 7.

Technical Field

The invention relates to a terahertz wave detection technology, in particular to a front-end circuit of a high-linearity CMOS terahertz detector.

Background

Terahertz waves are electromagnetic waves in the frequency range of 0.1THz to 10THz, the wavelength of which corresponds to 3 mm to 30 μm, and the spectrum of which lies between millimeter waves and infrared light. The terahertz signal has many excellent characteristics at a special position in an electromagnetic spectrum, and has wide application prospects in the fields of safety inspection, quality monitoring, medical imaging, nondestructive detection, communication and the like, so that the terahertz detector technology needs to be deeply researched.

Currently, terahertz detectors mainly include microbolometers, schottky diodes, quantum well terahertz detectors, and the like. However, the microbolometer needs to work under a low-temperature condition, the schottky diode process is complex and difficult to realize, and the quantum well terahertz detector is easily interfered by thermal disturbance. Therefore, a terahertz detector with high linearity and high sensitivity for realizing room temperature operation is an important development direction in the future.

For terahertz detectors, linearity is an important standard for measuring performance of the terahertz detectors. The linearity of the terahertz detector is improved, the resolution of the terahertz imaging system can be improved, and imaging is clearer. However, detection output signals realized by the conventional terahertz detector all show square law characteristics, and are not linear output signals. Therefore, the imaging of the traditional terahertz detector has the problems of imaging blurring, low resolution and the like.

Disclosure of Invention

The purpose of the invention is as follows: the invention aims to provide a high-linearity CMOS terahertz detector front-end circuit.

The technical scheme is as follows: the invention discloses a front-end circuit of a high-linearity CMOS terahertz detector, which comprises a biasing circuit, a detection circuit, a current mirror circuit and a square root operation circuit. The bias circuit is used for providing bias voltage for the grid electrode of the transistor of the detection circuit; the detection circuit is used for detecting amplitude information of the terahertz signal at the input end, specifically, the terahertz signal subjected to chopper modulation is received by an antenna and then is sent to a grid of an input transistor of the detection circuit, the terahertz signal is processed by the detection circuit to obtain a low-frequency detection signal which has the same frequency as the chopper modulation and contains envelope information, and the low-frequency detection signal contains the amplitude information of the terahertz signal at the input end; the current mirror circuit is used for copying the current information in the low-frequency detection signal and sending the current information to the square root operation circuit; the square root operation circuit carries out linearization processing on the copied low-frequency detection signal and finally outputs an output signal which is approximately square wave and has the same frequency as the chopping modulation. According to the invention, the detection transistor with the grid connected with the antenna is used for directly detecting the terahertz signal, and the detection signal is subjected to linearization processing, so that the linear detection of the voltage amplitude of the terahertz signal at room temperature is realized for the first time.

Preferably, the bias circuit comprises a transistor M6 and a resistor R, the source of the transistor M6 is grounded, the gate and the drain are both connected with a first bias voltage, one end of the resistor R is connected with the gate of the detection transistor M1 of the detection circuit, and the other end is connected with the first bias voltage.

Preferably, the detection circuit comprises a detection transistor M1, an N-type cascode transistor M2, a P-type cascode transistor M3 and a capacitor C, wherein the gate of the detection transistor M1 is connected to one end of a resistor R in the bias circuit and directly connected to the antenna, the chopped terahertz signal is received by the antenna and sent to the gate of the detection transistor M1, the source of the detection transistor M1 is grounded, the drain of the detection transistor M3538 is connected to the source of the N-type cascode transistor M2, and the drain of the N-type cascode transistor M2 is connected to the drain of the P-type cascode transistor M3 and grounded through the capacitor C; the grid electrode of the N-type cascode transistor M2 is connected with a second bias voltage, the grid electrode of the P-type cascode transistor M3 is connected with a third bias voltage, and the source electrode of the P-type cascode transistor M3 is connected with the input end of the current mirror circuit.

Preferably, the current mirror circuit includes a first PMOS transistor M4 and a second PMOS transistor M5, a gate of the first PMOS transistor M4 is connected to a gate of the second PMOS transistor M5, a source of the first PMOS transistor M4 and a source of the second PMOS transistor M5 are both connected to the power supply, a drain and a gate of the first PMOS transistor M4 are both connected to a source of a P-type cascode transistor M3 in the detection circuit, and a drain of the second PMOS transistor M5 is grounded through a first current source a1 and connected to an input terminal of the square root operation circuit.

Preferably, the square root operation circuit includes, but is not limited to, a transconductance linear loop composed of BJT transistors.

Preferably, the square root operation circuit is a transconductance linear loop formed by four BJT transistors, so as to implement nonlinear operation between current quantities; specifically, the power supply comprises a first BJT transistor T1, a second BJT transistor T2, a third BJT transistor T3, a fourth BJT transistor T4 and a second current source A2, wherein the emitter of the first BJT transistor T1 is grounded, the collector of the first BJT transistor T1 is connected with the base of the second BJT transistor T2, and the first BJT transistor T1 is used as an input end and receives an input current signal i_XA base connected to the emitter of a second BJT transistor T2; the emitter of the second BJT transistor T2 is connected to one end of the second current source A2, the base is connected to the base of the third BJT transistor T3, and the collector is connected to VDD; the collector of the third BJT transistor T3 is used as an output terminal for outputting a current signal i_OAn emitter connected to the collector and base of a fourth BJT transistor T4, and an emitter of the fourth BJT transistor T4 connected to ground; one terminal of the second current source a2 is connected to the emitter of the second BJT transistor T2, and the other terminal is connected to ground.

Wherein, the input current signal i of the square root operation circuit_XAnd output current signal i_OHave the following relationship between:

wherein i_YIs the current of a second current source A2, will i_YSetting to a determined value, the current i can be measured_XThe square root operation of (1), the calculation result is the output current signal i_O。

The array front-end circuit comprises one or more pixels arranged in a matrix form with rows and columns, and at least one high-linearity CMOS terahertz detector front-end circuit.

The working principle is as follows: the terahertz signal subjected to chopping modulation is an input signal of the detector, the terahertz signal is received by the antenna and transmitted to the grid of the detection transistor, and the detection transistor working in a saturation region directly detects the terahertz signal. Through the common processing of the N-type cascode transistor, the P-type cascode transistor and a capacitor, a low-frequency detection signal which has the same frequency as chopping modulation and contains envelope information is realized. Then, the current mirror circuit cancels the DC component of the low-frequency detection signal, allows only the low-frequency detection current signal to pass through, copies the low-frequency detection signal, and sends the copied low-frequency detection signal to the square root operation circuit for processing. The square root operation circuit performs square-open processing on the low-frequency detection signal obtained by copying the current mirror circuit to linearize the low-frequency detection signal, and finally obtains an output signal which is approximate to a square wave and has the same frequency as chopped wave modulation. The square root operation circuit comprises a transconductance linear loop formed by four BJT transistors, and realizes the nonlinear operation between current quantities.

Has the advantages that: compared with the prior art, the terahertz signal is directly detected by using the detection transistor with the grid connected with the antenna, and the low-frequency detection signal obtained by detection is subjected to linearization processing by using the current square root arithmetic circuit, so that the linearity of the detection signal is improved. The front-end circuit of the terahertz detector is simple in structure and easy to integrate with a reading circuit, and linear detection of terahertz signals at room temperature is achieved for the first time.

Drawings

FIG. 1 is a schematic diagram of a front-end circuit of a CMOS terahertz detector according to the present invention;

FIG. 2 is a schematic diagram of a current curve generated by the detection transistor M1 in response to a terahertz wave;

FIG. 3 is a diagram illustrating a low-frequency detection current curve generated at the source of the P-type cascode transistor M3;

FIG. 4 is a schematic diagram of a square root current operation circuit according to an embodiment of the present invention;

fig. 5 is a square rate characteristic output curve and an output curve after linearization processing.

Detailed Description

The technical solution of the present invention is further elaborated below with reference to the drawings and the embodiments.

As shown in FIG. 1, the front-end circuit of the high-linearity CMOS terahertz detector comprises a biasing circuit, a detection circuit, a current mirror circuit and a square root operation circuit. The bias circuit is used for providing bias voltage for the grid electrode of the transistor of the detection circuit; the detection circuit is used for detecting amplitude information of the terahertz signal at the input end, specifically, the terahertz signal subjected to chopper modulation is received by an antenna and then is sent to a grid of an input transistor of the detection circuit, the terahertz signal is processed by the detection circuit to obtain a low-frequency detection signal which has the same frequency as the chopper modulation and contains envelope information, and the low-frequency detection signal contains the amplitude information of the terahertz signal at the input end; the current mirror circuit is used for copying the current information in the low-frequency detection signal and sending the current information to the square root operation circuit; the square root operation circuit carries out linearization processing on the copied low-frequency detection signal and finally outputs an output signal which is approximately square wave and has the same frequency as the chopping modulation. According to the invention, the detection transistor with the grid connected with the antenna is used for directly detecting the terahertz signal, and the detection signal is subjected to linearization processing, so that the linear detection of the voltage amplitude of the terahertz signal at room temperature is realized for the first time.

The bias circuit comprises a transistor M6 and a resistor R, wherein the source electrode of the transistor M6 is grounded, the grid electrode and the drain electrode are both connected with a first bias voltage, one end of the resistor R is connected with the grid electrode of a detection transistor M1 of the detection circuit, and the other end of the resistor R is connected with the first bias voltage.

The detection circuit comprises a detection transistor M1, an N-type cascode transistor M2, a P-type cascode transistor M3 and a capacitor C. The gate of the detection transistor M1 is connected to one end of the resistor R in the bias circuit and is directly connected to the antenna, the chopped and modulated terahertz signal is received by the antenna and sent to the gate of the detection transistor M1, the source of the detection transistor M1 is grounded, and since the detection transistor M1 operates in the saturation region, the drain of the detection transistor M1 generates a response current along with the change of the intensity of the gate input signal, as shown in fig. 2. Due to the square-law characteristic of the MOS transistor, the magnitude of the response current and the amplitude of the input terahertz signal are in the square-law characteristic. The drain electrode of the detection transistor M1 is connected with the source electrode of the N-type cascode transistor M2, the drain electrode of the N-type cascode transistor M2 is connected with the drain electrode of the P-type cascode transistor M3, and the high-frequency signal is filtered out by grounding through a capacitor C; a low-frequency voltage signal having the same period as the chopping signal is generated between the drain of the N-type cascode transistor M2 and the drain of the P-type cascode transistor M3, and a low-frequency current signal having the same period as the chopping signal is output from the source of the P-type cascode transistor M3, as shown in fig. 3. The detection transistor M1 works in a saturation region to directly detect the terahertz signal, the N-type cascode transistor M2, the P-type cascode transistor M3 and the capacitor C realize the detection of the detection signal from the terahertz frequency to the modulation frequency, namely, the detection circuit finishes the primary detection of the terahertz signal and realizes the detection of a high-frequency signal to a low-frequency signal; the gate of the N-type cascode transistor M2 is connected to a second bias voltage, and the gate of the P-type cascode transistor M3 is connected to a third bias voltage.

The current mirror circuit cancels the DC component, and only allows the low-frequency detection current signal to pass through. The current mirror circuit comprises a first PMOS transistor M4 and a second PMOS transistor M5, the grid electrode of the first PMOS transistor M4 is connected with the grid electrode of the second PMOS transistor M5, the source electrode of the first PMOS transistor M4 and the source electrode of the second PMOS transistor M5 are both connected with a power supply, the drain electrode and the grid electrode of the first PMOS transistor M4 are both connected with the source electrode of the P-type cascode transistor M3, one path of the drain electrode of the second PMOS transistor M5 is grounded through a first current source A1, and the other path of the drain electrode is connected with the input end of the square root operation circuit; the source electrode of the P-type cascode transistor M3 is connected with the drain electrode of the first PMOS transistor M4, the low-frequency current signal detected by the detection circuit is sent to the current mirror circuit, and the low-frequency current signal is copied in proportion through the second PMOS transistor M5. In order to ensure that only the low-frequency current signal is sent to the square root circuit for processing, the current source a1 is used to cancel the operating point dc current of the second PMOS transistor M5, and finally the cancelled low-frequency current signal with the same period as the chopping signal is sent to the square root operation circuit for linearization processing.

The square root operation circuit includes but is not limited to transconductance linear loop composed of BJT transistors, and the present embodiment provides a structure of square root operation circuit, which copies the obtained low frequency detection signal to the current mirror circuitThe square-opening processing is performed to linearize the product. As shown in fig. 4, the square root operation circuit is a transconductance linear loop formed by four BJT transistors, so as to implement nonlinear operation between current amounts; specifically, it includes a first BJT transistor T1, a second BJT transistor T2, a third BJT transistor T3, a fourth BJT transistor T4, and a second current source a 2. The emitter of the first BJT transistor T1 is grounded, the collector is connected to the base of the second BJT transistor T2 and serves as an input terminal for receiving an input current signal i_XA base connected to the emitter of a second BJT transistor T2; the emitter of the second BJT transistor T2 is connected to one end of the second current source A2, the base is connected to the base of the third BJT transistor T3, and the collector is connected to VDD; the collector of the third BJT transistor T3 is used as an output terminal for outputting a current signal i_OAn emitter connected to the collector and base of a fourth BJT transistor T4, and an emitter of the fourth BJT transistor T4 connected to ground; one terminal of the second current source a2 is connected to the emitter of the second BJT transistor T2, and the other terminal is connected to ground. Wherein, the input current signal i of the square root operation circuit_XAnd output current signal i_OHave the following relationship between:

wherein i_YIs the current of a second current source A2, will i_YSetting to a determined value, the current i can be measured_XThe square root operation of (1), the calculation result is the output current signal i_O。

The detection current signal with square law characteristic is converted into a low-frequency current signal which is in linear relation with the intensity of the input signal through a square root operation circuit with controllable coefficients, and the whole detection process is completed. The final detection result is shown in fig. 5, and it can be seen that the detector has good linearity.

An array front-end circuit comprising one or more pixels arranged in a matrix having rows and columns, the array front-end circuit further comprising at least one of the aforementioned high linearity CMOS terahertz detector front-end circuits.