阅读说明：本技术 Rtc数字电路断电保护方法、rtc数字电路及其芯片 (RTC digital circuit power-off protection method, RTC digital circuit and chip thereof ) 是由 朱佳 翁秀梅 宋佳驹 黄维 刘勇 夏晓玲 雷丁扬 蒋云翔 于 2020-07-09 设计创作，主要内容包括：本发明公开了一种RTC数字电路断电保护方法,包括RTC数字电路内部的所有功能寄存器均无复位端；断电时对RTC数字电路的输入信号进行过滤处理；进行快时钟和慢时钟转换时通过握手和对信号进行计数的方式过滤循环溢出的异常；对apb接口的写操作和读操作进行访问延时的优化。本发明还公开了包括了所述RTC数字电路断电保护方法的RTC数字电路,以及包括了所述RTC数字电路断电保护方法和RTC数字电路的芯片。本发明通过增加三种断电保护电路提高模块的稳定性和鲁棒性,通过apb接口写操作和读操作的访问延时优化提高模块访问的效率和可靠性；本发明技术方案更为简洁,成本低廉,而且有效提高了RTC数字电路的工作效率和精度。(The invention discloses a power-off protection method for an RTC digital circuit, which comprises that all functional registers in the RTC digital circuit have no reset end; when the power is off, the input signal of the RTC digital circuit is filtered; filtering the abnormal cycle overflow by handshaking and counting signals when the fast clock and the slow clock are switched; and optimizing the access delay of the write operation and the read operation of the apb interface. The invention also discloses the RTC digital circuit comprising the RTC digital circuit power-off protection method, and a chip comprising the RTC digital circuit power-off protection method and the RTC digital circuit. According to the invention, the stability and robustness of the module are improved by adding three power-off protection circuits, and the access efficiency and reliability of the module are improved by optimizing the access delay of write operation and read operation of the apb interface; the technical scheme of the invention is simpler and has low cost, and the working efficiency and the precision of the RTC digital circuit are effectively improved.)

1. A power-off protection method for an RTC digital circuit comprises the following steps:

s1, all functional registers in the RTC digital circuit have no reset terminals;

s2, when power is off, filtering an input signal of the RTC digital circuit, so as to ensure that the apb interface cannot operate abnormally;

s3, when the fast clock and the slow clock are converted, filtering the abnormal cycle overflow in a handshaking mode and a signal counting mode;

and S4, optimizing access delay of write operation and read operation of the apb interface, so that the problem of access delay of the RTC digital circuit is solved.

2. The method according to claim 1, wherein in step S2, when power is off, the input signal of the RTC digital circuit is filtered, specifically, after the apb interface successfully handshakes with the RTC digital circuit, the handshake successful signal is edge-detected, and when a falling edge is detected, the configuration enable of the fast clock domain is generated.

3. The method according to claim 1, wherein in step S3, when switching between the fast clock and the slow clock, generating a handshake signal by means of handshaking and counting signals, specifically, from the configuration flag of the fast clock domain, performing two-beat cross-clock domain switching in the slow clock domain, generating a flag signal, and counting the valid flag of the flag signal; when the count is kept unchanged after the count is accumulated to the set value, the abnormal signal of the overflow of the count cycle generated when the main power supply of the chip is powered off can be filtered.

4. The method according to claim 1, wherein in step S4, the access delay of the write operation of the apb interface is optimized, specifically, the configuration flag of the fast clock domain is set, and the duration of the configuration flag of the fast clock domain is specified to be a set number of fast clock cycles; meanwhile, when the configuration flag of the fast clock domain is high, starting configuration asynchronous conversion, and simultaneously, updating the state position to be high to show that the configuration is in effect; and clearing the updating state after judging that the configuration synchronization processing is finished.

5. The power-off protection method for the RTC digital circuit according to claim 1, wherein in step S4, the access delay of the read operation of the apb interface is optimized, specifically, a slow clock domain register selected according to the address is selected, and the selected register is subjected to the fast clock domain delay shooting to obtain the flag variable; and judging whether the slow clock domain register and the flag variable selected according to the address are equal and continue for a set time, so as to judge whether the read data is stable and return the read data in due time.

6. An RTC digital circuit, characterized in that it comprises the power-off protection method of RTC digital circuit as claimed in any one of claims 1-5.

7. A chip, characterized in that it comprises the RTC digital circuit power-off protection method of any one of claims 1 to 5 and the RTC digital circuit of claim 6.

Technical Field

The invention belongs to the technical field of chip design, and particularly relates to a power-off protection method for an RTC digital circuit, the RTC digital circuit and a chip thereof.

Background

With the development of economic technology and the improvement of living standard of people, navigation application becomes an unnecessary and scarce auxiliary function in production and life of people, and brings endless convenience to production and life of people.

In the application of navigation products, in order to improve the starting speed of hot start and warm start and improve the efficiency of recapture, a real-time clock rtc module is used for recording the current accurate time during navigation. And the product software acquires the accurate time of satellite time service in the tracking process, calculates the frequency deviation of the crystal oscillator according to the accurate time and the current time of rtc, and calibrates the time and the frequency of the rtc module. A typical clock for rtc circuit operation is 32.768 KHz.

The rtc circuit solution is divided into an external rtc module and an internal rtc circuit. The typical external rtc chip DS1342 has extremely low standby current, 32KHz clock is input externally, configuration operation is carried out by using a high-speed I2C interface, the clock of the I2C interface is 400KHz, and the packaging area is 9mm²A typical operating circuit is shown in fig. 1. When the central processing unit of the user side is powered off, the rtc chip uses the button battery to supply power to continue working, and the current time is updated. When the user side is powered on, the current time is read through an I2C interface and is used for navigation hot start or warm start. The problem of this scheme is that a single rtc chip is added in the hardware design of the product, the hardware cost and the area of the product are increased, and meanwhile, the central processing unit accesses the current time and uses an I2C interfaceAnd the register needs to be read repeatedly, so that great uncertain delay is brought to rtc current time of access, the current time is not accurate enough, and the efficiency of hot start and warm start is influenced.

In a navigation product, when an SoC chip with higher integration level is designed, a built-in rtc circuit can be added in the chip design to realize the function of real-time counting. The rtc circuit needs to design a power domain independently, and when the main power supply of the chip is powered off, the rtc power domain can work continuously to ensure correct counting. rtc circuits operate at low frequencies, typically 32.768 KHz. The cpu and rtc access the rtc internal register through the apb interface, the apb interface clock is fast, and the typical value is more than 50 MHz; a typical block diagram is shown in fig. 2. The scheme improves the integration level of products, reduces the hardware cost and the design complexity of the products, and becomes a mainstream rtc solution. This scheme has two drawbacks in chip design: (1) the rtc circuit is an independent power domain, when the chip is powered off, only the rtc circuit works normally, and other circuits are in an uncertain state. The input interface of the rtc circuit is a random value, resetting and wrong apb operation are generated with probability, impact is generated on the rtc function, and the rtc time function is wrong; (2) the cpu accesses an internal register of the rtc circuit through an apb interface of a fast clock domain, and because the working clock of rtc is a 32.768KHz slow clock domain and two clocks are in an asynchronous relation, the apb interface needs to be converted from the fast clock to the slow clock in order to avoid generating a metastable state by crossing the clocks. asynchronous conversion of the apb interface has a large delay, typically 100us, which causes the bus access efficiency of the cpu to be significantly reduced, and the normal function of the service is affected in an extreme case.

Disclosure of Invention

One of the objectives of the present invention is to provide a power-off protection method for an RTC digital circuit, which has high reliability, good practicability, low cost and high precision.

The present invention also provides an RTC digital circuit including the RTC digital circuit power-off protection method.

The invention also aims to provide a chip comprising the RTC digital circuit power-off protection method and the RTC digital circuit.

The invention provides a power-off protection method for an RTC digital circuit, which comprises the following steps:

s1, all functional registers in the RTC digital circuit have no reset terminals;

s2, when power is off, filtering an input signal of the RTC digital circuit, so as to ensure that the apb interface cannot operate abnormally;

s3, when the fast clock and the slow clock are converted, filtering the abnormal cycle overflow in a handshaking mode and a signal counting mode;

and S4, optimizing access delay of write operation and read operation of the apb interface, so that the problem of access delay of the RTC digital circuit is solved.

When the power is off, the step S2 is to filter the input signal of the RTC digital circuit, specifically, after the apb interface successfully handshakes with the RTC digital circuit, perform edge detection on the signal that has successfully handshakes, and generate the configuration enable of the fast clock domain when a falling edge is detected.

When the fast clock and the slow clock are converted in step S3, a handshake signal is generated in a handshake manner and a signal counting manner, specifically, a handshake signal is generated from a configuration flag of a fast clock domain, a slow clock domain is beaten for two beats to perform clock domain crossing conversion, a flag signal is generated, and an effective flag of the flag signal is counted; when the count is kept unchanged after the count is accumulated to the set value, the abnormal signal of the overflow of the count cycle generated when the main power supply of the chip is powered off can be filtered.

Optimizing access delay of the write operation of the apb interface in the step S4, specifically, setting a configuration flag of a fast clock domain, and specifying that the duration length of the configuration flag of the fast clock domain is a set number of fast clock cycles; meanwhile, when the configuration flag of the fast clock domain is high, starting configuration asynchronous conversion, and simultaneously, updating the state position to be high to show that the configuration is in effect; and clearing the updating state after judging that the configuration synchronization processing is finished.

In the step S4, optimizing access delay for read operation of the apb interface, specifically, selecting a slow clock domain register selected according to an address, and performing fast clock domain delay shooting on the selected register to obtain a flag variable; and judging whether the slow clock domain register and the flag variable selected according to the address are equal and continue for a set time, so as to judge whether the read data is stable and return the read data in due time.

The invention also provides an RTC digital circuit, which comprises the RTC digital circuit power-off protection method.

The invention also provides a chip which comprises the RTC digital circuit power-off protection method and the RTC digital circuit.

According to the RTC digital circuit power-off protection method, the RTC digital circuit and the chip thereof, the stability and robustness of the module are improved by adding three power-off protection circuits, and the access efficiency and reliability of the module are improved by optimizing the access delay of write operation and read operation of an apb interface; compared with the traditional method, the technical scheme is simpler and has low cost, and the working efficiency and the accuracy of the RTC digital circuit are effectively improved.

Drawings

Fig. 1 is a schematic circuit diagram of a conventional external RTC chip clock circuit.

Fig. 2 is a schematic circuit diagram of a conventional clock circuit with a built-in RTC chip.

FIG. 3 is a schematic flow chart of the method of the present invention.

FIG. 4 is a schematic flow chart of the method of the present invention for filtering the input signal of the RTC digital circuit when power is off.

FIG. 5 is a flow chart illustrating filtering of a cycle overflow exception by means of handshaking and by means of counting signals according to the method of the present invention.

FIG. 6 is a flowchart illustrating the access latency optimization of the write operation of the apb interface according to the method of the present invention.

FIG. 7 is a flowchart illustrating the access latency optimization of the read operation of the apb interface according to the method of the present invention.

Detailed Description

FIG. 3 is a schematic flow chart of the method of the present invention: the invention provides a power-off protection method for an RTC digital circuit, which comprises the following steps:

s1, all functional registers in the RTC digital circuit have no reset terminals;

in specific implementation, the internal counter of the rtc circuit uses a 32.768KHz clock, and all functional registers such as the counter and configuration values and the like have no reset end, so that the internal counter and the configuration cannot be cleared when the chip is powered off and no matter the reset signal of the interface is in any state; the design requires that user software configures an initial value when used for the first time, and the starting state is ensured to be correct;

s2, when power is off, filtering an input signal of the RTC digital circuit, so as to ensure that the apb interface cannot operate abnormally; specifically, after the apb interface successfully handshakes with the RTC digital circuit, edge detection is carried out on a handshake successful signal, and configuration enabling of a fast clock domain is generated when a falling edge is detected;