阅读说明：本技术 具有浮动栅极晶体管类型存储单元的随机码产生器 (Random code generator with floating gate transistor type memory cell ) 是由 古惟铭 孙文堂 陈英哲 于 2020-04-09 设计创作，主要内容包括：一种随机码产生器,包括一存储单元、两个写入缓冲器与两个感测电路。存储单元包括第一编程路径、第二编程路径、第一读取路径与第二读取路径。第一编程路径连接于第一源极线与第一位线之间,第二编程路径连接于第一源极线与第二位线之间,第一读取路径连接于第二源极线与第三位线之间,第二读取路径连接于第三源极线与第四位线之间。两个写入缓冲器分别连接至第一位线与第二位线。两个感测电路分别连接至第三位线与第四位线。两个感测电路根据读取路径上的读取电流,产生第一输出信号与第二输出信号,分别传递至对应的写入缓冲器。(A random code generator includes a memory cell, two write buffers and two sensing circuits. The memory cell includes a first programming path, a second programming path, a first reading path and a second reading path. The first programming path is connected between the first source line and the first bit line, the second programming path is connected between the first source line and the second bit line, the first reading path is connected between the second source line and the third bit line, and the second reading path is connected between the third source line and the fourth bit line. The two write buffers are respectively connected to the first bit line and the second bit line. The two sensing circuits are respectively connected to the third bit line and the fourth bit line. The two sensing circuits generate a first output signal and a second output signal according to the read current on the read path, and the first output signal and the second output signal are respectively transmitted to the corresponding write buffers.)

1. A random code generator, comprising:

a memory cell including a first program path, a second program path, a first read path and a second read path, wherein the first program path is connected between a first source line and a first bit line, the second program path is connected between the first source line and a second bit line, the first read path is connected between a second source line and a third bit line, and the second read path is connected between a third source line and a fourth bit line;

a first write buffer connected to the first bit line;

a second write buffer connected to the second bit line;

a first sensing circuit connected to the third bit line, wherein the first sensing circuit generates a first output signal to the second write buffer according to a first read current on the first read path; and

a second sensing circuit coupled to the fourth bit line, wherein the second sensing circuit generates a second output signal to the first write buffer according to a second read current on the second read path;

when the first output signal is different from the second output signal, one of the first programming path and the second programming path stops the programming operation.

2. The random code generator of claim 1, wherein the first programming path comprises:

a first select transistor, wherein a first terminal of the first select transistor is connected to the first source line, a second terminal of the first select transistor is connected to a node, and a control terminal of the first select transistor is connected to a word line; and

a first floating-gate transistor, wherein a first terminal of the first floating-gate transistor is connected to the node and a second terminal of the first floating-gate transistor is connected to the first bit line.

3. The random code generator of claim 2, wherein the second programming path comprises:

the first selection transistor; and

a second floating-gate transistor, wherein a first terminal of the second floating-gate transistor is connected to the node and a second terminal of the second floating-gate transistor is connected to the second bit line.

4. The random code generator of claim 3, wherein the first read path comprises:

a second select transistor, wherein a first terminal of the second select transistor is connected to the second source line, and a control terminal of the second select transistor is connected to the word line; and

a third floating-gate transistor, wherein a first terminal of the third floating-gate transistor is connected to a second terminal of the second select transistor, and a second terminal of the third floating-gate transistor is connected to the third bit line;

wherein a floating gate of the first floating gate transistor is connected to a floating gate of the third floating gate transistor.

5. The random code generator of claim 4, wherein the second read path comprises:

a third select transistor, wherein a first terminal of the third select transistor is connected to the third source line, and a control terminal of the third select transistor is connected to the word line; and

a fourth floating-gate transistor, wherein a first terminal of the fourth floating-gate transistor is connected to a second terminal of the third select transistor, and a second terminal of the fourth floating-gate transistor is connected to the fourth bit line;

wherein a floating gate of the second floating-gate transistor is connected to a floating gate of the fourth floating-gate transistor.

6. The random code generator of claim 5, wherein during the register operation, the word line is provided with a ground voltage, the first source line is provided with a programming voltage, the second source line and the third source line are provided with a read voltage, the first bit line and the second bit line are provided with the ground voltage, the third bit line and the fourth bit line are provided with a first voltage, the first programming path and the second programming path are enabled to perform the programming operation, and the first read path and the second read path are enabled to perform the read operation.

7. The random code generator of claim 6, wherein the programming voltage is greater than the read voltage, the read voltage is greater than the first voltage, and the first voltage is greater than or equal to the ground voltage.

8. The random code generator of claim 6 wherein the first output signal is a first logic level when the first read current is less than a reference current; when the first reading current is larger than the reference current, the first output signal is a second logic level; when the second reading current is smaller than the reference current, the second output signal is the first logic level; when the second reading current is larger than the reference current, the second output signal is the second logic level.

9. The random code generator of claim 8, wherein when the first output signal changes from the first logic level to the second logic level and the second output signal remains at the first logic level, the second write buffer receives the first output signal and stops the second programming path from performing the programming operation, and the first write buffer receives the second output signal and continues the programming operation on the first programming path.

10. The random code generator of claim 9, wherein the programming voltage is increased while the first write buffer continues the programming operation on the first programming path.

11. The random code generator of claim 5, further comprising a first control path connected between a first control line and the floating gate of the first floating gate transistor and a second control path connected between a second control line and the floating gate of the second floating gate transistor.

12. The random code generator of claim 11, wherein the first control path includes a first capacitor connected between the first control line and the floating gate of the first floating gate transistor; and the second control path includes a second capacitor connected between the second control line and the floating gate of the second floating gate transistor.

13. The random code generator of claim 12, wherein an erase operation and a random program operation are performed on the second programming path before the registration operation is terminated.

14. The random code generator of claim 5, wherein the first sensing circuit comprises a first switch and a first sense amplifier, a first terminal of the first switch is connected to the third bit line, a second terminal of the first switch is connected to the first sense amplifier; the second sensing circuit comprises a second switch and a second sensing amplifier, wherein a first end of the second switch is connected to the fourth bit line, and a second end of the second switch is connected to the second sensing amplifier; the first sense amplifier generates the first output signal to the second switch and the second write buffer, and the second sense amplifier generates the second output signal to the first switch and the first write buffer.

15. The random code generator of claim 14, wherein when the first output signal changes from the first logic level to the second logic level and the second output signal remains at the first logic level, the second write buffer receives the first output signal and stops the programming operation on the second programming path, the second switch receives the first output signal and stops the reading on the second reading path, and the first write buffer receives the second output signal and continues the programming operation on the first programming path.

16. The random code generator of claim 1, wherein the read operation is performed using the first read path after the registration operation and is performed as a bit of a random code according to a logic level of the first output signal.

17. The random code generator of claim 1 wherein a scrambling operation is performed on the second programming path prior to terminating the registration operation.

18. The random code generator of claim 17, wherein the scrambling operation comprises a random programming operation.

19. The random code generator of claim 1, wherein the second source line and third source line are connected.

Technical Field

The present invention relates to a random code generator, and more particularly, to a random code generator having floating gate transistor type memory cells.

Background

Generally, a nonvolatile memory can be divided into a one-time programmable memory (OTP memory) and a multi-time programmable memory (MTP memory). The OTP memory is composed of a plurality of OTP memory cells, and the MTP memory is composed of a plurality of MTP memory cells. In addition, an OTP memory cell or an MTP memory cell may be formed of a floating gate transistor (floating gate transistor).

OTP memory cells consisting of floating gate transistors and MTP memory cells are described in US 8,941,167. Referring to fig. 1A and 1B, a conventional OTP memory cell with a floating gate transistor and bias voltage is illustrated.

The OTP memory cell 100 includes a select transistor Ms and a floating gate transistor Mf. A first terminal of the selection transistor Ms is connected to a source line SL, a control terminal of the selection transistor Ms is connected to the word line WL, a first terminal of the floating gate transistor Mf is connected to a second terminal of the selection transistor Ms, and a second terminal of the floating gate transistor Mf is connected to the bit line BL. A programming path (program path) and a read path (readpath) may be provided between the source line SL and the bit line BL of the OTP memory 100. That is, after providing proper bias voltages (bias voltages) to the word line WL, the source line SL and the bit line BL, a program operation (program operation) or a read operation (read operation) can be performed on the floating gate transistor Mf in the OTP memory cell 100.

As shown in fig. 1B, in the program operation (PGM), the source line SL receives the program voltage Vpp, and the word line WL and the bit line BL receive the ground voltage (0V). For example, the programming voltage Vpp is 8V.

At this time, the selection transistor Ms is turned on, and a programming current (program current) is generated in a programming path between the source line SL and the bit line BL. Furthermore, in the floating-gate transistor Mf, electrons are injected into the floating gate from a channel region of the floating-gate transistor Mf, and the program operation is completed.

In a READ operation (READ), the source line SL receives a READ voltage Vr, and the word line WL and the bit line BL receive a ground voltage (0V). For example, the read voltage Vr is 3.0V.

At this time, the selection transistor Ms is turned on, and a read current (readcurrent) is generated in a read path between the source line SL and the bit line BL. Furthermore, the magnitude of the read current can be determined according to whether the floating gate of the floating gate transistor Mf stores electrons. For example, when no electrons are stored in the floating gate, the read current is very small, approaching zero. In addition, when electrons are stored in the floating gate, the read current is large. Therefore, the storage state of the OTP memory 100 can be determined according to the magnitude of the read current on the bit line BL.

For example, a sense amplifier (not shown) is provided to be connected to the bit line BL, and a reference current is set in the sense amplifier. When the read current is less than the reference current, the sense amplifier may determine that the floating-gate transistor Mf in the OTP memory cell 100 is in the first storage state. When the read current is greater than the reference current, the sense amplifier may determine that the floating-gate transistor Mf in the OTP memory cell 100 is in the second storage state.

Referring to fig. 2A and 2B, a conventional MTP memory cell comprising a floating gate transistor and bias voltage are illustrated.

The MTP memory cell 200 includes a select transistor Ms, a floating gate transistor Mf, and a capacitor Ce. A first terminal of the selection transistor Ms is connected to a source line SL, a control terminal of the selection transistor Ms is connected to the word line WL, a first terminal of the floating gate transistor Mf is connected to a second terminal of the selection transistor Ms, and a second terminal of the floating gate transistor Mf is connected to the bit line BL. Further, the capacitor Ce is connected between the floating gate and the erase line EL. The source line SL and the bit line BL of the MTP memory cell 200 can be used as a programming path and a reading path, and the floating gate and the erase line EL can be used as an erase path (erase path).

As shown in fig. 2B, in the program operation (PGM), the source line SL receives the program voltage Vpp, and the word line WL, the bit line BL, and the erase line EL receive the ground voltage (0V). For example, the programming voltage Vpp is 8V.

At this time, the selection transistor Ms is turned on, and a programming current (program current) is generated in a programming path between the source line SL and the bit line BL. Furthermore, in the floating-gate transistor Mf, electrons are injected into the floating gate from a channel region of the floating-gate transistor Mf, and the program operation is completed.

In addition, during a READ operation (READ), the source line SL receives a READ voltage Vr, and the word line WL, the bit line BL, and the erase line EL receive a ground voltage (0V). For example, the read voltage Vr is 3.0V.

At this time, the selection transistor Ms is turned on, and a read current (readcurrent) is generated in a read path between the source line SL and the bit line BL. Furthermore, the magnitude of the read current can be determined according to whether the floating gate stores electrons, and the storage state of the MTP memory cell 200 can be determined. Similarly, a sense amplifier is provided and connected to the bit line BL and receives the read current. According to the magnitude of the read current, the sense amplifier can determine whether the floating-gate transistor Mf in the MTP memory cell 200 is in the first storage state or the second storage state.

In addition, during an erase operation (ERS), the source line SL, the word line WL, and the bit line BL receive a ground voltage (0V), and the erase line EL receives an erase voltage Vee. For example, the erase voltage Vee is 12.0V.

At this time, electrons stored on the floating gate are ejected to the erase line EL through the erase path. That is, electrons stored on the floating gate exit the erase line through capacitor Ce and exit the floating gate transistor Mf.

Physical Unclonable Function (PUF) technology is an innovative way to protect data inside a semiconductor chip and prevent the internal data of the semiconductor chip from being stolen. According to PUF technology, a semiconductor chip can provide a random code. The random code may be used as an ID code (ID code) unique to a semiconductor chip to protect internal data.

Generally, PUF technology utilizes manufacturing variations (manufacturing variations) of semiconductor chips to obtain unique random codes. Such manufacturing variations include process variations of semiconductors. That is, even if a precise process step is available, the random code is almost impossible to be copied (duplicate). Therefore, semiconductor chips with PUF technology are often used for high security applications (applications with high security requirements).

U.S. Pat. No. US 9,613,714 discloses a random code generator having an antifuse transistor type memory cell (antifuse type memory cell), and uses the storage state of the memory cell as a random code. It is contemplated that other types of memory cells may be used as the random code generator.

Disclosure of Invention

The main objective of the present invention is to provide a random code generator, which includes: a memory cell including a first program path, a second program path, a first read path and a second read path, wherein the first program path is connected between a first source line and a first bit line, the second program path is connected between the first source line and a second bit line, the first read path is connected between a second source line and a third bit line, and the second read path is connected between a third source line and a fourth bit line; a first write buffer connected to the first bit line; a second write buffer connected to the second bit line; a first sensing circuit connected to the third bit line, wherein the first sensing circuit generates a first output signal to the second write buffer according to a first read current on the first read path; and a second sensing circuit coupled to the fourth bit line, wherein the second sensing circuit generates a second output signal to the first write buffer according to a second read current on the second read path; when the logic level of the first output signal is different from that of the second output signal, one of the first programming path and the second programming path stops the programming operation.

Drawings

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments is made with reference to the accompanying drawings:

FIGS. 1A and 1B are schematic diagrams of a conventional OTP memory cell comprising floating gate transistors and bias voltages.

Fig. 2A and 2B are schematic diagrams of a conventional MTP memory cell composed of floating gate transistors and bias voltages.

FIG. 3A is a diagram of a random code generator according to a first embodiment of the present invention.

FIG. 3B is a flowchart illustrating a random code generator during a registration operation according to the present invention.

Fig. 4A to 4C are schematic diagrams illustrating bias voltages of the random code generator during a registration operation according to the present invention.

FIG. 5 is a diagram of a random code generator generating a random code.

FIG. 6 is another flow chart of the random code generator during the registration operation according to the present invention.

FIG. 7 is a diagram of a random code generator according to a second embodiment of the present invention.

FIG. 8 is a diagram of a random code generator according to a third embodiment of the present invention.

Detailed Description

The invention designs a floating grid transistor type storage unit by utilizing the characteristics of the floating grid transistor and applies the floating grid transistor type storage unit as a PUF storage unit to a random code generator. Referring to fig. 3A, a random code generator according to a first embodiment of the invention is shown. The random code generator 300 includes a PUF memory cell c1, two write buffers (write buffers) 302,304, and two sensing circuits (sensing circuits) 312, 314. The sensing circuits 312 and 314 may be sense amplifiers.

According to a first embodiment of the present invention, PUF cell c1 includes two programming paths and two read paths. A first programming path is formed between source line SLw and bit line BLw, a second programming path is formed between source line SLw and bit line BLw ', a first reading path is formed between source line SLr and bit line BLr, and a second reading path is formed between source line SLr ' and bit line BLr '. Furthermore, each path includes a floating gate transistor.

As shown in FIG. 3A, the first programming path includes the select transistor Ms1 and the floating-gate transistor Mf 1. A first terminal of the select transistor Ms1 is connected to a source line SLw, a control terminal of the select transistor Ms1 is connected to the word line WL, and a second terminal of the select transistor Ms1 is connected to node a. A first terminal of floating-gate transistor Mf1 is connected to node a, and a second terminal of floating-gate transistor Mf1 is connected to bit line BLw.

The second programming path includes select transistor Ms1 and floating gate transistor Mf 2. A first terminal of the floating-gate transistor Mf2 is connected to node a, and a second terminal of the floating-gate transistor Mf2 is connected to the bit line BLw'.

The first read path includes select transistor Ms2 and floating gate transistor Mf 3. The first terminal of the select transistor Ms2 is connected to a source line SLr, the control terminal of the select transistor Ms2 is connected to the word line WL, the first terminal of the floating-gate transistor Mf3 is connected to the second terminal of the select transistor Ms2, and the second terminal of the floating-gate transistor Mf3 is connected to the bit line BLr. In addition, the floating-gate transistor Mf1 of the first programming path and the floating-gate transistor Mf3 of the first read path have a shared floating gate (shared floating gate). That is, the floating gate of floating-gate transistor Mf1 is connected to the floating gate of floating-gate transistor Mf 3.

The second read path includes select transistor Ms3 and floating gate transistor Mf 4. The first terminal of the select transistor Ms3 is connected to a source line SLr ', the control terminal of the select transistor Ms3 is connected to the word line WL, the first terminal of the floating-gate transistor Mf4 is connected to the second terminal of the select transistor Ms3, and the second terminal of the floating-gate transistor Mf4 is connected to the bit line BLr'. In addition, the floating gate transistor Mf2 of the second programming path and the floating gate transistor Mf4 of the second read path have a shared floating gate. That is, the floating gate of floating-gate transistor Mf2 is connected to the floating gate of floating-gate transistor Mf 4.

Further, the write buffer 302 of the random code generator 300 is connected to the bit line BLw, the write buffer 304 is connected to the bit line BLw ', the sense circuit 312 is connected to the bit line BLr, and the sense circuit 314 is connected to the bit line BLr'.

According to the first embodiment of the present invention, the sensing circuit 312 may generate an output signal Out to the write buffer 304 for interrupting the operation of the write buffer 304 when the random code generator 300 performs an enroling operation (enrolingdetection). Similarly, the sensing circuit 314 may generate an output signal Out' to the write buffer 302 for interrupting the operation of the write buffer 302.

Referring to fig. 3B, a flow chart of the random code generator during the registration operation according to the present invention is shown.

First, a registration operation is started (step S320). During the register operation, the first programming path and the second programming path of the random code generator 300 perform the program operation, and the first read path and the second read path perform the read operation.

Next, when the output signal Out is different from the output signal Out' (step S322), the random code generator 300 performs a programming operation only by using a single programming path (step S324). That is, when one of the output signal Out and the output signal Out' changes logic level, the random code generator 300 continues the programming operation by using one of the first programming path and the second programming path, and the other programming path stops the programming operation. Thereafter, the random code generator 300 completes the registration operation (step S326). This is explained in detail below.

Fig. 4A to 4C are schematic diagrams illustrating bias voltages of the random code generator during a registration operation according to the present invention.

As shown in fig. 4A, during the register operation, the word line WL receives the ground voltage (0V), the source line SLw receives the program voltage Vpp, and the source lines SLr and SLr' receive the read voltage Vr. In addition, the write buffer 302 provides a ground voltage (0V) to the bit line BLw, the write buffer 304 provides a ground voltage (0V) to the bit line BLw ', the sense circuit 312 provides a first voltage (e.g., 0.4V) to the bit line BLr, and the sense circuit 314 provides a first voltage (e.g., 0.4V) to the bit line BLr'. For example, the program voltage Vpp is 7.25V, the read voltage Vr is 3.6V, and the first voltage is 0.4V. Of course, the first voltage may be equal to the ground voltage (0V). That is, the program voltage Vpp is greater than the read voltage Vr, the read voltage Vr is greater than the first voltage, and the first voltage is equal to or greater than the ground voltage (0V).

At this time, the selection transistors Ms1 to Ms3 are turned on, and the PUF memory cell c1 starts a registration operation. That is, the first programming path and the second programming path start the programming operation, and the first reading path and the second reading path start the reading operation.

According to the first embodiment of the present invention, in the initial stage of the registration operation of the PUF memory cell c1, the first read current Ir1 in the first read path is very small and close to zero because the shared floating gates of the floating gate transistors Mf1 and Mf3 do not store electrons. Similarly, since the shared floating gates of the floating-gate transistors Mf2, Mf4 do not store electrons, the second read current Ir2 of the second read path is very small, close to zero. Therefore, the reference current in the sensing circuit 312 is greater than the first read current Ir1, so that the output signal Out generates a first logic level "1" representing that the floating-gate transistors Mf1, Mf3 are in the first storage state. In addition. The reference current in the sensing circuit 314 is also greater than the second read current Ir2, such that the output signal Out' generates a first logic level "1" representing that the floating-gate transistors Mf2, Mf4 are in the first storage state. For example, the reference current in the sense circuits 312 and 314 may be set to 2 μ A.

As shown in fig. 4B, the floating gate transistor Mf1 of the first programming path and the floating gate transistor Mf2 of the second programming path have a slight difference due to manufacturing variations of the semiconductor process. This difference causes most of the electrons to be injected into one of the two floating gate transistors Mf1, Mf2 during the registration operation.

For example, in FIG. 4B, during the register operation, the first programming current Ip1 in the first programming path is greater than the second programming current Ip2 in the second programming path. In other words, most of the electrons are injected into the floating gate transistor Mf 1.

Since the shared floating gates of the floating-gate transistors Mf1, Mf3 begin to store electrons, and as the number of stored electrons increases, the first read current Ir1 generated by the floating-gate transistor Mf3 on the first read path also increases. In addition, since the shared floating gates of the floating-gate transistors Mf2 and Mf4 only store a small amount of electrons, the second read current Ir2 generated by the floating-gate transistor Mf4 in the second read path rises much faster than the first read current Ir 1.

Since the first read current Ir1 and the second read current Ir2 are rising but have not exceeded the reference currents in the sensing circuits 312 and 314, the output signal Out of the sensing circuit 312 and the output signal Out' of the sensing circuit 314 are both maintained at the first logic level "1".

As shown in FIG. 4C, after the shared floating gates of the floating-gate transistors Mf1, Mf3 inject a certain amount of electrons, the first read current Ir1 on the first read path will be greater than the reference current in the sense circuit 312, causing the output signal Out to generate a second logic level "0" representing a change of the floating-gate transistors Mf1, Mf3 to the second storage state.

Further, the sensing circuit 312 generates an output signal Out of a second logic level "0" to the write buffer 304, so that the write buffer 304 stops operating, and further controls the bit line BLw' to be in a floating state (floating). Thus, the second programming path stops the programming operation and electrons are no longer injected into the floating gate of the floating-gate transistor Mf2, so that the floating-gate transistors Mf2, Mf4 remain in the first storage state. At the same time, since the output signal Out' of the sensing circuit 314 is still maintained at the first logic level "1", the floating-gate transistor Mf1 on the first programming path will still be continuously injecting electrons.

In other words, when the output signal Out of the sensing circuit 312 is different from the output signal Out' of the sensing circuit 134, only a single programming path remains in the PUF memory cell c1 to continue the programming operation, and the other programming path stops the programming operation. Therefore, when the register operation is completed, the floating-gate transistors Mf1, Mf3 change to the second storage state, and the floating-gate transistors Mf2, Mf4 remain in the first storage state.

In another case, when the random code generator 300 performs the register operation, the second programming current Ip2 of the second programming path may be greater than the first programming current Ip1 of the first programming path, so that most electrons are injected into the floating-gate transistor Mf 2. Therefore, when the register operation is completed, the floating-gate transistors Mf2, Mf4 change to the second storage state, and the floating-gate transistors Mf1, Mf3 remain in the first storage state. The detailed operation principle is similar, and the detailed description is omitted here.

As can be seen from the above description, the random code generator 300 according to the first embodiment of the present invention can generate a random code by using PUF technology because the random code generator 300 cannot predict which floating gate transistor in the PUF memory cell c1 will be injected with a large number of electrons during an enrollment operation due to manufacturing variations in semiconductor manufacturing processes.

After the registration operation is completed, the random code generator 300 can perform the reading operation again to obtain the random code. According to the embodiment of the invention, the random code generator 300 can generate the random code by performing the read operation only through the first read path or the second read path.

The reading operation using the first read path and the sensing circuit 312 is described as an example. Referring to fig. 5, a schematic diagram of a random code generator generating a random code is shown. When the random code generator 300 performs a read operation after the registration operation is completed. The word line WL receives a ground voltage (0V), the source line SLr receives a read voltage Vr, and the sensing circuit 312 provides a first voltage (e.g., 0.4V) to the bit line BLr. In addition, since the first, second and second program paths are not operated, the write buffers 302,304 and the sense circuit 314 are maintained in standby (standby) so that the bit lines BLw, BLw ', BLr' are in a floating state.

As shown in FIG. 5, when electrons are stored in the shared floating gates of the floating-gate transistors Mf1 and Mf3, the first read current Ir1 generated in the first read path is larger than the reference current in the sense circuit 312, and the sense circuit 312 generates the output signal Out at the second logic level "0" as a bit of the random code.

On the other hand, if electrons are not stored in the shared floating gates of the floating-gate transistors Mf1 and Mf3, the first read current Ir1 generated in the first read path is smaller than the reference current in the sensing circuit 312, and the sensing circuit 312 generates the output signal Out at the first logic level "1" as a bit of the random code.

Furthermore, in an actual design, the word line WL of the random code generator 300 may be connected to a plurality of PUF memory cells, for example, 8 PUF memory cells. Furthermore, when a row of PUF memory cells connected to a word line WL is first subjected to a registration operation and then a read operation, a random code of 8 bits (one byte) is generated.

In addition, the flowchart of the registration operation shown in fig. 3B of the present invention may be further modified. For example, in the register operation and when the output signal Out is the same as the output signal Out', the random code generator 300 provides the program voltage Vpp to the source line SLw. When it is determined that the output signal Out is different from the output signal Out', the random code generator 300 further increases the programming voltage Vpp, for example (from 7.25V to 7.5V), when performing the programming operation on the single programming path (step S324), so as to improve the programming efficiency of the single programming path and inject more electrons into the floating gate transistor on the single programming path.

In addition, after the random code generator 300 completes the registration operation, the storage states of the floating-gate transistors Mf1 Mf4 in the PUF memory cell c1 are fixed and will not change. Therefore, a person of ordinary skill can scan the PUF memory cell c1 by electron beam inspection (electron beam inspection) and further derive the storage states of the floating-gate transistors Mf1 Mf4 and the random code. Thus, the random code of the random code generator 300 may be cracked, resulting in data theft inside the semiconductor chip.

Referring to fig. 6, another flow chart of the random code generator during the registration operation of the present invention is shown. Compared with fig. 3B, a scrambling operation (scrambling operation) on the second programming path is added (step S610).

Since the random code generator 300 utilizes the first read path and the sensing circuit 312 to perform a read operation and generate a random code. That is, the storage states of the floating-gate transistors Mf2 and Mf4 in the second read path and the second program path can be arbitrarily changed without affecting the contents of the random code. Therefore, the random code generator 300 can perform scrambling operation for the second programming path. For example, the scrambling action includes a random program operation (random program operation).

For example, the random code generator 300 includes 8 PUF memory cells. The random code generator 300 performs a random program operation (random program operation) on the second program path in the 8 PUF memory cells. That is, the storage state of floating-gate transistor Mf2 in the second programming path is randomly changed. After the random programming operation is completed, even if the contents of 8 PUF memory cells are scanned by electron beam detection (electron beam inspection), it is not easy to derive a random code. Therefore, data inside the semiconductor chip can be more effectively prevented from being stolen.

Of course, if the random code generator 300 utilizes the second read path and the sensing circuit 314 to perform a read operation and generate a random code. Then random code generator 300 may perform a scrambling action for the first programming path.

Referring to fig. 7, a random code generator according to a second embodiment of the invention is shown. The difference between the second embodiment random code generator 700 and the first embodiment random code generator 300 is the structure of the sensing circuits 312 and 314. Only this difference will be described below.

The sensing circuit 312 includes a switch 702 and a sense amplifier 704, a first terminal of the switch 702 is connected to the bit line BLr, a second terminal of the switch 702 is connected to the sense amplifier 704, and a control terminal of the switch 702 receives the output signal Out'.

The sensing circuit 314 includes a switch 712 and a sense amplifier 714, a first terminal of the switch 712 is connected to the bit line BLr', a second terminal of the switch 712 is connected to the sense amplifier 714, and a control terminal of the switch 712 receives the output signal Out. The switches 702 and 712 may be transmission gates (transmission gates).

According to the second embodiment of the present invention, when the random code generator 700 performs the register operation, the switches 702 and 712 are in the closed state (close state), the sense amplifiers 704 and 714 respectively receive the first read current Ir1 and the second read current Ir2, and generate the output signals Out and Out'.

In addition, when one of the two output signals Out, Out' changes the output logic level, the commanded switch changes to an open state (open state). For example, when the output signal Out of the sense amplifier 704 changes from the first logic level "1" to the second logic level "0", in addition to stopping the operation of the write buffer 304, the switch 712 in the sense circuit 314 is further controlled to be in an open state, so that the second read path stops operating. That is, the second read path no longer generates the second read current Ir 2. Thus, the random code generator 700 can reduce power consumption.

Similarly, when the output signal Out' of the sense amplifier 714 changes from the first logic level "1" to the second logic level "0", the switch 702 in the sense circuit 312 is further controlled to be in an open state in addition to the write buffer 302, so that the first read path stops operating.

Referring to fig. 8, a random code generator according to a third embodiment of the invention is shown. The difference between the third embodiment random code generator 800 and the first embodiment random code generator 300 is the structure of the PUF memory cell ca, in which two control paths are added. Only this difference will be described below.

The PUF memory cell ca further includes two capacitors C1 and C2. A first terminal of capacitor C1 is connected to the shared floating gate of floating-gate transistors Mf1, Mf3, and a second terminal of capacitor C1 is connected to a control line CL1 and forms a first control path. A first terminal of capacitor C2 is connected to the shared floating gate of floating-gate transistors Mf2, Mf4, and a second terminal of capacitor C2 is connected to a control line CL2 and forms a second control path.

Furthermore, the control lines CL1, CL2 may receive the erase voltage Vee such that the control path in the PUF memory cell ca is the erase path for electrons exiting the floating gate transistors Mf 1-Mf 4. Therefore, the PUF memory cell ca is an MTP memory cell. A first erase path is provided between the shared floating gates of the floating gate transistors Mf1 and Mf3 and the control line CL1, and a second erase path is provided between the shared floating gates of the floating gate transistors Mf2 and Mf4 and the control line CL 2. For example, the erase voltage Vee is 12.0V.

As can be seen from the above description, the random code generator 800 further performs an erase operation (erase operation), such that the electrons stored in the floating-gate transistors Mf1 and Mf3 exit the PUF memory cell ca through the first erase path, and the electrons stored in the floating-gate transistors Mf2 and Mf4 exit the PUF memory cell ca through the second erase path.

In addition, the PUF storage cell ca of the random code generator 800 is an MTP storage cell. Therefore, the scrambling operation performed on the second programming path during the register operation of the random code generator 800 may further include an erase operation.

Assume that the random code generator 800 utilizes the first read path and the sensing circuit 312 to perform a read operation and generate a random code. The random code generator 800 may scramble the second programming path without changing the random code. Furthermore, the scrambling operations include an erase operation and a random program operation.

For example, the random code generator 800 includes 8 PUF memory cells. Random code generator 800 performs an erase operation on the second erase path of the 8 PUF memory cells, so that the floating gate transistors in the second program path are restored to the first storage state. Next, the random code generator 800 performs a random programming operation on the second programming path of the 8 PUF memory cells. Therefore, after the random programming operation is completed, it is not easy to derive a random code even if the contents of 8 PUF memory cells are scanned using electron beam detection. Therefore, data inside the semiconductor chip can be more effectively prevented from being stolen.

Of course, if the random code generator 800 utilizes the second read path and the sensing circuit 314 to perform a read operation and generate a random code. The random code generator 800 may perform an erase operation for the first erase path. And then, carrying out random programming operation on the first programming path.

It is specifically noted that the structure of the random code generators 300,700, and 800 described above can also be adjusted for external requirements (e.g., area considerations). For example, the source lines SLr and SLr in the random code generators 300,700 and 800 can share a well region to connect the source lines, thereby achieving the purpose of area reduction.

From the foregoing, it can be seen that the present invention provides a random code generator having a floating gate transistor type memory cell. The PUF memory cell comprises two programming paths and two reading paths, and after the registering operation, two floating gate transistors on the two programming paths have different storage states. Since the storage states of the two floating gate transistors on the two programming paths cannot be accurately predicted. Thus, the random code generator of the present invention can indeed employ PUF technology to generate random codes.

While the present invention has been described with reference to the above embodiments, it is not intended to be limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention should be determined by the appended claims.

[ notation ] to show

100,200 memory cell

300,700,800 random code generator

302,304 write buffer

312,314 sensing circuit

702,712 switch

704,714 sense amplifier

S320-S326, S610, step flow