阅读说明：本技术 阻变存储器件 (Resistive memory device ) 是由 李基远 朴镇寿 于 2020-01-16 设计创作，主要内容包括：阻变存储器件可以包括多个存储单元和控制电路块。存储单元可以连接在全局字线和全局位线之间。控制电路块可以控制存储单元。控制电路块可以包括写入脉冲控制块。写入脉冲控制块可以包括连接在全局字线与选定存储单元之间的高电阻路径电路和旁通电路。写入脉冲控制块可以根据选定存储单元的位置来选择性地将高电阻路径电路和旁通电路中的任意一个使能。(The resistive memory device may include a plurality of memory cells and a control circuit block. The memory cells may be connected between a global word line and a global bit line. The control circuit block may control the memory cell. The control circuit block may include a write pulse control block. The write pulse control block may include a high resistance path circuit and a bypass circuit connected between the global word line and the selected memory cell. The write pulse control block may selectively enable either one of the high resistance path circuit and the bypass circuit according to the location of the selected memory cell.)

1. A resistive memory device, comprising:

a plurality of memory cells electrically coupled between the global word lines and the global bit lines; and

a control circuit block for controlling the plurality of memory cells,

wherein the control circuit block includes: a write pulse control block electrically coupled between the global word line and a selected memory cell among the plurality of memory cells to control a current flowing through the selected memory cell according to a location of the selected memory cell.

2. The resistive-switching memory device according to claim 1, wherein the write pulse control block comprises:

a high resistance path circuit; and

a bypass circuit for bypassing the power supply to the power supply,

wherein any one of the high resistance path circuit and the bypass circuit is selectively connected between the global word line and the selected memory cell according to a position of the selected memory cell.

3. The resistive-switching memory device according to claim 2, wherein the high-resistance path circuit is enabled when a memory cell near the control circuit block among memory cells is turned on, and the bypass circuit is enabled when a memory cell far from the control circuit block among memory cells is turned on.

4. The resistive-switching memory device according to claim 2, wherein the control circuit block comprises: a detection circuit block configured to detect conduction of the selected memory cell based on the current of the selected memory cell and generate a detection signal,

wherein the write pulse control block enables any one of the high resistance path circuit and the bypass circuit in response to the detection signal and the address information of the selected memory cell.

5. The resistive-switching memory device according to claim 4, wherein the control circuit block further comprises: a control signal generation circuit for logically combining the detection signal provided from the detection circuit block with the address information of the selected memory cell to generate a control signal for enabling the high resistance path circuit and the bypass circuit of the write pulse control block.

6. The resistive-switching memory device according to claim 1, wherein the write pulse control block comprises: a high resistance path circuit and a bypass circuit connected in parallel between the global word line and the selected memory cell, the high resistance path circuit including a MOS transistor, and a resistance of the MOS transistor of the high resistance path circuit being higher than a resistance when the bypass circuit is selected and lower than a resistance when the bypass circuit is not selected.

7. The resistive-switching memory device according to claim 1, wherein the write pulse control block comprises: a high resistance path circuit and a bypass circuit connected in parallel between the global word line and the selected memory cell, the high resistance path circuit including a variable resistance, and the variable resistance being higher than a resistance when the bypass circuit is selected and lower than a resistance when the bypass circuit is not selected.

8. The resistive-switching memory device according to claim 1, wherein the write pulse control block comprises: a high resistance path circuit and a bypass circuit connected in parallel between the global word line and the selected memory cell, and the high resistance path circuit includes a plurality of transistors connected in parallel, the plurality of transistors being selected in response to a plurality of current control signals.

9. The resistive-switching memory device according to claim 2, wherein the bypass circuit comprises a transmission gate comprising an NMOS transistor and a PMOS transistor.

10. The resistive-switching memory device according to claim 1, further comprising a voltage control circuit electrically coupled to the global bit line, wherein the voltage control circuit provides an initial voltage for maintaining conduction of the selected memory cell to the selected memory cell when the selected memory cell is not conducted, and provides a write voltage to the selected memory cell when the selected memory cell is conducted.

11. The resistive-switching memory device according to claim 1, further comprising a current control circuit electrically coupled to the global word line, wherein the current control circuit provides an initial current to the selected memory cell for maintaining conduction of the selected memory cell when the selected memory cell is not conducted, and provides a write current to the selected memory cell when the selected memory cell is conducted.

12. A resistive memory device, comprising:

a memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged between the plurality of word lines and the plurality of bit lines; and

a control circuit block disposed at an edge portion of the memory cell array to control the plurality of memory cells,

wherein the control circuit block includes:

a detection circuit block configured to detect conduction of a selected memory cell among the plurality of memory cells to generate a detection signal according to a detection result, an

A write pulse control block configured to selectively connect a word line connected to the selected memory cell among the plurality of word lines with a high resistance path circuit and a bypass circuit according to the detection signal and the address information of the selected memory cell.

13. The resistive-switching memory device according to claim 12, wherein the write pulse control block is configured to: when the detection signal is enabled and the address of the selected memory cell is within a near cell group disposed near the control circuit block, the high resistance path circuit is enabled, and the write pulse control block is configured to: the bypass circuit is enabled when the detection signal is not enabled or the address of the selected memory cell is within a remote group of cells disposed remote from the control circuit block.

14. The resistive-switching memory device of claim 12, wherein the control circuit block further comprises: a control signal generation circuit for logically combining the detection signal with address information of the selected memory cell to generate a control signal for enabling the high resistance path circuit and the bypass circuit of the write pulse control block.

15. The resistive-switching memory device according to claim 12, further comprising: a location storage block configured to classify the plurality of memory cells into a near cell group and a far cell group,

wherein the near cell group includes memory cells having a first error rate while being located near the control circuit block, an

The far cell group includes memory cells having a second error rate while being located far from the control circuit block, the second error rate being lower than the first error rate.

16. The resistive memory device according to claim 12, wherein the high-resistance path circuit includes a MOS transistor, and the MOS transistor of the high-resistance path circuit has a resistance higher than a resistance when the bypass circuit is selected and lower than a resistance when the bypass circuit is not selected.

17. The resistive-switching memory device according to claim 12, wherein the high-resistance path circuit includes a variable resistance, and the variable resistance is higher than a resistance when the bypass circuit is selected and lower than a resistance when the bypass circuit is not selected.

18. The resistive-switching memory device according to claim 12, wherein the high-resistance path circuit comprises a plurality of transistors connected in parallel, the plurality of transistors being selected in response to a plurality of current control signals.

19. The resistive-switching memory device according to claim 12, further comprising:

a global bit line connected to the plurality of bit lines; and

a voltage control circuit for providing a voltage to the global bit line,

wherein the voltage control circuit provides an initial voltage for maintaining conduction of the selected memory cell to the selected memory cell when the selected memory cell is not conducted, and provides a write voltage to the selected memory cell when the selected memory cell is conducted.

20. The resistive-switching memory device according to claim 12, further comprising:

a global word line connected to the plurality of word lines; and

a current control circuit for providing a current to the global word line,

wherein the current control circuit provides an initial current to the selected memory cell for maintaining conduction of the selected memory cell when the selected memory cell is not conducted, and provides a write current to the selected memory cell when the selected memory cell is conducted.

Technical Field

Various embodiments may generally relate to a nonvolatile memory device, and more particularly, to a resistive memory device for performing a memory operation according to a resistance change.

Background

Recently, next-generation memory devices for replacing DRAMs and flash memories have been studied. The next-generation memory device may include a resistive memory device. Resistive memory devices can include materials such as resistive switching materials that can be changed by an applied bias to switch to different resistance states. The resistive memory device may include a phase change ram (pcram), a magnetic ram (mram), a ferroelectric ram (feram), a resistive ram (reram), and the like.

The resistive memory device may include a memory cell array having a cross-point array structure. The cross-point array structure may be arranged between word lines and bit lines where access elements and memory cells may cross.

However, in a resistive memory device, particularly in a PCRAM, snapback (snapback) and overshoot may occur when a memory cell is turned on to generate a transient current due to characteristics of a resistive layer in the memory cell. Furthermore, after snapback or overshoot, a spike current may be generated when returning to normal write operation.

Transient currents, such as snapback currents, overshoot currents, and spike currents, may cause the memory cell to fail. In particular, a transient current may be generated in a cell group adjacent to a control circuit block for supplying a voltage and a current.

Disclosure of Invention

In an exemplary embodiment of the present disclosure, a resistive memory device may include a plurality of memory cells and a control circuit block. A plurality of memory cells may be connected between the global word line and the global bit line. The control circuit block may control a plurality of memory cells. The control circuit block may include a write pulse control block. The write pulse control block may include a high resistance path circuit and a bypass circuit connected between the global word line and the selected memory cell. The write pulse control block may selectively enable either one of the high resistance path circuit and the bypass circuit according to the location of the selected memory cell.

In an exemplary embodiment of the present disclosure, a resistive memory device may include a memory cell array and a control circuit block. The memory cell array may include a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged at intersections between the plurality of word lines and the plurality of bit lines. The control circuit block may be disposed at an edge portion of the memory cell array to control the plurality of memory cells. The control circuit block may include a detection circuit block and a write pulse control block. The detection circuit block may detect the conduction of the selected memory cell to generate a detection signal according to the detection result. The write pulse control block may selectively connect the high resistance path circuit and the bypass circuit to a word line that may be connected to the selected memory cell according to the detection signal and address information of the selected memory cell.

According to an example embodiment, when a memory cell in a cell group adjacent to the control circuit block is selected, the high resistance path circuit may be connected to the global word line or the selected word line after the turn-on of the memory cell. Therefore, during a return to a write operation after the memory cell is turned on, generation of a transient current can be reduced.

In addition, a voltage control circuit and a current control circuit may be installed at the global bit line and the global word line, respectively. Thus, before turning on a selected memory cell, a minimum voltage and a minimum current may be provided to the memory cell to turn on the memory cell. After the memory cell is turned on, a normal voltage and a normal current may be supplied to the memory cell. As a result, a snapback current and an overshoot current, which may be generated when the memory cell is turned on, may be reduced.

Drawings

The above and other aspects, features and advantages of the presently disclosed subject matter may be understood by the following detailed description in conjunction with the accompanying drawings, in which:

fig. 1 is a block diagram illustrating a resistance change memory system according to an exemplary embodiment.

Fig. 2 is a view illustrating a resistive memory device according to an exemplary embodiment.

Fig. 3 is a view illustrating a memory cell array of a resistive memory device according to an exemplary embodiment.

Fig. 4 is a circuit diagram illustrating a memory cell structure according to an exemplary embodiment.

Fig. 5 is a view showing a hierarchical structure of word lines and bit lines according to an exemplary embodiment.

Fig. 6 is a circuit diagram illustrating a write pulse control block according to an exemplary embodiment.

Fig. 7 to 9 are detailed circuit diagrams illustrating a write pulse control block according to an exemplary embodiment.

Fig. 10 is a graph illustrating an operation current under a write operation of a resistive memory device according to an exemplary embodiment.

Fig. 11 is a circuit diagram illustrating a control signal generation circuit according to an exemplary embodiment.

Fig. 12 is a circuit diagram illustrating an operation of a resistive memory device according to an exemplary embodiment.

Fig. 13 is a circuit diagram illustrating a resistive memory device according to an exemplary embodiment.

Detailed Description

Various embodiments of the present teachings are described in detail with reference to the drawings. The figures are schematic diagrams of various embodiments (and intermediate structures). As such, variations from the configurations and shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Accordingly, the described embodiments should not be construed as limited to the particular configurations and shapes shown herein but may include deviations in configurations and shapes that do not depart from the spirit and scope of the disclosure as defined in the appended claims.

The present disclosure is described herein with reference to cross-sectional and/or plan views of idealized embodiments. However, the embodiments of the present disclosure should not be construed as limiting the present disclosure. While a limited number of possible embodiments of the present disclosure have been shown and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention.

Fig. 1 is a block diagram illustrating a resistance change memory system according to an exemplary embodiment.

Referring to fig. 1, a semiconductor system 100 may include a processor 10, a controller 50, and a resistive memory device PCM.

The processor 10 may be connected to the controller 50 via a bus 15. The processor 10 may provide memory access requests (read requests, write requests, etc.) to the controller 50, including memory addresses and data.

The controller 50 may provide the resistive memory device PCM with a command CMD, an address ADD, DATA, and a control signal CTRL for operating the resistive memory device PCM. The controller 50 may include a position storage block 60. The position storage block 60 may store position information of memory cells in the memory cell array 110 of the resistive memory device PCM. For example, location storage block 60 may classify memory cells into memory cells in a near group of cells and memory cells in a far group of cells based on the addresses of the memory cells. Location storage block 60 may include registers. The resistive memory device PCM may include a memory cell array 110 and a control circuit block CB.

In an exemplary embodiment, the controller 50 may include a position storage block 60. Alternatively, the control circuit block CB of the resistive memory device PCM may include a position storage block 60.

Fig. 2 is a view illustrating a resistive memory device according to an exemplary embodiment, fig. 3 is a view illustrating a memory cell array of the resistive memory device according to an exemplary embodiment, and fig. 4 is a circuit diagram illustrating a memory cell structure according to an exemplary embodiment.

Referring to fig. 2, the resistive memory device PCM may include a memory cell array 110 for controlling an operation of the memory cell array 110 and a control circuit block CB.

Referring to fig. 2 and 3, the memory cell array 110 may include a plurality of word lines WL0 through WLn and a plurality of bit lines BL0 through BLm. The word lines WL0 WLn and the bit lines BL0 BLm may cross each other. The memory cells MC may be arranged at intersections between the word lines WL 0-WLn and the bit lines BL 0-BLm. This structure may be referred to as a cross-point array structure.

The memory cells MC of the memory cell array 110 may be classified into a near cell group NC and a far cell group FC according to a distance between the memory cells MC and the control circuit block CB. That is, the memory cells MC adjacent to the control circuit block CB may be defined as the near cell group NC. In contrast, the memory cells MC far from the control circuit block CB may be defined as a far cell group FC. The location information of the near cell group NC and the far cell group FC may be stored in the location storage block 60.

In an exemplary embodiment, the position storage block 60 may store memory cells MC (MC) near the control circuit block CB<WL0～WLa:BL0～BLm>And MC<WL0～WLn:BL0～BLb>) Classified as near cell group NC. Position storage block 60 may store memory cells MC (MC) spaced apart from control circuit block CB<WLa₊₁～WLn：BLb₊₁～BLm>) Classified as a far cell group FC. When the address of the selected memory cell is input into the position storage block 60, the position storage block 60 may determine whether the selected memory cell belongs to the near cell group NC or the far cell group FC. The location storage block 60 may then output the result of the determination as address information. For example, the position storage block 60 may include a Mode Register Set (MRS). The MRS may include address information for distinguishing the near cell group NC and the far cell group FC from each other.

Referring to fig. 4, a memory cell MC may include a selection element S and a variable resistor R connected between a word line WL and a bit line BL.

The selection element S may comprise a diode or a MOS transistor. The selection element S may comprise an Ovonic Threshold Switch (OTS) comprising a phase change storage layer.

The variable resistor R may include a memory layer. The variable resistor R may exhibit different resistance values by a voltage difference between the bit line BL and the word line WL. The variable resistor R may include a phase change layer or a resistance change layer. The phase change layer may include: mixtures of two elements, such as GaSb, InSb, InSe, Sb₂Te₃GeTe, and the like; ternary mixtures of elements, e.g. GeSbTe, GaSeTe, InSbTe, SnSb₂Te₄InSbGe, etc.; quaternary element mixtures, such as AgInSbTe, (GeSn) SbTe, GeSb (SeTe), Te₈₁Ge₁₅Sb₂S₂And the like.

The phase change layer may have an amorphous state with a relatively high resistance and a crystalline state with a relatively low resistance. The phase change layer may have a variable phase according to joule heat generated by the amount of current and a cooling time.

Each memory cell MC may include a single level cell for storing one bit of data. In this case, the memory cell MC may have two resistance distributions according to the stored data. In addition, each memory cell MC may be a multi-level cell for storing at least two bits of data. In this case, the memory cell MC may have four or eight resistance distributions according to the stored data.

Referring to fig. 2, the control circuit block CB may include a column switch block 120, a row switch block 150, a write pulse control block 160, control logic 200, and a detection circuit block 250.

Column switch block 120 may be electrically coupled between global bit line GBL and bit lines BL <0: m >. The column switch block 120 may select any one of the bit lines BL <0: m > in response to column selection signals GYB and/or LYB provided from the control logic 200. For example, the global bit line GBL may be connected to the bit line voltage terminal Va. The bit line voltage terminal Va may be a voltage source for supplying a write voltage or a read voltage.

Row switch block 150 may be electrically coupled between global word line GWL and word lines WL <0: n >. The row switch block 150 may select any one of the word lines WL <0: n > in response to a row selection signal GX and/or LX provided from the control logic 200. For example, the global word line GWL may be connected to a current source Iwrite for providing a write current. A current source Iwrite may be coupled to the word line voltage terminal Vb.

Although not shown in the drawings, the global bit line GBL and the global word line GWL may include a plurality of lines. Through the hierarchical structure, a plurality of local bit lines or local word lines may be electrically coupled to one global bit line or one global word line, respectively, and a plurality of bit lines or word lines may be connected to one local bit line or one local word line, respectively.

FIG. 5 is a diagram illustrating a hierarchy of word lines and bit lines in accordance with an illustrative embodiment.

Referring to fig. 5, in order to select any one of the bit lines BL arranged in a hierarchical shape, the column switch block 120 may include a global bit line switch GBS and a local bit line switch LBS connected between one global bit line GBL and one bit line BL. To select any one of the word lines WL arranged in a hierarchical shape, the row switch block 150 may include a global word line switch GWS and a local word line switch LWS connected between one global word line GWL and one word line WL.

The write pulse control block 160 may be electrically coupled between the global word line GWL and the memory cell array. Specifically, the write pulse control block 160 may be connected with the global word line GWL and the row switch block 150 to control the amount of current applied to the global word line GWL and the selected word line WL. For example, the write pulse control block 160 may select a transmission path of a write current from the global word line GWL to the selected word line WL based on an address of the selected memory cell and conduction of the selected memory cell. By operation of the write pulse control block 160, the write current can be passed to the selected word line through a high resistance path or bypass.

Fig. 6 is a circuit diagram illustrating a write pulse control block according to an exemplary embodiment, and fig. 7 to 9 are detailed circuit diagrams illustrating a write pulse control block according to an exemplary embodiment.

Referring to fig. 6, the write pulse control block 160 may include a high resistance path circuit HP and a bypass circuit BP. The high-resistance path circuit HP and the bypass circuit BP may be connected in parallel between the row switch block 150 and the global word line GWL.

Referring to fig. 7, the high-resistance path circuit HP may include a transistor having a high resistance, hereinafter referred to as a high-resistance transistor Tr. The high-resistance transistor Tr may be driven in response to the control signal AB. The high-resistance transistor Tr may include an NMOS transistor. The control signal AB for driving the high-resistance transistor Tr may include a VDD voltage or a VSS voltage. For example, when the VSS voltage may be used as the gate voltage AB of the high-resistance transistor Tr, the gate-source voltage Vgs of the high-resistance transistor Tr may be lower than the gate-source voltage of the high-resistance transistor Tr when the VDD voltage may be used as the gate voltage AB. Therefore, when the VSS voltage can be used as the gate voltage AB under the condition that the same resistance can be used, the size W/L (W: channel width, L: channel length) of the high-resistance transistor Tr can be reduced. In an exemplary embodiment, the high-resistance transistor Tr may include an NMOS transistor. Alternatively, the high-resistance transistor Tr may include a PMOS transistor. Here, the control signal AB may be a signal for inverting the control signal AB. For example, when the memory cells MC of the near cell group NC may be selected, the control signal AB may be enabled to a high level. The generation of the control signals a and AB will be described in detail later.

For example, when the memory cells of the near cell group NC may be selected and turned on, the control signal AB may be enabled to a high level, so that the high resistance path circuit HP may be connected between the global word line GWL and the row switch block 150. Accordingly, a write current applied to the global word line GWL may pass through the high-resistance path circuit HP to reduce the value of the write current.

When the memory cell of the near cell group NC may be selected while the memory cell is not turned on or the memory cell of the far cell group FC may be selected and turned on, the control signal AB may be enabled so that the bypass circuit BP may be connected between the global word line GWL and the row switch block 150. Therefore, the write current applied to the global word line GWL can be transmitted to the selected word line through the bypass circuit BP without reducing the write current.

In an exemplary embodiment, the high resistance path circuit HP may include an NMOS transistor. Alternatively, the high-resistance path circuit HP may include a variable resistance Rv, which is higher than the resistance of the bypass circuit BP, for providing a resistance path. For example, the variable resistance Rv may be higher than the resistance of the selected bypass circuit BP and lower than the resistance of the unselected bypass circuit BP. Further, in response to the control signal AB, the variable resistor Rv may provide a higher resistance value than the selected bypass circuit BP.

Referring to fig. 9, the high-resistance path circuit HP may include a plurality of transistors tr <0: n > connected in parallel with each other. For example, transistors tr <0: n > may be selectively driven in response to current control signals C <0: n >. The current control signals C <0: n > may be generated from the control logic 200 in fig. 2. The resistance of the high resistance path circuit HP can be controlled by the amount by which the transistors tr <0: n > are turned on. That is, the high resistance path circuit HP may have a relatively low resistance when most of the transistors tr <0: n > may be turned on. Conversely, when the minority transistor tr <0: n > may be turned on, the high-resistance path circuit HP may have a relatively high resistance.

The bypass circuit BP may include a transmission gate T including an NMOS transistor and a PMOS transistor. The resistances of the NMOS and PMOS transistors of the bypass circuit BP may be much lower than the resistance of the high-resistance path circuit HP. The NMOS transistor of the bypass circuit BP may be driven in response to the control signal a. The PMOS transistor of the bypass circuit BP may be driven in response to the control signal AB.

Referring to fig. 2, the sensing circuit block 250 may sense a current flowing through a selected memory cell MC. In addition, the detection circuit block 250 may generate the detection signal D when the selected memory cell MC may be turned on. Detection circuit block 250 may then provide detection signal D to control logic 200.

Fig. 10 is a graph illustrating an operation current under a write operation of a resistive memory device according to an exemplary embodiment.

Referring to fig. 10, when a memory cell of the conventional resistive memory device can be selected by initiating a write operation, a current lower than a write current can flow through the selected memory cell. When a voltage difference of not less than a threshold voltage may be generated between a selected word line and a selected bit line, a storage layer of the variable resistance may be charged so that a large amount of write current may flow through the selected memory cell. In contrast, the detection circuit block 250 of the exemplary embodiment may be connected to the global word line GWL. The detection circuit block 250 may detect the turn-on point of the memory cell MC using the current amount of the selected memory cell MC. In an exemplary embodiment, the detection circuit block 250 may include a sense amplifier.

Control logic 200 may include a control signal generation circuit 210 for generating control signals a and AB.

Fig. 11 is a circuit diagram illustrating a control signal generation circuit according to an exemplary embodiment.

Referring to fig. 11, the control signal generation circuit 210 may receive the detection signal D and address information ADD _ info supplied from the position storage block 60 of the controller 50 to generate the first control signal a and the second control signal AB. For example, when the selected memory cell MC corresponds to the near cell group NC, the address information ADD _ info may be a signal of a high level. In contrast, when the selected memory cell MC corresponds to the far cell group FC, the address information ADD _ info may be a signal of a low level.

For example, the detection signal D may be enabled to a high level when the selected memory cell MC is turned on. When the selected memory cell MC corresponds to the near cell group NC, the control signal generation circuit 210 may generate the first control signal a having a low level and the second control signal AB having a high level to enable the high resistance path circuit HP in the write pulse control block 160.

In contrast, when the selected memory cell MC of the far cell group FC is turned on and the detection signal D is enabled to a high level or the selected memory cell MC is not turned on, the control signal generation circuit 210 may generate the first control signal a having a high level and the second control signal AB having a low level to enable the bypass circuit BP in the write pulse control block 160.

Specifically, as shown In fig. 11, the control signal generation circuit 210 may include a first inverter In1, a nand gate ND, and a second inverter In 2.

The nand gate ND may receive the detection signal D and the address information ADD _ info inverted by the first inverter In1 to output the first control signal a. The second inverter In2 may receive the first control signal a. The second inverter In2 may then invert the first control signal a to output the second control signal AB.

In an exemplary embodiment, the control signal generation circuit 210 may include an inverter and a nand gate. Alternatively, the control signal generation circuit 210 may include various logic circuits.

Further, although not shown in the drawings, the control logic 200 may include various circuits and a control signal generation circuit 210 to generate column selection signals GYB and LYB, row selection signals GX and LX, current control signals C <0: n >, and various control signals.

Fig. 12 is a circuit diagram illustrating an operation of a resistive memory device according to an exemplary embodiment.

Referring to fig. 12, when a write operation is initiated, a write current may be applied to a global bit line GBL electrically connected to a selected memory cell. In addition, a word line voltage and a write current may also be applied to the selected global word line GWL.

The control logic 200 may output column selection signals GYB and LYB and row selection signals GX and LX to the column switch block 120 and the row switch block 150, respectively, based on an address ADD supplied from the controller 50.

When the global bit line switch GYT and the local bit line switch LYT of the column switch block 120 are turned on in response to the column selection signals GYB and LYB, the write voltage Va applied to the global bit line GBL may be transmitted to the selected bit line BL.

When the global word line switch GXT and the local word line switch LXT of the row switch block 150 are turned on in response to the row selection signals GX and LX, a word line voltage applied to the global word line GWL may be transmitted to the selected word line WL.

The memory layer R in the variable resistance of the memory cell MC may not be charged because a sufficient voltage difference may not be generated between the word line WL and the bit line BL at the start of the write operation. Accordingly, a current lower than the set write current may flow through the global word line GWL, so that the detection circuit block 250 may output the disabled detection signal D to the control signal generation circuit 210. Accordingly, the control signal generation circuit 210 may output the first control signal a and the second control signal AB to enable the bypass circuit BP of the write pulse control block 160.

When a sufficient voltage difference is generated between the word line WL and the bit line BL after a certain time, the memory cell MC may be turned on. The current amount of the global word line GWL may be significantly increased so that the detection circuit block 250 may provide the enabled detection signal D to the control signal generation circuit 210. When the turned-on memory cell MC may correspond to the near cell group NC, the control signal generation circuit 210 may output the first control signal a and the second control signal AB to enable the high resistance path circuit HP of the write pulse control block 160. In contrast, when the memory cells MC that are turned on may correspond to the far cell group FC, the control signal generation circuit 210 may output the first control signal a and the second control signal AB to enable the bypass circuit BP of the write pulse control block 160.

For example, when the high-resistance path circuit HP may be connected in the write pulse control block 160 after the memory cell MC is turned on, a spike current that may be more seriously generated in the near cell group NC may pass through the high-resistance path circuit HP to reduce the spike current. Therefore, after the memory cell MC is turned on, a stable write current can be supplied to the memory cell MC. As a result, a disturbance error of the memory cell caused by a spike current in the write current can be prevented.

When the bypass circuit BP may be connected in the write pulse control block 160, the write current applied to the global word line GWL may be supplied to the turned-on memory cell MC without loss of the write current.

In general, in order to prevent disturbance to the memory cells in the near cell group, a technique of controlling the driving force of the local word line switch LXT of the local switch block may be used. However, in order to control the driving force of the local word line switch LXT, various row selection voltage sources (local word line voltages) and various row selection voltage lines may be required. Therefore, it can be very difficult to apply the techniques to small memory cell arrays.

However, according to an exemplary embodiment, the write pulse control block 160 having a simple switching structure may be connected with the global word line GWL to control a spike current of the near cell group NC, so that the resistive memory device may have an advantageous layout.

Fig. 13 is a circuit diagram illustrating a resistive memory device according to an exemplary embodiment.

Referring to fig. 13, the resistive memory device PCMa of this exemplary embodiment may include substantially the same elements as the resistive memory device PCM of fig. 2 except for further including a voltage control circuit 130 and a current control circuit 170. Accordingly, like reference numerals may refer to like elements, and any further explanation regarding the like elements may be omitted herein for the sake of brevity.

The voltage control circuit 130 may be connected with the global bit line GBL to supply a voltage. Before turning on the memory cell MC, the voltage control circuit 130 may transmit the initial voltage VL to the global bit line GBL. After turning on the memory cell MC, the voltage control circuit 130 may transmit the write voltage Vwrite to the global bit line GBL. The initial voltage VL may have a minimum level for maintaining the conduction of the memory cell MC. The voltage control circuit 130 may include a voltage supply circuit 130a and a voltage selection circuit 130 b.

The voltage supply circuit 130a may include a first switch P1 and a second switch P2. The first switch P1 may provide the initial voltage VL to the voltage selection circuit 130b in response to the first driving signal ENPL. The second switch P2 may provide the write voltage Vwrite to the voltage selection circuit 130b in response to the second drive signal ENPH. The first and second driving signals ENPL and ENPH may be generated from the control logic 200. For example, the first driving signal ENPL may be a signal that is enabled before the detection signal D is generated. The second driving signal ENPH may be a signal that is enabled after the detection signal D is generated. For example, when the first and second switches P1 and P2 may include PMOS transistors, the first and second driving signals ENPL and ENPH may be enabled to a low level.

To apply the initial voltage VL to the global bit line GBL before generating the detection signal D, the voltage selection circuit 130b may electrically connect the global bit line GBL with the first switch P1. In order to apply the write voltage Vwrite to the global bit line GBL after generating the detection signal D, the voltage selection circuit 130b may electrically connect the global bit line GBL with the second switch P2. For example, the voltage selection circuit 130b may include a PMOS transistor PM1 driven in response to the detection signal D and an NMOS transistor NM1 driven in response to the detection signal D. When the detection signal D may be disabled, the PMOS transistor PM1 may electrically connect the first switch P1 with the global bit line GBL. When the detection signal D may be enabled, the NMOS transistor NM1 may electrically connect the second switch P2 with the global bit line GBL. In an exemplary embodiment, the voltage selection circuit 130b may include a PMOS transistor PM1 and an NMOS transistor NM 1. Alternatively, the voltage selection circuit 130b may include various selection circuits.

Current control circuit 170 may be connected to global word line GWL to provide current. Current control circuit 170 may be connected between global word line GWL and word line voltage terminal Vb. The current control circuit 170 may provide the initial current Isel according to the initial voltage before turning on the memory cell MC. After turning on the memory cell MC, the current control circuit 170 may provide a write current Iwrite according to the write voltage.

The current control circuit 170 may include a current supply circuit 170a and a current selection circuit 170 b. The current supply circuit 170a may include an initial current source Isel and a write current source Iwrite connected to the word line voltage terminal Vb. For example, the initial current source Isel may provide an initial current corresponding to the initial voltage VL. The write current source Iwrite may provide a write current corresponding to the write voltage Vwrite.

The current selection circuit 170b may include a PMOS transistor PM2 driven in response to the detection signal D and an NMOS transistor NM2 driven in response to the detection signal D. The PMOS transistor PM2 may electrically connect the initial current source Isel to the write pulse control block 160 when the detection signal D may be disabled to a low level. When the detection signal D may be enabled to a high level, the NMOS transistor NM2 may electrically connect the write current source Iwrite with the write pulse control block 160. In an exemplary embodiment, the current selection circuit 170b may include a PMOS transistor PM2 and an NMOS transistor NM 2. Alternatively, the current selection circuit 170b may include various selection circuits.

When the memory cell MC can be selected, and before the selected memory cell MC is turned on, the minimum voltage VL and the minimum current Isel can be applied to the selected memory cell MC by driving the voltage control circuit 130 and the current control circuit 170 to maintain the turning on of the memory cell MC. Therefore, since the voltage and current applied to the memory cell MC at the start of selection may be small, the snapback current (voltage) and the overshoot current (voltage) generated simultaneously with the conduction of the selected memory cell MC may also be reduced. Therefore, the influence of the snapback current (voltage) and the overshoot current (voltage) on the memory cell can be significantly reduced. When the detection signal D can be detected after the memory cell MC is turned on, the voltage control circuit 130 and the current control circuit 170 may supply the write voltage Vwrite and the write current Iwrite to the memory cell so that the memory cell MC may perform a normal write operation.

According to an exemplary embodiment, when memory cells adjacent to the control circuit block in the near cell group may be selected, the high resistance path may be connected to the global word line or the selected word line after the memory cells are turned on. Therefore, during the return to the write operation after the memory cell is turned on, generation of a transient current can be reduced.

In addition, a voltage control circuit and a current control circuit may be installed at the global bit line and the global word line, respectively. Therefore, before the memory cell is turned on, a minimum voltage and a minimum current for maintaining the turning on of the memory cell may be supplied to the memory cell. After the memory cell is turned on, a normal write voltage and current may be supplied to the memory cell. As a result, the influence of the snapback current and the overshoot current generated at the time of the turn-on of the memory cell can be reduced.

The above-described embodiments of the present disclosure are intended to be illustrative, but not limiting, of the present disclosure. Various alternatives and equivalents are possible. The present disclosure is not limited to the embodiments described herein. The present disclosure is also not limited to any particular type of semiconductor device. Other additions, subtractions or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.