阅读说明：本技术 碳化硅半导体装置 (Silicon carbide semiconductor device ) 是由 荒冈干 于 2020-02-21 设计创作，主要内容包括：本发明提供能够防止绝缘破坏的碳化硅半导体装置。栅极多晶硅层的第一部分在边缘终端区隔着栅极绝缘膜设置在半导体基板的正面的第一表面上,构成栅极流道。栅极多晶硅层的第一部分沿深度方向Z与边缘p<Sup>++</Sup>型接触区对置。栅极多晶硅层的第一部分的芯片端部侧的端部位于边缘p<Sup>++</Sup>型接触区的面内。场氧化膜从芯片端部向芯片中央侧延伸,并在半导体基板的正面的第一表面上终止于比栅极多晶硅层的第一部分更靠芯片端部侧的位置,与栅极多晶硅层分离地配置。因此,在栅极多晶硅层的表面不产生因场氧化膜而引起的阶梯,遍及栅极多晶硅层的整个表面是平坦的。场氧化膜的芯片中央侧的端部位于比边缘p<Sup>++</Sup>型接触区更靠芯片端部侧的位置,位于p型基区上。(The invention provides a silicon carbide semiconductor device capable of preventing insulation breakdown. A first portion of the gate polysilicon layer is provided on a first surface of the front surface of the semiconductor substrate via a gate insulating film in the edge termination region, constituting a gate runner. First of gate polysilicon layerA part along the depth direction Z and the edge p ++ The contact regions are opposed. The end of the first part of the gate polysilicon layer on the chip end side is located at the edge p ++ In-plane of the land region. The field oxide film extends from the chip end portion toward the chip center side, and is disposed on the first surface of the front surface of the semiconductor substrate so as to terminate at a position closer to the chip end portion side than the first portion of the gate polysilicon layer, and is separated from the gate polysilicon layer. Therefore, a step due to the field oxide film is not generated on the surface of the gate polysilicon layer, and the entire surface of the gate polysilicon layer is flat. The end of the field oxide film on the chip center side is located at the edge p ++ The type contact region is located on the p-type base region further toward the chip end portion side.)

1. A silicon carbide semiconductor device is characterized by comprising:

an insulated gate structure which is provided on the front surface side of a semiconductor substrate made of silicon carbide in an active region and has a three-layer structure of a metal-oxide film-semiconductor of an insulated gate bipolar transistor;

a first conductivity type semiconductor layer constituting the semiconductor substrate and constituting a drift region of the insulated gate bipolar transistor;

a second conductivity type semiconductor layer provided between the front surface of the semiconductor substrate and the first conductivity type semiconductor layer, constituting the semiconductor substrate, and constituting a base region of the insulated gate bipolar transistor;

a trench provided on a front surface side of the semiconductor substrate and extending in a first direction parallel to the front surface of the semiconductor substrate;

a gate electrode of the insulated gate bipolar transistor, which is provided inside the trench with an insulating film interposed therebetween;

a second-conductivity-type high-concentration region having an impurity concentration higher than that of the second-conductivity-type semiconductor layer, provided in a surface region of the front surface of the semiconductor substrate in a termination region surrounding the periphery of the active region, and forming a second-conductivity-type junction having an impurity concentration different from that of the second-conductivity-type semiconductor layer;

a first gate polysilicon layer provided on the front surface of the semiconductor substrate with the insulating film interposed therebetween, facing the second conductivity type high concentration region with the insulating film interposed therebetween in the depth direction, surrounding the periphery of the active region in a rectangular shape, and electrically connected to the gate electrode at an end of the trench; and

a field oxide film provided on the front surface of the semiconductor substrate via the insulating film in the termination region, extending from the outside to the inside, and surrounding the periphery of the first gate polysilicon layer in a rectangular shape,

the field oxide film has four sides, at least a portion parallel to a second direction terminating at a position further to the outside than the first gate polysilicon layer, the second direction being orthogonal to the first direction.

2. The silicon carbide semiconductor device according to claim 1,

the field oxide film extends inward in the second direction along at least one of two sides parallel to the first direction to the same position as the end of the inner side of the first gate polysilicon layer.

3. The silicon carbide semiconductor device according to claim 2,

the part of the field oxide film parallel to the first direction extends to the inner side in the second direction to the same position as the end part of the inner side of the first gate polysilicon layer.

4. The silicon carbide semiconductor device according to any one of claims 1 to 3,

the second conductivity type high concentration region terminates at a position further inside than the second conductivity type semiconductor layer,

at least an inner end of a portion of the field oxide film parallel to the second direction faces the second conductive type semiconductor layer through the insulating film in a depth direction at a position outside the second conductive type junction.

5. The silicon carbide semiconductor device according to any one of claims 1 to 4,

an end portion of an outer side of the first gate polysilicon layer is located within a plane of the second conductivity type high concentration region.

6. The silicon carbide semiconductor device according to any one of claims 1 to 5,

the silicon carbide semiconductor device is flat throughout the entire surface of the first gate polysilicon layer.

7. The silicon carbide semiconductor device according to any one of claims 1 to 6,

the silicon carbide semiconductor device further includes:

a second gate polysilicon layer provided on the front surface of the semiconductor substrate via the insulating film in the active region and connected to the first gate polysilicon layer; and

a gate pad provided on the second gate polysilicon layer with an interlayer insulating film therebetween and electrically connected to the second gate polysilicon layer,

the field oxide film is not disposed between the front surface of the semiconductor substrate and the second gate polysilicon layer.

8. The silicon carbide semiconductor device according to any one of claims 1 to 7,

the insulating film is a high-temperature oxide film or a thermal oxide film,

the field oxide film is a silicon oxide film,

the thickness of the field oxide film is thicker than that of the insulating film.

Technical Field

The present invention relates to a silicon carbide semiconductor device.

Background

Conventionally, a trench Gate type SiC-MOSFET (Metal Oxide semiconductor Field Effect Transistor) having an insulated Gate formed of a three-layer structure of Metal-Oxide film-semiconductor, in which silicon carbide (SiC) is used as a semiconductor material, has a structure in which a Gate polysilicon (poly-Si) layer forming a Gate runner extends over a Field Oxide film (Field Oxide) directly below a Gate Metal (Gate Metal) layer in an edge termination region. The structure of the edge termination region of a conventional semiconductor device will be described.

Fig. 13 is a plan view showing a layout of a conventional silicon carbide semiconductor device as viewed from the front surface side of the semiconductor substrate. Fig. 14 is an enlarged plan view of the rectangular frame AA of fig. 13. The rectangular frame AA in fig. 13 has a pair of diagonal vertices, which are a vertex AA1 on the corner side of the semiconductor substrate 150 and a vertex AA2 on the center side of the semiconductor substrate 150. The portion surrounded by the rectangular frame AA is a part of the edge termination region 102 of the semiconductor substrate (semiconductor chip) 150. Fig. 15 is a sectional view showing a sectional structure at a cutting line BB-BB' of fig. 14. Fig. 16 is a sectional view showing a sectional structure at a cutting line CC-CC of fig. 13.

The conventional silicon carbide semiconductor device 110 shown in fig. 13 to 16 is a vertical MOSFET having a trench gate structure in which a gate metal layer 113 and a gate polysilicon layer 114 are provided in an edge termination region 102 surrounding the active region 101. In the active region 101, portions constituting a MOS gate structure are provided on the front surface side of the semiconductor substrate 150. In the active region 101, a source pad 111 and a gate pad 112 are provided separately from each other on a first surface 153a of the front surface of the semiconductor substrate 150, which will be described later. The source pad 111 has a substantially rectangular planar shape with a portion recessed inward.

Source pad 111 occupies a large half of the surface area of active region 101 and extends from active region 101 to edge termination region 102. In fig. 13, an outer periphery 111a of the source pad 111 is indicated by a broken line thinner than a field oxide film 121 described later. Gate pad 112 is disposed in a recess of source pad 111, and has a substantially rectangular planar shape surrounded on three sides by source pad 111. In the edge termination region 102, on the front surface of the semiconductor substrate 150, a gate insulating film 137 extends from the inner wall of the trench 136 constituting the MOS gate structure in the active region 101.

A field oxide film 121 is provided on a gate insulating film 137 on a second surface 153b, which will be described later, of the front surface of the semiconductor substrate 150. The field oxide film 121 extends from an end portion (hereinafter, referred to as a chip end portion) of the semiconductor substrate 150 toward the active region 101 side (hereinafter, referred to as a chip center side), and terminates in the edge termination region 102 on the first surface 153a of the front surface of the semiconductor substrate 150. The field oxide film 121 is disposed on the first surface 153a of the front surface of the semiconductor substrate 150, directly below the gate metal layer 113, directly below the gate pad 112, and directly below a metal layer (hereinafter, referred to as a gate connection metal layer) 113a connecting the gate pad 112 and the gate metal layer 113.

The gate polysilicon layer 114 is provided on the gate insulating film 137 on the front surface of the semiconductor substrate 150 on the chip center side of the field oxide film 121. The gate polysilicon layer 114 extends from above the gate insulating film 137 onto the field oxide film 121 along the chip end portion side, is disposed directly below the gate metal layer 113, directly below the gate pad 112, and directly below the gate link metal layer 113a, and terminates within the plane of the first surface 153a of the front surface of the semiconductor substrate 150. A first portion 114a of the gate polysilicon layer 114 directly below the gate metal layer 113 is a gate runner connected to the gate electrode 138 at an end of the trench 136.

A first portion 114a of the gate polysilicon layer 114 surrounds the periphery of the active region 101. An end portion 114a 'of the first portion 114a of the gate polysilicon layer 114 on the chip center side is located further on the chip center side than an end portion 121 a' of the first portion 121a of the field oxide film 121 on the chip center side directly below the gate metal layer 113. An end portion 114b 'of the second portion 114b of the gate polysilicon layer 114 directly under the gate pad 112 is terminated at a position farther from the gate pad 112 than an end portion 121 b' of the second portion 121b of the field oxide film 121 directly under the gate pad 112.

An end 114c 'of the third portion 114c of the gate polysilicon layer 114 directly under the gate link metal layer 113a is terminated at a position farther from the gate pad 112 than an end 121 c' of the third portion 121c of the field oxide film 121 directly under the gate link metal layer 113 a. The trenches 136 are arranged in a stripe shape in the active region 101 along a first direction X parallel to the front surface of the semiconductor substrate 150 and extend from the active region 101 to the edge termination region 102. An end portion of the trench 136 is opposed to the end portion 114 a' of the first portion 114a of the gate polysilicon layer 114 on the chip center side in the depth direction Z.

A gate electrode 138 is provided in the trench 136 via a gate insulating film 137. In fig. 13, an end 114a ' of the first portion 114a of the gate polysilicon layer 114 on the chip center side, an end of the first portion 114a on the chip end side, and ends 114b ' and 114c ' of the second and third portions 114b and 114c are indicated by thick solid lines. An end portion on the chip end portion side of the first portion 121a of the field oxide film 121 is located at the chip end portion. In fig. 13, an end portion 121a ' of the first portion 121a of the field oxide film 121 on the chip center side and end portions 121b ', 121c ' of the second and third portions 121b, 121c of the field oxide film 121 are indicated by a thicker dotted line than the outer periphery 111a of the source pad 111.

On the first portion 114a of the gate polysilicon layer 114, a gate metal layer 113 is provided on the interlayer insulating film 122. The gate metal layer 113 surrounds the periphery of the active region 101. The gate metal layer 113 is electrically connected to the first portion 114a of the gate polysilicon layer 114 through the contact hole 122a of the interlayer insulating film 122, and is electrically connected to the gate pad 112 through the gate link metal layer 113 a. The portion directly below the gate metal layer 113 has a three-layer structure in which the gate insulating film 137, the first portion 121a of the field oxide film 121, and the first portion 114a of the gate polysilicon layer 114 are sequentially stacked on the front surface of the semiconductor substrate 150.

Also, the end portion 114a 'of the first portion 114a of the gate polysilicon layer 114 extends further toward the chip center side than the end portion 121 a' of the first portion 121a of the field oxide film 121 toward the chip center side. Therefore, in the three-layer structure, a portion adjacent to the chip center side has a two-layer structure in which only the gate insulating film 137 and the first portion 114a of the gate polysilicon layer 114 are sequentially stacked on the front surface of the semiconductor substrate 150. Between the portion on the field oxide film 121 and the portion on the gate insulating film 137, a step 115 corresponding to the thickness of the field oxide film 121 is generated in the first portion 114a of the gate polysilicon layer 114.

The surface of the first portion 114a of the gate polysilicon layer 114 is recessed toward the semiconductor substrate 150 at a portion closer to the chip center side than the first portion 121a of the field oxide film 121 by the step 115. Similarly to the surface of the first portion 114a of the gate polysilicon layer 114, the surfaces of the second portion 114b and the third portion 114c of the gate polysilicon layer 114 also form a step 115 corresponding to the thickness of the field oxide film 121 between the portion on the field oxide film 121 and the portion on the gate insulating film 137. The gate polysilicon layer 114 and the field oxide film 121 are covered with an interlayer insulating film 122.

The gate polysilicon layer 114 is in contact with and electrically connected to the gate metal layer 113 via the contact hole 122a of the interlayer insulating film 122. In fig. 14 and 15, reference numeral 141 denotes the gate metal layer 113, and shows a portion from an end portion of the gate metal layer 113 on the chip end portion side to an end portion on the chip center side. Reference numeral 142 denotes a contact hole 122a of the interlayer insulating film 122. A contact portion between the gate metal layer 113 and the gate polysilicon layer 114 is formed in the contact hole 122 a. Symbol 143 is a portion between the gate metal layer 113 and the source pad 111.

The boundary between the symbol 143 and the symbol 144 is the end position of the source pad 111. The boundary between the symbol 144 and the symbol 145 is the end 121 a' position on the chip center side of the first portion 121a of the field oxide film 121. Reference numeral 145 denotes a portion having a structure in which a gate insulating film 137 and a gate polysilicon layer 114 are sequentially stacked on the front surface of the semiconductor substrate 150. Reference numeral 146 denotes a portion from the end 114 a' of the first portion 114a of the gate polysilicon layer 114 on the chip center side to the end of the interlayer insulating film 122 covering the first portion 114a of the gate polysilicon layer 114 on the chip center side.

The semiconductor substrate 150 is at n⁺On a type starting substrate (not shown) so that n is^-And an epitaxial substrate in which the type semiconductor layer 151 and the p-type semiconductor layer 152 are sequentially epitaxially grown. n is^-N is formed by the type semiconductor layer 151^-A drift region 131. The p-type semiconductor layer 152 is etched away at the end of the chip to leave a mesa (mesa) shape in the center of the chip. By removing a portion of the p-type semiconductor layer 152 on the chip end side, a step 153 is formed on the front surface of the semiconductor substrate 150 in the edge termination region 102. The side surface of the p-type semiconductor layer 152 remaining in a mesa shape is exposed at the mesa edge 153c of the step 153.

The front surface of the semiconductor substrate 150 is recessed toward the drain electrode (not shown) on the second surface 153b closer to the chip end portion side than the first surface 153a on the chip center side, with the step 153 as a boundary. The p-type semiconductor layer 152 constitutes the p-type base region 132. That is, the p-type base region 132 extends from the active region 101 to the mesa edge 153c of the step 153 of the edge termination region 102. The land 153c of the step 153 is a surface connecting the first surface 153a on the chip center side of the step 153 and the second surface 153b of the recess on the chip end side of the step 153 on the front surface of the semiconductor substrate 150.

In the edge termination region 102 of the p-type semiconductor layer 152 (p-type base region 132), p-type ohmic contact with the source electrode 139 is made in the contact hole 122b of the interlayer insulating film 122⁺⁺Type contact region 135 (hereinafter, referred to as edge p)⁺⁺Type contact regions 135') extend from the active region 101. Edge p⁺⁺The type contact region 135' extends further to the chip end side than the first portion 114a of the gate polysilicon layer 114, and terminates further to the chip center side than the land 153c of the step 153. Edge p⁺⁺The type contact region 135' also extends directly under the gate pad 112.

From the edge 153c to the edge p of the step 153⁺⁺The distance d101 to the pattern contact region 135' is 15 μm. Chip end side end and edge p of first portion 114a of gate polysilicon layer 114⁺⁺The distance d102 between the chip end side ends of the type contact regions 135' is 2 μm. From the end of the first portion 114a of the gate polysilicon layer 114 on the chip end side to the chip center of the first portion 121a of the field oxide film 121The distance d103 from the side end 121 a' is 73 μm. The distance d104 from the gate metal layer 113 to the source pad 111 was 10 μm. The width d105 of the gate metal layer 113 is 36 μm.

At n^-A surface region of the semiconductor layer 151, which forms a portion of the second surface 153b of the front surface of the semiconductor substrate 150, is selectively formed with p by ion implantation^-A type region 163. p is a radical of^-The region 163 is electrically connected to the source electrode 139, and constitutes a voltage-resistant structure such as a Junction Termination Extension (JTE) structure. p is a radical of^-The type region 163 surrounds the active region 101. At p^-P regions adjacent to each other and facing each other in the depth direction Z are provided between the type region 163 and the active region 101 at positions closer to the drain electrode than the p-type base region 132⁺ Regions 162a ', 162 b'.

p⁺Type regions 162 a' and p^-Type region 163 and p⁺The pattern region 162 b' contacts. p is a radical of⁺ Type regions 162 b' and p^-Type region 163 is in contact with p-type base region 132. p is a radical of⁺The type regions 162a ', 162 b' surround the periphery of the active region 101. p is a radical of⁺The type regions 162a ', 162 b' extend directly below the gate pad 112. p is a radical of⁺ Type regions 162a ', 162 b' and p of active region 101⁺The type regions 162a, 162b are formed simultaneously. P of active region 101⁺The pattern regions 161, 162a, 162b have the following functions: depletion at turn-off of the MOSFET relaxes the electric field applied to the bottom surface of the trench 136.

A plurality of p-type base regions 132 are provided at positions closer to the drain electrode than the p-type base regions 132, and are separated from the p-type base regions 132⁺The pattern section 161. p is a radical of⁺The land 161 is opposed to the bottom surface of the groove 136 in the depth direction Z. Between the trenches 136 adjacent to each other, with the trenches 136 and p⁺The pattern region 161 is separately provided with p⁺Regions 162a, 162 b. p is a radical of⁺The type region 162a is provided at a position closer to the drain electrode than the p-type base region 132, separately from the p-type base region 132. p is a radical of⁺ Type region 162b is disposed between p-type base region 132 and p⁺Between type region 162a and with p-type base regions 132 and p⁺The type region 162a contacts.

In the contact hole 122b of the interlayer insulating film 122, the source electrode 139 and n⁺Source region 134 and p⁺⁺The type contact region 135 makes ohmic contact. The source electrode 139 is connected to the source pad 111 in the contact hole 122b of the interlayer insulating film 122. N is provided on the back surface side of the semiconductor substrate 150⁺A drain region and a drain electrode. Symbol 123 denotes a passivation protective film. Symbol 133 is set at n^-Inside the type drift region 131, a so-called Current Spreading Layer (CSL) is an n-type region that reduces the carrier expansion resistance.

As such a conventional SiC-MOSFET, there has been proposed a device in which a gate polysilicon layer is provided on a gate insulating film between a gate metal layer in an edge termination region and the gate insulating film extending from an active region to a position directly below the gate metal layer on a front surface of a semiconductor substrate (see, for example, patent documents 1 to 3 below). In patent document 1, a p-type region for extracting charges (holes) is arranged at a corner (a vertex of a rectangle) of an active region, and thus an electric field due to charges generated in an edge termination region is not applied to a field oxide film between the p-type base region and a gate runner, thereby preventing dielectric breakdown of the field oxide film.

In patent document 2, a p-type resurf region is disposed between the active region and the dielectric structure of the edge termination region so as to face the terrace edge of the step in the depth direction, whereby a portion where electric field concentration does not occur between the active region and the dielectric structure is formed, and dielectric breakdown is suppressed. In patent document 3, the thickness of the portion of the interlayer insulating film above the active region is made thinner than the thickness of the portion of the interlayer insulating film above the edge termination region, and the thickness of the portion of the interlayer insulating film above the edge termination region is designed to be a thickness that does not affect the electric field distribution in the edge termination region, thereby flattening the source pad and preventing variation in the withstand voltage characteristics and defective withstand voltage due to the variation.

Disclosure of Invention

Technical problem

However, in the reliability test in which the conventional silicon carbide semiconductor device 110 (see fig. 13 to 16) applied a voltage of 1200V between the drain and the source at a high temperature (for example, about 175 ℃) and applied a voltage so that the gate and the source are negatively biased, it was confirmed that the semiconductor device was broken at a measurement time of about 500 hours or more with respect to 1000 hours, which is a target measurement time. Therefore, the silicon carbide semiconductor device 110 causing the excessive destruction was subjected to cross-sectional analysis based on luminescence analysis using an Emission Microscope (EMS).

As a result of cross-sectional analysis based on the luminescence analysis, in a portion 145 having a double-layer structure in which the gate insulating film 137 and the gate polysilicon layer 114 were sequentially stacked on the front surface of the semiconductor substrate 150, the end portion 121a ' of the first portion 121a of the field oxide film 121 on the chip center side, and the second portion 121b of the field oxide film 121, and the end portions 121b ', 121c ' of the third portion 121c were adjacent to the chip center side, luminescence 170 indicating that a leakage current occurred was observed, and it was confirmed that the gate insulating film 137 was damaged in the portion of the luminescence 170 (fig. 14 and 15).

The reason why the breakdown is caused in the portion 145 of the double-layer structure is presumably because, when a voltage is applied under the predetermined condition, an electric field is concentrated in the end portion 114a ' of the gate polysilicon layer 114 on the chip center side of the first portion 114a, and the end portions 114b ', 114c ' of the second portion 114b and the third portion 114 c. At turn-off, is generated in the edge termination region 102 and passes through the edge p⁺⁺A part of the hole current drawn from type contact region 135' to source electrode 139 becomes a leakage current, and is injected into gate insulating film 137 at the electric field concentration portion, causing dielectric breakdown.

In order to solve the above-described problems of the prior art, an object of the present invention is to provide a silicon carbide semiconductor device capable of preventing dielectric breakdown.

Technical scheme

In order to solve the above problems and achieve the object of the present invention, a silicon carbide semiconductor device of the present invention has the following features. In the active region, an insulated gate structure having a three-layer structure of a metal-oxide film-semiconductor of an insulated gate bipolar transistor is provided on the front surface side of a semiconductor substrate made of silicon carbide. The first conductivity type semiconductor layer constitutes the semiconductor substrate, and constitutes a drift region of the insulated gate bipolar transistor. The second conductivity type semiconductor layer is provided between the front surface of the semiconductor substrate and the first conductivity type semiconductor layer to constitute the semiconductor substrate, and to constitute a base region of the insulated gate bipolar transistor.

The trench is provided on a front surface side of the semiconductor substrate, and extends in a first direction parallel to the front surface of the semiconductor substrate. A gate electrode of the insulated gate bipolar transistor is provided inside the trench with an insulating film interposed therebetween. In the termination region surrounding the periphery of the active region, a second conductivity type high concentration region having an impurity concentration higher than that of the second conductivity type semiconductor layer is provided in a surface region of the front surface of the semiconductor substrate. The second conductive type high concentration region forms a second conductive type junction having an impurity concentration different from that of the second conductive type semiconductor layer. A first gate polysilicon layer is provided on the front surface of the semiconductor substrate with the insulating film interposed therebetween.

The first gate polysilicon layer is opposed to the second conductivity type high concentration region with the insulating film interposed therebetween in the depth direction, and surrounds the periphery of the active region in a rectangular shape. The first gate polysilicon layer is electrically connected to the gate electrode at an end of the trench. In the termination region, a field oxide film is provided on the front surface of the semiconductor substrate with the insulating film interposed therebetween. The field oxide film extends from the outside to the inside, and surrounds the periphery of the first gate polysilicon layer in a rectangular manner. The field oxide film has four sides in which at least a portion parallel to a second direction is terminated at a position further to the outside than the first gate polysilicon layer, and the second direction is a direction orthogonal to the first direction.

In the silicon carbide semiconductor device according to the present invention, a portion of the field oxide film along at least one of two sides parallel to the first direction extends inward in the second direction to the same position as an inner end portion of the first gate polysilicon layer.

In the silicon carbide semiconductor device according to the present invention, a portion of the field oxide film parallel to the first direction extends inward in the second direction to the same position as an inner end portion of the first gate polysilicon layer.

In the silicon carbide semiconductor device according to the present invention, the second conductivity type high concentration region is terminated at a position inside the second conductivity type semiconductor layer. At least an inner end of a portion of the field oxide film parallel to the second direction faces the second conductive type semiconductor layer through the insulating film in a depth direction at a position outside the second conductive type junction.

In the silicon carbide semiconductor device according to the present invention, in addition to the above invention, an outer end portion of the first gate polysilicon layer is located within the plane of the second conductivity type high concentration region.

In the silicon carbide semiconductor device according to the present invention, the first gate polysilicon layer is formed on the surface of the silicon carbide semiconductor device.

In the silicon carbide semiconductor device according to the present invention, the second gate polysilicon layer and the gate pad are provided. In the active region, the second gate polysilicon layer is provided on the front surface of the semiconductor substrate with the insulating film interposed therebetween, and is connected to the first gate polysilicon layer. The gate pad is provided over the second gate polysilicon layer with an interlayer insulating film interposed therebetween, and is electrically connected to the second gate polysilicon layer. The field oxide film is not disposed between the front surface of the semiconductor substrate and the second gate polysilicon layer.

In the silicon carbide semiconductor device according to the present invention, the insulating film is a high-temperature oxide film or a thermal oxide film, and the field oxide film is a silicon oxide film. The thickness of the field oxide film is thicker than that of the insulating film.

Technical effects

According to the silicon carbide semiconductor device of the present invention, the following effects are exhibited: since no step due to the field oxide film is generated on the surface of the gate polysilicon layer, electric field concentration near the inner end of the gate polysilicon layer is not generated, and thus dielectric breakdown can be prevented.

Drawings

Fig. 1 is a plan view showing a layout of a silicon carbide semiconductor device according to a first embodiment when viewed from a front surface side of a semiconductor substrate.

Fig. 2 is a plan view showing the rectangular frame a of fig. 1 in an enlarged manner.

Fig. 3 is a sectional view showing a sectional structure of a cutting line B-B' of fig. 2.

Fig. 4 is a sectional view showing a sectional structure of a cutting line C-C' of fig. 1.

Fig. 5 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to a second embodiment.

Fig. 6 is a sectional view showing the structure of a silicon carbide semiconductor device according to a third embodiment.

Fig. 7 is a plan view showing a layout of the silicon carbide semiconductor device according to the fourth embodiment as viewed from the front surface side of the semiconductor substrate.

Fig. 8 is a sectional view showing a sectional structure of a cutting line D-D' of fig. 7.

Fig. 9 is a plan view showing an example of a layout of the silicon carbide semiconductor device according to the fifth embodiment as viewed from the front surface side of the semiconductor substrate.

Fig. 10 is a plan view showing an example of a layout of the silicon carbide semiconductor device according to the fifth embodiment as viewed from the front surface side of the semiconductor substrate.

Fig. 11 is a plan view showing an example of a layout of the silicon carbide semiconductor device according to the fifth embodiment as viewed from the front surface side of the semiconductor substrate.

Fig. 12 is a plan view showing an example of the layout of the silicon carbide semiconductor device according to the fifth embodiment as viewed from the front surface side of the semiconductor substrate.

Fig. 13 is a plan view showing a layout of a conventional silicon carbide semiconductor device as viewed from the front surface side of the semiconductor substrate.

Fig. 14 is a plan view showing the rectangular frame AA of fig. 13 in an enlarged manner.

Fig. 15 is a sectional view showing a sectional structure of the cutting line BB-BB' of fig. 14.

Fig. 16 is a sectional view showing a sectional structure of a cutting line CC-CC of fig. 13.

Description of the symbols

1 active region

2 edge termination region

10. 71-77 silicon carbide semiconductor device

11 source bonding pad

11a outer periphery of the source pad

12 gate pad

13 grid metal layer

13a gate link metal layer

14 grid polysilicon layer

14a first portion of the gate polysilicon layer directly below the gate metal layer

14 a' end of the first portion of the gate polysilicon layer

14b a second portion of the gate polysilicon layer directly below the gate pad

14 b' end of the second portion of the gate polysilicon layer

14c a third portion of the gate polysilicon layer directly below the gate link metal layer

14 c' end of the third portion of the gate polysilicon layer

15 drain electrode

21. 21' field oxide film

21a, 21 a', 21b field oxide film at the end of the chip center side

22 interlayer insulating film

22a, 22b contact hole

23 passivation protective film

31 n^-Type drift region

32 p type base region

33 n type region

34 n⁺Source region of the pattern

35 p⁺⁺Type contact zone

35' edge p⁺⁺Type contact zone

36 groove

37. 37' gate insulating film

38 gate electrode

39 source electrode

40 n⁺Drain region of the type

50 semiconductor substrate

51 n^-Type semiconductor layer

52 p-type semiconductor layer

53 steps of front surface of semiconductor substrate

53a first surface of the front side of the semiconductor substrate

53b second surface of front side of semiconductor substrate

53c, 53 c' step edges of front surface of semiconductor substrate

54 n⁺Type starting substrate

61、62a、62a’、62b、62b’ p⁺Type region

63 p^-Type region

X first direction parallel to front surface of semiconductor substrate (direction in which grooves extend in stripe shape)

Y is parallel to the front surface of the semiconductor substrate and is orthogonal to the first direction

In the Z depth direction

d1 going from the step edge to the edge p of the front surface of the semiconductor substrate⁺⁺Distance to the contact region

End and edge p of the first portion of the d2 gate polysilicon layer on the chip end side⁺⁺Chip end of contact regionDistance between lateral ends

d3 distance of end of field oxide film at chip center extending from step edge to chip center

d 3' from the end of the field oxide film on the chip center side to the edge p⁺⁺Distance to the contact region

d4 distance from the gate metal layer to the source pad

Width of d5 gate metal layer

Detailed Description

Preferred embodiments of the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In the present specification and the drawings, in a layer or a region to which n or p is prepended, it is indicated that electrons or holes are majority carriers, respectively. In addition, the + and-marked on n or p indicate that the impurity concentration is higher or lower than that of the layer or region not marked with the + and-respectively. In the following description of the embodiments and the drawings, the same components are denoted by the same reference numerals, and redundant description thereof is omitted.

(embodiment I)

The structure of the silicon carbide semiconductor device according to the first embodiment will be described. Fig. 1 is a plan view showing a layout of a silicon carbide semiconductor device according to a first embodiment when viewed from a front surface side of a semiconductor substrate. Fig. 2 is a plan view showing the rectangular frame a of fig. 1 in an enlarged manner. A portion surrounded by a rectangular frame a having a set of diagonal vertices of a vertex a1 on the corner side of the semiconductor substrate 50 (one vertex of the semiconductor substrate (semiconductor chip) 50 in a substantially rectangular planar shape) and a vertex a2 on the center side of the semiconductor substrate 50 is a portion of the edge termination region 2. Fig. 3 is a sectional view showing a sectional structure at a cutting line B-B' of fig. 2. Fig. 4 is a sectional view showing a sectional structure at a cutting line C-C' of fig. 1.

A silicon carbide semiconductor device 10 according to the first embodiment shown in fig. 1 to 4 is a vertical MOSFET having a trench gate structure including a gate metal layer 13 and a gate polysilicon (poly-Si) layer 14 in an edge termination region 2 surrounding an active region 1. The active region 1 is a region through which current flows when the element is in an on state. The edge termination region 2 is a region between the active region 1 and the end portion of the semiconductor substrate 50, and is a region for relieving an electric field on the front surface side of the semiconductor substrate 50 and maintaining a withstand voltage. A voltage-resistant structure such as a Junction Termination Extension (JTE) structure is arranged in the edge termination region 2. The withstand voltage is a limit voltage at which the element does not cause malfunction or destruction.

In the active region 1, a source pad 11 and a gate pad 12 are provided separately from each other on a first surface 53a, which will be described later, of the front surface of the semiconductor substrate 50. The source pad 11 has a substantially rectangular planar shape with a portion recessed inward. The source pad 11 occupies a large half of the surface area of the active region 1 and extends from the active region 1 to the edge termination region 2. In fig. 1, an outer periphery 11a of the source pad 11 is indicated by a broken line thinner than a field oxide film 21 described later. Gate pad 12 is disposed in a recess of source pad 11, and has a substantially rectangular planar shape surrounded on three sides by source pad 11.

In the active region 1, portions constituting a MOS gate structure are provided on the front surface side of the semiconductor substrate 50. The semiconductor substrate 50 is at n⁺On a type starting substrate 54, n is^-And an epitaxial substrate in which the type semiconductor layer 51 and the p-type semiconductor layer 52 are epitaxially grown in this order. The main surface of the semiconductor substrate 50 on the p-type semiconductor layer 52 side is defined as a front surface, and n of the semiconductor substrate 50 is defined as a rear surface⁺Main surface (n) of the type starting substrate 54 side⁺The back surface of the type start substrate 54) is set as the back surface. The chip size of the semiconductor substrate 50 may be, for example, 3.8mm × 3.8 mm. The MOS grid structure is composed of p-type base regions 32 and n⁺Source region 34, p⁺⁺ Type contact region 35, trench 36, gate insulating film 37, and gate electrode 38.

n⁺The type starting substrate 54 constitutes n⁺And a drain region 40. n is^-N is a structure of the semiconductor layer 51^- A drift region 31. At n^-The drift region 31 may be provided therein with an n-type region 33 and a p⁺And regions 61, 62a, 62 b. The n-type region 33 is a so-called Current Spreading Layer (CSL) that reduces the resistance to carrier expansion. n-type regions 33 are disposed adjacent to each other in p⁺Type regions 61 and p⁺Between the molding regions 62 a. The n-type region 33 may extend to the edge termination region 2, in which case the n-type region 33 terminates, for example, in a ratioThe step 53 has a step edge 53c located closer to the center (inner side) of the chip. p is a radical of⁺The type regions 61, 62a, 62b have a function of being depleted at the time of MOSFET turn-off to relax the electric field applied to the bottom surface of the trench 36.

p⁺The type region 61 is provided at a position closer to the drain electrode 15 than the p-type base region 32, separately from the p-type base region 32. p is a radical of⁺The land 61 is opposed to the bottom surface of the groove 36 in the depth direction. p is a radical of⁺ Type regions 62a, 62b and trenches 36 and p⁺The pattern regions 61 are separately disposed between the trenches 36 adjacent to each other. p is a radical of⁺ Type region 62a is provided at a position closer to drain electrode 15 than p-type base region 32, apart from p-type base region 32. p is a radical of⁺ Type region 62b is disposed between p-type base region 32 and p⁺Between type region 62a and with p-type base region 32 and p⁺The pattern regions 62a contact.

The p-type semiconductor layer 52 is removed by etching at the end (hereinafter referred to as the end of the chip) to leave a mesa (mesa) shape in the center of the chip. By removing a portion of the p-type semiconductor layer 52 on the chip end side (outer side), a step 53 is formed on the front surface of the semiconductor substrate 50 in the edge termination region 2. The side surface of the remaining mesa-shaped p-type semiconductor layer 52 is exposed at the mesa edge 53c of the step 53. The front surface of the semiconductor substrate 50 is recessed toward the drain electrode 15 described later on a second surface 53b closer to the chip end portion side than a first surface 53a on the active region 1 side (hereinafter, referred to as the chip center side) with the step 53 as a boundary.

The p-type semiconductor layer 52 constitutes the p-type base region 32. That is, p-type base region 32 extends from active region 1 to a ledge 53c of step 53 of edge termination region 2. The step 53 has a step edge 53c which connects a first surface 53a of the front surface of the semiconductor substrate 50 on the chip center side of the step 53 and a second surface 53b of the recess on the chip end side of the step 53. In the active region 1, n is selectively provided between the first surface 53a of the front surface of the semiconductor substrate 50 and the p-type base region 32 in contact with the p-type base region 32⁺Source regions 34 and p⁺⁺And a pattern contact region 35.

The groove 36 runs through n⁺Source region 34 and p-base region 32 to reach n^- A drift region 31. The trench 36 is not provided directly below the gate pad 12. The trenches 36 extend in a stripe shape from the active region 1 to the edge termination region 2 along a first direction X parallel to the front surface of the semiconductor substrate 50. The end of the trench 36 faces the end 14 a' of the gate polysilicon layer 14 on the chip center side of the first portion 14a, which will be described later, in the depth direction Z. The end portions of the trench 36 face end portions 14b 'and 14 c' of second and third portions 14b and 14c of the gate polysilicon layer 14, which will be described later, in the depth direction Z.

A gate electrode 38 made of polysilicon is provided inside the trench 36 via a gate insulating film 37. For example, the gate insulating film 37 may be a High Temperature Oxide (HTO) film or a thermal Oxide film. Gate electrode 38 may be, for example, a polysilicon layer. At the end of the trench 36, the gate electrode 38 is connected to any one of the first to third portions 14a to 14c of the gate polysilicon layer 14. The interlayer insulating film 22 is provided on the entire front surface of the semiconductor substrate 50 so as to cover the gate electrode 38. As the interlayer insulating film 22, for example, NSG (Non doped Silicate Glass: Non-infiltrated Silicate Glass) and BPSG (borophosphosilicate Glass) may be stacked in this order.

In the contact hole 22b of the interlayer insulating film 22, the source electrode 39 and n⁺Source regions 34 and p⁺⁺The type contact region 35 makes ohmic contact and is connected to the source pad 11. The source pad 11 is provided on the interlayer insulating film 22 so as to bury the contact hole 22b of the interlayer insulating film 22, covering almost the entire portion of the first surface 53a of the front surface of the semiconductor substrate 50 in the active region 1 except for the gate pad 12. The gate pad 12 is disposed on the interlayer insulating film 22, and covers a part of the first surface 53a of the front surface of the semiconductor substrate 50 in the active region 1. The gate pad 12 is electrically connected to all the gate electrodes 38 via the gate polysilicon layer 14.

In the edge termination region 2, on the front surface of the semiconductor substrate 50, the gate insulating film 37 is extended from the inner wall of the trench 36 of the active region 1. The field oxide film 21 is provided in contact with the gate insulating film 37 of the second surface 53b of the front surface of the semiconductor substrate 50. The field oxide film 21 extends from the chip end portion toward the chip center side, and terminates on the first surface 53a of the front surface of the semiconductor substrate 50 at a position closer to the chip end portion side than the first portion 14a of the gate polysilicon layer 14. The field oxide film 21 is disposed separately from the gate polysilicon layer 14, the field oxide film 21 surrounding the periphery of the first portion 14a of the gate polysilicon layer 14.

The end 21a of the field oxide film 21 on the chip center side is located closer to the chip center side than the step 53 edge 53c and is located closer to the edge p to be described later⁺⁺The pattern contact region 35' is located further toward the chip end side. I.e. at the step 53 edge 53c and edge p⁺⁺In the portion 44 between the type contact regions 35', the end portion 21a of the field oxide film 21 on the chip center side is located on the p-type base region 32 exposed on the first surface 53a of the front surface of the semiconductor substrate 50. This prevents p from occurring⁺⁺The field oxide film 21 on the type contact region 35' is damaged by insulation.

At the step 53, the step edge 53c and the edge p⁺⁺The position of the end portion 21a of the field oxide film 21 on the chip center side, the portion 44 between the land regions 35', can be variously changed according to design conditions. Specifically, from the step edge 53c to the edge p of the step 53⁺⁺The distance d1 between the land areas 35' is predetermined by design specifications, and is, for example, about 15 μm. In this case, the end portion 21a of the field oxide film 21 on the chip center side ends at a position more than 0.5 μm away from the step edge 53c of the step 53 toward the chip center side, and ends at a position less than 15 μm from the step edge 53c of the step 53 toward the chip center side.

When the distance d3 extending from the step 53c toward the chip center side of the end portion 21a on the chip center side of the field oxide film 21 is 13 μm, the end portion 21a on the chip center side of the field oxide film 21 is extended to the edge p⁺⁺The distance d3 'between the pattern contact regions 35' is 2 μm. In addition, in the case where the distance d3 is 10 μm, it extends from the end 21a of the field oxide film 21 on the chip center side to the edge p⁺⁺The distance d3 'to the pattern contact region 35' is 5 μm. The field oxide film 21 may be, for example, silicon oxide (SiO) having a higher band gap and higher heat resistance than other insulating films₂) And (3) a membrane. The thickness of the field oxide film 21 may be thicker than that of the gate insulating film 37.

The gate polysilicon layer 14 is thicker than the field oxide film21 are provided on the gate insulating film 37 on the front surface of the semiconductor substrate 50 at positions closer to the center of the chip. The gate polysilicon layer 14 is disposed directly below the gate metal layer 13, directly below the gate pad 12, and directly below a metal layer (hereinafter, referred to as a gate connection metal layer) 13a connecting the gate pad 12 and the gate metal layer 13, and terminates within the surface of the first surface 53a of the front surface of the semiconductor substrate 50. The gate polysilicon layer 14 is entirely located at the edge p⁺⁺Within the surface of the land region 35'. Note that, in the drawings, the gate insulating film 37 is formed by thermal oxidation. Normally, the step of forming the field oxide film 21 is a step before the step of forming the gate insulating film 37, and therefore, when the gate insulating film 37 is an HTO film, the upper and lower lamination relationships between the field oxide film 21 and the gate insulating film 37 are interchanged.

A first portion 14a of the gate polysilicon layer 14 directly below the gate metal layer 13 is a gate runner connected to the gate electrode 38 at the end of the trench 36. The first portion 14a of the gate polysilicon layer 14 is opposed to the entirety of the gate metal layer 13 in the depth direction, and surrounds the periphery of the active region 1. An end portion 14 a' of the first portion 14a of the gate polysilicon layer 14 on the chip center side extends toward the chip center side and terminates at a position facing the outer periphery 11a of the source pad 11 in the depth direction Z. The end of the first portion 14a of the gate polysilicon layer 14 on the chip end side is located at an edge p described later⁺⁺Within the surface of the land region 35'. For example, the chip end side end and the edge p of the first portion 14a of the gate polysilicon layer 14⁺⁺The distance d2 between the chip end side ends of the land 35' is about 2 μm.

A second portion 14b of the gate polysilicon layer 14 immediately below the gate pad 12 is opposed to the entirety of the gate pad 12 in the depth direction Z. An end portion 14 b' of the second portion 14b of the gate polysilicon layer 14 extends in a direction (first direction X, second direction Y) parallel to the front surface of the semiconductor substrate 50 in a direction away from the gate pad 12, and terminates at a position facing the outer periphery 11a of the source pad 11 in the depth direction Z. A third portion 14c of the gate polysilicon layer 14 directly below the gate connection metal layer 13a faces the entire gate connection metal layer 13a in the depth direction Z. An end portion 14 c' of the third portion 14c of the gate polysilicon layer 14 extends in a direction parallel to the front surface of the semiconductor substrate 50 (the first direction X in fig. 1) in a direction separating from the gate link metal layer 13a, and terminates at a position facing the outer periphery 11a of the source pad 11 in the depth direction Z.

The planar shape of the inner periphery of the gate polysilicon layer 14 is slightly smaller than the outer periphery 11a of the source pad 11, and is the same planar shape as the outer periphery 11a of the source pad 11. The planar shape of the outer periphery of the gate polysilicon layer 14 is a rectangle slightly smaller than the inner periphery of the field oxide film 21. In fig. 1, an end 14a ' of the gate polysilicon layer 14 on the chip center side of the first portion 14a, an end of the first portion 14a on the chip end side, and ends 14b ' and 14c ' of the second and third portions 14b and 14c are indicated by thick solid lines. In fig. 1, an end portion 21a of the field oxide film 21 on the chip center side is indicated by a thick dotted line with respect to the outer periphery 11a of the source pad 11. The end of the field oxide film 21 on the chip end side is located at the chip end.

On the first portion 14a of the gate polysilicon layer 14, the gate metal layer 13 is provided on the interlayer insulating film 22. The gate metal layer 13 surrounds the periphery of the active region 1. The gate metal layer 13 is electrically connected to the first portion 14a of the gate polysilicon layer 14 through the contact hole 22a of the interlayer insulating film 22, and is electrically connected to the gate pad 12 through the gate link metal layer 13 a. The portion directly below the gate metal layer 13 extends over the entire first portion 14a of the gate polysilicon layer 14, and has a two-layer structure in which the gate insulating film 37 and the first portion 14a of the gate polysilicon layer 14 are sequentially stacked on the first surface 53a of the front surface of the semiconductor substrate 50. That is, in the first portion 14a of the gate polysilicon layer 14, the thickness (thickness) of the insulating film existing between the gate polysilicon layer 14 and the first surface 53a of the front surface of the semiconductor substrate 50 is the same as the thickness of the gate insulating film 37 formed in the trench 36 in the active region 1. The same film thickness may be formed by the same manufacturing process, and includes a range of in-plane variation up to ± 10% of the film thickness variation.

The second portion 14b of the gate polysilicon layer 14 has a two-layer structure in which the gate insulating film 37 and the second portion 14b of the gate polysilicon layer 14 are sequentially stacked on the first surface 53a of the front surface of the semiconductor substrate 50 over the entire second portion 14b of the gate polysilicon layer 14. The third portion 14c of the gate polysilicon layer 14 has a two-layer structure in which the gate insulating film 37 and the third portion 14c of the gate polysilicon layer 14 are sequentially stacked on the first surface 53a of the front surface of the semiconductor substrate 50 over the entire third portion 14c of the gate polysilicon layer 14.

Thus, the field oxide film 21 does not face the gate polysilicon layer 14 in the depth direction Z. Therefore, the surface of the gate polysilicon layer 14 is flat over the entire gate polysilicon layer 14, and a step 115 (fig. 15 and 16) due to the field oxide film 121 as in the conventional structure is not formed on the surface of the gate polysilicon layer 14. Since the insulating film between the gate polysilicon layer 14 and the first surface 53a of the front surface of the semiconductor substrate 50 is only the gate insulating film 37, when a voltage is applied under the above conditions, electric field concentration is not caused at the end portion 14a ' of the gate polysilicon layer 14 on the chip center side of the first portion 14a and the end portions 14b ', 14c ' of the second and third portions 14b, 14c, as in the conventional structure.

The gate polysilicon layer 14 and the field oxide film 21 are covered with an interlayer insulating film 22. The gate polysilicon layer 14 is electrically connected to the gate metal layer 13 through the contact hole 22a of the interlayer insulating film 22. A contact portion between the gate metal layer 13 and the gate polysilicon layer 14 is formed in the contact hole 22a of the interlayer insulating film 22. Symbols 41 to 44, 44 ', 45 to 49 in fig. 3 correspond to symbols 41 to 44, 44', 45 to 49 in fig. 2, respectively. The distance d4 from the gate metal layer 13 to the source pad 11 is, for example, about 10 μm. The width d5 of the gate metal layer 13 is, for example, about 36 μm. The distances d1 to d4 between the respective portions and the width d5 of the gate metal layer 13 are determined according to design specifications and do not depend on the chip size of the semiconductor substrate 50.

In the edge termination region 2, p extends from the active region 1 between the first surface 53a of the front surface of the semiconductor substrate 50 and the p-type base region 32⁺⁺The contact region 35 (hereinafter, referred to as an edge)p⁺⁺The land pattern 35'). Edge p⁺⁺The type contact region 35' extends further toward the chip end side than the first portion 14a of the gate polysilicon layer 14, and terminates further toward the chip center side than the end 21a of the field oxide film 21 on the chip center side. Edge p⁺⁺The type contact region 35' makes ohmic contact with the source electrode 39 at the contact hole 22b of the interlayer insulating film 22.

Edge p⁺⁺The contact portion (electric contact portion) between the type contact region 35' and the source electrode 39 is for passing through the edge p⁺⁺The type contact region 35' draws a contact portion of the hole current generated in the edge termination region 2 at the time of off-state to the source electrode 39. For example, the edge p⁺⁺The type contact region 35' also extends directly below the gate pad 12. At n^-The surface region of the semiconductor layer 51, which forms the second surface 53b of the front surface of the semiconductor substrate 50, is selectively formed with p by ion implantation^-And a patterned region 63. p is a radical of^-The type region 63 is electrically connected to the source electrode 39 and constitutes a voltage-resistant structure such as a Junction Termination Extension (JTE) structure. p is a radical of^-The type region 63 surrounds the periphery of the active region 1.

At p^-P-type regions 63 and active region 1 are provided between p-type region 32 and drain electrode 15 so as to face each other and be adjacent to each other in depth direction Z⁺The pattern regions 62a ', 62 b'. p is a radical of⁺ Type regions 62 a' and p^-Type regions 63 and p⁺The pattern region 62 b' contacts. p is a radical of⁺ Type regions 62 b' and p^-Type region 63 is in contact with p-type base region 32. p is a radical of⁺The type regions 62a ', 62 b' surround the periphery of the active region 1. p is a radical of⁺The type regions 62a ', 62 b' extend, for example, directly below the gate pad 12. p is a radical of⁺ Type regions 62a ', 62 b' and p of active region 1⁺The molding regions 62a, 62b are formed simultaneously.

The front surface of the semiconductor substrate 50 is covered with the passivation film 23. The entire back surface of the semiconductor substrate 50 is provided with the drain electrode 15, and⁺a drain region 40 (n)⁺Type start substrate 54).

As described above, according to the first embodiment, the end portion of the field oxide film on the chip center side is located on the chip end portion side with respect to the first portion of the gate polysilicon layerAnd terminating so that a step due to the field oxide film is not generated on the surface of the gate polysilicon layer and is flat throughout the entire surface of the gate polysilicon layer. Therefore, when a voltage is applied under the above-described predetermined condition, electric field concentration at the end portion on the chip center side of the first portion of the gate polysilicon layer, which is generated in the conventional structure, is not generated. Thus, the turn-off occurs at the edge termination region and passes through the edge p⁺⁺Part of the hole current (leakage current) extracted from the source electrode by the type contact region is not injected into the gate insulating film in the vicinity of the contact portion for extracting the hole current. Therefore, dielectric breakdown of the gate insulating film can be prevented.

(second embodiment)

Next, the structure of the silicon carbide semiconductor device according to the second embodiment will be described. Fig. 5 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to a second embodiment. The silicon carbide semiconductor device 71 according to the second embodiment is different from the silicon carbide semiconductor device 10 (see fig. 1 to 4) according to the first embodiment in that a field oxide film covering the front surface of the semiconductor substrate 50 in the edge termination region 2 is not provided. The silicon carbide semiconductor device 71 according to the second embodiment has the same planar structure as the silicon carbide semiconductor device in which the field oxide film 21 is removed from fig. 1 and 2. Fig. 5 corresponds to the sectional structure of the cutting line B-B' of fig. 2.

As described above, according to the second embodiment, even if the field oxide film is not provided, a step is not generated on the surface of the gate polysilicon layer, and therefore, the same effect as that of the first embodiment can be obtained.

(third embodiment)

Next, the structure of the silicon carbide semiconductor device according to the third embodiment will be described. Fig. 6 is a sectional view showing the structure of a silicon carbide semiconductor device according to a third embodiment. The silicon carbide semiconductor device 72 according to the third embodiment is different from the silicon carbide semiconductor device 10 according to the first embodiment (see fig. 1 to 4) in that the step edge 53 c' of the step 53 is inclined at an obtuse angle with respect to the first surface 53a of the front surface of the semiconductor substrate 50. The plane structure of the silicon carbide semiconductor device 72 according to the third embodiment is the same as that of fig. 1 and 2. Fig. 6 corresponds to the sectional structure at the cutting line B-B' of fig. 2.

In the third embodiment, the field oxide film 21 ' and the gate insulating film 37 ' are arranged on the step 53 at an inclination along the step 53c '. This allows the field oxide film 21 'to be uniformly deposited on the mesa edge 53 c', thereby improving reliability. Therefore, it is possible to prevent the end portion 21a ' of the field oxide film 21 ' on the chip center side from moving to the chip center side and being positioned at the edge p due to variations in the processing accuracy of the field oxide film 21 ' or the like⁺⁺The end portion 21a 'of the field oxide film 21' on the chip center side is moved to the chip end portion side and positioned on the step 53 along the step 53c 'on the land 35'.

As described above, according to the third embodiment, the same effects as those of the first embodiment can be obtained. In addition, according to the third embodiment, the step edge is inclined at an obtuse angle with respect to the first surface and the second surface of the front surface of the semiconductor substrate, so that the step edge and the edge p are formed at the step edge⁺⁺Between the type contact regions, the position of the end portion of the field oxide film on the chip center side extending from the step edge toward the first surface of the front surface of the semiconductor substrate can be set with high accuracy in the p-type base region exposed on the first surface of the front surface of the semiconductor substrate.

(fourth embodiment)

Next, the structure of the silicon carbide semiconductor device according to the fourth embodiment will be described. Fig. 7 is a plan view showing a layout of the silicon carbide semiconductor device according to the fourth embodiment as viewed from the front surface side of the semiconductor substrate. Fig. 8 is a sectional view showing a sectional structure of a cutting line D-D' of fig. 7. The silicon carbide semiconductor device 73 according to the fourth embodiment is different from the silicon carbide semiconductor device 10 (see fig. 1 to 4) according to the first embodiment in that an end portion 21b of the field oxide film 21 on the chip center side, which is parallel to the first direction X, is located at the same position as an end portion 14 a' of the first portion 14a of the gate polysilicon layer 14 on the chip center side.

Specifically, in the second direction Y parallel to the front surface of the semiconductor substrate 50 and orthogonal to the first direction X, the end 21b of the field oxide film 21 on the chip center side in a portion parallel to the first direction X extends to the same position as the end 14 a' on the chip center side in a portion parallel to the first direction X of the first portion 14a of the gate polysilicon layer 14. Therefore, at a portion of the first portion 14a of the gate polysilicon layer 14 parallel to the first direction X, a step due to the field oxide film 21 is not generated on the surface of the first portion 14a of the gate polysilicon layer 14. In fig. 7, end portions 21a and 21b of the field oxide film 21 on the chip center side are indicated by a thick dotted line with respect to the outer periphery 11a of the source pad 11.

Thus, at a position parallel to the first direction X of the first portion 14a of the gate polysilicon layer 14, the end portion 21b of the field oxide film 21 on the chip center side of the portion parallel to the first direction X can be extended further toward the chip center side than the first portion 14a of the gate polysilicon layer 14 so that no step due to the field oxide film 21 is generated on the surface of the first portion 14a of the gate polysilicon layer 14. Therefore, the end portion 21b of the field oxide film 21 on the chip center side of the portion parallel to the first direction X may extend slightly toward the chip center side than the end portion 14 a' of the first portion 14a of the gate polysilicon layer 14 on the chip center side of the portion parallel to the first direction X.

On the other hand, a portion of the first portion 14a of the gate polysilicon layer 14 parallel to the second direction Y is a position facing an end of the trench 36 in the depth direction Z. As in the embodiment, the end 21a of the field oxide film 21 on the chip center side in the portion parallel to the second direction Y is terminated at a position closer to the chip end side than the portion parallel to the second direction Y of the first portion 14a of the gate polysilicon layer 14. Therefore, at a portion of the first portion 14a of the gate polysilicon layer 14 parallel to the second direction Y, a step due to the field oxide film 21 is not generated on the surface of the first portion 14a of the gate polysilicon layer 14.

That is, the gate insulating film 37, the field oxide film 21, and the first portion 14a of the gate polysilicon layer 14 are sequentially stacked on the front surface of the semiconductor substrate 50 at a portion of the gate metal layer 13 parallel to the first direction X, directly below the gate metal layer 13. The gate metal layer 13 has a double-layer structure in which the gate insulating film 37 and the first portion 14a of the gate polysilicon layer 14 are sequentially stacked on the front surface of the semiconductor substrate 50 directly below the gate metal layer 13 at a portion parallel to the second direction Y of the gate metal layer 13. Therefore, the total film thickness of the insulating films (37, 21) present between the front surface of the semiconductor substrate 50 and the gate polysilicon layer 14 is thicker at the portion parallel to the first direction than at the portion parallel to the second direction Y.

Thus, when the positions of the end portions 21a and 21b of the field oxide film 21 on the chip center side are different in the first direction X and the second direction Y, a step due to the field oxide film 21 is generated on the surface of the first portion 14a of the gate polysilicon layer 14 at the corner portions of the semiconductor substrate 50 (four vertices of the semiconductor substrate 50 having a substantially rectangular planar shape). In addition, although a step due to the field oxide film 21 is generated on the surface of the third portion 14c of the gate polysilicon layer 14 by the arrangement of the gate pad 12, the degree of freedom of design is improved for the arrangement of the field oxide film 21.

In the second portion 14b of the gate polysilicon layer 14, as in the embodiment, since the field oxide film 21 is not present directly below the second portion 14b of the gate polysilicon layer 14, a step due to the field oxide film 21 is not generated on the surface of the second portion 14b of the gate polysilicon layer 14.

As described above, according to the fourth embodiment, the end portion of the field oxide film on the chip center side is extended to the chip center side to the same position as the end portion of the first portion of the gate polysilicon layer on the chip center side, so that the step due to the field oxide film is not generated on the surface of the first portion of the gate polysilicon layer, and therefore, the same effect as that of the first embodiment can be obtained.

(fifth embodiment)

Next, the structure of the silicon carbide semiconductor device according to the fifth embodiment will be described. Fig. 9 to 12 are plan views showing an example of the layout of the silicon carbide semiconductor device according to the fifth embodiment as viewed from the front surface side of the semiconductor substrate. Fig. 9 to 12 schematically illustrate the gate polysilicon layer 14, the chip center side end portions 21a and 21b (only the end portion 21a in fig. 9) of the field oxide film 21, and the trench 36 of the silicon carbide semiconductor devices 74 to 77 according to the fifth embodiment, respectively, and other components are not illustrated. The end portions 21a and 21b of the field oxide film 21 on the chip center side are indicated by broken lines.