阅读说明：本技术 电子器件 (Electronic device ) 是由 A·巴纳尔吉 P·莫恩斯 于 2020-03-25 设计创作，主要内容包括：本发明题为“电子器件”。本发明公开了一种电子器件,并且该电子器件可以包括HEMT。在实施方案中,该HEMT可以包括栅极电极、漏极电极和存取区域。该存取区域可以包括更靠近栅极电极的第一部分和更靠近漏极电极的第二部分。下介电膜可以覆盖存取区域的一部分,并且上介电区域可以覆盖存取区域的另一部分。在另一实施方案中,介电膜可以具有相对正或负电荷以及变化的厚度。在另一实施方案中,HEMT可以包括栅极互连,该栅极互连穿过接触开口延伸到栅极电极。(The invention provides an electronic device. An electronic device is disclosed and may include a HEMT. In an embodiment, the HEMT may include a gate electrode, a drain electrode, and an access region. The access region may include a first portion closer to the gate electrode and a second portion closer to the drain electrode. The lower dielectric film may cover a portion of the access region, and the upper dielectric region may cover another portion of the access region. In another embodiment, the dielectric film may have a relatively positive or negative charge and a varying thickness. In another embodiment, the HEMT may include a gate interconnect that extends through the contact opening to the gate electrode.)

1. An electronic device comprising a high electron mobility transistor, the electronic device comprising:

a gate electrode;

a drain electrode;

an access region including a first portion closer to the gate electrode and a second portion closer to the drain electrode;

a first dielectric film comprising a first material and overlying the first portion of the access region and not overlying the second portion of the access region; and

a second dielectric film comprising a second material overlying the second portion of the access region, wherein the second material is different from the first material.

2. The electronic device of claim 1, wherein the gate electrode has a top surface and a first sidewall that intersect at a first corner, and the first dielectric film contacts the top surface and sidewall of the gate electrode at the first corner.

3. The electronic device of claim 2, further comprising a gate interconnect, wherein the gate electrode has a second sidewall opposite the first sidewall, the second sidewall intersects the top surface at a second corner, and the gate interconnect contacts a portion of the top surface of the gate electrode and is spaced apart from the first corner and the second corner.

4. The electronic device of claim 3, wherein a gate field electrode is part of or electrically connected to the gate interconnect, wherein the first dielectric film is disposed between the first portion of the access region and the gate field electrode and extends a first distance over the access region, the gate field electrode extends a second distance over the access region, and the second distance is in a range of 0.5 to 2.0 times the first distance.

5. The electronic device of claim 3, further comprising a source electrode, wherein the second dielectric film comprises a first portion extending from the gate interconnect to the drain electrode and a second portion extending from the gate interconnect to the source electrode.

6. The electronic device of claim 1, wherein the gate electrode has a body region and an extension region extending from the body region, wherein the body region and the extension region have the same composition and are located along a bottom surface of the gate electrode, and the drain electrode is closer to the extension region than to the body region.

7. The electronic device of any of claims 1-6, wherein:

the first dielectric film comprises Si₃N₄、SiO_kN_l、AlN、AlO_rN_sOr another nitrogen-containing dielectric material providing a negatively-charged dielectric film, wherein k<l, wherein r<s, and

the second dielectric film includes Al₂O₃、AlO_tN_u、SiO₂、HfO₂、SiO_mN_nOr another oxygen-containing dielectric material providing a positively charged dielectric film, wherein t>u, wherein m>n。

8. An electronic device comprising a high electron mobility transistor, the electronic device comprising:

a gate electrode having a top surface and sidewalls;

a drain electrode;

an access region including a first portion closer to the gate electrode and a second portion closer to the drain electrode; and

a dielectric film contacting the top surface and sidewalls of the gate electrode and overlying the access region, wherein:

the dielectric film is a negatively charged film and is relatively thick over the first portion of the access region and relatively thin over the second portion of the access region, or

The dielectric film is a positively charged film and is relatively thin over the first portion of the access region and relatively thick over the second portion of the access region.

9. The electronic device of claim 8, further comprising a gate field electrode as part of or electrically connected to the gate electrode, wherein the gate field electrode extends over a relatively thin portion of the dielectric film and does not extend over a relatively thick portion of the dielectric film.

10. An electronic device comprising a high electron mobility transistor, the electronic device comprising:

a gate electrode;

a dielectric film overlying the gate electrodes and defining openings to the gate electrodes, wherein a portion of the dielectric film is disposed between the openings; and

a gate interconnect extending into the opening of the dielectric film and contacting the gate electrode and the portion of the dielectric film.

Technical Field

The present disclosure relates to an electronic device, and more particularly, to an electronic device including a high electron mobility transistor including a gate electrode and a dielectric film.

Background

The enhancement mode hemt may have a gate field electrode extending toward a drain electrode to help improve the reliability of the device. However, the gate field plate increases the gate-to-drain capacitance C_GDThis results in a Miller ratio C_GD/C_GSHigher, wherein C_GSIs the gate-source capacitance. Other parameters that affect device performance include subthreshold slope and on-resistance R_DSON. For sub-threshold slope, the drain current I can be plotted when the transistor is on_DAnd gate voltage V_GS. May be specific I when the device is off_DOr I_DThe range determines the subthreshold slope. Ideally, the subthreshold slope is uniform when the device is on, and R is_DSONLow. Improving a variable usually comes at the expense of one of the other parameters. For example, increased resistance to gate bounce may be associated with lower device reliability, and increased uniformity of subthreshold slope may be associated with higher R_DSONAnd the like. Thus, those skilled in the art seek improved performance with little or no adverse effect on device parameters.

Disclosure of Invention

The problem to be solved by the invention is to reduce the miller ratio of high electron mobility transistors without increasing the on-state resistance of the high electron mobility transistors to an unacceptable level.

According to an aspect of the present invention, an electronic device is provided. The electronic device may include a high electron mobility transistor. The high electron mobility transistor may include: a gate electrode; a drain electrode; an access region including a first portion closer to the gate electrode and a second portion closer to the drain electrode; a first dielectric film comprising a first material and covering a first portion of the access region and not covering a second portion of the access region; a second dielectric film comprising a second material and covering a second portion of the access region, wherein the second material is different from the first material.

In an embodiment, the gate electrode has a top surface and a first sidewall that intersect at a first corner, and the first dielectric film contacts the top surface and the sidewall of the gate electrode at the first corner.

In a particular embodiment, the electronic device can further include a gate interconnect, wherein the gate electrode has a second sidewall opposite the first sidewall, the second sidewall intersects the top surface at a second corner, and the gate interconnect contacts a portion of the top surface of the gate electrode and is spaced apart from the first corner and the second corner.

In a more particular embodiment, the gate field electrode is part of or electrically connected to a gate interconnect, wherein the first dielectric film is disposed between the gate field electrode and the first portion of the access region and extends a first distance above the access region, the gate field electrode extends a second distance above the access region, and the second distance is in a range of 0.5 to 2.0 times the first distance.

In another more particular embodiment, the electronic device may further include a source electrode, wherein the second dielectric film includes a first portion extending from the gate interconnect to the drain electrode and a second portion extending from the gate interconnect to the source electrode.

In another embodiment, the gate electrode has a body region and an extension region extending from the body region, wherein the body region and the extension region have the same composition and are located along a bottom surface of the gate electrode, and the drain electrode is closer to the extension region than to the body region.

In a further embodiment, the first dielectric film comprises Si₃N₄、SiO_kN_l(where k is<l)、AlN、AlO_rN_s(wherein r is<s) or another nitrogen-containing dielectric material providing a negatively charged dielectric film, and the second dielectric film comprises Al₂O₃、AlO_tN_u(where t is>u)、SiO₂、HfO₂、SiO_mN_n(wherein m is>n) or another oxygen-containing dielectric material that provides a positively charged dielectric film.

In another aspect, an electronic device is provided. The electronic device may include a high electron mobility transistor. The high electron mobility transistor may include: a gate electrode having a top surface and sidewalls; a drain electrode; an access region including a first portion closer to the gate electrode and a second portion closer to the drain electrode; a dielectric film contacting the top surface and sidewalls of the gate electrode and covering the access region. The dielectric film may be a negatively charged film and be relatively thick over the first portion of the access region and relatively thin over the second portion of the access region, or the dielectric film may be a positively charged film and be relatively thin over the first portion of the access region and relatively thick over the second portion of the access region.

In an embodiment, the electronic device may further comprise a gate field electrode as part of or electrically connected to the gate electrode, wherein the gate field electrode extends over the relatively thin portion of the dielectric film and does not extend over the relatively thick portion of the dielectric film.

In a further aspect, an electronic device is provided. The electronic device may include a high electron mobility transistor. The high electron mobility transistor may include: a gate electrode; a dielectric film covering the gate electrodes and defining openings to the gate electrodes, wherein a portion of the dielectric film is disposed between the openings; and a gate interconnect extending into the opening of the dielectric film and contacting a portion of the dielectric film and the gate electrode.

The technical effect achieved by the present invention allows high electron mobility transistors to have a relatively low miller ratio without increasing the on-resistance of the high electron mobility transistors to an unacceptable level.

Drawings

Embodiments are shown by way of example in the drawings and the embodiments are not limited thereto.

Fig. 1 includes an illustration including a cross-sectional view of a portion of a workpiece including a substrate, a buffer layer, a channel layer, a barrier layer, and a gate electrode.

FIG. 2 includes an illustration of a cross-sectional view of the workpiece including FIG. 1 after forming a lower dielectric film.

FIG. 3 includes an illustration of a cross-sectional view of the workpiece including FIG. 2 after forming mask features and patterning the lower dielectric film.

FIG. 4 includes an illustration of a cross-sectional view of the workpiece including FIG. 3 after removing the mask features and forming the upper dielectric film.

FIG. 5 includes an illustration of a cross-sectional view of the workpiece including FIG. 4 after forming an interlayer dielectric layer and drain and source electrodes.

FIG. 6 includes an illustration of a cross-sectional view of the workpiece including FIG. 5 after forming another interlevel dielectric layer, a conductive member, and a gate interconnect.

FIG. 7 includes an illustration of a cross-sectional view of the workpiece including FIG. 6 after forming another interlevel dielectric layer and a patterned conductive layer.

Fig. 8 and 9 include illustrations of a top view and a cross-sectional view of a portion of a workpiece including a patterned opening to a gate electrode in accordance with another embodiment.

FIG. 10 includes an illustration of a cross-sectional view of a portion of a workpiece including a barrier layer having recesses, in accordance with another embodiment.

FIG. 11 includes an illustration of a cross-sectional view including a portion of a workpiece including a lower dielectric film formed within a recessed barrier layer according to another embodiment.

Fig. 12 includes an illustration of a cross-sectional view including a portion of a workpiece including a lower dielectric film including a portion extending from a gate electrode toward a source electrode, in accordance with another embodiment.

Fig. 13 includes an illustration of a cross-sectional view including a portion of a workpiece including a gate electrode having a body region and an extension region, in accordance with another embodiment.

Fig. 14 includes an illustration of a cross-sectional view including a portion of a workpiece including a dielectric film having a varying thickness over a drain-side access region, in accordance with another embodiment.

Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.

Detailed Description

The following description, in conjunction with the drawings, is provided to assist in understanding the teachings disclosed herein. The following discussion will focus on specific implementations and embodiments of the teachings. This focus is provided to help describe the teachings and should not be construed as limiting the scope or applicability of the teachings. However, other embodiments may be employed based on the teachings as disclosed in this application.

III-V material is intended to mean a material comprising at least one group 13 element and at least one group 15 element. III-N materials are intended to mean semiconductor materials comprising at least one group 13 element and nitrogen.

When referring to a film or layer, the terms "negatively charged" and "positively charged" are used with respect to the electron density of a two-dimensional electron gas along a heterojunction between two layers, such as a channel layer and a barrier layer. The two-dimensional electron gas has a baseline electron density without a negatively or positively charged membrane or layer overlying an upper layer (e.g., a barrier layer) of the two layers. When a negatively charged membrane or layer overlies an overlying layer (e.g., a barrier layer), electrons are repelled from the heterojunction, thereby reducing the electron density and increasing the sheet resistance of the two-dimensional electron gas. When a positively charged membrane or layer overlies an overlying layer (e.g., a barrier layer), electrons are attracted to the heterojunction, thereby increasing the electron density and decreasing the sheet resistance of the two-dimensional electron gas. Negatively and positively charged films or layers have opposite effects on the hole density of the two-dimensional hole gas. A negatively charged membrane or layer increases the hole density of the two-dimensional hole gas, while a positively charged membrane or layer decreases the hole density of the two-dimensional hole gas.

The terms "comprises," "comprising," "includes," "including," "has," "having" or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a method, article, or apparatus that comprises a list of features is not necessarily limited to only those features but may include other features not expressly listed or inherent to such method, article, or apparatus. In addition, unless expressly stated to the contrary, "or" means an inclusive or, rather than an exclusive or. For example, condition a or B is satisfied by either: a is true (or present) and B is false (or not present), a is false (or not present) and B is true (or present), and both a and B are true (or present).

In addition, "a" or "an" is used to describe elements and components described herein. This is done merely for convenience and to give a general sense of the scope of the invention. The description is to be construed as including one, at least one, or the singular also includes the plural and vice versa unless it is explicitly stated that the contrary is intended. For example, when a single item is described herein, more than one item may be used in place of a single item. Similarly, where more than one item is described herein, a single item may be substituted for the more than one item.

The use of the words "about", "about" or "substantially" is intended to mean that the value of a parameter is close to a specified value or location. However, a slight difference may prevent the value or position from being exactly as specified. Thus, from an ideal target as fully described, a difference of at most ten percent (10%) for the value is a reasonable difference.

The group numbers correspond to columns in the periodic table of the elements based on the IUPAC periodic table, version 28/11/2016.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The materials, methods, and examples are illustrative only and not intended to be limiting. Many details regarding specific materials and processing acts are conventional and may be found in textbooks and other sources within the semiconductor and electronics arts, without being described herein.

The characteristics of a High Electron Mobility Transistor (HEMT) may be used and the performance of the HEMT is improved. The extended region of the lower dielectric film can locally increase the sheet resistance of the two-dimensional electron gas (2DEG) near the gate electrode and allow faster depletion of the charge. The locally higher sheet resistance can be designed so that the R of the HEMT is_DSONCannot be increased by more than 1ohm. The upper dielectric film may help reduce the sheet resistance of the 2DEG to help offset some of the increased sheet resistance corresponding to the lower dielectric film. C_GDMay be lower and provide a lower miller ratio. Output capacitance (C) of HEMT_OSS) Is lower than. Thus, the HEMT has improved switching characteristics. The lower dielectric film may cover corners of portions of the top surface of the gate electrode and contribute to a more uniform sub-threshold slope and increase the gate breakdown voltage during turn-on.

Other features may also provide other advantages or alternatives to the design of the HEMT. When the HEMT is on, the contact area between the gate electrode and the gate interconnect can be reduced to reduce the gate current. A recess within the barrier layer near the gate electrode may be used to help increase the threshold voltage of the HEMT. The recess may or may not include an extension region of the lower dielectric film. The lower dielectric film may include a source side extension region over the source side access region of the blocking layer. The source side extension region may help increase the threshold voltage of the HEMT. The gate electrode may include a body region and an extension region that may help increase the threshold voltage of the HEMT.

In an aspect, an electronic device may include a high electron mobility transistor including a gate electrode, a drain electrode, and an access region including a first portion closer to the gate electrode and a second portion closer to the drain electrode. The electronic device may further include a first dielectric film including a first material and covering the first portion but not the second portion of the access region, and a second dielectric film including a second material and covering the second portion of the access region, wherein the second material is different from the first material.

In another aspect, an electronic device may include a high electron mobility transistor including a gate electrode having a top surface and sidewalls, a drain electrode, and an access region including a first portion closer to the gate electrode and a second portion closer to the drain electrode. The electronic device may further include a dielectric film contacting the top surface and the sidewalls of the gate electrode and covering the access region. The dielectric film may comprise a negatively charged first material and be relatively thick over a first portion of the access region and relatively thin over a second portion of the access region, or the dielectric film may comprise a positively charged second material and be relatively thin over the first portion of the access region and relatively thick over the second portion of the access region.

In another aspect, an electronic device may include a high electron mobility transistor including a gate electrode; a dielectric film covering the gate electrodes and defining openings to the gate electrodes, wherein a portion of the dielectric film is disposed between the openings; and a gate interconnect extending into the opening of the dielectric film and contacting a portion of the dielectric film and the gate electrode.

Fig. 1 includes a cross-sectional view of a portion of a workpiece 100 where a HEMT is being formed. The workpiece 100 may include a substrate 102, a buffer layer 104, a channel layer 106, a barrier layer 108, and a gate electrode 124. The substrate 102 may comprise silicon, sapphire (single crystal Al)₂O₃) Silicon carbide (SiC), aluminum nitride (AlN), gallium oxide (Ga)₂O₃) Spinel (MgAl)₂O₄) Another suitable substantially single crystal material, etc. The selection of the particular material and crystal orientation along the major surface may be selected according to the composition of the overlying semiconductor layer.

The buffer layer 104 may include a III-N material, and in particular embodiments, Al_aGa_(1-a)N, wherein a is more than or equal to 0 and less than or equal to 1. The composition of the buffer layer 104 may depend on the composition of the channel layer 106 and the design operating voltage of the HEMT. The composition of the buffer layer 104 may vary with thickness such that the buffer layer 104 has a relatively high aluminum content closer to the substrate 102 and a relatively high gallium content closer to the channel layer 106. In particular embodiments, the cation (metal atom) content in the buffer layer 104 proximate to the substrate 102 may be 10 atomic% to 100 atomic% Al, the remainder being Ga, and the cation content in the buffer layer 104 proximate to the channel layer 106 may be 0 atomic% to 50 atomic% Al, the remainder being Ga. In another embodiment, the buffer layer 104 may include a plurality of films. The buffer layer 104 may have a thickness in the range of about 1 to 5 microns.

The channel layer 106 may include Al_xGa_(1-x)N, wherein 0X ≦ 0.1, and has a thickness in a range of about 20nm to 4000 nm. In a particular embodiment, the channel layer 106 is a GaN layer (x ═ 0). The channel layer 106 may be inadvertently doped or doped with an electron donor (n-type) dopant or an electron acceptor (p-type) dopant. The 2DEG110 may be formed near the interface of the channel layer 106 and the barrier layer 108 and is responsible for high mobility and lower resistivity of the transistor structure when in the on state. Any reduction in 2DEG electrons will increase the R of the HEMT_DSON. In one embodiment, the concentration of acceptor (when the carrier is an electron) or donor (when the carrier is a hole) can be kept as low as reasonably possible.

In particular embodiments, when Metal Organic Chemical Vapor Deposition (MOCVD) is used to form the channel layer 106, the acceptor may include a source gas (e.g., Ga (CH))₃)₃) Carbon (c) of (a). In one particular embodiment, the lowest trap concentration is desired, but may be limited by growth or deposition conditions and precursor purity. Thus, as the channel layer 106 grows, some carbon may become incorporated, and such carbon may lead to unintentional doping. The carbon content can be controlled by controlling deposition conditions such as deposition temperature and flow rate. In an embodiment, the channel layer 106 has a thickness greater than 0 and less than 1 × 10¹⁴Atom/cm³Or less than 1X 10¹⁵Atom/cm³And in another embodiment at most 1X 10¹⁶Atom/cm³The carrier impurity concentration of (1). In yet another embodiment, the carrier impurity concentration is at 1 × 10¹³One atom/cubic centimeter to 1 x 10¹⁶In the range of one atom per cubic centimeter.

In one embodiment, the channel layer 106 has a thickness of at least 50 nm. When the thickness is less than 50nm, 2DEG may be more difficult to generate, maintain, or both. In another embodiment, the channel layer 106 has a thickness of at most 5000 nm. In another embodiment, the thickness of the channel layer 106 may be up to 1000nm and provide good dynamic R_DSON. In particular embodiments, a thickness in the range of 50nm to 1000nm may provide a sufficiently thick channel layer 106 to allow for proper generation and maintenance of a 2DEG, and stillReasonable dynamic R is then obtained_DSON. Although not shown, a spacer layer may be used between the channel layer 106 and the barrier layer 108 if desired.

The barrier layer 108 may comprise a III-V semiconductor material, such as a III-N semiconductor material. In an embodiment, the barrier layer 108 may include Al_yIn_zGa_(1-y-z)N, wherein y is 0. ltoreq. y.ltoreq.1.0, z is 0. ltoreq. z.ltoreq.0.3, and 0<(y + z) is less than or equal to 1. The barrier layer 108 may have a lower Ga content than the channel layer 106. In an embodiment, the barrier layer 108 may be undoped or unintentionally doped as previously described with respect to the channel layer 106. The barrier layer 108 may have any dopant concentration as previously described with respect to the channel layer 106. In embodiments, the barrier layer 108 and the channel layer 106 may have substantially the same concentration or different dopant concentrations. In another embodiment, at least a portion of the barrier layer 108 may be doped with a p-type dopant that may improve contact resistance; however, the lower contact resistance may be accompanied by an increase in sheet resistance associated with the 2DEG110 at the interface between the channel layer 106 and the barrier layer 108.

The barrier layer 108 may comprise a single film or multiple films. When the barrier layer 108 includes multiple films, the aluminum content may remain substantially the same or increase with increasing distance from the channel layer 106. As the aluminum content in the barrier layer 108 increases, the thickness of the barrier layer 108 may be relatively thin. In one embodiment, the barrier layer 108 has a thickness of at least 10nm, and in another embodiment, the barrier layer 108 has a thickness of at most 150 nm. In a particular embodiment, the barrier layer 108 has a thickness in the range of 20nm to 90 nm.

The buffer layer 104, the channel layer 106, and the barrier layer 108 are formed using epitaxial growth techniques, and thus at least a portion of the barrier layer 108, the channel layer 106, and the buffer layer 104 may be monocrystalline. In one embodiment, the metal-containing film can be formed using metal organic chemical vapor deposition.

The gate electrode 124 may comprise a III-V semiconductor material. Examples of such materials may include p-type semiconductor materials. In an embodiment, the gate electrode 124 may includeP-type doped Al_cGa₍₁-_c)N, wherein c is more than or equal to 0 and less than or equal to 1. In a particular embodiment, the gate electrode 124 includes a p-type dopant, such as Mg, Zn, Cd, and the like. In another embodiment, the dopant concentration in the gate electrode 124 may have at least 1 × 10¹⁸Atom/cm³The dopant concentration of (c). In another embodiment, the dopant concentration is at most 1X 10²¹One atom per cubic centimeter. The thickness of the gate electrode 124 is in the range of 20nm to 300 nm.

The gate electrode layer for gate electrode 124 may be formed using any technique that may be used to form channel layer 106 or barrier layer 108. The p-type dopant may be incorporated in situ or introduced into the film after deposition. The gate electrode layer may be patterned to form a gate electrode 124. The 2DEG110 is positioned along the interface between the channel layer 106 and the barrier layer 108, except under the gate 124. Thus, the transistor formed is an enhancement mode HEMT. Gate electrode 124 has a drain side sidewall 1242, a source side sidewall 1246, a top surface 1244 and a bottom surface 1248. Drain-side sidewall 1242 and top surface 1244 intersect at an upper drain-side corner, and drain-side sidewall 1242 and bottom surface 1248 intersect at a lower drain-side corner. The source-side sidewall 1246 and top surface 1244 intersect at an upper source-side corner, and the source-side sidewall 1246 and bottom surface 1248 intersect at a lower source-side corner. The importance of the surfaces and corners will be described later in this specification. The portion of the blocking layer 108 not covered by the gate electrode 124 is referred to herein as an access region and includes a drain side access region 132 and a source side access region 136.

As shown in fig. 2, a lower dielectric film 242 is formed over the gate electrode 124 and the barrier layer 108. The lower dielectric film 242 may be a negatively charged film. The negative charge within the negatively charged film can result from (1) a fixed negative charge at the interface between such film (e.g., lower dielectric film 242) and an immediately adjacent film or layer closer to the 2DEG (e.g., barrier layer 108) or (2) a negative charge within the bulk of such film (e.g., lower dielectric film 242). Thus, electrons are repelled from the interface between the channel layer 106 and the barrier layer 108. The 2DEG210 is located similarly to the 2DEG110 and has a higher sheet resistance than the 2DEG110(lower conductivity). In an embodiment, the lower dielectric film 242 may include a nitrogen-containing compound. When the material of the lower dielectric film 242 includes oxynitride, the atomic content of N in the oxynitride may be larger than the atomic content of O in the oxynitride. The lower dielectric film 242 may include Si₃N₄、SiO_kN_l(where k is<1)、AlN、AlO_rN_s(wherein r is<s), or another nitrogen-containing dielectric material suitable for producing a negatively charged film.

The thickness of the lower dielectric film 242 is sufficient to affect the sheet resistance of the 2 DEG. The lower dielectric film 242 contacts sidewalls 1242 and 1246 and a top surface 1244 of the gate electrode 124. In an embodiment, the thickness of the lower dielectric film 242 is at least 1 nm. The sheet resistance of the 2DEG increases as the thickness of the lower dielectric film 242 increases until the thickness is greater than 10 nm. Further increases in thickness may be used; however, such increased thickness will not significantly increase sheet resistance. In embodiments, the thickness may be at most 50nm, at most 25nm, or at most 15 nm. The lower dielectric film 242 may be formed using Plasma Enhanced Atomic Layer Deposition (PEALD) or Low Pressure Chemical Vapor Deposition (LPCVD). The lower dielectric film 242 may be annealed at a temperature in the range of 400 c to 800 c for a time in the range of 2 minutes to 120 minutes, if needed or desired. A variety of different gases may be used during annealing. The annealing gas may include ammonia (NH)₃) Hydrogen (H) with or without inert gases such as noble gases₂) Oxygen (O)₂) And the like.

As shown in fig. 3, mask features 342 are formed over the lower dielectric film 242 and the exposed portions of the lower dielectric film 242 are removed. The remaining portion of the lower dielectric film 242 covers the sidewalls 1242 and 1246 and top surface 1244 of the gate electrode 124 and includes a drain-side extension region 2422 that covers the drain-side access region 132 of the barrier layer 108 and extends laterally toward the location where the drain electrode will be subsequently formed. When the drain-side sidewalls 1242, the top surface 1244, and the upper drain-side corners of the gate electrode 124 are covered, the sub-threshold slope of the HEMT (more uniform when the transistor is on) can be improved compared to the absence of the lower dielectric film 242 at the top surface 1244 and the upper corners of the gate electrode 124. More information about the drain-side extension 2422 is provided later in this specification with respect to a subsequently formed gate field plate. In another embodiment shown and described later in this specification, the lower dielectric film 242 may have a source side extension region that overlies the source side access region 136 and extends laterally toward where the source electrode will be subsequently formed. After the lower dielectric film 242 is patterned, the mask features are removed.

As shown in fig. 4, an upper dielectric film 444 is formed over the lower dielectric film 242 and the barrier layer 108. The upper dielectric film 444 may be a positively charged film. The positive charge within the positively charged film can be created by (1) a fixed positive charge at the interface between such film (e.g., upper dielectric film 444) and an immediately adjacent film or layer closer to the 2DEG (e.g., barrier layer 108) or (2) a positive charge within the bulk of such film (e.g., upper dielectric film 444). Accordingly, electrons may be attracted to the interface between the channel layer 106 and the barrier layer 108. The 2DEG 410 has a lower sheet resistance (higher conductivity) than the 2DEG 210. The 2DEG 410 may have substantially the same or lower sheet resistance than the 2DEG 110. In an embodiment, the upper dielectric film 444 may include an oxygen-containing compound. When the material of the upper dielectric film 444 includes oxynitride, the atomic content of O in the oxynitride may be larger than the atomic content of N in the oxynitride. The upper dielectric film 444 may include Al₂O₃、AlO_tN_u(where t is>u)、SiO₂、HfO₂、SiO_mN_n(wherein m is>n) or another oxygen-containing dielectric material suitable for producing positively charged films.

The thickness of the upper dielectric film 444 is sufficient to affect the sheet resistance of the 2 DEG. In an embodiment, the thickness of the upper dielectric film 444 is at least 1 nm. The sheet resistance decreases as the thickness of the upper dielectric film 444 increases until the thickness is greater than 10 nm. Further increases in thickness may be used; however, such increased thickness does not significantly reduce sheet resistance. In embodiments, the thickness may be at most 50nm, at most 25nm, or at most 15 nm. The upper dielectric film 444 may be formed using Plasma Enhanced Atomic Layer Deposition (PEALD) or depositing a thin film of metal and thermally oxidizing the metal. Unlike the lower dielectric film 242, the upper dielectric film 444 covers allRegions 132 and 136 are accessed and are not patterned at this point in the process. The upper dielectric film 444 can be annealed at a temperature in the range of 400 c to 800 c for a time in the range of 2 minutes to 120 minutes, if needed or desired. A variety of different gases may be used during annealing. The annealing gas may include ammonia (NH)₃) Hydrogen (H) with or without inert gases such as noble gases₂) Oxygen (O)₂) And the like. In certain embodiments, the lower dielectric film 242 may not be annealed prior to forming the upper dielectric film 444, and both dielectric films 242 and 444 may be annealed during the same anneal.

Fig. 5 shows the workpiece after formation of an interlayer dielectric (ILD) layer 500, a drain electrode 522, and a source electrode 526. An ILD layer 500 may be formed over the upper dielectric film 444. The ILD layer 500 may comprise an oxide, nitride, or oxynitride and comprise one film or more than one film. The ILD layer 500 may have a thickness in the range of 50nm to 500 nm.

The ILD layer 500 may be patterned to define contact openings 502 and 506 for the drain electrode 522 and the source electrode 526. Contact openings 502 and 506 may extend through ILD layer 500 and dielectric films 242 and 444. In an embodiment, contact openings 502 and 506 fall on barrier layer 108. In another embodiment, the contact openings 502 and 506 may extend through a portion, but not the entire thickness, of the barrier layer 108, or through the entire thickness of the barrier layer 108 and in contact with the channel layer 106. In a particular embodiment, the contact openings 502 and 506 are formed such that portions of the barrier layer 108 are disposed between the channel layer 106 and the drain and source electrodes 522 and 526. The thickness of barrier layer 108 under drain electrode 522 and source electrode 526 may be different than the thickness of barrier layer 108 under bottom surface 1248 of gate electrode 124.

Conductive layers for the drain electrode 522 and the source electrode 526 are formed over the ILD layer 500 and within the contact openings 502 and 506. The conductive layer may comprise a single film or multiple films. In one embodiment, the conductive layer may include an adhesive film and a barrier film. Such films may comprise Ta, TaSi, Ti, TiW, TiSi, TiN, etc. The conductive layer may further include a conductive film. The body film may comprise Al, Cu, or another material that is more conductive than other films within the conductive layer. In one embodiment, the body film can comprise at least 90 wt.% Al or Cu. The body film can have a thickness at least as thick as the other films within the conductive layer. In one embodiment, the thickness of the body film is in the range of 20nm to 900nm, and in a more specific embodiment, in the range of 50nm to 500 nm. More or fewer films may be used in the conductive layer. The number and composition of the films within the conductive layer may depend on the needs or desires of a particular application. After reading this specification, the skilled person will be able to determine the composition of the conductive layer modulated to suit his device. The conductive layer is patterned to form a drain electrode 522 and a source electrode 526.

Fig. 6 shows the workpiece after formation of another ILD layer 600, conductive members 622 and 626, and gate interconnect 624. The insulating layer 600 may have any composition, number of films, and thickness as previously described with respect to the ILD layer 500. The ILD 600 may have the same composition or a different composition, the same or a different number of films, and the same or a different thickness than the ILD layer 500.

The ILD layer 600 may be patterned to define openings for the conductive members 622 and 626 and the gate interconnect 624. Contact openings for conductive members 622 and 626 extend through ILD layer 600 to drain electrode 522 and source electrode 526. Contact openings for gate interconnect 624 may extend through ILD layers 500 and 600 and dielectric films 242 and 444. As can be seen in fig. 6, the contact openings for gate interconnect 624 are laterally offset such that dielectric films 242 and 444 cover the upper drain-side and upper source-side corners of gate electrode 124 and a portion of top surface 1244. The embodiments described herein have a better subthreshold slope compared to a self-aligned gate process (where the upper corners are not covered by a dielectric film having a relatively negative charge) because the lower dielectric film 242 helps to cancel holes (positive charge carriers) in the gate electrode 124.

Conductive layers for the conductive members 622 and 626 and the gate interconnect 624 are formed over the ILD layer 600 and within the contact opening. The conductive layers for the conductive members 622 and 626 and the gate interconnect 624 may have any composition, number of films, and thickness as previously described with respect to the conductive layers for the drain electrode 522 and the source electrode 526. The conductive layers for the conductive members 622 and 626 and the gate interconnect 624 may have the same composition or different compositions, the same or different numbers of films, and the same or different thicknesses than the conductive layers for the drain electrode 522 and the source electrode 526. The conductive layer is patterned to form conductive members 622 and 626 and gate interconnect 624.

In this embodiment, the gate interconnect 624 includes a gate field electrode 6242. Each of the drain-side extension 2422 and the gate field electrode 6242 of the lower dielectric film 242 extends laterally over the drain-side access region 132. As used herein, the lateral direction or lateral direction is substantially parallel to the interface between the channel layer 106 and the barrier layer 108. In an implementation, each drain-side extension region 2422 and gate field electrode 6242 extends laterally up to 8 microns, up to 6 microns, or up to 4 microns over the drain-side access region 132. When expressed as a fraction, each drain-side extension region 2422 and gate field plate may extend laterally at most 0.5 times, at most 0.4 times, or at most 0.3 times the distance of the drain-side access region 132 between the gate electrode 124 and the drain electrode 522. In an embodiment, the distance that the drain-side extension region 2422 and the gate field electrode 6242 extend laterally over the drain-side access region 132 may be substantially the same. In an embodiment, the gate field electrode 6242 may extend laterally over the drain-side access region 132 a distance in the range of 0.5 to 2.0 times the distance the drain-side extension 2422 of the lower dielectric film 242 extends laterally over the drain-side access region 132. In a particular implementation, the drain-side extension region 2422 and the gate field electrode 6242 extend laterally a substantially same distance above the drain-side access region 132.

In another embodiment, the gate field electrode 6242 may be separate from the gate interconnect 624. For example, an intervening conductive member may provide a gate interconnect, and another conductive member may include a gate field electrode 6242. In another embodiment, an intervening conductive member may be located between the gate electrode 124 and another conductive member including the gate interconnect and the gate field electrode. In all embodiments, the gate field electrode 6242 is not required. The gate field electrode 6242 is an optional feature that may help influence the electric field near the gate electrode 124 along the drain side of the transistor.

Fig. 7 shows the workpiece after formation of another ILD layer 700 and conductive members 722 and 726. The insulating layer 700 may have any composition, number of films, and thickness as previously described with respect to the ILD layer 500. The ILD 700 may have the same composition or a different composition, the same or a different number of films, and the same thickness or a different thickness than each of the ILD layers 500 and 600. The ILD layer 700 may be patterned to define openings for the conductive members 722 and 726. Contact openings for conductive members 722 and 726 extend through the ILD layer 700 to conductive members 622 and 626 connected to the drain electrode 522 and the source electrode 526, respectively.

A conductive layer for the conductive members 722 and 726 is formed over the ILD layer 700 and within the contact openings. The conductive layers for the conductive members 722 and 726 may have any composition, number of films, and thickness as previously described with respect to the conductive layers of the drain electrode 522 and the source electrode 526. The conductive layers for the conductive members 722 and 726 may have the same composition or different compositions, the same or different numbers of films, and the same or different thicknesses than the conductive layers for the drain and source electrodes 522 and 526 and the conductive members 622 and 626. The conductive layer is patterned to form conductive members 722 and 726.

In this embodiment, the conductive member 722 includes a drain field electrode 7222 extending laterally over the drain-side access region 132, and the conductive member 726 includes a source field electrode 7262 extending laterally over the drain-side access region 132. The space between the drain and source field electrodes 7222 and 7262 is sufficient to provide little chance of breakdown or leakage current between the drain and source terminals coupled to the conductive members 722 and 726. Similar to the gate field electrode 6242, the drain and source field electrodes 7222, 7262 affect the electric field along and below the drain-side access region 132. The source field electrode 7262 extends laterally further over the drain-side access region 132 than the gate field electrode 6242, and the drain electrode 522 is closer to the source field electrode 7262 than the gate field electrode 6242.

Fig. 8 and 9 show a workpiece having a patterned opening to the gate electrode 124 according to another embodiment. After forming the upper dielectric film 444 as shown in fig. 4, the lower dielectric film 242 and the upper dielectric film 444 above the gate electrode 124 may be patterned to define an opening 824 to the gate electrode 124. In the embodiment shown, the remaining portions of the dielectric films 242 and 444 form a lattice that defines openings 824. After the ILD layer 500 is formed, the ILD layer 500 is patterned to form source contact openings 506 and gate contact openings 904. A conductive layer is formed and patterned to form a source electrode 526 and a gate interconnect 924. In this embodiment, the gate interconnect 924 is formed from the same conductive layer as the source electrode 526. In another embodiment, the gate interconnect 924 may be formed at a different height than the source electrode 526. Gate interconnect 924 includes gate field electrode 9242, which may have any composition and dimensions as previously described with respect to gate interconnect 624 and gate field electrode 6242. The drain electrode 522 may also be formed; however, fig. 8 and 9 are on a different scale than fig. 5-7 to better illustrate the features in fig. 8 and 9.

Opening 824 reduces the amount of contact area between gate electrode 124 and gate interconnect 924 compared to the contact opening for gate interconnect 624. The reduced contact area increases the resistance between the gate terminal coupled to the gate interconnect 924 and the gate electrode 124. When the HEMT is on or the HEMT is driven by a negative gate voltage (V)_GS<0) The increased resistance may help to reduce the gate current (I) when off_G)。

In another embodiment, as shown in fig. 10, the barrier layer 108 may include a recess 1032 within the drain-side access region 132. The recesses 1032 can help to increase the threshold voltage of the HEMT formed. The recesses 1032 may have a depth that extends through at most 60%, at most 40%, or at most 20% of the thickness of the barrier layer 108. The recess 1032 may extend laterally into the drain side access region 132 any distance as previously described with respect to the drain side extension region 2422 of the lower dielectric film 242. In a particular embodiment, the lower dielectric film 242 may not be formed, and the remaining process of the above beginning of the formation of the dielectric film 444 may be performed as described above. In another particular embodiment, the lower dielectric film 242 with or without the drain side extension regions 2422 may be formed within the recesses 1032, as shown in fig. 11. The recesses 1032 may extend laterally approximately the same distance into the drain-side access region 132 as compared to the drain-side extension region 2422. In another embodiment, the drain-side extension region 2422 may extend laterally a significantly different distance into the drain-side access region 132 than the drain-side extension region 2422. When expressed as a fraction, the recess 1032 may extend laterally into the drain-side access region 132 a distance in a range of 0.5 to 2.0 times the distance that the drain-side extension 2422 extends laterally over the drain-side access region 132. The 2DEG 1110 is located below the drain-side extension 2422 and has a higher sheet resistance than the 2DEG 410. The sheet resistance of the 2DEG 1110 may be substantially the same as or significantly higher than the 2DEG 210.

Fig. 12 shows an embodiment in which the lower dielectric film 1243 includes a drain-side extension region 12432 and a source-side extension region 12436. The drain-side extension region 12432 may be used for any of the reasons previously described with respect to the extension region 2422 of the lower dielectric film 242. The source side extension region 12436 may help increase the threshold voltage of the HEMT.

Lower dielectric film 1243 can have any composition and thickness as previously described for lower dielectric film 242. The drain-side extension region 12432 may extend any distance above the drain-side access region 132. Source side extension region 12436 may extend laterally from gate electrode 124 partially or completely over source side access region 136 to source electrode 526. In an embodiment, source side extension region 12436 may extend laterally from gate electrode 124 a distance in a range of 0.1 microns to 0.2 microns. Such a distance may help increase the threshold voltage without increasing the sheet resistance of the 2DEG, which would increase the sheet resistance of the 2DEG if the source side extension region 12436 covered all of the source side access region 136. The 2DEG210 is located below the source side extension region 12436, while the 2DEG 410 is located below the portion of the source side access region 136 not covered by the source side extension region 12436.

Fig. 13 shows another embodiment, in which a gate electrode 1324 includes a body region 13244 and an extension region 13242. The extension region 13242 may help increase the sheet resistance of the 2DEG 1310 below the extension region 13242. The thickness of the extension region 13242 is sufficient to increase the sheet resistance of the 2DEG 1310, but is not so thick as to effectively eliminate the 2DEG 1310. In embodiments, the thickness of extended region 13242 is at least 5nm, at least 8nm, or at least 11nm, and in another embodiment, the thickness of extended region 13242 is at most 40nm, at most 36nm, or at most 32 nm. The extension region 13242 may extend laterally toward the drain electrode 522 any distance as previously described with respect to the extension region 2422 of the lower dielectric film 242. Thus, the drain electrode 522 is closer to the extension region 13242 than to the body region 13244. The lower dielectric film 242 is not necessary, and therefore, the lower dielectric film 242 is optional. In another implementation (not shown), another extended region of the gate electrode 1324 may extend laterally from the body region 13244 toward the source electrode 526.

Fig. 14 includes another embodiment in which a dielectric film 1444 with varying thickness can be used as an alternative to the upper dielectric film 242 and the lower dielectric film 444. The dielectric film 1444 is not drawn to scale to improve understanding of the concept. In the embodiment shown, dielectric film 1444 can be a negatively charged film and include any of the materials previously described with respect to lower dielectric film 242. Over drain-side access region 132, dielectric film 1444 is thicker closer to gate electrode 124 and thinner closer to drain electrode 522. The change in thickness results in a change in electron density within the 2DEG 1410. For the 2DEG 1410, near the gate electrode 124, the electron density is lower and the sheet resistance is higher, and near the drain electrode 522, the electron density is higher and the sheet resistance is lower.

In another embodiment (not shown), dielectric film 1444 can be a positively charged film and include any of the materials described above with respect to upper dielectric film 444. Over drain-side access region 132, dielectric film 1444 is thinner closer to gate electrode 124 and thicker closer to drain electrode 522. The change in thickness results in a change in electron density within the 2DEG 1410. For the 2DEG 1410, near the gate electrode 124, the electron density is lower and the sheet resistance is higher, and near the drain electrode 522, the electron density is higher and the sheet resistance is lower.

When the thickness of the negatively or positively charged dielectric film is greater than 10nm or more, the change in electron density of the 2DEG 1410 becomes insignificant with further increase in the dielectric film thickness. When dielectric film 1444 is a negatively charged film, its thickness may be at least 10nm or more in the vicinity of gate electrode 124, and may have a thickness of 1nm near drain electrode 522. Dielectric film 1444 may or may not extend completely to drain electrode 522. When dielectric film 1444 is positively charged, its thickness may be at least 10nm or more near drain electrode 522, and may have a thickness of 1nm near gate electrode 124. Dielectric film 1444 may or may not extend completely to gate electrode 124. The thickness of the dielectric film 1444 may vary as a continuous function of distance or may vary in discrete steps.

In yet another embodiment, dielectric film 1444 and its varying thickness can be used with upper dielectric film 444 when dielectric film 1444 (as a lower dielectric film) is a negatively charged film, or with lower dielectric film 242 when dielectric film 1444 (as an upper dielectric film) is a positively charged film.

In another embodiment, gate electrode 124 may be replaced by a gate dielectric layer and a metal gate electrode. The gate dielectric layer may comprise one or more films of electrically insulating nitride or oxide. The thickness of the gate dielectric layer may be in the range of 2nm to 40 nm. The gate electrode may include one or more films of metal, metal alloy, metal silicide, or the like. The film closest to the gate dielectric layer may have a work function that helps provide the desired threshold voltage for the HEMT. The gate electrode may include Ti, TiN, Al, Pd, Pt, W, Au, Ni, or a stack thereof, or any combination thereof, and has a thickness in a range of 50nm to 500 nm. Other compositions and thicknesses for the gate dielectric layer and the gate electrode may be used without departing from the concepts described herein. The process flow may continue to form the lower dielectric film 242 of fig. 2 and other subsequently formed features as previously described.

Embodiments as described herein may contribute to the performance of a transistor. The extension region of the lower dielectric film can be partiallyThe section increases the sheet resistance of the 2DEG near the gate electrode and allows faster depletion of charge. The locally higher sheet resistance can be designed so that the R of the transistor is_DSONCannot be increased more than 1ohm. The upper dielectric film may help reduce the sheet resistance of the 2DEG to help offset some of the increased sheet resistance corresponding to the lower dielectric film. C_GDMay be lower and provide a lower miller ratio. Output capacitance (C) of HEMT_OSS) Lower. Thus, the HEMT has improved switching characteristics. The lower dielectric film helps to achieve a more uniform sub-threshold slope during turn-on and increases the gate breakdown voltage.

Particular embodiments may provide other advantages or alternatives to the design of HEMTs. When the HEMT is on, the contact area between the gate electrode and the gate interconnect can be reduced to reduce the gate current. Such an embodiment may be useful when the gate electrode contacts the barrier layer or the channel layer. A recess within the barrier layer near the gate electrode may be used to help increase the threshold voltage of the HEMT. The recess may or may not include an extension region of the lower dielectric film.

The lower dielectric film may include a source side extension region over the source side access region of the blocking layer. The source side extension region may help increase the threshold voltage of the HEMT. In a particular embodiment, the source-side extension may extend only partially laterally toward the source electrode, and thus, the 2DEG near the source electrode may have a lower sheet resistance than the source-side extension that extends fully to the source electrode.

In yet another embodiment, the gate electrode may include a body region and an extension region. The extension region for the lower dielectric film may or may not be used. The lower dielectric film along the sidewalls and top surface of the gate electrode can still be used to protect the upper drain-side and source-side corners of the gate electrode, which can help improve the subthreshold characteristics of the HEMT.

Many different aspects and embodiments are possible. Some of those aspects and embodiments are described below. Upon reading this specification, skilled artisans will appreciate that those aspects and embodiments are exemplary only, and do not limit the scope of the invention. Implementations may be in accordance with any one or more of the items listed below.