阅读说明：本技术 多跨阻恒定带宽超低噪声tia (Multi-transimpedance constant-bandwidth ultra-low noise TIA ) 是由 李景虎 于建海 涂航辉 于 2020-07-27 设计创作，主要内容包括：多跨阻恒定带宽超低噪声TIA,属于光通信芯片技术领域,本发明为解决常用的可选跨阻TIA带宽和噪声变化大,进而影响灵敏度和输出信号的线性度,最终无法保证TIA整体性能的问题。本发明在跨阻R<Sub>F1</Sub>两端并联电容C1,在跨阻R<Sub>F2</Sub>两端并联电容C2,调整电容C1和C2的大小以满足开关S1闭合前和闭合后TIA带宽恒定。在跨阻R<Sub>F1</Sub>两端进一步并联电路结构：电阻R3和电容C5串联后并联在电容C4的两端,再与电阻R2串联后并联在跨阻R<Sub>F1</Sub>两端；在跨阻R<Sub>F2</Sub>两端进一步并联电路结构：电容C3和电阻R1串联后并联在跨阻R<Sub>F2</Sub>两端；通过调整电容C1～C5的大小来满足开关S1闭合前和闭合后TIA带宽恒定。(The invention discloses a multi-transimpedance constant-bandwidth ultra-low-noise TIA (TIA), belongs to the technical field of optical communication chips, and aims to solve the problems that the bandwidth and noise variation of a commonly-used selectable transimpedance TIA are large, so that the sensitivity and the linearity of an output signal are influenced, and the overall performance of the TIA cannot be ensured finally. The invention is in trans-resistance R F1 A capacitor C1 connected in parallel across the resistor R F2 The capacitor C2 is connected in parallel at two ends, and the sizes of the capacitors C1 and C2 are adjusted to meet the requirement that the TIA bandwidth is constant before and after the switch S1 is closed. At trans-resistance R F1 The two ends are further connected with a circuit structure in parallel: the resistor R3 and the capacitor C5 are connected in series and then connected in parallel at two ends of the capacitor C4, and then connected in series with the resistor R2 and then connected in parallel at the transimpedance R F1 Two ends; at trans-resistance R F2 The two ends are further connected with a circuit structure in parallel: the capacitor C3 and the resistor R1 are connected in series and then connected in parallel to the transimpedance R F2 Two ends; the TIA bandwidth is constant before and after the switch S1 is closed by adjusting the sizes of the capacitors C1-C5.)

1. The multi-transimpedance constant-bandwidth ultra-low noise TIA is characterized in that the transimpedance R_F1A capacitor C1 connected in parallel across the resistor R_F2The capacitor C2 is connected in parallel at two ends, and the sizes of the capacitors C1 and C2 are adjusted to meet the requirement that the TIA bandwidth is constant before and after the switch S1 is closed.

2. The TIA of claim 1, wherein R is the transimpedance_F1The two ends are further connected with a circuit structure in parallel: the resistor R3 and the capacitor C5 are connected in series and then connected in parallel at two ends of the capacitor C4, and then connected in series with the resistor R2 and then connected in parallel at the transimpedance R_F1Two ends;

at trans-resistance R_F2The two ends are further connected with a circuit structure in parallel: the capacitor C3 and the resistor R1 are connected in series and then connected in parallel to the transimpedance R_F2Two ends;

the TIA bandwidth is constant before and after the switch S1 is closed by adjusting the sizes of the capacitors C1-C5.

3. The TIA of claim 1 or 2, further comprising a frequency compensation structure, wherein the frequency compensation structure comprises PMOS transistors MP 1-MP 4, NMOS transistors MN 1-MN 3, resistors R4-R5 and capacitors C6-C7;

the grid electrode of the PMOS tube MP3 and the grid electrode of the PMOS tube MP4 are simultaneously connected with a bias voltage input end VB, and the source electrode of the PMOS tube MP3 and the source electrode of the PMOS tube MP4 are simultaneously connected with a power supply VCC;

the grid electrode of the PMOS tube MP1 is connected with the signal input end VN, and the source electrode of the PMOS tube MP1 and the source electrode of the PMOS tube MP2 are simultaneously connected with the drain electrode of the PMOS tube MP 3; the drain electrode of the PMOS tube MP1 is simultaneously connected with the drain electrode and the grid electrode of the NMOS tube MN1 and the grid electrode of the NMOS tube MN 2; the sources of the NMOS tubes MN 1-MN 3 are simultaneously connected with GND;

the grid of the PMOS tube MP2 is connected with the signal input end VP, the drain of the PMOS tube MP2 is simultaneously connected with the drain of the NMOS tube MN2, one end of the switch S2, one end of the capacitor C6 and the grid of the NMOS tube MN3, the other end of the switch S2 is connected with one end of the capacitor C7, the other end of the capacitor C7 is connected with one end of the resistor R5, the other end of the capacitor C6 is connected with one end of the resistor R4, and the drain of the PMOS tube MP4, the drain of the NMOS tube MN3, the other end of the resistor R4 and the other end of the resistor R5 are simultaneously connected with the output end OUTP;

the switch S2 operates in synchronization with the switch S1.

Technical Field

The invention belongs to the technical field of optical communication chips, and relates to a technology for keeping a bandwidth constant in trans-impedance and trans-impedance switching of a TIA (transimpedance amplifier) with multiple trans-impedances.

Background

At a receiving end of an optical fiber communication integrated circuit, an optical signal needs to be converted into a current signal through a Photodiode (PD), and then the current signal is converted into a voltage signal through a transimpedance amplifier (TIA). Inside a linear TIA chip, a multi-transimpedance mode is generally designed to increase the dynamic range of the TIA to meet the requirements of various application scenarios. However, the variation of the transimpedance value inevitably changes the whole bandwidth of the chip greatly, the input equivalent noise is also deteriorated, and the harsh requirements of application scenes cannot be met. Therefore, a special circuit structure is used in the TIA, and the multi-impedance constant-bandwidth ultra-low noise TIA is designed.

FIG. 1 shows a schematic diagram of a conventional multi-transimpedance TIA circuit having two transimpedance R_F1、R_F2Wherein R is_F2In series with switch S1. In fig. 1, the purpose of changing the TIA transimpedance is achieved by closing the switch S1.

Switch S1 is opened, R in FIG. 1_F1Is the feedback resistance of an ideal voltage amplifier-A.

Because:

V_X＝V_OUTP/(-A) (1)

(V_OUTP+V_OUTP/A)/R_F1＝-I_in-(V_OUTP/A)sC_D(2)

namely:

the feedback amplifier provides a feedback signal of about R_F1Has a time constant of R_F1C_D/(A + 1). Thus, the bandwidth of the dominant pole is equal to:

the TIA transimpedance value of FIG. 1 will become closed switch S1The bandwidth of the dominant pole will therefore become:

the bandwidth before the switch S1 is closed is the bandwidth after the switch S1 is closed

And is approximately equal to the noise before and after the switch S1 is closedAnd (4) doubling.

In the above formula, A is the gain of operational amplifier, C_DIs the input capacitance of a photodiode, V_XIs the voltage of node X, V_OUTPFor TIA output voltage, I_inThe output current value of the photodiode equivalent current source.

From the above formula, it can be seen that the bandwidth is increased and the noise is also increased after the transimpedance value is decreased. This will result in different transimpedance values for the same rate input signal, which will greatly affect the sensitivity of the TIA and the linearity of the output signal. The circuit structure cannot meet the performance requirement of the high-bandwidth TIA.

Disclosure of Invention

The invention aims to solve the problems that the bandwidth and noise change of a common optional transimpedance TIA are large, the sensitivity and the linearity of an output signal are further influenced, and the overall performance of the TIA cannot be ensured finally, and provides a multi-transimpedance constant-bandwidth ultra-low-noise TIA.

The multi-transimpedance constant-bandwidth ultra-low noise TIA is applied to transimpedance R_F1A capacitor C1 connected in parallel across the resistor R_F2The capacitor C2 is connected in parallel at two ends, and the sizes of the capacitors C1 and C2 are adjusted to meet the requirement that the TIA bandwidth is constant before and after the switch S1 is closed.

Preferably, at transimpedance R_F1The two ends are further connected with a circuit structure in parallel: the resistor R3 and the capacitor C5 are connected in series and then connected in parallel at two ends of the capacitor C4, and then connected in series with the resistor R2 and then connected in parallel at the transimpedance R_F1Two ends;

at trans-resistance R_F2The two ends are further connected with a circuit structure in parallel: the capacitor C3 and the resistor R1 are connected in series and then connected in parallel to the transimpedance R_F2Two ends;

the TIA bandwidth is constant before and after the switch S1 is closed by adjusting the sizes of the capacitors C1-C5.

Preferably, the frequency compensation structure comprises PMOS tubes MP 1-MP 4, NMOS tubes MN 1-MN 3, resistors R4-R5 and capacitors C6-C7;

the grid electrode of the PMOS tube MP3 and the grid electrode of the PMOS tube MP4 are simultaneously connected with a bias voltage input end VB, and the source electrode of the PMOS tube MP3 and the source electrode of the PMOS tube MP4 are simultaneously connected with a power supply VCC;

the grid electrode of the PMOS tube MP1 is connected with the signal input end VN, and the source electrode of the PMOS tube MP1 and the source electrode of the PMOS tube MP2 are simultaneously connected with the drain electrode of the PMOS tube MP 3; the drain electrode of the PMOS tube MP1 is simultaneously connected with the drain electrode and the grid electrode of the NMOS tube MN1 and the grid electrode of the NMOS tube MN 2; the sources of the NMOS tubes MN 1-MN 3 are simultaneously connected with GND;

the grid of the PMOS tube MP2 is connected with the signal input end VP, the drain of the PMOS tube MP2 is simultaneously connected with the drain of the NMOS tube MN2, one end of the switch S2, one end of the capacitor C6 and the grid of the NMOS tube MN3, the other end of the switch S2 is connected with one end of the capacitor C7, the other end of the capacitor C7 is connected with one end of the resistor R5, the other end of the capacitor C6 is connected with one end of the resistor R4, and the drain of the PMOS tube MP4, the drain of the NMOS tube MN3, the other end of the resistor R4 and the other end of the resistor R5 are simultaneously connected with the output end OUTP;

the switch S2 operates in synchronization with the switch S1.

The invention has the beneficial effects that: the invention provides a circuit structure of a multi-transimpedance invariant bandwidth ultra-low noise TIA (three-dimensional interactive application), which solves the problems of abrupt bandwidth change and large noise change when a common multi-transimpedance TIA circuit switches transimpedance, and finally influences the overall performance of the TIA, and passes simulation result verification.

The multi-transimpedance invariant-bandwidth ultra-low noise TIA provided by the invention can ensure that the bandwidth of the multi-transimpedance TIA is constant, the noise is reduced to the minimum, the sensitivity and the linearity of the TIA are ensured while the dynamic range of the TIA is increased, and the performance requirements of the TIA in multiple fields are met.

Drawings

FIG. 1 is a schematic diagram of a conventional optional transimpedance TIA circuit;

fig. 2 is a schematic diagram of a TIA circuit in a first embodiment;

fig. 3 is a schematic diagram of a TIA circuit of a second embodiment;

FIG. 4 is a structural diagram of frequency compensation required to be used in cooperation with the inside of an amplifier-A in the present invention;

FIG. 5 is an AC curve for different transimpedance values;

fig. 6 shows equivalent input noise curves for different transimpedance values.

Detailed Description

The following detailed description of the embodiments of the present invention will be provided with reference to the drawings and examples, so that how to apply the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.