阅读说明：本技术 差分放大器 (Differential amplifier ) 是由 蔡宗玲 张书麟 陈志龙 于 2019-04-15 设计创作，主要内容包括：本发明公开了一种差分放大器,包含一输入电路、一检测和控制电路、以及一输出电路。该输入电路依据一差分输入信号的电压以及一偏压点的电压来输出输入电流至两个输出点。该检测和控制电路依据一控制偏压以及该偏压点的电压来输出补偿电流至该两个输出点,其中该偏压点的电压与该补偿电流相关于该差分输入信号的电压。该输出电路耦接该两个输出点,并依据该输入电流与该补偿电流的和输出一差分输出信号。通过该检测和控制电路输出该补偿电流,该差分放大器能够在该输入电流不足或为零时,避免进入一锁死状态。(The invention discloses a differential amplifier, which comprises an input circuit, a detection and control circuit and an output circuit. The input circuit outputs input current to two output points according to the voltage of a differential input signal and the voltage of a bias point. The detection and control circuit outputs compensation current to the two output points according to a control bias voltage and the voltage of the bias point, wherein the voltage of the bias point and the compensation current are related to the voltage of the differential input signal. The output circuit is coupled to the two output points and outputs a differential output signal according to the sum of the input current and the compensation current. By outputting the compensation current through the detection and control circuit, the differential amplifier can avoid entering a lock-up state when the input current is insufficient or zero.)

1. A differential amplifier, comprising:

the input circuit is used for outputting input current to two output points according to the voltage of a differential input signal and the voltage of a bias point;

a detection and control circuit for outputting a compensation current to the two output points according to a control bias voltage and a voltage of the bias point, wherein the voltage of the bias point and the compensation current are related to the voltage of the differential input signal; and

and the output circuit is coupled with the two output points and used for outputting a differential output signal according to the sum of the input current and the compensation current.

2. The differential amplifier of claim 1, further comprising: a level decision circuit for generating a control voltage according to the differential output signal; and a load circuit for determining a DC of the differential output signal according to the control voltage.

3. The differential amplifier of claim 1, wherein the input current is proportional to the voltage of the differential input signal or the input current is a minimum input current, the compensation current is proportional to the voltage of the differential input signal or the compensation current is a maximum compensation current, when the voltage of the differential input signal reaches a voltage threshold.

4. The differential amplifier of claim 1, further comprising: a bias circuit for providing an input bias current to the input circuit and the detection and control circuit, wherein the compensation current and the input current are both derived from the input bias current.

5. The differential amplifier of claim 1, wherein the sum of the input current and the compensation current is a first current when the voltage of the differential input signal does not reach a voltage threshold; when the voltage of the differential input signal reaches the voltage threshold, the sum of the input current and the compensation current is a second current; the second current is not greater than the first current, and the second current is greater than zero.

6. The differential amplifier as in claim 1, wherein said input circuit is connected in parallel with said detection and control circuit, said input circuit comprising two input transistors for outputting said input current according to a voltage of said differential input signal, said detection and control circuit comprising two control transistors for outputting said compensation current according to said control bias.

7. A differential amplifier, comprising:

a bias circuit for providing an input bias current to an input circuit and a detection and control circuit;

the input circuit is used for outputting input current to two output points according to the voltage of a differential input signal, wherein the input current is derived from the input bias current;

the detection and control circuit is used for outputting compensation current to the two output points according to the voltage of the differential input signal, wherein the compensation current is derived from the input bias current; and

and the output circuit is coupled with the two output points and used for outputting a differential output signal according to the sum of the input current and the compensation current.

8. The differential amplifier of claim 7, wherein the input current is proportional to the voltage of the differential input signal or the input current is a minimum input current, the compensation current is proportional to the voltage of the differential input signal or the compensation current is a maximum compensation current, when the voltage of the differential input signal reaches a voltage threshold.

9. The differential amplifier as in claim 8, wherein the sum of the input current and the compensation current is a first current when the voltage of the differential input signal does not reach the voltage threshold; when the voltage of the differential input signal exceeds the voltage threshold, the sum of the input current and the compensation current is a second current; the second current is equal to or less than the first current, and the second current is greater than zero.

10. A differential amplifier as claimed in claim 7 wherein said input circuit is connected in parallel with said detection and control circuit.

Technical Field

The present invention relates to amplifiers, and more particularly to differential amplifiers.

Background

In a conventional differential input and differential output amplifier (hereinafter referred to as "differential amplifier"), when an input voltage of the differential amplifier exceeds an operational range, a MOS transistor of an input stage of the differential amplifier enters a cut-off region, which may cause a bias error of a differential mode loop and a common mode loop of the differential amplifier; when the input voltage of the differential amplifier returns to normal, the differential amplifier requires additional time to adjust the loop, which causes unnecessary transient voltage variations in the additional time. In addition, the aforementioned bias error may cause a loop lock-up (dead lock), which makes the amplifier unable to operate normally; for example, when the voltage levels of the input terminals of the two transistors of the input stage of the differential amplifier are both high and the common mode feedback voltage level of the differential amplifier is low, the voltage state of the output point of the first stage of the differential amplifier is undefined (undefined), which causes malfunction of the common mode loop and leads to loop lock-up. Accordingly, there is a need to ameliorate the problems encountered with conventional differential amplifiers.

Disclosure of Invention

It is an object of the present invention to provide a differential amplifier that improves upon the prior art.

An embodiment of a differential amplifier of the present invention comprises an input circuit, a detection and control circuit, and an output circuit. The input circuit is used for outputting input current to two output points according to the voltage of a differential input signal and the voltage of a bias point. The detection and control circuit is used for outputting compensation current to the two output points according to a control bias voltage and the voltage of the bias point, wherein the voltage of the bias point and the compensation current are related to the voltage of the differential input signal. The output circuit is coupled to the two output points and is used for outputting a differential output signal according to the sum of the input current and the compensation current. By outputting the compensation current through the detection and control circuit, the differential amplifier can avoid malfunction when the input current is insufficient or zero.

Another embodiment of the differential amplifier of the present invention comprises a bias circuit, an input circuit, a detection and control circuit, and an output circuit. The bias circuit is used for providing input bias current to an input circuit and a detection and control circuit. The input circuit is used for outputting input current to two output points according to the voltage of a differential input signal, wherein the input current is derived from the input bias current. The detection and control circuit is used for outputting a compensation current to the two output points according to the voltage of the differential input signal, wherein the compensation current is derived from the input bias current. The output circuit is coupled to the two output points and is used for outputting a differential output signal according to the sum of the input current and the compensation current. By outputting the compensation current through the detection and control circuit, the differential amplifier can avoid malfunction when the input current is insufficient or zero.

The features, implementations, and technical advantages of the present invention are described in detail below with reference to the accompanying drawings.

Drawings

FIG. 1 shows an embodiment of a differential amplifier of the present invention;

FIG. 2 shows an embodiment of the bias circuit of FIG. 1;

FIG. 3 shows an embodiment of the input circuit of FIG. 1;

FIG. 4 illustrates one embodiment of the detection and control circuit of FIG. 1;

FIG. 5a shows an example of the compensation current and the input current of FIG. 1 varying with the differential input signal;

FIG. 5b shows an example of the compensation current and the input current of FIG. 1 varying with the differential input signal on the time axis;

FIG. 6a shows another example of the compensation current and the input current of FIG. 1 varying with the differential input signal;

FIG. 6b shows another example of the compensation current and the input current of FIG. 1 varying with the differential input signal on the time axis;

FIG. 7 shows an embodiment of the output circuit of FIG. 1;

FIG. 8a shows an embodiment of the level decision circuit of FIG. 1;

FIG. 8b illustrates an embodiment of the load circuit of FIG. 1;

FIG. 9 shows another embodiment of a differential amplifier of the present invention; and

FIG. 10 illustrates one embodiment of the detection and control circuit of FIG. 9.

Description of the symbols

100 differential amplifier

110 bias circuit

120 input circuit

130 detection and control circuit

140 output circuit

150 level decision circuit

160 load circuit

112 bias point

122. 124 output point

INP, INN differential input signal

OUTP, OUTN differential output signal

I_INInputting bias current

IN1, IN2 input current

IS1, IS2 Compensation currents

V_BIASControlling bias voltage

200 current mirror circuit

V_DDSupply voltage

I_REFReference current

P1-P10 PMOS transistor

I_TOTALSum of input current and compensating current

N1-N4 NMOS transistor

810 voltage division circuit

820 operational amplifier

R1, R2 resistance

V_DIVPartial pressure

V_REFReference voltage

V_CMFBCommon mode feedback voltage

900 differential amplifier

910 bias circuit

920 input circuit

930 detection and control circuit

940 output circuit

950 level determination circuit

960 load circuit

1010 voltage detector

Detailed Description

The invention discloses a differential amplifier, which can provide a compensation current when an input current is insufficient or zero so as to avoid malfunction of the differential amplifier.

Fig. 1 shows an embodiment of a differential amplifier according to the present invention. The differential amplifier 100 of fig. 1 includes a bias circuit 110, an input circuit 120, a detection and control circuit 130, an output circuit 140, a level decision circuit 150, and a load circuit 160, which are described below.

Please refer to fig. 1. The bias circuit 110 is used to provide a predetermined input bias current (I)_IN) Via a bias point 112 to the input circuit 120 and the detection and control circuit 130. FIG. 2 shows an embodiment of the bias circuit 110, including a current mirror circuit 200, where V_DDIs the supply voltage, I_REFIs a reference current. As shown in fig. 2, the current mirror circuit 200 provides the input bias current according to the reference current and a transistor size ratio (i.e., the size ratio of the transistor P1 to the transistor P3). Since the current mirror circuit 200 of fig. 2 and its equivalents are, individually, common knowledge in the art, details thereof are omitted herein.

Please refer to fig. 1. The input circuit 120 is used for outputting input currents (IN1, IN2) to two output points 122, 124 according to the voltage of a differential input signal (signal INP at the positive input terminal and signal INN at the negative input terminal) and the voltage at the bias point 112, wherein the input currents are derived from the input bias currents. FIG. 3 shows an embodiment of the input circuit 130, which includes a PMOS transistor pair (P5, P6). The PMOS transistor pair determines its own conduction state according to the voltage of the differential input signal and the voltage of the bias point 112, so as to output or stop outputting the input current to the two output points 122 and 124. Since the PMOS transistor pair of fig. 3 and its equivalents are common knowledge in the art alone, the details thereof are omitted here.

Please refer to fig. 1. The detection and control circuit 130 is connected in parallel with the input circuit 120 between the bias point 112 and the two output points 122, 124. The detection and control circuit 130 is used for controlling the bias voltage (V) according to a control bias voltage_BIAS) And bias the voltage at the point 112 to output the compensation currents (IS1, IS2) to the two output points122. 124. In one example, the bias voltage is controlled from the bias circuit 110 (e.g., the gate voltages of the PMOS transistors P1, P2, P3, and P4 of FIG. 2), wherein the voltage at the bias point 112 and the compensation current are related to the voltage of the differential input signal; for example, when the voltage of the differential input signal exceeds the normal operation interval of the input circuit 120 (the exceeding of the normal operation interval refers to when the voltages (INP, INN) of the positive and negative input terminals of the differential input signal reach a voltage threshold determined by the device characteristics of the input circuit 120 (e.g., the characteristics of the PMOS transistor pair of FIG. 3)), which is called an abnormal condition, the input circuit 120 is gradually turned off or turned off, so that the input current gradually decreases or becomes zero, at which point the voltage of the bias point 112 is higher than the voltage of the bias point 112 in a normal condition (e.g., a condition when the voltage of the differential input signal does not exceed the normal operation interval of the input circuit 120 or a condition when the voltages of the positive and negative input terminals of the differential input signal do not reach the voltage threshold), and the absolute value of the difference between the control bias voltage and the voltage of the bias point 112 is greater than a threshold voltage (e.g., a threshold voltage) (e.g., FIG. 4) Of the PMOS transistor of the detection and control circuit 130_GSWherein the gate voltage is greater than the source voltage in the normal condition to reduce or stop outputting the compensation current), so that the compensation current outputted by the detection and control circuit 130 is increased or is a fixed compensation current. FIG. 4 shows an embodiment of the detection and control circuit 130, which includes a PMOS transistor pair (P7, P8) outputting the compensation current to two output points 122, 124 according to the control bias and the voltage at the bias point 112; in one implementation example, under the normal condition, the PMOS transistor pair does not reach the conducting condition (i.e., the gate-to-source voltage | V of the PMOS transistor)_GS|<V_thIn which V is_thA threshold voltage of a PMOS transistor) is substantially non-conductive when the compensation current is zero or negligible, and in the abnormal situation the PMOS transistor is conductive when a conductive condition is reached when the compensation current is greater than zero and has a substantial effect on the differential output signal. Since the PMOS transistor pair of FIG. 4 and its equivalents are art in isolationThe general knowledge of the domain, the details of which are omitted here. It is noted that the compensation current and the input current are both derived from the input bias current; in one implementation example, the input bias current is equal to the sum (I) of the input current and the compensation current_TOTAL＝IN1+IN2+IS1+IS2＝I_IN) (ii) a In one implementation, the sum of the input current and the compensation current is greater than zero to prevent differential amplifier 100 from entering a lock-up state or other malfunctioning state. Further, it should be understood that the aforementioned control bias (V)_BIAS) The gate voltage from the bias circuit 110 or the current mirror circuit in the bias circuit 110 should not be limited, and the control bias voltage only needs to be a substantially fixed reference potential; one skilled in the art can select a reference voltage (e.g., the power supply voltage V of the differential amplifier 100) as desired_DDThe voltage divided by the resistor) is connected to the detection and control circuit 130 as the control bias voltage for detecting the voltage variation of the bias point 112 to output the compensation current.

Fig. 5 a-5 b show an exemplary implementation of the compensation current and the input current varying with the differential input signal. As shown in FIGS. 5 a-5 b, the sum I of the input current and the compensation current in the normal case_TOTALEqual to the sum I of the input current and the compensation current in the abnormal situation_TOTAL(ii) a IN the abnormal situation, the input current is proportional to the voltage of the differential input signal (e.g., inversely proportional when the input circuit 120 employs PMOS transistor pairs; proportional when the input circuit 120 employs NMOS transistor pairs) or the input current is a fixed input current IN_MIN1(IN_MIN1Not less than 0); the compensation current IS proportional to the voltage of the differential input signal under the abnormal condition (e.g., proportional when the input circuit 120 employs a PMOS transistor pair; inversely proportional when the input circuit 120 employs an NMOS transistor pair) or the compensation current IS a fixed compensation current IS_MAX1(IS_MAX1>0). Fig. 6 a-6 b show another exemplary embodiment of the compensation current and the input current varying with the differential input signal. As shown in fig. 6a to 6b, the input is made in the normal conditionSum of current and the compensating current I_TOTALGreater than the sum of the input current and the compensation current in the abnormal situation_TOTAL(ii) a IN the abnormal situation, the input current is proportional to the voltage of the differential input signal (e.g., inversely proportional when the input circuit 120 employs PMOS transistor pairs; proportional when the input circuit 120 employs NMOS transistor pairs) or the input current is a fixed input current IN_MIN2(IN_MIN2Not less than 0); and the compensation current IS proportional to the voltage of the differential input signal under the abnormal condition (e.g., proportional when the input circuit 120 employs a PMOS transistor pair; inversely proportional when the input circuit 120 employs an NMOS transistor pair) or the compensation current IS a fixed compensation current IS_MAX2(IS_MAX2>0)。

Please refer to fig. 1. The output circuit 140 is coupled to the two output points 122 and 124, and is used for outputting a differential output signal (the signal OUTP at the positive output terminal and the signal OUTN at the negative output terminal) according to the sum of the input current and the compensation current; more specifically, the voltages of the two output points 122 and 124 are related to the sum of the input current and the compensation current, and the output circuit 140 determines the differential output signal according to the voltages of the two output points. Fig. 7 shows an embodiment of the output circuit 140, which includes a pair of NMOS transistors (N1, N2) coupled to a plurality of bias terminals, wherein the voltages and/or currents provided by the bias terminals (e.g., the currents output by the transistors P2, P4 of fig. 2) depend on implementation requirements, and the pair of NMOS transistors determines the differential output signal according to the voltages of the two output points 122, 124 (i.e., the gate voltages of the pair of NMOS transistors). Since the NMOS transistor pair of fig. 7 and its equivalents are common knowledge in the art alone, the details thereof are omitted herein.

Please refer to fig. 1. The level determination circuit 150 and the load circuit 160 are commonly used to determine the dc level of the differential output signal according to the differential output signal. FIG. 8a shows an embodiment of the level determination circuit 150, which includes a common mode feedback circuit. The common mode feedback circuit includes a voltage divider 810 and an operational amplifier 820. The voltage divider circuit 810 includes two resistors (R1, R2) for generating a divided voltage (V) according to the differential output signal_DIV)；For example, when the two resistors have the same resistance value, the divided voltage is the average voltage of the differential output signalThe operational amplifier 820 is based on the divided voltage and a reference voltage (V)_REF) Outputting a common mode feedback voltage (V)_CMFB) To the load circuit 160. The load circuit 160 is coupled to the two output points 122 and 124, and determines the dc levels of the two output points 122 and 124 according to the common mode feedback voltage and the sum of the input current and the compensation current; one embodiment of the load circuit 160 is shown in FIG. 8b and includes an NMOS transistor pair (N3, N4). In one implementation example, the variation of the common mode feedback voltage is related to the variation of the sum of the input current and the compensation current; for example, the variation trend of the common mode feedback voltage is inversely proportional to the variation trend of the sum of the input current and the compensation current.

Fig. 9 shows another embodiment of the differential amplifier of the present invention. The differential amplifier 900 of fig. 9 includes a bias circuit 910, an input circuit 920, a detection and control circuit 930, an output circuit 940, a level decision circuit 950, and a load circuit 960. The bias circuit 910 is the bias circuit 110 of FIG. 1 or its equivalent; the input circuit 920 is the input circuit 120 of fig. 1 or its equivalent; output circuit 940 or output circuit 140 of fig. 1 or an equivalent thereof; the level decision circuit 950 is the level decision circuit 150 of fig. 1 or equivalent thereof; and load circuit 960 is load circuit 160 of fig. 1 or an equivalent thereof. The detection and control circuit 930 is used to output a compensation current to two output points 122, 124 according to the voltage of the differential input signal, wherein the compensation current is derived from the input bias current; more specifically, when the voltage of the differential input signal exceeds the normal operation interval of the input circuit 910, the input current outputted by the input circuit 920 gradually decreases or becomes a fixed input current not less than zero, and the detection and control circuit 930 gradually increases or makes the compensation current become a fixed compensation current greater than zero according to the change of the voltage of the differential input signal, thereby preventing the input current from being insufficient to cause malfunction of the differential amplifier 900. Compared to fig. 1, the detection and control circuit 930 of fig. 9 does not need to output the compensation current according to the control bias. Fig. 10 shows an embodiment of the detection and control circuit 930, which includes a voltage detector 1010 and a PMOS transistor pair (P9, P10), wherein the voltage detector 1010 is used for detecting the differential input signal to generate a gate voltage, and the PMOS transistor pair is used for outputting the compensation current according to the gate voltage. Since it is common knowledge in the art that the voltage detector 1010 and each of the PMOS transistor pairs individually are omitted here in detail.

Since the details and variations of the embodiments of fig. 9 to 10 can be understood by those skilled in the art with reference to the disclosure of the embodiments of fig. 1 to 8, that is, the technical features of the embodiments of fig. 1 to 8 can be reasonably applied to the embodiments of fig. 9 to 10, the repeated and redundant description is omitted here. It should be noted that in FIGS. 1 to 10, each of the inverted triangular symbols

Representing a power source terminal, a bias point or a ground point, which can be set by the implementation inventor according to the implementation requirements.

It is to be noted that, when the implementation is possible, a person skilled in the art may selectively implement some or all of the technical features of any one of the foregoing embodiments, or selectively implement a combination of some or all of the technical features of the foregoing embodiments, thereby increasing the flexibility in implementing the invention. It is to be noted that although some embodiments of the present disclosure employ PMOS transistors, this is not a limitation of the present disclosure, and those skilled in the art can understand how to implement the present disclosure using NMOS transistors.

In summary, the present invention can provide a compensation current when the input current is insufficient or zero, so as to avoid malfunction of the differential amplifier. In addition, the circuit of the invention is simple and easy to implement, and has cost benefit.

Although the embodiments of the present invention have been described above, the embodiments are not intended to limit the present invention, and those skilled in the art can make variations on the technical features of the present invention according to the explicit or implicit contents of the present invention, and all such variations may fall within the scope of the patent protection sought by the present invention.