阅读说明：本技术 显示装置以及其驱动方法 (Display device and driving method thereof ) 是由 上野哲也 于 2018-03-19 设计创作，主要内容包括：本发明是将实现不引起亮度的偏差的能够补偿驱动晶体管的阈值电压的偏差的电流驱动型的显示装置设为目的。像素电路(10)包含发光元件(OLED)、驱动晶体管(Tdr)、电源供给控制晶体管(TA)、发光控制晶体管(TB)、第一写入控制晶体管(TC)、阈值电压补偿晶体管(TD)、第二写入控制晶体管(TE)、初始化晶体管(TF)、数据保持电容器(C)。在数据写入期间,扫描信号(G(n))激活,初始化电压(Vini)经由驱动晶体管Tdr施加到数据保持电容器(C)的第一电极并且数据电压施加到数据保持电容器(C)的第二电极。(The invention aims to realize a current-driven display device which can compensate the deviation of the threshold voltage of a driving transistor without causing the deviation of brightness. The pixel circuit (10) includes a light-emitting element (OLED), a drive transistor (Tdr), a power supply control Transistor (TA), a light emission control Transistor (TB), a first write control Transistor (TC), a threshold voltage compensation Transistor (TD), a second write control Transistor (TE), an initialization Transistor (TF), and a data holding capacitor (C). During data writing, the scan signal (g (n)) is activated, the initialization voltage (Vini) is applied to the first electrode of the data holding capacitor (C) via the driving transistor Tdr and the data voltage is applied to the second electrode of the data holding capacitor (C).)

1. A display device, comprising:

pixel circuits arranged in a matrix;

a first power supply wiring to which a first power supply voltage is applied;

a second power supply wiring to which a second power supply voltage is applied;

an initialization power supply wiring line to which an initialization voltage for initializing the pixel circuit is applied; and

data signal lines provided for each column and to which a data voltage is applied; wherein

The pixel circuit includes:

a display element provided between the first power supply wiring and the second power supply wiring, and emitting light at a luminance corresponding to the amount of current supplied;

a capacitive element comprising:

a first electrode; and

a second electrode;

a driving transistor provided between the first power supply wiring and the second power supply wiring in series with the display element, including:

a control terminal connected to the first electrode of the capacitive element;

a first conduction terminal to which the first power supply voltage is applied during light emission; and

a second conduction terminal electrically connected to the control terminal during data writing and electrically isolated from the control terminal during the light emission;

an initialization transistor comprising:

a control terminal to which an activated signal is applied during initialization;

a first conduction terminal connected to the control terminal of the drive transistor

A wiring between the second conduction terminals; and

a second conduction terminal connected to the initialization power supply wiring;

a first write control transistor comprising:

a control terminal to which an activated signal is applied during the data writing;

a first conduction terminal connected to the data signal line; and

a second conduction terminal connected to the second electrode of the capacitor element; and

a second write control transistor comprising:

a control terminal to which an activated signal is applied during the data writing;

a first conduction terminal connected to the initialization power supply wiring; and

a second conduction terminal connected to the first conduction terminal of the driving transistor.

2. The display device according to claim 1,

the pixel circuit further includes:

a light emission control unit that controls supply of current to the display element;

a power supply control unit for electrically connecting the second electrode of the capacitor element and the first power supply line during the initialization period and the light emission period; and

and a threshold voltage compensation section for electrically connecting the first electrode of the capacitor element and the initialization power supply wiring during the initialization period and the data writing period.

3. The display device according to claim 2,

the light emission control section is constituted by a light emission control transistor including:

a control terminal to which an activation signal is applied during the light emission;

a first conduction terminal connected to the first power supply wiring; and

a second conduction terminal connected to the first conduction terminal of the driving transistor;

the power supply control unit is composed of a power supply control transistor, and the power supply control transistor includes:

a control terminal to which a signal representing a logical sum of a signal activated during the initialization and a signal activated during the light emission is applied;

a first conduction terminal connected to the first power supply wiring; and

a second conduction terminal connected to the second electrode of the capacitor element;

the threshold voltage compensation unit is composed of a threshold voltage compensation transistor including:

a control terminal to which a signal indicating a logical sum of a signal activated during initialization and a signal activated during data writing is applied;

a first conduction terminal connected to a second conduction terminal of the driving transistor; and

a second conduction terminal connected to the control terminal of the drive transistor.

4. The display device according to claim 2,

the light emission control section is constituted by a light emission control transistor including:

a control terminal to which an activation signal is applied during the light emission;

a first conduction terminal connected to the first power supply wiring; and

a second conduction terminal connected to the first conduction terminal of the driving transistor;

the power supply control unit is configured by a first power supply control transistor and a second power supply control transistor, and the first power supply control transistor includes:

a control terminal to which an activated signal is applied during initialization;

a first conduction terminal connected to the first power supply wiring; and

a second conduction terminal connected to the second electrode of the capacitor element;

the second power supply control transistor includes:

a control terminal to which an activation signal is applied during the light emission;

a first conduction terminal connected to a second conduction terminal of the light emission control transistor; and

a second conduction terminal connected to the second electrode of the capacitor element;

the threshold voltage compensation unit is composed of a threshold voltage compensation transistor including:

a control terminal to which a signal indicating a logical sum of a signal activated during initialization and a signal activated during data writing is applied;

a first conduction terminal connected to a second conduction terminal of the driving transistor; and

a second conduction terminal connected to the control terminal of the drive transistor.

5. The display device according to claim 2,

the light emission control unit is configured by a first light emission control transistor and a second light emission control transistor, and the first light emission control transistor includes:

a control terminal to which an activation signal is applied during the light emission;

a first conduction terminal connected to the first power supply wiring; and

a second conduction terminal;

the second emission control transistor includes:

a control terminal to which an activation signal is applied during the light emission;

a first conduction terminal connected to a second conduction terminal of the first light emission control transistor; and

a second conduction terminal connected to the first conduction terminal of the driving transistor;

the power supply control unit is configured by a first power supply control transistor and a second power supply control transistor, and the first power supply control transistor includes:

a control terminal to which an activated signal is applied during initialization;

a first conduction terminal connected to the first power supply wiring; and

a second conduction terminal connected to the second electrode of the capacitor element;

the second power supply control transistor includes:

a control terminal to which an activation signal is applied during the light emission;

a first conduction terminal connected to a second conduction terminal of the first light emission control transistor; and

a second conduction terminal connected to the second electrode of the capacitor element;

the threshold voltage compensation unit is composed of a threshold voltage compensation transistor including:

a control terminal to which a signal indicating a logical sum of a signal activated during initialization and a signal activated during data writing is applied;

a first conduction terminal connected to a second conduction terminal of the driving transistor; and

a second conduction terminal connected to the control terminal of the drive transistor.

6. The display device according to claim 2,

the light emission control section is constituted by a light emission control transistor including:

a control terminal to which an activation signal is applied during the light emission;

a first conduction terminal connected to the first power supply wiring; and

a second conduction terminal connected to the first conduction terminal of the driving transistor;

the power supply control unit is composed of a power supply control transistor, and the power supply control transistor includes:

a control terminal to which a signal indicating a logical sum of a signal activated during initialization and a signal activated during light emission is applied;

a first conduction terminal connected to the first power supply wiring; and

a second conduction terminal connected to the second electrode of the capacitor element;

the threshold voltage compensation unit includes a first threshold voltage compensation transistor and a second threshold voltage compensation transistor, and the first threshold voltage compensation transistor includes:

a control terminal to which an activated signal is applied during initialization;

a first conduction terminal connected to a second conduction terminal of the driving transistor; and

a second conduction terminal connected to the control terminal of the drive transistor;

the second threshold voltage compensation transistor includes:

a control terminal to which an activated signal is applied during data writing;

a first conduction terminal connected to a second conduction terminal of the driving transistor; and

a second conduction terminal connected to the control terminal of the drive transistor.

7. The display device according to claim 2,

the light emission control unit is configured by a first light emission control transistor and a second light emission control transistor, and the first light emission control transistor includes:

a control terminal to which an activation signal is applied during the light emission;

a first conduction terminal connected to the first power supply wiring; and

a second conduction terminal;

the second emission control transistor includes:

a control terminal to which an activation signal is applied during the light emission;

a first conduction terminal connected to a second conduction terminal of the first light emission control transistor; and

a second conduction terminal connected to the first conduction terminal of the driving transistor;

the power supply control unit is configured by a first power supply control transistor and a second power supply control transistor, and the first power supply control transistor includes:

a control terminal to which an activated signal is applied during initialization;

a first conduction terminal connected to the first power supply wiring; and

a second conduction terminal connected to the second electrode of the capacitor element;

the second power supply control transistor includes:

a control terminal to which an activation signal is applied during the light emission;

a first conduction terminal connected to a second conduction terminal of the first light emission control transistor; and

a second conduction terminal connected to the second electrode of the capacitor element;

the threshold voltage compensation unit includes a first threshold voltage compensation transistor and a second threshold voltage compensation transistor, and the first threshold voltage compensation transistor includes:

a control terminal to which an activated signal is applied during initialization;

a first conduction terminal connected to a second conduction terminal of the driving transistor; and

a second conduction terminal connected to the control terminal of the drive transistor;

the second threshold voltage compensation transistor includes:

a control terminal to which an activated signal is applied during data writing;

a first conduction terminal connected to a second conduction terminal of the driving transistor; and

a second conduction terminal connected to the control terminal of the drive transistor.

8. The display device according to claim 1,

the display element is an organic EL display element.

9. A driving method of a display device including a pixel circuit, the pixel circuit comprising:

a display element provided between a first power supply wiring to which a first power supply voltage is applied and a second power supply wiring to which a second power supply voltage is applied, and emitting light at a luminance corresponding to the amount of current supplied;

a capacitive element comprising:

a first electrode; and

a second electrode;

a driving transistor provided between the first power supply wiring and the second power supply wiring in series with the display element, including:

a control terminal, a first conduction terminal, a second conduction terminal, and a first electrode connected to the capacitor element; and

a light emission control unit that controls supply of current to the display element; wherein the method comprises:

an initialization step of applying an initialization voltage to a control terminal of the driving transistor in a state where supply of a current to the display element is cut off by the light emission control section; a data writing step of applying the initialization voltage to the first electrode of the capacitor element and applying a data voltage to the second electrode of the capacitor element via the driving transistor in a state where the supply of the current to the display element is cut off by the light emission control section; and

a light emission step of electrically connecting the light emission control section to the first power supply wiring and the second power supply wiring in such a manner that a current is supplied to the display element.

10. The driving method according to claim 9,

the display device includes:

an initialization power supply line to which the initialization voltage is applied; and

data signal lines provided for each column and to which the data voltages are applied; wherein a first control signal, a second control signal, a third control signal, a fourth control signal, and a fifth control signal are applied to the pixel circuit;

the light emission control section is constituted by a light emission control transistor including:

a control terminal to which the third control signal is applied;

a first conduction terminal connected to the first power supply wiring; and

a second conduction terminal connected to the first conduction terminal of the driving transistor;

the pixel circuit further includes:

an initialization transistor comprising:

a control terminal to which the first control signal is applied;

a first conduction terminal connected to the control terminal of the drive transistor

A wiring between the second conduction terminals; and

a second conduction terminal connected to the initialization power supply wiring;

a first write control transistor comprising:

a control terminal to which the second control signal is applied;

a first conduction terminal connected to the data signal line; and

a second conduction terminal connected to the second electrode of the capacitor element; and

a second write control transistor comprising:

a control terminal to which a second control signal is applied;

a first conduction terminal connected to the initialization power supply wiring; and

a second conduction terminal connected to the first conduction terminal of the driving transistor;

a power supply control transistor comprising:

a control terminal to which the fifth control signal is applied;

a first conduction terminal connected to the first power supply wiring; and

a second conduction terminal connected to the second electrode of the capacitor element; and

a threshold voltage compensation transistor comprising:

a control terminal to which the fourth control signal is applied;

a first conduction terminal connected to a second conduction terminal of the driving transistor; and

a second conduction terminal connected to the control terminal of the drive transistor; wherein

In the initialization step, the first control signal, the fourth control signal and the fifth control signal are set to be activated, and the second control signal and the third control signal are set to be deactivated;

in the data writing step, the second control signal and the fourth control signal are set to be activated, and the first control signal, the third control signal and the fifth control signal are set to be deactivated;

in the light emitting step, the third control signal and the fifth control signal are activated, and the first control signal, the second control signal and the fourth control signal are inactivated.

11. The driving method according to claim 9,

the display device includes:

an initialization power supply line to which the initialization voltage is applied; and

data signal lines provided for each column and to which the data voltages are applied; wherein a first control signal, a second control signal, a third control signal, and a fourth control signal are applied to the pixel circuit;

the light emission control section is constituted by a light emission control transistor including:

a control terminal to which the third control signal is applied;

a first conduction terminal connected to the first power supply wiring; and

a second conduction terminal connected to the first conduction terminal of the driving transistor;

the pixel circuit further includes:

an initialization transistor comprising:

a control terminal to which the first control signal is applied;

a first conduction terminal connected to the control terminal of the drive transistor

A wiring between the second conduction terminals; and

a second conduction terminal connected to the initialization power supply wiring;

a first write control transistor comprising:

a control terminal to which the second control signal is applied;

a first conduction terminal connected to the data signal line; and

a second conduction terminal connected to the second electrode of the capacitor element; and

a second write control transistor comprising:

a control terminal to which a second control signal is applied;

a first conduction terminal connected to the initialization power supply wiring; and

a second conduction terminal connected to the first conduction terminal of the driving transistor;

a first power supply control transistor comprising:

a control terminal to which the first control signal is applied;

a first conduction terminal connected to the first power supply wiring; and

a second conduction terminal connected to the second electrode of the capacitor element;

a second power supply control transistor comprising:

a control terminal to which the third control signal is applied;

a first conduction terminal connected to a second conduction terminal of the light emission control transistor; and

a second conduction terminal connected to the second electrode of the capacitor element; and

a threshold voltage compensation transistor comprising:

a control terminal to which the fourth control signal is applied;

a first conduction terminal connected to a second conduction terminal of the driving transistor; and

a second conduction terminal connected to the control terminal of the drive transistor; wherein

In the initialization step, the first control signal and the fourth control signal are set to be activated, and the second control signal and the third control signal are set to be deactivated;

in the data writing step, the second control signal and the fourth control signal are set to be activated, and the first control signal and the third control signal are set to be deactivated; in the light emitting step, the third control signal is activated, and the first control signal, the second control signal, and the fourth control signal are inactivated.

12. The driving method according to claim 9,

the display device includes:

an initialization power supply line to which the initialization voltage is applied; and

data signal lines provided for each column and to which the data voltages are applied; wherein a first control signal, a second control signal, a third control signal, and a fourth control signal are applied to the pixel circuit;

the light emission control unit is configured by a first light emission control transistor and a second light emission control transistor, and the first light emission control transistor includes:

a control terminal to which the third control signal is applied;

a first conduction terminal connected to the first power supply wiring; and

a second conduction terminal;

the second emission control transistor includes:

a control terminal to which the third control signal is applied;

a first conduction terminal connected to a second conduction terminal of the first light emission control transistor; and

a second conduction terminal connected to the first conduction terminal of the driving transistor;

the pixel circuit further includes:

an initialization transistor comprising:

a control terminal to which the first control signal is applied;

a first conduction terminal connected to the control terminal of the drive transistor

A wiring between the second conduction terminals; and

a second conduction terminal connected to the initialization power supply wiring;

a first write control transistor comprising:

a control terminal to which the second control signal is applied;

a first conduction terminal connected to the data signal line; and

a second conduction terminal connected to the second electrode of the capacitor element; and

a second write control transistor comprising:

a control terminal to which a second control signal is applied;

a first conduction terminal connected to the initialization power supply wiring; and

a second conduction terminal connected to the first conduction terminal of the driving transistor;

a first power supply control transistor comprising:

a control terminal to which the first control signal is applied;

a first conduction terminal connected to the first power supply wiring; and

a second conduction terminal connected to the second electrode of the capacitor element;

a second power supply control transistor comprising:

a control terminal to which the third control signal is applied;

a first conduction terminal connected to a second conduction terminal of the first light emission control transistor; and

a second conduction terminal connected to the second electrode of the capacitor element; and

a threshold voltage compensation transistor comprising:

a control terminal to which the fourth control signal is applied;

a first conduction terminal connected to a second conduction terminal of the driving transistor; and

a second conduction terminal connected to the control terminal of the drive transistor; wherein

In the initialization step, the first control signal and the fourth control signal are set to be activated, and the second control signal and the third control signal are set to be deactivated;

in the data writing step, the second control signal and the fourth control signal are set to be activated, and the first control signal and the third control signal are set to be deactivated;

in the light emitting step, the third control signal is activated, and the first control signal, the second control signal, and the fourth control signal are inactivated.

13. The driving method according to claim 9,

the display device includes:

an initialization power supply line to which the initialization voltage is applied; and

data signal lines provided for each column and to which the data voltages are applied; wherein

A first control signal, a second control signal, a third control signal, and a fifth control signal are applied to the pixel circuit;

the light emission control section is constituted by a light emission control transistor including:

a control terminal to which the third control signal is applied;

a first conduction terminal connected to the first power supply wiring; and

a second conduction terminal connected to the first conduction terminal of the driving transistor;

the pixel circuit further includes:

an initialization transistor comprising:

a control terminal to which the first control signal is applied;

a first conduction terminal connected to the control terminal of the drive transistor

A wiring between the second conduction terminals; and

a second conduction terminal connected to the initialization power supply wiring;

a first write control transistor comprising:

a control terminal to which the second control signal is applied;

a first conduction terminal connected to the data signal line; and

a second conduction terminal connected to the second electrode of the capacitor element; and

a second write control transistor comprising:

a control terminal to which a second control signal is applied;

a first conduction terminal connected to the initialization power supply wiring; and

a second conduction terminal connected to the first conduction terminal of the driving transistor;

a power supply control transistor comprising:

a control terminal to which the fifth control signal is applied;

a first conduction terminal connected to the first power supply wiring; and

a second conduction terminal connected to the second electrode of the capacitor element;

a first threshold voltage compensation transistor comprising:

a control terminal to which the first control signal is applied;

a first conduction terminal connected to a second conduction terminal of the driving transistor; and

a second conduction terminal connected to the control terminal of the drive transistor; and

a second threshold voltage compensation transistor comprising:

a control terminal to which the second control signal is applied;

a first conduction terminal connected to a second conduction terminal of the driving transistor; and

a second conduction terminal connected to the control terminal of the drive transistor;

wherein

In the initialization step, the first control signal and the fifth control signal are set to be active, and the second control signal and the third control signal are set to be inactive;

in the data writing step, the second control signal is set to be activated, and the first control signal, the third control signal and the fifth control signal are set to be deactivated;

in the light emitting step, the third control signal and the fifth control signal are activated, and the first control signal and the second control signal are inactivated.

14. The driving method according to claim 9,

the display device includes:

an initialization power supply line to which the initialization voltage is applied; and

data signal lines provided for each column and to which the data voltages are applied; wherein

A first control signal, a second control signal, and a third control signal are applied to the pixel circuit;

the light emission control unit is configured by a first light emission control transistor and a second light emission control transistor, and the first light emission control transistor includes:

a control terminal to which the third control signal is applied;

a first conduction terminal connected to the first power supply wiring; and

a second conduction terminal;

the second emission control transistor includes:

a control terminal to which the third control signal is applied;

a first conduction terminal connected to a second conduction terminal of the first light emission control transistor; and

a second conduction terminal connected to the first conduction terminal of the driving transistor;

the pixel circuit further includes:

an initialization transistor comprising:

a control terminal to which the first control signal is applied;

a first conduction terminal connected to the control terminal of the drive transistor

A wiring between the second conduction terminals; and

a second conduction terminal connected to the initialization power supply wiring;

a first write control transistor comprising:

a control terminal to which the second control signal is applied;

a first conduction terminal connected to the data signal line; and

a second conduction terminal connected to the second electrode of the capacitor element; and

a second write control transistor comprising:

a control terminal to which the second control signal is applied;

a first conduction terminal connected to the initialization power supply wiring; and

a second conduction terminal connected to the first conduction terminal of the driving transistor;

a first power supply control transistor comprising:

a control terminal to which the first control signal is applied;

a first conduction terminal connected to the first power supply wiring; and

a second conduction terminal connected to the second electrode of the capacitor element;

a second power supply control transistor comprising:

a control terminal to which the third control signal is applied;

a first conduction terminal connected to a second conduction terminal of the first light emission control transistor; and

a second conduction terminal connected to the second electrode of the capacitor element; and

a first threshold voltage compensation transistor comprising:

a control terminal to which the first control signal is applied;

a first conduction terminal connected to a second conduction terminal of the driving transistor; and

a second conduction terminal connected to the control terminal of the drive transistor; and

a second threshold voltage compensation transistor comprising:

a control terminal to which the second control signal is applied;

a first conduction terminal connected to a second conduction terminal of the driving transistor; and

a second conduction terminal connected to the control terminal of the drive transistor; wherein

In the initialization step, the first control signal is set to be active, and the second control signal and the third control signal are set to be inactive;

in the data writing step, the second control signal is set to be activated, and the first control signal and the third control signal are set to be inactivated;

in the light emitting step, the third control signal is activated, and the first control signal and the second control signal are inactivated.

Technical Field

The following disclosure relates to a display device, and more particularly, to a display device including a current-driven display element such as an organic EL display device and a driving method thereof.

Background

In recent years, organic EL display devices including pixel circuits including organic Electroluminescence (EL) elements (hereinafter, referred to as "organic EL elements") have been put to practical use. The organic EL element is a self-luminous display element that emits light at a luminance corresponding to the amount of current flowing through it. An organic EL display device using organic EL elements, which are self-luminous display elements, can be easily made thinner, lower in power consumption, higher in luminance, and the like, as compared with a liquid crystal display device that requires a backlight, a color filter, and the like. Therefore, in recent years, the development of organic EL display devices has been actively carried out.

In an image circuit of an organic EL display device, a TFT (thin film transistor) is typically used as a driving transistor which is a transistor for controlling supply of a current to an organic EL element. However, with respect to the TFT, variations in characteristics are likely to occur here. Specifically, variations tend to occur in the threshold voltage. When variations in threshold voltage occur in the driving transistors provided in the display portion, the display quality is degraded due to variations in luminance. Therefore, various processes (compensation processes) for compensating for variations in threshold voltage have been proposed.

As a method of the compensation process, there are known an internal compensation method in which a capacitor for holding information on the threshold voltage of the driving transistor is provided in the pixel circuit to perform the compensation process, and an external compensation method in which a current flowing through the driving transistor is measured by a circuit provided outside the pixel circuit under a predetermined condition, for example, and the video signal is corrected based on the measurement result to perform the compensation process.

As a configuration of a pixel circuit of an organic EL display device using an internal compensation method in compensation processing, for example, a configuration shown in fig. 26 is known. In addition, it is assumed that the pixel circuit 90 shown in fig. 26 is a pixel circuit located in the nth row. The pixel circuit 90 includes a light emitting element OLED, seven transistors T91 to T97 (a driving transistor T91, a writing control transistor T92, a power supply control transistor T93, a light emission control transistor T94, a threshold voltage compensation transistor T95, a first initialization transistor T96, a second initialization transistor T97), and a data holding capacitor C9. In the pixel circuit 90, in addition to the three kinds of voltages (the high-level power supply voltage ELVDD, the low-level power supply voltage ELVSS, and the initialization voltage Vini) which are fixed to be large, the scanning signal G (n) applied to the scanning signal line in the nth row, the scanning signal G (n-1) applied to the scanning signal line in the (n-1) th row, the light emission control signal em (n) applied to the light emission control line in the nth row, and the data signal D are applied.

In the pixel circuit 90 shown in fig. 26, after initialization, data is written (charging of the data holding capacitor C9 by the data signal D) by turning the write control transistor T92 and the threshold voltage compensation transistor T95 ON, and turning the power supply control transistor T93, the emission control transistor T94, the first initialization transistor T96, and the second initialization transistor T97 OFF. At this time, a data voltage (voltage of the data signal D) is applied to one electrode of the data holding capacitor C9 through the driving transistor T91 as indicated by an arrow denoted by reference numeral 91 in fig. 27, and a high-level power supply voltage ELVDD is applied to the other electrode of the data holding capacitor C9 as indicated by an arrow denoted by reference numeral 92 in fig. 27. By thus writing data, the gate voltage Vg of the driving transistor T91 becomes a value shown in the following expression (1).

Vg＝Vdata-Vth...(1)

Here, Vdata is a data voltage, and Vth is a threshold voltage (absolute value) of the driving transistor T91.

After data writing, the write control transistor T92 and the threshold voltage compensation transistor T95 are turned OFF, the power supply control transistor T93 and the emission control transistor T94 are turned ON, and the drive current Ioled is supplied to the light emitting element OLED. Thereby, the light emitting element OLED emits light according to the magnitude of the driving current Ioled. At this time, the drive current Ioled has a magnitude shown in the following expression (2).

Ioled＝(β/2)·(Vgs-Vth)²...(2)

Here, β is a constant, and Vgs is a source-gate voltage of the driving transistor T91.

Incidentally, considering the above equation (1), the source-gate voltage Vgs of the driving transistor T91 is expressed by the following equation (3).

Vgs＝ELVDD-Vg

＝ELVDD－Vdata+Vth...(3)

If the above formula (3) is substituted into the above formula (2), the following formula (4) is obtained.

Ioled＝β/2·(ELVDD-Vdata)²...(4)

In the above equation (4), the term of the threshold voltage Vth is not included. That is, regardless of the magnitude of the threshold voltage Vth of the driving transistor T91, the driving current Ioled according to the magnitude of the data voltage Vdata is supplied to the light emitting element OLED. In this way, the deviation of the threshold voltage Vth of the driving transistor T91 is compensated.

Further, japanese patent application laid-open No. 2016 and 110055 discloses an invention of an organic EL display device capable of sufficiently securing a time for compensation processing.

Disclosure of Invention

Technical problem to be solved by the invention

According to the conventional organic EL display device (the organic EL display device including the pixel circuit 90 having the configuration shown in fig. 26) in which the internal compensation method is adopted in the compensation process, data is written in a state where the high-level power supply voltage ELVDD is applied to one end of the data holding capacitor C9. However, the magnitude of the high-level power supply voltage ELVDD varies depending on the display pattern and the position of the pixel. This is because the magnitude of the voltage Drop (IR-Drop, voltage Drop due to the product of the current I and the wiring resistance R) affecting the high-level power supply voltage ELVDD varies depending on the display pattern and the position of the pixel. In more detail, the high level power voltage ELVDD varies according to the display pattern due to the display pattern variation and the amount of the current I varies. Further, the wiring resistance R varies depending on the position of the pixel, and thus the high-level power supply voltage ELVDD varies depending on the position of the pixel. For the above reason, even if the data voltage Vdata is the same, the luminance may be different.

Therefore, the following disclosure is directed to realizing a current-driven display device capable of compensating for a threshold voltage variation of a driving transistor without causing a luminance variation.

Means for solving the problems

A display device according to some embodiments of the present invention includes: pixel circuits arranged in a matrix; a first power supply wiring to which a first power supply voltage is applied; a second power supply wiring to which a second power supply voltage is applied; an initialization power supply wiring line to which an initialization voltage for initializing the pixel circuit is applied; and data signal lines provided for each column and to which a data voltage is applied; wherein the content of the first and second substances,

the pixel circuit includes:

a display element provided between the first power supply wiring and the second power supply wiring, and emitting light at a luminance corresponding to the amount of current supplied;

a capacitive element comprising: a first electrode; and a second electrode;

a driving transistor provided between the first power supply wiring and the second power supply wiring in series with the display element, including: a control terminal connected to the first electrode of the capacitive element; a first conduction terminal to which the first power supply voltage is applied during light emission; and a second conduction terminal electrically connected to the control terminal during data writing and electrically isolated from the control terminal during the light emission period;

an initialization transistor comprising: a control terminal to which an activated signal is applied during initialization; a first conduction terminal connected to a wiring between the control terminal of the drive transistor and the second conduction terminal; and a second conduction terminal connected to the initialization power supply wiring;

a first write control transistor comprising: a control terminal to which an activated signal is applied during the data writing; a first conduction terminal connected to the data signal line; and a second conduction terminal connected to the second electrode of the capacitive element; and

a second write control transistor comprising: a control terminal to which an activated signal is applied during the data writing; a first conduction terminal connected to the initialization power supply wiring; and a second conduction terminal connected to the first conduction terminal of the driving transistor.

A driving method of a display device according to some embodiments of the present invention is a driving method of a display device including a pixel circuit, the pixel circuit including: a display element provided between a first power supply wiring to which a first power supply voltage is applied and a second power supply wiring to which a second power supply voltage is applied, and emitting light at a luminance corresponding to the amount of current supplied; a capacitive element comprising: a first electrode; and a second electrode; a driving transistor provided between the first power supply wiring and the second power supply wiring in series with the display element, including: a control terminal, a first conduction terminal, a second conduction terminal, and a first electrode connected to the capacitor element; and a light emission control unit for controlling supply of current to the display element; wherein, include:

an initialization step of applying an initialization voltage to a control terminal of the driving transistor in a state where supply of a current to the display element is cut off by the light emission control section;

a data writing step of applying the initialization voltage to the first electrode of the capacitor element and applying a data voltage to the second electrode of the capacitor element via the driving transistor in a state where the supply of the current to the display element is cut off by the light emission control section; and

a light emission step of electrically connecting the light emission control section to the first power supply wiring and the second power supply wiring in such a manner that a current is supplied to the display element.

Effects of the invention

According to some embodiments of the present invention, writing of data into the pixel circuit is performed in such a manner that a data voltage is applied to the second electrode of the capacitive element (data holding capacitor) in a state where an initialization voltage is applied to the first electrode of the capacitive element via the driving transistor. In this regard, the amount of current flowing through the initialization power supply wiring that delivers the initialization voltage is significantly reduced compared to the amount of current flowing through the first power supply wiring that delivers the first power supply voltage (high-level power supply voltage). Therefore, the variation in the voltage magnitude is small for the initialization voltage. That is, data writing to the capacitor element is performed such that a data voltage is applied to an electrode (second electrode) facing an electrode (first electrode) to which a substantially constant voltage is applied. Therefore, stable data writing can be performed. This prevents the occurrence of luminance variations when data writing is performed based on data voltages of the same magnitude. Although the magnitude of the drive current depends on the magnitude of the threshold voltage of the drive transistor, a voltage corresponding to the data voltage and the threshold voltage of the drive transistor is held in the capacitive element before light emission of the display element (for example, an organic EL element). Thus, when the display element emits light, the influence of the threshold voltage is canceled, and a drive current having a magnitude corresponding to the data voltage is supplied to the display element. That is, the threshold voltage deviation of the driving transistor is compensated. As described above, a current-driven display device capable of compensating for a threshold voltage variation of a driving transistor without causing a luminance variation is realized.

Drawings

Fig. 1 is a circuit diagram showing a configuration of a pixel circuit according to a first embodiment.

Fig. 2 is a block diagram showing the entire configuration of the organic EL display device in the first embodiment.

Fig. 3 is a diagram for explaining an OR circuit that generates a signal to be applied to the gate terminal of the power supply control transistor in the first embodiment.

Fig. 4 is a diagram for explaining an OR circuit that generates a signal to be applied to the gate terminal of the threshold voltage compensation transistor in the first embodiment.

Fig. 5 is a timing chart for explaining a driving method of the pixel circuit in the first embodiment.

Fig. 6 is a diagram for explaining an operation in the initialization period in the first embodiment.

Fig. 7 is a diagram for explaining an operation in the data writing period in the first embodiment.

Fig. 8 is a diagram for explaining the operation of the light emission period in the first embodiment.

Fig. 9 is a circuit diagram showing the configuration of the pixel circuit according to the second embodiment.

Fig. 10 is a timing chart for explaining a driving method of the pixel circuit in the second embodiment.

Fig. 11 is a diagram for explaining an operation in the initialization period in the second embodiment.

Fig. 12 is a diagram for explaining an operation in the data writing period in the second embodiment.

Fig. 13 is a diagram for explaining the operation of the light emission period in the second embodiment.

Fig. 14 is a circuit diagram showing a configuration of a pixel circuit according to a modification of the second embodiment.

Fig. 15 is a circuit diagram showing a configuration of a pixel circuit according to the third embodiment.

Fig. 16 is a timing chart for explaining a driving method of the pixel circuit in the third embodiment.

Fig. 17 is a diagram for explaining an operation in the initialization period in the third embodiment.

Fig. 18 is a diagram for explaining an operation in the data writing period in the third embodiment.

Fig. 19 is a diagram for explaining an operation in the light emission period in the third embodiment.

Fig. 20 is a circuit diagram showing a configuration of a pixel circuit according to the fourth embodiment.

Fig. 21 is a timing chart for explaining a driving method of the pixel circuit in the fourth embodiment.

Fig. 22 is a diagram for explaining an operation in the initialization period in the fourth embodiment.

Fig. 23 is a diagram for explaining an operation in the data writing period in the fourth embodiment.

Fig. 24 is a diagram for explaining an operation in the light emission period in the fourth embodiment.

Fig. 25 is a diagram showing a configuration of a pixel circuit in which the contents of the first to fourth embodiments (including the modified examples) are summarized.

Fig. 26 is a circuit diagram showing a configuration of a conventional pixel circuit.

Fig. 27 is a diagram for explaining an operation of the conventional pixel circuit.

Detailed Description

Hereinafter, the embodiments will be described with reference to the attached drawings. In the following, i and j are integers of 2 or more, and n is an integer of 1 or more and i or less.

<1 > first embodiment >

<1.1 Overall configuration >

Fig. 2 is a block diagram showing the entire configuration of the organic EL display device of the first embodiment. The organic EL display device includes a display section 100, a display control circuit 200, a gate driver 300, an emission driver 400, and a source driver 500. In addition, for example, the gate driver 300 and the emission driver 400 are provided in the organic EL panel in addition to the display section 100, and the display control circuit 200 and the source driver 500 are provided on a substrate other than the organic EL panel.

The display unit 100 includes (i +1) scanning signal lines GL (0) to GL (i) and j data signal lines DL (1) to DL (j) orthogonal to the scanning signal lines GL (0) to GL (i). In the display unit 100, i light emission control lines EML (1) to EML (i) are provided so as to correspond one-to-one to i scanning signal lines GL (1) to GL (i) other than the scanning signal line GL (0). In the display section 100, the scanning signal lines GL (0) to GL (i) and the light-emission control lines EML (1) to EML (i) are typically parallel to each other. In the display unit 100, i × j pixel circuits 10 are arranged in a matrix so as to correspond to intersections of i scanning signal lines GL (1) to GL (i) other than the scanning signal line GL (0) and j data signal lines DL (1) to DL (i). By providing i × j pixel circuits 10 in this manner, a pixel matrix of i rows × j columns is formed in the display portion 100. The detailed configuration of the pixel circuit 10 will be described later.

Each pixel circuit 10 is supplied with three types of voltages (a high-level power supply voltage ELVDD, a low-level power supply voltage ELVSS, and an initialization voltage Vini) by using wiring lines (not shown) in a fixed manner. Hereinafter, the wiring for transmitting the high-level power supply voltage ELVDD may be referred to as a "first power supply wiring", the wiring for transmitting the low-level power supply voltage ELVSS may be referred to as a "second power supply wiring", and the wiring for transmitting the initialization voltage Vini may be referred to as an "initialization power supply wiring". In addition, the high-level power supply voltage ELVDD corresponds to a first power supply voltage, and the low-level power supply voltage ELVSS corresponds to a second power supply voltage.

The following describes operations of the respective components shown in fig. 2. The display control circuit 200 receives an input video signal DIN and a timing signal group (horizontal synchronization signal, vertical synchronization signal, etc.) TG transmitted from the outside, and outputs a digital video signal DV, a gate control signal GCTL for controlling the operation of the gate driver 300, an emission driver control signal EMCTL for controlling the operation of the emission driver 400, and a source control signal SCTL for controlling the operation of the source driver 500. The gate control signal GCTL and the emission control signal EMCTL include a start pulse signal and a clock signal, respectively. The source control signal SCTL includes a start pulse signal (source start pulse signal), a clock signal (source clock signal), a latch strobe signal (latch strobe signal), and the like.

The gate driver 300 is connected to the i scanning signal lines GL (1) to GL (i). The gate driver 300 is configured by a shift register (shift register), a logic circuit, and the like. The gate driver 300 drives the i scanning signal lines GL (1) to GL (i) based on the gate control signal GCTL outputted from the display control circuit 200. More specifically, the gate driver 300 sequentially selects one scanning signal line from the i scanning signal lines GL (1) to GL (i), and applies an active scanning signal (in the present embodiment, a low-level scanning signal) to the selected scanning signal line.

The emission driver 400 is connected to the i light emission control lines EML (1) to EML (i). The transmission driver 400 is composed of a shift register, a logic circuit, and the like. The emission driver 400 drives the i light emission control lines EML (1) to EML (i) based on the emission control signal EMCTL output from the display control circuit 200. More specifically, the emission driver 400 sequentially selects one emission control line from the i scanning signal lines EML (1) to EML (i), and applies an active emission control signal (in the present embodiment, a low-level emission control signal) to the selected emission control line.

The source driver 500 is connected to j data signal lines DL (1) to DL (j). The source driver 500 receives the digital video signal DV and the source control signal SCTL output from the display control circuit 200, and applies data signals to j data signal lines DL (1) to DL (j). The source driver 500 includes a shift register of j bits (bit), a sampling circuit, a latch circuit, j D/a converters, and the like, which are not shown. The shift register includes j registers connected in cascade (cascade connect). The shift register sequentially transfers pulses of a source start pulse signal supplied to the register of the first stage from an input terminal to an output terminal based on a source clock signal. According to the transmission of this pulse, sampling pulses are output from the respective stages of the shift register. Based on this sampling pulse, the sampling circuit stores the digital video signal DV. The latch circuit takes in the digital video signal DV stored in a row of the sampling circuit according to the latch strobe signal, thereby holding the digital video signal DV. The D/a converter is provided so as to correspond to each of the data signal lines DL (1) to DL (j). The D/a converter converts the digital video signal DV, which has been held in the latch circuit, into an analog voltage. The converted analog voltage is applied to all the data signal lines DL (1) to DL (j) as a data signal.

As described above, the display section 100 displays an image based on the input image signal DIN by driving the i scanning signal lines GL (1) to GL (i), the i light emission control lines EML (1) to EML (i), and the j data signal lines DL (1) to DL (j).

In the following description, the scanning signal mark G (n) applied to the scanning signal line GL (n) of the nth row, the scanning signal mark G (n-1) applied to the scanning signal line GL (n-1) of the (n-1) th row, and the emission control signal mark em (n) applied to the emission control line eml (n) of the nth row are indicated.

<1.2 construction of pixel Circuit >

Next, the structure of the pixel circuit 10 according to the present embodiment will be described with reference to fig. 1. Here, attention is focused on the pixel circuit 10 located in the nth row. The pixel circuit 10 includes a light emitting element OLED, seven transistors (a driving transistor Tdr, a power supply control transistor TA, a light emission control transistor TB, a first writing control transistor TC, a threshold voltage compensation transistor TD, a second writing control transistor TE, and an initialization transistor TF), and a capacitance element (hereinafter referred to as a "data holding capacitor") C. The seven transistors are p-channel type thin film transistors. The data holding capacitor C is a capacitive element including two electrodes (a first electrode and a second electrode).

In the p-channel thin film transistor, the higher potential of the drain and the source is called the source, but the potential of the two terminals other than the gate terminal (control terminal) among the transistors in the pixel electrode 10 changes in level depending on the state. Therefore, in the following description, one of two terminals other than the gate terminal of the transistor in the pixel circuit 10 may be referred to as a "first conduction terminal", and the other may be referred to as a "second conduction terminal".

For the driving transistor Tdr, a gate terminal is connected to a first electrode of the data holding capacitor C and a second conduction terminal of the threshold voltage compensation transistor TD, a first conduction terminal is connected to a second electrode of the light emission control transistor TB and a second conduction terminal of the second write control transistor TE, and a second conduction terminal is connected to a first conduction terminal of the threshold voltage compensation transistor TD, a first conduction terminal of the initialization transistor TF, and an anode terminal of the light emitting element OLED. The power supply control transistor TA has a gate terminal connected to a wiring (hereinafter referred to as "first logic sum signal wiring") through which a signal indicating the logic sum of the scanning signal G (n-1) and the emission control signal em (n) is transmitted, a first conductive terminal connected to the first power supply wiring, and a second conductive terminal connected to the second electrode of the data holding capacitor C and the second conductive terminal of the first write control transistor TC. For the light emission control transistor TB, the gate terminal is connected to the light emission control line eml (n), the first conduction terminal is connected to the first power supply wiring, and the second conduction terminal is connected to the first conduction terminal of the drive transistor Tdr and the second conduction terminal of the second write control transistor TE.

For the first writing control transistor TC, the gate terminal is connected to the scanning signal line gl (n), the first on terminal is connected to the data signal line DL, and the second on terminal is connected to the second on terminal of the power supply control transistor TA and the second electrode of the data holding capacitor C. The threshold voltage compensation transistor TD has a gate terminal connected to a wiring (hereinafter referred to as "second logical sum signal wiring") that transmits a signal indicating the logical sum of the scan signal G (n-1) and the scan signal G (n), a first conduction terminal connected to the second conduction terminal of the driving transistor Tdr, the first conduction terminal of the initialization transistor TF, and the anode terminal of the light-emitting element OLED, and a second conduction terminal connected to the gate terminal of the driving transistor Tdr and the first electrode of the data holding capacitor C. For the second writing control transistor TE, the gate terminal is connected to the scanning signal line gl (n), the first on terminal is connected to the initialization power supply wiring, and the second on terminal is connected to the first on terminal of the driving transistor Tdr and the second on terminal of the light-emission control transistor TB. The initialization transistor TF has a gate terminal connected to the scanning signal line GL (n-1), a first on terminal connected to the second on terminal of the driving transistor Tdr, the first on terminal of the threshold voltage compensation transistor TD, and the anode terminal of the light emitting element OLED, and a second on terminal connected to the initialization power supply line.

With respect to the data holding capacitor C, a first electrode is connected to the gate terminal of the driving transistor Tdr and the second on terminal of the threshold voltage compensation transistor TD, and a second electrode is connected to the second on terminal of the power supply control transistor TA and the second on terminal of the first write control transistor TC. The anode terminal of the light-emitting element OLED is connected to the second conduction terminal of the driving transistor Tdr, the first conduction terminal of the threshold voltage compensation transistor TD, and the first conduction terminal of the initialization transistor TF, and the cathode terminal thereof is connected to the second power supply wiring.

As described above, with the pixel circuit 10 located in the nth row, the scanning signal G (n-1) applied to the scanning signal line GL (n-1) in the (n-1) th row is applied to the gate terminal of the initialization transistor TF, the scanning signal G (n) applied to the scanning signal line GL (n) in the nth row is applied to the gate terminal of the first write control transistor TC and the gate terminal of the second write control transistor TE, the emission control signal em (n) applied to the emission control line eml (n) in the nth row is applied to the gate terminal of the emission control transistor TB, a signal representing the logical sum of the scanning signal G (n-1) and the scanning signal G (n) is applied to the gate terminal of the threshold voltage compensation transistor TD, and a signal representing the logical sum of the scanning signal G (n-1) and the emission control signal em (n) is applied to the gate terminal of the power supply control transistor TA.

In this embodiment, the light emission control unit is implemented by the light emission control transistor TB, the power supply control unit is implemented by the power supply control transistor TA, and the threshold voltage compensation unit is implemented by the threshold voltage compensation transistor TD.

In addition, it is preferable to use TFTs having a double gate structure in which off current is reduced for the power supply control transistor TA, the light emission control transistor TB, the first write control transistor TC, and the second write control transistor TE among seven transistors in the pixel circuit 10.

Incidentally, in order to generate a signal to be applied to the gate terminal of the power supply control transistor TA, the OR circuit 11, in which the scan signal G (n-1) is applied to one input terminal and the emission control signal em (n) is applied to the other input terminal, is provided, for example, in the vicinity of the end portion of the display portion 100 as shown in fig. 3. Similarly, in order to generate a signal to be applied to the gate terminal of the threshold voltage compensation transistor TD, the OR circuit 12, in which the scan signal G (n-1) is applied to one input terminal and the scan signal G (n) is applied to the other input terminal, is provided, for example, in the vicinity of the end portion of the display portion 100 as shown in fig. 4. An output terminal of the OR circuit 11 is connected to the first logic sum signal wiring described above, and an output terminal of the OR circuit 12 is connected to the second logic sum signal wiring described above. A conventional configuration can be adopted for the specific internal configuration of the OR circuit 11 and the OR circuit 12. In addition, the notation of "#" of fig. 1, fig. 3, or the like is an output representing a logical sum (logical sum of two signal values).

In the present embodiment, each circuit is active and low. Therefore, when at least one of the scanning signal G (n-1) and the emission control signal em (n) is at a low level, an output signal from the OR circuit 11 (a signal indicating a logical sum of the scanning signal G (n-1) and the emission control signal em (n)) is at a low level. When at least one of the scan signal G (n-1) and the scan signal G (n) is at a low level, an output signal from the OR circuit 12 (a signal indicating a logical sum of the scan signal G (n-1) and the scan signal G (n)) is at a low level.

Since the OR circuits 11 and 12 are provided for each row as described above, i first logic and signal wirings and i second logic and signal wirings are provided in the display portion 100 in the present embodiment (however, these are omitted in fig. 2).

<1.3 Driving method >

Next, a driving method will be described. Fig. 5 is a timing chart for explaining a driving method of the pixel circuit 10 located in the nth row (the pixel circuit shown in fig. 1). In fig. 5, the period before the time t10 and the period after the time t15 are light-emitting periods for the pixel circuits 10 located in the nth row, and the periods from the time t10 to the time t15 are non-light-emitting periods for the pixel circuits 10 located in the nth row. When the non-emission period is considered, the period from time t11 to time t12 is an initialization period, and the period from time t13 to time t14 is a data writing period. As can be understood from fig. 5, the scanning signal G (n-1) is a signal activated in the initialization period, the scanning signal G (n) is a signal activated in the data writing period, and the emission control signal em (n) is a signal activated in the emission period.

Before time t10, scan signal G (n-1) and scan signal G (n) are at high level, and emission control signal em (n) is at low level. At this time, the power supply control transistor TA and the light emission control transistor TB are turned ON, and the first write control transistor TC, the threshold voltage compensation transistor TD, the second write control transistor TE, and the initialization transistor TF are turned OFF. Thereby, a drive current having a magnitude corresponding to the voltage between the first on terminal and the gate terminal of the drive transistor Tdr is supplied to the light emitting element OLED, and the light emitting element OLED emits light.

At time t10, emission control signal em (n) changes from low level to high level. Thereby, the power supply control transistor TA and the light emission control transistor TB are turned OFF. As a result, the supply of current to the light emitting element OLED is cut off, and the light emitting element OLED is in a non-emission state (off state).

At time t11, the scanning signal G (n-1) changes from high level to low level. Thereby, the power supply control transistor TA, the threshold voltage compensation transistor TD, and the initialization transistor TF are turned ON. The threshold voltage compensation transistor TD and the initialization transistor TF are turned ON, whereby the initialization voltage Vini is applied to the first electrode of the data holding capacitor C as indicated by an arrow denoted by reference numeral 611 in fig. 6. Further, the power supply control transistor TA is turned ON, and thereby the high-level power supply voltage ELVDD is applied to the second electrode of the data holding capacitor C as indicated by an arrow denoted by reference numeral 612 in fig. 6. As a result, the voltage having the magnitude of "ELVDD-Vini" is held in the data holding capacitor C. In this manner, the gate voltage of the driving transistor Tdr is initialized.

At time t12, the scanning signal G (n-1) changes from low to high. Thereby, the power supply control transistor TA, the threshold voltage compensation transistor TD, and the initialization transistor TF are turned OFF. Thereby, initialization of the gate voltage of the driving transistor Tdr is ended.

At time t13, the scanning signal g (n) changes from high level to low level. Thereby, the first write control transistor TC, the threshold voltage compensation transistor TD, and the second write control transistor TE are turned ON. The first write control transistor TC is turned ON, and thereby a data voltage (voltage of the data signal D) Vdata is applied to the second electrode of the data holding capacitor C as indicated by an arrow denoted by reference numeral 613 in fig. 7. In this regard, in a state where the voltage having the magnitude of "ELVDD-Vini" is held in the data holding capacitor C as described above, the first write control transistor TC is turned ON. Therefore, the gate voltage Vg of the driving transistor Tdr has a magnitude shown in the following expression (5).

Vg＝Vdata-(ELVDD-Vini)

＝(Vdata-ELVDD)+Vini...(5)

Here, the maximum value of the data voltage Vdata is set to a value smaller than the high-level power supply voltage ELVDD, and "Vdata-ELVDD" is a negative value. Therefore, the gate voltage Vg of the driving transistor Tdr becomes smaller than the initialization voltage Vini, and a current flows between the first conductive terminal and the second conductive terminal of the driving transistor Tdr as indicated by an arrow denoted by reference numeral 614 in fig. 7. When the threshold voltage (absolute value) of the driving transistor Tdr is denoted by Vth, a voltage having a magnitude of "Vini-Vth" is applied to the first electrode of the data holding capacitor C. Since the data voltage Vdata is applied to the second electrode of the data holding capacitor C, a voltage of the magnitude of "Vdata- (Vini-Vth)" is held in the data holding capacitor C. In this manner, data is written (charging of the data storage capacitor C by the data signal D) from time t13 to time t 14.

At time t14, the scanning signal g (n) changes from low level to high level. Thereby, the first write control transistor TC, the threshold voltage compensation transistor TD, and the second write control transistor TE are turned OFF. This completes the data writing.

At time t15, emission control signal em (n) changes from high level to low level. Thereby, the power supply control transistor TA and the light emission control transistor TB are turned ON. As a result, a drive current having a magnitude corresponding to the voltage between the first on terminal and the gate terminal of the drive transistor Tdr is supplied to the light emitting element OLED as indicated by an arrow denoted by reference numeral 615 in fig. 8, and the light emitting element OLED emits light according to the magnitude of the drive current. Then, at time t10 of the next frame, the light emitting element OLED emits light until the light emission control signal em (n) changes from the low level to the high level.

Incidentally, at time t15, the power supply control transistor TA is turned ON, and the high-level power supply voltage ELVDD is applied to the second electrode of the data storage capacitor C. Before time t15, the voltage having the magnitude of "Vdata- (Vini-Vth)" is held in the data holding capacitor C as described above. Therefore, the gate voltage Vg of the driving transistor Tdr has a magnitude shown in the following expression (6) during the light emission period.

Vg＝ELVDD-(Vdata-(Vini-Vth))

＝ELVDD-(Vdata-Vini+Vth)...(6)

At this time, the voltage Vgs between the first on terminal and the gate terminal of the driving transistor Tdr is expressed by the following equation (7).

Vgs＝ELVDD-Vg

＝ELVDD-(ELVDD-(Vdata-Vini+Vth))

＝Vdata-Vini+Vth...(7)

The drive current Ioled is obtained by the above equation (2). If the above formula (7) is substituted into the above formula (2), the following formula (8) is obtained.

Ioled＝β/2·(Vdata-Vini)²...(8)

In the above equation (8), the term of the threshold voltage Vth is not included. That is, regardless of the magnitude of the threshold voltage Vth of the driving transistor Tdr, the driving current Ioled according to the magnitude of the data voltage Vdata is supplied to the light emitting element OLED. Therefore, the deviation of the threshold voltage Vth of the driving transistor Tdr is compensated.

In this embodiment, the scan signal G (n-1) corresponds to a first control signal, the scan signal G (n) corresponds to a second control signal, the emission control signal em (n) corresponds to a third control signal, a signal indicating the logical sum of the scan signal G (n-1) and the scan signal G (n) corresponds to a fourth control signal, and a signal indicating the logical sum of the scan signal G (n-1) and the emission control signal em (n) corresponds to a fifth control signal. The operation performed during the period from time t11 to time t12 corresponds to the initialization step, the operation performed during the period from time t13 to time t14 corresponds to the data writing step, and the operation performed during the period before time t10 and the period after time t15 corresponds to the light emitting step.

<1.4 Effect >

According to the present embodiment, data is written by applying the state data voltage Vdata applied to the first electrode of the data holding capacitor C via the driving transistor Tdr at the initialization voltage Vini to the second electrode of the data holding capacitor C. In this regard, in the organic EL panel, the amount of current flowing through the initialization power supply wiring that delivers the initialization voltage Vini is significantly less than the amount of current flowing through the first power supply wiring that delivers the high-level power supply voltage ELVDD (since the high-level power supply voltage ELVDD contributes to the supply of current to cause the light emitting element OLED to emit light). Therefore, the variation in the magnitude of the voltage is small for the initialization voltage Vini. That is, data is written into the data holding capacitor C by applying the data voltage Vdata to the electrode (second electrode) facing the electrode (first electrode) to which a substantially constant voltage is applied. Therefore, stable data writing can be performed. This prevents the occurrence of luminance variations when writing data with the same magnitude of the data voltage Vdata. Although the magnitude of the driving current Ioled depends on the magnitude of the threshold voltage Vth of the driving transistor Tdr, a voltage corresponding to the data voltage Vdata and the threshold voltage of the driving transistor Tdr is held in the data holding capacitor C before the light emitting element OLED emits light. Thus, when the light emitting element OLED emits light, the influence of the threshold voltage Vth is canceled, and the drive current Ioled having a magnitude corresponding to the data voltage Vdata is supplied to the light emitting element OLED. That is, the deviation of the threshold voltage Vth of the driving transistor Tdr is compensated. As described above, according to the present embodiment, an organic EL display device capable of compensating for the variation in the threshold voltage Vth of the driving transistor Tdr without causing the variation in luminance is realized.

<2 > second embodiment

The second embodiment will be explained. Note that, since the entire configuration is the same as that of the first embodiment, the description thereof is omitted.

<2.1 construction of pixel Circuit >

The structure of the pixel circuit 10 according to the present embodiment will be described with reference to fig. 9. As shown in fig. 9, the pixel circuit 10 includes a light emitting element OLED, eight transistors (a driving transistor Tdr, a first power supply control transistor TA1, a second power supply control transistor TA2, a light emission control transistor TB, a first writing control transistor TC, a threshold voltage compensation transistor TD, a second writing control transistor TE, and an initialization transistor TF), and a data holding capacitor C. Hereinafter, description will be given mainly on points different from the first embodiment, and description will be appropriately omitted on points similar to the first embodiment.

In the first embodiment, one power supply control transistor TA (refer to fig. 1) is provided in order to apply the high-level voltage ELVDD to the second electrode of the data holding capacitor C during the initialization period and the light emission period. In contrast, in the present embodiment, a first power supply control transistor TA1 and a second power supply control transistor TA2 are provided instead of the power supply control transistor TA of the first embodiment, as shown in fig. 9. The first power supply control transistor TA1 has a gate terminal connected to the scanning signal line GL (n-1), a first on terminal connected to the first power supply wiring, and a second on terminal connected to the second electrode of the data holding capacitor C, the second on terminal of the first write control transistor TC, and the second on terminal of the second power supply control transistor TA2. The second power supply control transistor TA2 has a gate terminal connected to the emission control line eml (n), a first on terminal connected to the first on terminal of the driving transistor Tdr, the second on terminal of the emission control transistor TB, and the second on terminal of the second write control transistor TE, and a second on terminal connected to the second electrode of the data holding capacitor C9, the second on terminal of the first power supply control transistor TA1, and the second on terminal of the first write control transistor TC.

In this embodiment, the light emission control section is implemented by the light emission control transistor TB, the power supply control section is implemented by the first power supply control transistor TA1 and the second power supply control transistor TA2, and the threshold voltage compensation section is implemented by the threshold voltage compensation transistor TD.

Further, it is preferable to use TFTs having a double gate structure in which off current is reduced for the first power supply control transistor TA1, the second power supply control transistor TA2, the light emission control transistor TB, the first write control transistor TC, and the second write control transistor TE.

<2.2 Driving method >

Next, a driving method will be described. Fig. 10 is a timing chart for explaining a driving method of the pixel circuit 10 located in the nth row (the pixel circuit shown in fig. 9). Since it is easy to compare with the first embodiment, the same reference numerals as those in fig. 5 are used for the reference numerals indicating the time (the same applies to fig. 16 and 21).

Before time t10, scan signal G (n-1) and scan signal G (n) are at high level, and emission control signal em (n) is at low level. At this time, the light emission control transistor TB and the second power supply control transistor TA2 are turned ON, and the first power supply control transistor TA1, the first write control transistor TC, the threshold voltage compensation transistor TD, the second write control transistor TE, and the initialization transistor TF are turned OFF. Thus, a drive current having a magnitude corresponding to the voltage between the first on terminal and the gate terminal of the drive transistor Tdr is supplied to the light emitting element OLED, and the light emitting element OLED emits light.

At time t10, emission control signal em (n) changes from low level to high level. Thereby, the light emission control transistor TB and the second power supply control transistor TA2 are turned OFF. As a result, the supply of current to the light emitting element OLED is cut off, and the light emitting element OLED is in a non-emission state (off state).

At time t11, the scanning signal G (n-1) changes from high level to low level. Thus, as in the first embodiment, the initialization voltage Vini is applied to the first electrode of the data holding capacitor C (see the arrow denoted by reference numeral 621 in fig. 11), and the high-level power supply voltage ELVDD is applied to the second electrode of the data holding capacitor C (see the arrow denoted by reference numeral 622 in fig. 11). As a result, the voltage having the magnitude of "ELVDD-Vini" is held in the data holding capacitor C. At time t12, the scanning signal G (n-1) changes from low to high. Thereby, similarly to the first embodiment, initialization of the gate voltage of the driving transistor Tdr is completed.

At time t13, the scanning signal g (n) changes from high level to low level. Thus, as in the first embodiment, the data voltage Vdata is applied to the second electrode of the data holding capacitor C (see the arrow denoted by reference numeral 623 in fig. 12), and a voltage having a magnitude of "Vini-Vth" is applied to the first electrode of the data holding capacitor C (see the arrow denoted by reference numeral 624 in fig. 12). As a result, a voltage having a magnitude of "Vdata- (Vini-Vth)" is held in the data holding capacitor C. At time t14, the scanning signal g (n) changes from low level to high level. Thus, the data writing is completed as in the first embodiment.

At time t15, emission control signal em (n) changes from high level to low level. Thereby, the light emission control transistor TB and the second power supply control transistor TA2 are turned ON. At this time, in the first embodiment, the high-level power supply voltage ELVDD is applied to the second electrode of the data holding capacitor C via the power supply control transistor TA (refer to fig. 1), but in the present embodiment, the high-level power supply voltage ELVDD is applied to the second electrode of the data holding capacitor C via the light emission control transistor TB and the second power supply control transistor TA2. As a result, the same operation as the first embodiment is performed. That is, a drive current having a magnitude corresponding to the voltage between the first on terminal and the gate terminal of the drive transistor Tdr is supplied to the light emitting element OLED as shown by an arrow denoted by reference numeral 625 in fig. 13, and the light emitting element OLED emits light according to the magnitude of the drive current. The gate voltage Vg of the driving transistor Tdr, the voltage Vgs between the first on terminal and the gate terminal of the driving transistor Tdr, and the driving current Ioled in the light emission period are the same as those in the first embodiment. Therefore, as in the first embodiment, the variation in the threshold voltage Vth of the driving transistor Tdr is compensated.

<2.3 Effect >

In the present embodiment, data is also written into the data holding capacitor C by applying the data voltage Vdata to the electrode (second electrode) facing the electrode (first electrode) to which a substantially constant voltage is applied. Therefore, stable data writing can be performed, and the occurrence of luminance variation when data is written by the data voltage Vdata of the same magnitude can be prevented. In the present embodiment, a voltage corresponding to the data voltage Vdata and the threshold voltage of the driving transistor Tdr is held in the data holding capacitor C before the light emitting element OLED emits light. Therefore, when the light emitting element OLED emits light, the deviation of the threshold voltage Vth of the driving transistor Tdr is compensated. As described above, the organic EL display device capable of compensating for the variation in the threshold voltage Vth of the driving transistor Tdr without causing the variation in luminance is realized as in the first embodiment.

In the present embodiment, unlike the first embodiment, it is not necessary to apply a signal (composite signal) indicating the logical sum of the scanning signal G (n-1) and the emission control signal em (n) to the pixel circuit 10. Therefore, the first logic and signal wiring (i first logic and signal wirings in the entire display unit 100) is not necessary. Therefore, the number of control lines required to operate the pixel circuit 10 can be reduced as compared with the first embodiment.

<2.4 modification >

Fig. 14 is a circuit diagram showing the configuration of the pixel circuit 10 according to a modification of the second embodiment. In this modification, a first light emission control transistor TB1 and a second light emission control transistor TB2 are provided instead of the one light emission control transistor TB of the second embodiment as shown in fig. 14. The first light emission control transistor TB1 has a gate terminal connected to the light emission control line eml (n), a first on terminal connected to the first power supply wiring, and a second on terminal connected to the first on terminal of the second light emission control transistor TB2 and the first on terminal of the second power supply control transistor TA2. For the second light emission control transistor TB2, the gate terminal is connected to the light emission control line eml (n), the first conduction terminal is connected to the second conduction terminal of the first light emission control transistor TB1 and the first conduction terminal of the second power supply control transistor TA2, and the second conduction terminal is connected to the first conduction terminal of the drive transistor Tdr and the second conduction terminal of the second write control transistor TE. In the present modification, the light emission control section is implemented by the first light emission control transistor TB1 and the second light emission control transistor TB2. Note that, since the driving method is the same as that of the second embodiment, the description thereof is omitted (see fig. 10).

In the configuration of the second embodiment (see fig. 9), it is preferable to use TFTs having a double gate structure for the second emission control transistor TB2 and the second power supply control transistor TA2, but according to the configuration of the present modification, the off current can be sufficiently reduced even in the case of using TFTs having a single gate structure for the three TFTs (the first emission control transistor TB1, the second emission control transistor TB2, and the second power supply control transistor TA 2). This can reduce the total number of TFTs in the pixel circuit 10.

<3 > third embodiment

The third embodiment will be explained. Note that, since the entire configuration is the same as that of the first embodiment, the description thereof is omitted.

<3.1 construction of pixel Circuit >

The structure of the pixel circuit 10 according to the present embodiment will be described with reference to fig. 15. As shown in fig. 15, the pixel circuit 10 includes a light emitting element OLED, eight transistors (a driving transistor Tdr, a power supply control transistor TA, a light emission control transistor TB, a first write control transistor TC, a first threshold voltage compensation transistor TD1, a second threshold voltage compensation transistor TD2, a second write control transistor TE, and an initialization transistor TF), and a data holding capacitor C.

In the first embodiment, one threshold voltage compensating transistor TD (see fig. 1) is provided between the gate terminal and the second conductive terminal of the driving transistor Tdr to electrically connect the driving transistor Tdr during the initialization period and the data writing period. In contrast, in the present embodiment, a first threshold voltage compensation transistor TD1 and a second threshold voltage compensation transistor TD2 are provided instead of the threshold voltage compensation transistor TD of the first embodiment, as shown in fig. 15.

For the first threshold voltage compensation transistor TD1, the gate terminal is connected to the scanning signal line GL (n-1), the first on terminal is connected to the second on terminal of the driving transistor Tdr, the first on terminal of the initialization transistor TF, the first on terminal of the second threshold voltage compensation transistor TD2, and the anode terminal of the light emitting element OLED, and the second on terminal is connected to the gate terminal of the driving transistor Tdr, the second on terminal of the second threshold voltage compensation transistor TD2, and the first electrode of the data holding capacitor C. The second threshold voltage compensation transistor TD2 has a gate terminal connected to the scanning signal line gl (n), a first on terminal connected to the second on terminal of the driving transistor Tdr, the first on terminal of the initialization transistor TF, the first on terminal of the first threshold voltage compensation transistor TD1, and the anode terminal of the light emitting element OLED, and a second on terminal connected to the gate terminal of the driving transistor Tdr, the second on terminal of the first threshold voltage compensation transistor TD1, and the first electrode of the data holding capacitor C. In this way, the first threshold voltage compensation transistor TD1 is connected between the gate terminal and the second conduction terminal of the driving transistor Tdr in parallel with the second threshold voltage compensation transistor TD2.

In this embodiment, the light emission control unit is implemented by the light emission control transistor TB, the power supply control unit is implemented by the power supply control transistor TA, and the threshold voltage compensation unit is implemented by the first threshold voltage compensation transistor TD1 and the second threshold voltage compensation transistor TD2.

<3.2 Driving method >

Next, a driving method will be described. Fig. 16 is a timing chart for explaining a driving method of the pixel circuit 10 located in the nth row (the pixel circuit shown in fig. 15).

Before time t10, scan signal G (n-1) and scan signal G (n) are at high level, and emission control signal em (n) is at low level. At this time, the power supply control transistor TA and the light emission control transistor TB are turned ON. Therefore, as in the first embodiment, a drive current having a magnitude corresponding to the voltage between the first on terminal and the gate terminal of the drive transistor Tdr is supplied to the light emitting element OLED, and the light emitting element OLED emits light.

At time t10, emission control signal em (n) changes from low level to high level. Thus, as in the first embodiment, the supply of current to the light emitting element OLED is cut off, and the light emitting element OLED is in a non-emission state (light-off state).

At time t11, the scanning signal G (n-1) changes from high level to low level. Thereby, the power supply control transistor TA, the first threshold voltage compensation transistor TD1, and the initialization transistor TF are turned ON. The first threshold voltage compensation transistor TD1 and the initialization transistor TF are turned ON, and thereby the initialization voltage Vini is applied to the first electrode of the data holding capacitor C through the first threshold voltage compensation transistor TD1 as indicated by an arrow denoted by reference numeral 631 in fig. 17. In addition, the high-level power supply voltage ELVDD is applied to the second electrode of the data holding capacitor C (see the arrow denoted by reference numeral 632 in fig. 17) as in the first embodiment. As a result, the voltage having the magnitude of "ELVDD-Vini" is held in the data holding capacitor C.

At time t12, the scanning signal G (n-1) changes from low to high. Thereby, the power supply control transistor TA, the first threshold voltage compensation transistor TD1, and the initialization transistor TF are turned OFF, and initialization of the gate voltage of the drive transistor Tdr is completed.

At time t13, the scanning signal g (n) changes from high level to low level. Thereby, the first write control transistor TC, the second threshold voltage compensation transistor TD2, and the second write control transistor TE are turned ON. When the first write control transistor TC is turned ON, the data voltage Vdata is applied to the second electrode of the data holding capacitor C (see the arrow designated by reference numeral 633 in fig. 17), as in the first embodiment. Further, the second threshold voltage compensation transistor TD2 and the second write control transistor TE are turned ON, and thus a voltage having a magnitude of "Vini-Vth" is applied to the first electrode of the data holding capacitor C via the second threshold voltage compensation transistor TD2 as indicated by an arrow denoted by reference numeral 634 in fig. 18. As a result, a voltage having a magnitude of "Vdata- (Vini-Vth)" is held in the data holding capacitor C.

At time t14, the scanning signal g (n) changes from low level to high level. Thereby, the first write control transistor TC, the second threshold voltage compensation transistor TD2, and the second write control transistor TE are turned OFF, and data writing is completed.

At time t15, emission control signal em (n) changes from high level to low level. Thereby, the power supply control transistor TA and the light emission control transistor TB are turned ON. Therefore, as in the first embodiment, a drive current having a magnitude corresponding to the voltage between the first on terminal and the gate terminal of the drive transistor Tdr is supplied to the light emitting element OLED as shown by an arrow denoted by reference numeral 635 in fig. 19, and the light emitting element OLED emits light according to the magnitude of the drive current. The gate voltage Vg of the driving transistor Tdr, the voltage Vgs between the first on terminal and the gate terminal of the driving transistor Tdr, and the driving current Ioled in the light emission period are the same as those in the first embodiment. Therefore, as in the first embodiment, the variation in the threshold voltage Vth of the driving transistor Tdr is compensated.

<3.3 Effect >

In the present embodiment, as in the first embodiment, an organic EL display device capable of compensating for variations in the threshold voltage Vth of the driving transistor Tdr without causing variations in luminance is also realized. In the present embodiment, unlike the first embodiment, it is not necessary to apply a signal (composite signal) indicating the logical sum of the scanning signal G (n-1) and the scanning signal G (n) to the pixel circuit 10. Therefore, the second logic and signal wiring (i second logic and signal wirings in the entire display unit 100) is not necessary. Therefore, the number of control lines required to operate the pixel circuit 10 can be reduced as compared with the first embodiment.

<4 > fourth embodiment

A fourth embodiment will be explained. In the present embodiment, the pixel circuit 10 has a configuration in which the configuration of the modification of the second embodiment (see fig. 14) and the configuration of the third embodiment (see fig. 15) are combined. Note that, since the entire configuration is the same as that of the first embodiment, the description thereof is omitted.

<4.1 construction of pixel Circuit >

The structure of the pixel circuit 10 according to the present embodiment will be described with reference to fig. 20. As shown in fig. 20, the pixel circuit 10 includes a light emitting element OLED, ten transistors (a driving transistor Tdr, a first power supply control transistor TA1, a second power supply control transistor TA2, a first light emission control transistor TB1, a second light emission control transistor TB2, a first writing control transistor TC, a first threshold voltage compensation transistor TD1, a second threshold voltage compensation transistor TD2, a second writing control transistor TE, and an initialization transistor TF), and a data holding capacitor C.

As can be understood from fig. 20, similarly to the modification of the second embodiment, a first power supply control transistor TA1 and a second power supply control transistor TA2 are provided instead of the power supply control transistor TA of the first embodiment. In addition, as in the modification of the second embodiment, a first light emission control transistor TB1 and a second light emission control transistor TB2 are provided instead of the light emission control transistor TB of the first embodiment. In addition, as in the third embodiment, a first threshold voltage compensation transistor TD1 and a second threshold voltage compensation transistor TD2 are provided instead of the threshold voltage compensation transistor TD of the first embodiment.

In this embodiment, the light emission control unit is implemented by the first light emission control transistor TB1 and the second light emission control transistor TB2, the power supply control unit is implemented by the first power supply control transistor TA1 and the second power supply control transistor TA2, and the threshold voltage compensation unit is implemented by the first threshold voltage compensation transistor TD1 and the second threshold voltage compensation transistor TD2.

In the present embodiment, it is preferable that the first write control transistor TC and the second write control transistor TE are TFTs having a double gate structure with a small off-current.

<4.2 Driving method >

Next, a driving method will be described. Fig. 21 is a timing chart for explaining a driving method of the pixel circuit 10 located in the nth row (the pixel circuit shown in fig. 20).

Before time t10, scan signal G (n-1) and scan signal G (n) are at high level, and emission control signal em (n) is at low level. At this time, the first light emission control transistor TB1, the second light emission control transistor TB2, and the second power supply control transistor TA2 are turned ON, and the first power supply control transistor TA1, the first write control transistor TC, the first threshold voltage compensation transistor TD1, the second threshold voltage compensation transistor TD2, the second write control transistor TE, and the initialization transistor TF are turned OFF. Thus, a drive current having a magnitude corresponding to the voltage between the first on terminal and the gate terminal of the drive transistor Tdr is supplied to the light emitting element OLED, and the light emitting element OLED emits light.

At time t10, emission control signal em (n) changes from low level to high level. Thereby, the first light emission controlling transistor TB1, the second light emission controlling transistor TB2, and the second power supply controlling transistor TA2 are turned OFF. As a result, the supply of current to the light emitting element OLED is cut off, and the light emitting element OLED is in a non-emission state (off state).

At time t11, the scanning signal G (n-1) changes from high level to low level. Thus, as in the third embodiment, the initialization voltage Vini is applied to the first electrode of the data storage capacitor C via the first threshold voltage compensation transistor TD1 as indicated by an arrow denoted by reference numeral 641 in fig. 22. In addition, as in the second embodiment, the high-level power supply voltage ELVDD is applied to the second electrode of the data holding capacitor C (see the arrow denoted by reference numeral 642 in fig. 22). As a result, the voltage having the magnitude of "ELVDD-Vini" is held in the data holding capacitor C.

At time t12, the scanning signal G (n-1) changes from low to high. Thereby, the first power supply control transistor TA1, the first threshold voltage compensation transistor TD1, and the initialization transistor TF are turned OFF, and the initialization of the gate voltage of the driving transistor Tdr is completed.

At time t13, the scanning signal g (n) changes from high level to low level. Thus, as in the first embodiment, the data voltage Vdata is applied to the second electrode of the data holding capacitor C (see an arrow denoted by 643 in fig. 23). In the same manner as in the third embodiment, a voltage having a magnitude of "Vini-Vth" is applied to the first electrode of the data storage capacitor C via the second threshold voltage compensation transistor TD2 as indicated by an arrow denoted by reference numeral 644 in fig. 23. As a result, a voltage having a magnitude of "Vdata- (Vini-Vth)" is held in the data holding capacitor C.

At time t14, the scanning signal g (n) changes from low level to high level. Thereby, the first write control transistor TC, the second threshold voltage compensation transistor TD2, and the second write control transistor TE are turned OFF, and data writing is completed.

At time t15, emission control signal em (n) changes from high level to low level. Thereby, the first light emission controlling transistor TB1, the second light emission controlling transistor TB2, and the second power supply controlling transistor TA2 are turned ON. At this time, the high-level power supply voltage ELVDD is applied to the second electrode of the data holding capacitor C via the first light emission controlling transistor TB1 and the second power supply controlling transistor TA2, as in the second embodiment. As a result, a drive current having a magnitude corresponding to the voltage between the first conduction terminal and the gate terminal of the drive transistor Tdr is supplied to the light emitting element OLED as indicated by an arrow denoted by reference numeral 645 in fig. 24, and the light emitting element OLED emits light according to the magnitude of the drive current. The gate voltage Vg of the driving transistor Tdr, the voltage Vgs between the first on terminal and the gate terminal of the driving transistor Tdr, and the driving current Ioled in the light emission period are the same as those in the first embodiment. Therefore, as in the first embodiment, the variation in the threshold voltage Vth of the driving transistor Tdr is compensated.

<4.3 Effect >

In the present embodiment, as in the first embodiment, an organic EL display device capable of compensating for variations in the threshold voltage Vth of the driving transistor Tdr without causing variations in luminance is also realized. Unlike the first embodiment, it is not necessary to apply a signal (composite signal) indicating the logical sum of the scanning signal G (n-1) and the emission control signal em (n), and a signal (composite signal) indicating the logical sum of the scanning signal G (n-1) and the scanning signal G (n) to the pixel circuit 10. Therefore, the first logic and signal wiring (i first logic and signal wirings in the entire display unit 100) and the second logic and signal wiring (i second logic and signal wirings in the entire display unit 100) are not required. Therefore, the number of control lines required to operate the pixel circuit 10 can be significantly smaller than that in the first embodiment. In addition, similarly to the modification of the second embodiment, even when TFTs having a single-gate structure are used for the first light emission controlling transistor TB1, the second light emission controlling transistor TB2, and the second power supply controlling transistor TA2, the off current can be sufficiently reduced. Therefore, the total number of TFTs in the pixel circuit 10 can be reduced.

<5. summary >

In summary, the pixel circuit 10 described below (see fig. 25) can be used in the first to fourth embodiments (including the modifications).

The pixel circuit 10 includes:

a light emitting element OLED disposed between the first power supply wiring to which the high-level power supply voltage ELVDD is applied and the second power supply wiring to which the low-level power supply voltage ELVSS is applied, and emitting light at a luminance corresponding to the amount of current supplied;

a data holding capacitor C including: a first electrode; and a second electrode;

a driving transistor Tdr including: a gate terminal provided between the first power supply wiring and the second power supply wiring in series with the light emitting element OLED, connected to the first electrode of the data holding capacitor C; a first turn-on terminal to which a high-level power supply voltage ELVDD is applied during light emission; and a second conduction terminal electrically connected to the gate terminal during data writing and electrically isolated from the gate terminal during the light emission period;

an initialization transistor TF comprising: a gate terminal to which an activated signal is applied during initialization; a first on terminal connected to a wiring between the gate terminal of the driving transistor Tdr and the second on terminal; and a second conduction terminal connected to the initialization power supply wiring;

a first write control transistor TC comprising: a gate terminal to which an activated signal is applied during the data writing; a first on terminal connected to the data signal line DL; and a second conduction terminal connected to the second electrode of the data holding capacitor C;

a first write control transistor TE, including: a gate terminal to which an activated signal is applied during the data writing; a first conduction terminal connected to the initialization power supply wiring; and a second conduction terminal connected to the first conduction terminal of the driving transistor Tdr;

a light emission control unit 71 that controls supply of current to the light emitting element OLED;

a power supply control section 72 for electrically connecting the second electrode of the data holding capacitor C and the first power supply wiring during the initialization period and the light emission period; and

the threshold voltage compensation unit 73 is used to electrically connect the first electrode of the data holding capacitor C and the initialization power supply line during the initialization period and the data writing period.

<6. others >

Although the organic EL display device is exemplified in the above embodiments (including the modifications), the type of the display device is not particularly limited. As a display device including a display element whose luminance is controlled by a current (current-driven display device), the present invention can be applied to an inorganic EL display device including an inorganic Light Emitting Diode, a QLED display device including a QLED (quantum dot Light Emitting Diode), and the like.

Description of the reference numerals

A pixel circuit; 100.. a display portion; a display control circuit; a gate driver; a firing driver; a source driver; DL (1) -DL (j.. data signal lines; GL (1) -GL (i).. scan signal lines; an EML (1) to EML (i).. emission control line; a drive transistor; TA.. a power supply control transistor; a first power supply control transistor; a second power supply control transistor; TB.. a light emission control transistor; a first lighting control transistor; a second emission control transistor; TC.. a first write control transistor; TD.. a threshold voltage compensation transistor; a first threshold voltage compensation transistor; a second threshold voltage compensation transistor; TE.. a second write control transistor; TF.. initializing a transistor; a data signal; g (1) -G (i.. scan signals); EM (1) -EM (i.). luminescence control signal; data voltage; initializing a voltage; an elvdd.. high level power supply voltage; low level supply voltage