阅读说明：本技术 半导体器件及其制造方法 (Semiconductor device and method for manufacturing the same ) 是由 罗军 赵超 刘实 于 2017-01-10 设计创作，主要内容包括：本发明涉及一种半导体器件及其制造方法。提供了一种半导体器件,包括：具有鳍的半导体衬底；与鳍相交的栅极以及位于栅极两侧的鳍内的源区和漏区；分别在源区和漏区处形成且与源区和漏区相接触的金属硅化物；其中在所述金属硅化物与源区、漏区接触的界面处存在能够降低金属硅化物与源区、漏区之间的肖特基势垒高度的杂质掺杂物。所提供的半导体器件能够降低金属硅化物与源区、漏区之间的肖特基势垒高度,进而减小接触的比电阻。(The present invention relates to a semiconductor device and a method of manufacturing the same. Provided is a semiconductor device including: a semiconductor substrate having a fin; a gate intersecting the fin and a source region and a drain region in the fin on both sides of the gate; metal silicides formed at and contacting the source region and the drain region, respectively; wherein impurity dopants capable of reducing the Schottky barrier height between the metal silicide and the source region and the drain region are present at the interfaces of the metal silicide, the source region and the drain region. The semiconductor device can reduce the Schottky barrier height between the metal silicide and the source region and the drain region, and further reduce the specific resistance of the contact.)

1. A semiconductor device, comprising:

a semiconductor substrate having a fin;

the gate is intersected with the fin, and the source region and the drain region are positioned in the fin on two sides of the gate and comprise n-type doped silicon;

metal silicide respectively formed on at least part of the upper surfaces of the source region and the drain region and contacted with the source region and the drain region;

the method comprises the steps of performing non-crystallization treatment before forming contact metal silicide in a source drain region to form a non-crystallization region in the source region and a drain region, wherein the metal silicide is formed by performing impurity dopant injection in the non-crystallization region, then depositing metal and annealing, wherein the impurity dopant exists at an interface where the metal silicide is in contact with the source region and the drain region, and the Schottky barrier height between the metal silicide and the source region and the drain region can be reduced; the implantation energy for impurity dopant implantation is between 0.5keV and 5 keV.

2. The semiconductor device of claim 1, wherein the impurity dopant comprises at least one selected from the group consisting of: C. ge, N, P, As, O, S, Se, Te, F, Cl.

3. The semiconductor device of claim 1, wherein the gate comprises a high-K gate dielectric and a metal gate conductor.

4. The semiconductor device of claim 1, wherein the metal silicide comprises titanium silicide.

5. A method of manufacturing a semiconductor device, comprising:

forming a fin on a semiconductor substrate;

forming a gate intersecting the fin;

forming a source region and a drain region in the fin on two sides of the grid electrode, wherein the source region and the drain region comprise n-type doped silicon;

depositing a dielectric on the fin;

etching the dielectric to form contact trenches over the source and drain regions, respectively, to expose at least portions of the upper surfaces of the source and drain regions;

performing amorphization treatment on at least part of the exposed upper surface through the contact groove;

implanting impurity dopants into at least a portion of the exposed upper surface through the contact trench;

depositing a metal in the contact trench after impurity dopant implantation, and performing annealing to form a metal silicide;

the impurity dopant can reduce the Schottky barrier height between the metal silicide and the source region and the drain region; the implantation energy for impurity dopant implantation is between 0.5keV and 5 keV.

6. The method of claim 5, wherein the implanted impurity dopants precipitate at the interfaces of the metal silicide with the source and drain regions during the annealing, thereby reducing the Schottky barrier height between the metal silicide and the source and drain regions.

7. The method of claim 5, wherein the precipitated impurity dopant is selected from any one of the following group: C. ge, N, P, As, O, S, Se, Te, F, Cl.

8. The method of claim 5, wherein the gate comprises a high-K gate dielectric and a metal gate conductor.

9. The method of claim 5, wherein the deposited metal comprises Ti/TiN and the metal silicide comprises titanium silicide.

10. The method of claim 5, wherein the annealing comprises rapid thermal annealing, laser annealing, and/or dynamic surface annealing.

11. The method of claim 5, wherein the amorphizing process comprises: a germanium implant is performed.

12. The method of claim 9, further comprising:

depositing tungsten in the contact trench to form a tungsten layer on the Ti/TiN;

chemical mechanical polishing is performed to planarize the upper surface of the tungsten layer.

13. The method of claim 5 wherein the amorphous silicon regions formed after the amorphizing process have a depth of 10nm or less.

14. The method of claim 13 wherein the impurity dopants are implanted into an amorphous silicon region.

15. The method of claim 14 wherein a majority of the implanted impurity dopants are confined in the amorphous silicon region.

16. The method of claim 13, further comprising: during the anneal, at least a portion of the amorphous silicon is regrown as crystalline silicon.

17. The method of claim 13, further comprising: after annealing, the amorphous silicon disappears by reaction with the deposited metal and/or solid phase epitaxial regrowth.

Technical Field

The present disclosure relates to the field of semiconductors, and in particular, to a semiconductor device and a method of manufacturing the same.

Background

As the size of planar semiconductor devices becomes smaller, short channel effects become more pronounced. For this reason, a three-dimensional type semiconductor device such as a FinFET (fin field effect transistor) is proposed. In general, a FinFET includes a fin vertically formed on a substrate and a gate intersecting the fin.

As the size of the FinFET becomes smaller, the source-drain series parasitic resistance of the FinFET has a greater and greater impact on the performance of the entire device. In order to improve the device performance, the source-drain series parasitic resistance needs to be further reduced. Meanwhile, as the size of the FinFET is smaller and smaller, the contact resistance of the source region and the drain region accounts for larger and larger proportion in the whole source-drain series parasitic resistance, so that the source-drain series parasitic resistance can be obviously reduced by reducing the contact resistance of the source region and the drain region. Therefore, the specific resistance (ρ) of the contact is further reduced_c) Will be a constant aim for the skilled person.

In the mainstream FinFET process at present, metal silicide/silicon contacts are generally used to form the source and drain contacts, for example, titanium silicide (TiSi)_x) TiSi forming source and drain regions with n-type doped silicon (n-Si)_xn-Si contact.

In order to further reduce the specific resistance (p) of the metal silicide/silicon contact_c) In the current mainstream process, one skilled in the art increases the doping concentration in silicon to reduce the specific resistance (ρ) of the metal silicide/silicon contact_c) I.e., increasing the impurity activation concentration by various methods (e.g., in-situ P doping (Si: P), Dynamic Surface Annealing (DSA), etc.), thereby reducing the specific resistance (ρ) of the metal silicide/silicon contact_c). In fact, since the metal silicide/silicon contact is a schottky contact, the schottky barrier height also significantly affects the specific resistance (ρ)_c) Size of (2). For example, TiSi_xSince the fermi level of the/n-Si contact is pinned in the middle of the band gap, the schottky barrier height to electrons is high, about 0.6 eV. Thus, a higher schottky barrier height prevents the specific resistance (ρ) of the metal silicide/silicon contact_c) Is further reduced.

Therefore, there is a need to provide a semiconductor device that reduces the schottky barrier height between the metal silicide and the source and drain regions.

Disclosure of Invention

In view of the above, it is an object of the present disclosure to provide a semiconductor device and a method for manufacturing the same, which reduces a schottky barrier height between a metal silicide and source and drain regions.

According to an aspect of the present disclosure, there is provided a semiconductor device including: a semiconductor substrate having a fin; a gate intersecting the fin and a source region and a drain region in the fin on both sides of the gate; metal silicides formed at and contacting the source region and the drain region, respectively; wherein impurity dopants capable of reducing the Schottky barrier height between the metal silicide and the source region and the drain region are present at the interfaces of the metal silicide, the source region and the drain region.

Further, the impurity dopant includes at least one selected from the group consisting of: C. ge, N, P, As, O, S, Se, Te, F, Cl.

According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: forming a fin on a semiconductor substrate; forming a gate intersecting the fin; forming a source region and a drain region in the fin on two sides of the grid; depositing a dielectric on the fin; etching the dielectric to form contact trenches over the source and drain regions, respectively, to expose at least portions of the upper surfaces of the source and drain regions; performing amorphization treatment on at least part of the exposed upper surface through the contact groove; implanting impurity dopants into at least a portion of the exposed upper surface through the contact trench; after impurity dopant implantation, metal is deposited in the contact trench, and annealing is performed to form metal silicide, wherein the impurity dopant is capable of reducing the schottky barrier height between the metal silicide and the source and drain regions.

Further, during annealing, the implanted impurity dopant is precipitated at the interfaces of the metal silicide with the source and drain regions, thereby reducing the schottky barrier height between the metal silicide and the source and drain regions.

Further, the depth of the amorphous silicon region formed after the amorphization process is 10nm or less.

Further, after annealing, amorphous silicon disappears by reaction with the deposited metal and/or Solid Phase Epitaxial Regrowth (SPER).

According to the embodiment of the disclosure, the Schottky barrier height between the metal silicide and the silicon of the source region and the drain region is reduced due to the existence of the impurity dopant at the contact interface, so that the contact specific resistance is reduced, the source-drain series parasitic resistance is further reduced, and the device performance is improved.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

FIG. 1 illustrates an example FinFET according to the prior art;

fig. 2-10 are schematic cross-sectional views illustrating stages in a process flow for fabricating a semiconductor device, taken along direction a-a' in fig. 1, in accordance with an embodiment of the present disclosure.

Like reference numerals refer to like parts throughout the drawings.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

A perspective view of an example prior art FinFET is shown in fig. 1. As shown in fig. 1, the FinFET includes: a substrate 101; a fin 102 formed on a substrate 101; a gate 103 intersecting the fin 102, a gate dielectric layer being provided between the gate 103 and the fin 102; and an isolation layer. In this example, the fin 102 is integral with the substrate 101, being formed by a portion of the substrate 101. In this FinFET, under the control of the gate 103, a conductive channel may be created in the fin 102, specifically in three sidewalls (left and right sidewalls and a top wall in the figure) of the fin 102, as indicated by arrows in fig. 1. That is, the portion of the fin 102 under the gate 103 serves as a channel region, and the source region and the drain region are respectively located at two sides of the channel region.

According to an embodiment of the present disclosure, a semiconductor device (e.g., a FinFET, particularly a 3D FinFET) including a fin is provided. The semiconductor device may include: a semiconductor substrate having a fin; a gate intersecting the fin and a source region and a drain region in the fin on both sides of the gate; and metal silicides formed at and in contact with the source region and the drain region, respectively. And impurity dopants capable of reducing the Schottky barrier height between the metal silicide and the source region and the drain region exist at the contact interfaces of the metal silicide and the source region and the drain region.

Impurity dopants are precipitated at the interfaces of the metal silicide with the source region and the drain region, thereby reducing the Schottky barrier height between the metal silicide and the source region and the drain region.

The impurity dopant includes at least one selected from the group consisting of: C. ge, N, P, As, O, S, Se, Te, F, Cl.

The gate includes a high-K gate dielectric and a metal gate conductor.

The metal silicide includes titanium silicide.

The present disclosure may be embodied in various forms, some of which will be described below, and for convenience of explanation, the following will be described taking a silicon-based material as an example.

Fig. 2-10 are schematic cross-sectional views illustrating various stages in a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

As shown in fig. 2, a semiconductor substrate 101 is provided. A fin 102 is formed on the semiconductor substrate 101. The fin 102 is integral with the substrate 101 and is formed from a portion of the substrate 101. Fig. 2 shows a cross-sectional view taken in the longitudinal extension direction of the fin (i.e., in the direction a-a' in fig. 1). Over the substrate 101, a sacrificial gate stack may be formed that intersects the fin. The sacrificial gate stack may include a sacrificial gate dielectric layer 1006, a sacrificial gate conductor 1008, and a cap layer 1014, which are formed in sequence. The semiconductor substrate 101 comprises, for example, a silicon wafer, the sacrificial gate dielectric layer 1006 comprises, for example, an oxide, and the sacrificial gate conductor 1008 comprises, for example, polysilicon. After the sacrificial gate stack is formed, ion implantation (source/drain formation, etc.), spacer formation, and the like may be performed. Specifically, ion implantation is performed in the fins on both sides of the sacrificial gate stack to form source and drain regions 1002 and 1004, respectively. The source region 1002 and the drain region 1004 comprise, for example, n-type doped silicon (n-Si). A gate sidewall layer 1010 is formed on the sidewalls of the sacrificial gate stack. The gate sidewall layer 1010 may comprise a single layer or a multi-layer configuration, and may comprise various suitable dielectric materials such as SiO₂、Si₃N₄Or SiON, or a combination thereof. In addition, Shallow Trench Isolations (STI)1012 may be formed outside the source region 1002 and the drain region 1004, respectively, for device isolation.

After the above process is completed, a dielectric layer 1016 is deposited over the fins, covering the entire source 1002 and drain 1004 regions, as shown in fig. 3. Dielectric layer 1016 may comprise various suitable dielectric materials such as SiO₂、Si₃N₄Or SiON, or a combination thereof. In the case where a replacement gate process is applied, as shown in fig. 4, dielectric layer 1014 may be subjected to a planarization process such as Chemical Mechanical Polishing (CMP). The CMP may be performed until the sacrificial gate conductor 1008 is exposed.

In this way, a replacement gate process may be subsequently applied to form the final gate stack. Specifically, a gate trench may be formed inside the gate sidewall 1012, for example, by selectively etching away the sacrificial gate conductor 1008 and optionally the sacrificial gate dielectric layer 1006. In the gate trench, a real gate dielectric layer and a real gate conductor may be formed in sequence, for example by a deposition and etch back process. Specifically, as shown in fig. 5, a gate dielectric layer 1018 and a gate conductor 1020 are sequentially formed on the fin 102. The gate dielectric layer 1018 may comprise a high-K gate dielectric such as HfO₂、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al₂O₃、La₂O₃、ZrO₂(ii) LaAlO, or a combination thereof; the gate conductor layer 1020 may include a metal gate conductor such as Ti, Co, Ni, Al, W, or an alloy thereof, or a metal nitride, etc. In addition, the gate dielectric layer 1020 may also include a thin layer of oxide on which the high-K gate dielectric is formed. A work function adjusting layer (not shown) may also be formed between the gate dielectric layer 1006 and the gate conductor 1008.

After forming the gate dielectric layer 1018 and the gate conductor 1020, as shown in fig. 6, an anisotropic etch process (e.g., plasma etch, reactive ion etch, etc.) is used to open a hole in the dielectric layer 1016 to form contact trenches 1022 and 1024 over the source and drain regions 1002 and 1004, respectively, to expose portions of the upper surfaces of the source and drain regions 1002 and 1004.

After forming the contact trenches 1022 and 1024, as shown in fig. 7, portions of the upper surfaces of the exposed source and drain regions 1002 and 1004 are amorphized by the contact trenches 1022 and 1024 to form amorphized regions within the source and drain regions 1002 and 1004, respectively, under the contact trenches 1022 and 1024. For example, the amorphization process may be performed as follows. Specifically, germanium ion implantation (i.e., Ge pre-amorphization ion implantation (PAI)) may be performed, which amorphizes the shallow (≦ 10nm) surface of the source 1002 and drain 1004 regions, thereby forming amorphized regions. A pre-amorphizing ion implantation of Ge or Si may also be performed to form the amorphized region. Where the source 1002 and drain 1004 regions comprise n-type doped silicon, the amorphized regions are formed as amorphous silicon regions 1026 and 1028.

After forming amorphous silicon regions 1026 and 1028, the formed amorphous silicon regions 1026 and 1028 are impurity dopant implanted through contact trenches 1022 and 1024 as shown in fig. 8. The impurity dopant includes at least one selected from the group consisting of: C. ge, N, P, As, O, S, Se, Te, F, Cl. The implantation energy for impurity dopant implantation is between 0.5keV and 5 keV. The implanted impurity dopants enter amorphous silicon regions 1026 and 1028 and a majority of the impurity dopants are confined in amorphous silicon regions 1026 and 1028.

After the impurity dopant implantation is completed, as shown in fig. 9, metal layers 1030 and 1032 are deposited within contact trenches 1022 and 1024, and an anneal is performed to form metal silicide in amorphous silicon regions 1026 and 1028 and thereby form a contact of the metal silicide with the n-type doped silicon of the source/drain regions. The deposited metal may comprise Ti/TiN, and thus, the metal silicide formed may comprise titanium silicide (TiSi)_x). In this case, titanium silicide and n-type doped silicon (TiSi) are formed_xn-Si).

In a conventional mainstream process, in order to reduce contact resistance between a metal silicide and n-type doped silicon of a source/drain region, various methods are used to increase a doping concentration in the n-type doped silicon, such as: and the method of in-situ doping P (Si: P), Dynamic Surface Annealing (DSA) and the like is adopted to improve the impurity activation concentration. However, since the fermi level of the titanium silicide/n-type doped silicon contact is pinned in the middle of the band gap, the schottky barrier height to electrons is high, being about 0.6 eV. Therefore, in order to further reduce the contact resistance between the titanium silicide and the n-type doped silicon, in addition to increasing the doping concentration in the n-type doped silicon, it is also necessary to reduce the schottky barrier height between the titanium silicide and the n-type doped silicon.

In accordance with the principles of the present invention, metal is being formed as amorphous silicon regions 1026 and 1028 have previously been impurity dopedDuring the silicide process, the implanted impurity dopant is precipitated at the interface between the metal silicide and the source region and the drain region during the annealing process, thereby reducing the Schottky barrier height between the metal silicide and the source region and the drain region. Referring specifically to the right enlarged view of fig. 9, when the titanium reacts with the amorphous silicon to form titanium silicide 1034, the implanted impurity dopants precipitate at the interface between the titanium silicide and the n-type doped silicon, which precipitated impurity dopants 1036 will cause a reduced schottky barrier height. Therefore, the contact resistance between titanium silicide and n-type doped silicon, that is, the specific resistance ρ of the contact between titanium silicide and n-type doped silicon can be reduced_c。

Further, after annealing, the amorphous silicon of the amorphous silicon regions 1026 and 1028 disappears by reaction with the deposited metal and/or Solid Phase Epitaxy Regrowth (SPER). Specifically, as described above, during annealing, amorphous silicon reacts with titanium to form titanium silicide, and at the same time, at least part of the amorphous silicon is regrown to crystalline silicon. Thus, after annealing, the amorphous silicon of amorphous silicon regions 1026 and 1028 disappears by reacting with titanium and/or regrowing.

After forming the contact between the metal silicide having the reduced schottky barrier height and the source/drain regions, the method may further include forming a contact plug in the contact trench, as shown in fig. 10. For example, tungsten (W) may be deposited within contact trenches 1022 and 1024 to form tungsten (W) layers 1038 and 1040 on deposited metal layers (e.g., Ti/TiN)1030 and 1032, respectively; CMP is performed to planarize the upper surface of the tungsten layers 1038 and 1040. The tungsten layer may be used as a contact plug.

Thus, a semiconductor device according to an embodiment of the present disclosure is obtained. As shown in fig. 10, the semiconductor device may include: a semiconductor substrate 101 having a fin, a gate dielectric 1018 and a gate conductor 1020 formed on the fin 102 (which form a gate stack), gate spacers 1010 formed on the sidewalls of the left and right sides of the gate stack, and source 1002 and drain 1004 regions formed in the fin on either side of the gate stack. A dielectric material 1016 is formed over the fin 102. A dielectric material 1016 covers the source 1002 and drain 1004 regions and forms contact trenches therein to expose the source 1002 and drain 1004 regions toA small portion of the upper surface. Metal layers (e.g., Ti/TiN)1030 and 1032 and tungsten layers 1038 and 1040 are sequentially formed in the contact trench. Metal layers (e.g., Ti/TiN)1030 and 1032 form metal silicide 1034 at the source region 1002 and the drain region 1004, respectively, with an extracted impurity dopant 1036 at the interface of the metal silicide 1034 with the source region 1002 and the drain region 1004. The precipitated impurity dopant 1036 significantly reduces the schottky barrier height between the metal silicide 1034 and the n-type doped silicon of the source and drain regions 1002, 1004, thereby effectively reducing the specific resistance ρ of the contact_c。

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.