阅读说明：本技术 一种三维相变存储器及其控制方法 (Three-dimensional phase change memory and control method thereof ) 是由 刘峻 李博文 于 2021-05-07 设计创作，主要内容包括：本发明公开了一种三维相变存储器,包括：沿第三方向依次交替堆叠分布的至少两条导电线和至少一个相变存储单元,每个所述相变存储单元位于相邻两条导电线之间,其中,奇数条所述导电线沿第一方向延伸,偶数条所述导电线沿第二方向延伸,所述第一方向、所述第二方向与所述第三方向相互垂直；所述相变存储单元包括依次堆叠分布的第一电极、选通层、第二电极、相变存储层以及第三电极；其中,所述第三电极与所述相变存储层之间的相对赛贝克系数的绝对值大于所述第二电极与所述相变存储层之间的相对赛贝克系数的绝对值。(The invention discloses a three-dimensional phase change memory, which comprises: at least two conductive lines and at least one phase change memory cell which are sequentially and alternately stacked and distributed along a third direction, wherein each phase change memory cell is positioned between two adjacent conductive lines, odd conductive lines extend along the first direction, even conductive lines extend along the second direction, and the first direction, the second direction and the third direction are perpendicular to each other; the phase change memory unit comprises a first electrode, a gating layer, a second electrode, a phase change memory layer and a third electrode which are sequentially stacked and distributed; wherein an absolute value of a relative seebeck coefficient between the third electrode and the phase-change memory layer is larger than an absolute value of a relative seebeck coefficient between the second electrode and the phase-change memory layer.)

1. A three-dimensional phase change memory, comprising:

at least two conductive lines and at least one phase change memory cell which are sequentially and alternately stacked and distributed along a third direction, wherein each phase change memory cell is positioned between two adjacent conductive lines, odd conductive lines extend along the first direction, even conductive lines extend along the second direction, and the first direction, the second direction and the third direction are perpendicular to each other;

the phase change memory unit comprises a first electrode, a gating layer, a second electrode, a phase change memory layer and a third electrode which are sequentially stacked and distributed; wherein the content of the first and second substances,

an absolute value of a relative seebeck coefficient between the third electrode and the phase-change memory layer is larger than an absolute value of a relative seebeck coefficient between the second electrode and the phase-change memory layer.

2. The three-dimensional phase change memory of claim 1, wherein an absolute value of a relative seebeck coefficient between the second electrode and the pass layer is greater than an absolute value of a relative seebeck coefficient between the second electrode and the phase change storage layer.

3. The three-dimensional phase change memory of claim 1, wherein an absolute value of a relative seebeck coefficient between the second electrode and the gate layer is greater than an absolute value of a relative seebeck coefficient between the first electrode and the gate layer.

4. The three-dimensional phase change memory according to claim 1, wherein the at least one phase change memory cell comprises at least two phase change memory cells adjacently arranged along a third direction, one of the at least two phase change memory cells comprises a first electrode, a gate layer, a second electrode, a phase change memory layer and a third electrode which are sequentially stacked and distributed along the third direction, and the other of the at least two phase change memory cells comprises a third electrode, a phase change memory layer, a second electrode, a gate layer and a first electrode which are sequentially stacked and distributed along the third direction; and the distance between two phase change memory layers in the at least two phase change memory units is smaller than the distance between two gating layers.

5. The three-dimensional phase change memory according to claim 1, wherein an absolute value of a relative seebeck coefficient between the phase change memory layer and the third electrode and/or an absolute value of a relative seebeck coefficient between the gate layer and the second electrode is greater than 200 mV/K.

6. A control method of a three-dimensional phase change memory is characterized by comprising the following steps:

providing a three-dimensional phase change memory comprising: at least two conductive lines and at least one phase change memory cell which are sequentially and alternately stacked and distributed along a third direction, wherein each phase change memory cell is positioned between two adjacent conductive lines, odd conductive lines extend along the first direction, even conductive lines extend along the second direction, and the first direction, the second direction and the third direction are perpendicular to each other; the phase change memory unit comprises a first electrode, a gating layer, a second electrode, a phase change memory layer and a third electrode which are sequentially stacked and distributed along a third direction; wherein an absolute value of a relative seebeck coefficient between the third electrode and the phase-change memory layer is larger than an absolute value of a relative seebeck coefficient between the second electrode and the phase-change memory layer;

applying a voltage to the conductive line, the voltage being controlled such that a current direction in the three-dimensional phase-change memory flows from the gate layer to the phase-change storage layer.

7. The method of controlling a three-dimensional phase change memory according to claim 6, comprising:

the phase change memory unit comprises at least two phase change memory units which are adjacently arranged along a third direction, one of the at least two phase change memory units comprises a first electrode, a gating layer, a second electrode, a phase change memory layer and a third electrode which are sequentially stacked and distributed along the third direction, and the other of the at least two phase change memory units comprises a third electrode, a phase change memory layer, a second electrode, a gating layer and a first electrode which are sequentially stacked and distributed along the third direction; and the distance between two phase change memory layers in the at least two phase change memory units is smaller than the distance between two gating layers.

8. The method of claim 7, wherein the applying the voltage to the conductive line comprises:

the conductive lines between two adjacent phase change memory layers are grounded or negatively biased, and the other conductive lines are positively biased.

9. The three-dimensional phase change memory of claim 6, wherein an absolute value of a relative seebeck coefficient between the second electrode and the pass layer is greater than an absolute value of a relative seebeck coefficient between the second electrode and the phase change storage layer.

10. The three-dimensional phase change memory of claim 6, wherein an absolute value of a relative seebeck coefficient between the second electrode and the gating layer is greater than an absolute value of a relative seebeck coefficient between the first electrode and the gating layer.

Technical Field

The invention relates to the technical field of storage devices, in particular to a three-dimensional phase change memory and a control method thereof.

Background

Memory (Memory) is a Memory device used in modern information technology to store information. With the increasing demands of various electronic devices for integration and data storage density, it is increasingly difficult for a common two-dimensional memory device to meet the demands, and in such a situation, a three-dimensional (3D) memory has come into play.

The 3D memory includes a memory array and peripheral devices for controlling signals to and from the memory array. For example, a Phase Change Memory (PCM) may convert an electrical signal into a thermal signal to apply heat and quench to a Phase Change material to drive the Phase Change material to reversibly Change between a crystalline state and an amorphous state, thereby implementing data storage. In the working process, due to the existence of the heat dissipation problem, the power consumption of the three-dimensional phase change memory is larger, and the energy utilization rate is low. Therefore, improving the efficiency of the three-dimensional phase change memory is an important research direction in the field.

Disclosure of Invention

In view of the above, the present invention provides a three-dimensional phase change memory and a control method thereof.

In order to achieve the purpose, the technical scheme of the invention is realized as follows:

a three-dimensional phase change memory, comprising:

at least two conductive lines and at least one phase change memory cell which are sequentially and alternately stacked and distributed along a third direction, wherein each phase change memory cell is positioned between two adjacent conductive lines, odd conductive lines extend along the first direction, even conductive lines extend along the second direction, and the first direction, the second direction and the third direction are perpendicular to each other;

the phase change memory unit comprises a first electrode, a gating layer, a second electrode, a phase change memory layer and a third electrode which are sequentially stacked and distributed; wherein the content of the first and second substances,

an absolute value of a relative seebeck coefficient between the third electrode and the phase-change memory layer is larger than an absolute value of a relative seebeck coefficient between the second electrode and the phase-change memory layer.

In the foregoing scheme, an absolute value of a relative seebeck coefficient between the second electrode and the pass layer is larger than an absolute value of a relative seebeck coefficient between the second electrode and the phase change memory layer.

In the above scheme, an absolute value of a relative seebeck coefficient between the second electrode and the gate layer is larger than an absolute value of a relative seebeck coefficient between the first electrode and the gate layer.

In the above scheme, the at least one phase change memory cell includes at least two phase change memory cells adjacently disposed along a third direction, one of the at least two phase change memory cells includes a first electrode, a gate layer, a second electrode, a phase change memory layer, and a third electrode that are sequentially stacked and distributed along the third direction, and the other of the at least two phase change memory cells includes a third electrode, a phase change memory layer, a second electrode, a gate layer, and a first electrode that are sequentially stacked and distributed along the third direction; and the distance between two phase change memory layers in the at least two phase change memory units is smaller than the distance between two gating layers.

In the above scheme, an absolute value of a relative seebeck coefficient between the phase change memory layer and the third electrode and/or an absolute value of a relative seebeck coefficient between the gate layer and the second electrode is greater than 200 mV/K.

The invention also provides a control method of the three-dimensional phase change memory, which comprises the following steps:

providing a three-dimensional phase change memory comprising: at least two conductive lines and at least one phase change memory cell which are sequentially and alternately stacked and distributed along a third direction, wherein each phase change memory cell is positioned between two adjacent conductive lines, odd conductive lines extend along the first direction, even conductive lines extend along the second direction, and the first direction, the second direction and the third direction are perpendicular to each other; the phase change memory unit comprises a first electrode, a gating layer, a second electrode, a phase change memory layer and a third electrode which are sequentially stacked and distributed along a third direction; wherein an absolute value of a relative seebeck coefficient between the third electrode and the phase-change memory layer is larger than an absolute value of a relative seebeck coefficient between the second electrode and the phase-change memory layer;

applying a voltage to the conductive line, the voltage being controlled such that a current direction in the three-dimensional phase-change memory flows from the gate layer to the phase-change storage layer.

In the scheme, the method comprises the following steps: the phase change memory unit comprises at least two phase change memory units which are adjacently arranged along a third direction, one of the at least two phase change memory units comprises a first electrode, a gating layer, a second electrode, a phase change memory layer and a third electrode which are sequentially stacked and distributed along the third direction, and the other of the at least two phase change memory units comprises a third electrode, a phase change memory layer, a second electrode, a gating layer and a first electrode which are sequentially stacked and distributed along the third direction; and the distance between two phase change memory layers in the at least two phase change memory units is smaller than the distance between two gating layers.

In the above aspect, the applying a voltage to the conductive line includes: the conductive lines between two adjacent phase change memory layers are grounded or negatively biased, and the other conductive lines are positively biased.

In the foregoing scheme, an absolute value of a relative seebeck coefficient between the second electrode and the pass layer is larger than an absolute value of a relative seebeck coefficient between the second electrode and the phase change memory layer.

In the above scheme, an absolute value of a relative seebeck coefficient between the second electrode and the gate layer is larger than an absolute value of a relative seebeck coefficient between the first electrode and the gate layer.

The three-dimensional phase change memory provided by the embodiment of the invention comprises: at least two conductive lines and at least one phase change memory cell which are sequentially and alternately stacked and distributed along a third direction, wherein each phase change memory cell is positioned between two adjacent conductive lines, odd conductive lines extend along the first direction, even conductive lines extend along the second direction, and the first direction, the second direction and the third direction are perpendicular to each other; the phase change memory unit comprises a first electrode, a gating layer, a second electrode, a phase change memory layer and a third electrode which are sequentially stacked and distributed; wherein an absolute value of a relative seebeck coefficient between the third electrode and the phase-change memory layer is larger than an absolute value of a relative seebeck coefficient between the second electrode and the phase-change memory layer. Therefore, by adopting the three-dimensional phase change memory structure, the extra joule heat generated by the pletier effect is utilized to realize the effects of reducing the heat loss of the three-dimensional phase change memory, improving the energy utilization rate, reducing the power consumption and the like.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

FIG. 1 is a schematic structural diagram of a three-dimensional phase change memory according to the related art;

FIG. 2 is a schematic diagram of a three-dimensional phase change memory;

FIG. 3 is a schematic structural diagram of a three-dimensional phase change memory according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a three-dimensional phase change memory according to another embodiment of the present invention;

FIG. 5 is a flowchart illustrating a method for controlling a three-dimensional phase change memory according to an embodiment of the present invention;

FIGS. 6a-6b are schematic diagrams of the pleiter thermal distribution of the three-dimensional phase change memory in different current directions.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.

In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. And the discussion of a second element, component, region, layer or section does not necessarily imply that a first element, component, region, layer or section is present in the invention.

Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

As used in the following description, the term "three-dimensional memory" refers to a semiconductor device having the following memory cells: the memory cells are arranged vertically on a laterally oriented substrate such that the number of memory cells increases in the vertical direction relative to the substrate. As used herein, the term "vertical" means nominally perpendicular to a lateral surface of a substrate.

FIG. 1 is a schematic structural diagram of a three-dimensional phase change memory according to the related art; fig. 2 is a schematic diagram of a three-dimensional phase change memory. As shown in fig. 1, a three-dimensional phase change memory 100 in the related art includes a word line 101 extending along a first direction and a bit line 102 extending along a second direction, and a phase change memory cell 110 disposed along a third direction and located at an intersection of the word line 101 and the bit line 102, where the phase change memory cell 110 includes a lower electrode 111, a gate layer 112, an intermediate electrode 113, a phase change memory layer 114, and an upper electrode 115 sequentially stacked and distributed along the third direction. Wherein the upper electrode 115 and the intermediate electrode 113 can perform the phase change memory layer 114 according to an electric signalHeating and quenching operations are performed to drive the phase change memory layer 114 into a phase change. Specifically, as shown in fig. 2, in the writing operation, upper electrode 115 and intermediate electrode 113 perform a heating operation on phase-change memory layer 114, so that the temperature of at least a portion of the region in the phase-change memory layer is raised to crystallization temperature T_cIn the above, the phase change memory layer is changed from the amorphous state to the crystalline state at this time, and the resistance is reduced; in the erasing operation, upper electrode 115 and intermediate electrode 113 perform a quenching operation on phase-change memory layer 114 according to an electric signal, so that the temperature of phase-change memory layer 114 is raised to melting point temperature T_mAfter that, the phase change memory layer is rapidly cooled, so that the crystalline phase change memory layer is driven to be amorphous and is converted into an amorphous structure, and the resistance is increased. That is, the storage of the three-dimensional phase change memory is realized by converting an electric signal into a thermal signal and then driving the change of the internal structure of the material of the phase change memory layer. However, the thermal driving process is difficult to avoid the problem of thermal diffusion, as shown in fig. 1, heat diffuses out from the thermal core region of the phase-change memory layer 114. The three-dimensional phase change memory has the problems of large power consumption, low thermal efficiency and the like caused by the heat lost due to thermal diffusion.

The embodiment of the invention provides a three-dimensional phase change memory 300, and fig. 3 is a schematic structural diagram of the three-dimensional phase change memory 300 according to the embodiment of the invention. As shown in fig. 3, the three-dimensional phase change memory 300 includes:

at least two conductive lines 301 and at least one phase change memory cell 310 are sequentially and alternately stacked and distributed along a third direction, wherein each phase change memory cell 310 is located between two adjacent conductive lines 301, odd conductive lines 301-1 extend along a first direction, even conductive lines 301-2 extend along a second direction, and the first direction, the second direction and the third direction are perpendicular to each other;

the phase-change memory unit 310 comprises a first electrode 311, a gate layer 312, a second electrode 313, a phase-change memory layer 314 and a third electrode 315 which are sequentially stacked and distributed along a third direction; wherein the content of the first and second substances,

the absolute value of the relative seebeck coefficient between the third electrode 315 and the phase change memory layer 314 is larger than the absolute value of the relative seebeck coefficient between the second electrode 313 and the phase change memory layer 314.

In practice, the material of the conductive line includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof, and the phase-change memory layer 314 may be a P-type semiconductor. The odd conductive lines 301-1 extending in the first direction and the even conductive lines 301-2 extending in the second direction may be used as word lines (wordlines) or bit lines (bitlines), respectively. It should be understood that the three-dimensional phase change memory structure with more than 4 stacked layers illustrated in fig. 3 is only an illustration of some embodiments of the present invention, and it should be understood that the three-dimensional phase change memory 300 provided by the embodiments of the present invention may also be a single stacked layer structure, a 2 stacked layer structure and a 3 stacked layer structure.

According to the pletier effect, when a current passes through a circuit composed of a conductor and a semiconductor, in addition to irreversible joule heat, additional heat generation or cooling is generated according to the direction of the current. Specifically, when current flows from the semiconductor to the conductor, the electrons will release energy and the material will heat up, and conversely, when current flows from the conductor to the semiconductor, the electrons will absorb energy and will cool.

In conjunction with the three-dimensional phase-change memory 300 shown in fig. 3, it can be seen that when a current flows from the second electrode 313 to the phase-change memory layer 314 along the direction of the gate layer 312 toward the phase-change memory layer 314, the current flows from the second electrode 313 to the semiconductor, and the electrons absorb energy, so that a heat absorption effect is generated at the interface between the second electrode 313 and the phase-change memory layer 314, and a cold junction is generated at the side of the phase-change memory layer 314 close to the second electrode 313. Current continues to flow from the phase-change memory layer 314 to the third electrode 315, which is equivalent to flowing from a semiconductor to a conductor, and electrons will discharge energy, which will produce a heat-release effect at the interface of the phase-change memory layer 314 and the third electrode 315, and a hot terminal at the side of the phase-change memory layer 314 near the third electrode 315. The additional heat release effect generated at the interface of the phase change memory layer 314 and the third electrode 315, in addition to joule heat, can strengthen the thermal environment of the phase change memory layer 314, which has beneficial effects on improving the thermal efficiency of the three-dimensional phase change memory and reducing power consumption, and conversely, the heat absorption effect generated at the interface of the phase change memory layer 314 and the second electrode 313 at least partially offsets the heat generated by the second electrode 313 and the third electrode 315 for heating and quenching the phase change memory layer 314, which can result in low thermal efficiency and is not favorable for device performance.

The different materials have specific seebeck coefficient values, the relative seebeck coefficients of the two materials are the difference of the seebeck coefficients of the two materials, and the absolute value of the relative seebeck coefficients of the two materials is directly related to the heat absorbed or released by the pletier effect between the two materials. According to the embodiment of the invention, the specific relative seebeck coefficient is obtained by specifically selecting the materials of the related layers in the phase change memory unit 310, so that the thermal environment around the phase change memory layer 314 can be regulated and controlled, the energy utilization efficiency is improved, and the power consumption is reduced.

Specifically, in the above embodiment, the absolute value of the relative seebeck coefficient between the third electrode 315 and the phase change memory layer 314 is larger than the absolute value of the relative seebeck coefficient between the second electrode 313 and the phase change memory layer 314. Specifically, the relative seebeck coefficient α 34 between the second electrode 313 and the phase-change memory layer 314 is α 3 — α 4, where α 3 is the seebeck coefficient of the second electrode 313, and α 4 is the seebeck coefficient of the phase-change memory layer 314; a relative seebeck coefficient α 45 between the phase change memory layer 314 and the third electrode 315 is α 4- α 5, where α 4 is the seebeck coefficient of the phase change memory layer 314, and α 5 is the seebeck coefficient of the third electrode 315. In the three-dimensional phase change memory 300 provided in the embodiment of the present invention, the absolute value of the relative seebeck coefficient between the third electrode 315 and the phase change memory layer 314 is set to be greater than the absolute value of the relative seebeck coefficient between the second electrode 313 and the phase change memory layer 314, so that the heat released at the interface between the third electrode 315 and the phase change memory layer 314 is greater than the heat absorbed at the interface between the phase change memory layer 314 and the second electrode 313, and thus, for the phase change memory layer 314, the heating effect can be ensured to be greater than the cooling effect, and finally, the heating effect beneficial to enhancing the thermal environment is obtained, so that the energy utilization efficiency of heating and quenching is improved, the operating voltage can be reduced, the memory efficiency is improved, and the power consumption is reduced.

Typically, the gate layer 312 is made of a semiconductor material, and thus, additional pleiter endothermic and exothermic effects are also generated between the gate layer 312 and the first and second electrodes 311 and 313. Specifically, referring to fig. 3, when the current in the phase-change memory cell 310 flows along the direction of the gate layer 312 toward the phase-change memory layer 314, the current flows from the first electrode 311 to the gate layer 312, i.e., from the conductor to the semiconductor, the electrons absorb heat, which is equivalent to generating a cooling effect at the interface between the gate layer 312 and the first electrode 311, and the side of the gate layer 312 close to the first electrode 311 becomes the cold end; when a current flows from the gate layer 312 to the second electrode 313, the electrons release heat, which is equivalent to a heat generation effect at the interface between the gate layer 312 and the second electrode 313, and the side of the gate layer 312 close to the second electrode 313 becomes a hot side. The hot side of the pass layer 312 is close to the phase change memory layer 314, having a heating effect on the phase change memory layer 314.

In some embodiments, the absolute value of the relative seebeck coefficient between the second electrode 313 and the pass layer 312 is greater than the absolute value of the relative seebeck coefficient between the second electrode 313 and the phase change storage layer 314. Specifically, the relative seebeck coefficient α 23 between the gating layer 312 and the second electrode 313 is α 2 — α 3, where α 2 is the seebeck coefficient of the gating layer 312, and α 3 is the seebeck coefficient of the second electrode 313; the relative seebeck coefficient between the second electrode 313 and the phase-change memory layer 314 is α 34 ═ α 3 — α 4, where α 3 is the seebeck coefficient of the second electrode 313 and α 4 is the seebeck coefficient of the phase-change memory layer 314. In the three-dimensional phase change memory 300 provided in the embodiment of the present invention, the absolute value of the relative seebeck coefficient between the second electrode 313 and the gating layer 312 is set to be greater than the absolute value of the relative seebeck coefficient between the second electrode 313 and the phase change memory layer 314, so that the heat released at the interface between the second electrode 313 and the gating layer 312 is greater than the heat absorbed at the interface between the phase change memory layer 314 and the second electrode 313, thereby canceling out the adverse refrigeration effect at the interface between the phase change memory layer 314 and the second electrode 313, facilitating to strengthen the thermal environment around the phase change memory layer 314, and improving the utilization efficiency of energy.

In one embodiment, the absolute value of the relative seebeck coefficient between the second electrode 313 and the gating layer 312 is greater than the absolute value of the relative seebeck coefficient between the first electrode 311 and the gating layer 312. Specifically, the relative seebeck coefficient α 23 between the gating layer 312 and the second electrode 313 is α 2 — α 3, where α 2 is the seebeck coefficient of the gating layer 312, and α 3 is the seebeck coefficient of the second electrode 313; the relative seebeck coefficient between the first electrode 311 and the gate layer 312 is α 12 ═ α 1 — α 2, where α 1 is the seebeck coefficient of the first electrode 311 and α 2 is the seebeck coefficient of the gate layer 312. In the three-dimensional phase change memory 300 provided by the embodiment of the present invention, the absolute value of the relative seebeck coefficient between the second electrode 313 and the gating layer 312 is set to be greater than the absolute value of the relative seebeck coefficient between the first electrode 311 and the gating layer 312, so that the amount of heat released at the interface between the second electrode 313 and the gating layer 312 is greater than the amount of heat absorbed at the interface between the first electrode 311 and the gating layer 312, and thus it can be ensured that the whole pletier effect around the gating layer 312 is heat release, which is beneficial to enhancing the thermal environment around the phase change memory layer 314 and improving the utilization efficiency of energy.

In an embodiment, the absolute value of the relative seebeck coefficient between the phase-change memory layer 314 and the third electrode 315 and/or the absolute value of the relative seebeck coefficient between the gate layer 312 and the second electrode 313 is greater than 200 mV/K; in a preferred embodiment, the absolute value of the relative seebeck coefficient between the phase-change memory layer 314 and the third electrode 315 and/or the absolute value of the relative seebeck coefficient between the gate layer 312 and the second electrode 313 is larger than 500 mV/K. Through the parameter setting, the pleiter heat release effect at the interface of the third electrode 315 and the phase-change memory layer 314 and at the interface of the second electrode 313 and the gate layer 312 can be enhanced, so that the power consumption is reduced.

In one embodiment, the absolute value of the relative seebeck coefficient between the second electrode 313 and the phase-change memory layer 314 and/or the absolute value of the relative seebeck coefficient between the first electrode 311 and the gate layer 312 is less than 100 mV/K; in a preferred embodiment, the absolute value of the relative seebeck coefficient between the second electrode 313 and the phase-change memory layer 314 and/or the absolute value of the relative seebeck coefficient between the first electrode 311 and the gate layer 312 is less than 20 mV/K. Through the parameter setting, the refrigeration effect on the interface of the second electrode 313 and the gating layer 315 and the interface of the second electrode 313 and the phase change storage layer 314 can be reduced as much as possible, and unnecessary heat loss is avoided, so that the energy utilization efficiency is improved, and the power consumption is reduced.

In some embodiments, the first electrode, the gate layer, the second electrode, the phase change memory layer, and the fifth electrode described in embodiments of the present invention may be formed by consulting a table of relative seebeck coefficients to obtain a material having a particular relative seebeck coefficient.

In an embodiment, as shown in fig. 4, the at least one phase-change memory cell includes at least two phase-change memory cells adjacently disposed along a third direction, one of the at least two phase-change memory cells includes a first electrode 311, a gate layer 312, a second electrode 313, a phase-change memory layer 314, and a third electrode 315 sequentially stacked and distributed along the third direction, and another of the at least two phase-change memory cells includes a third electrode 315, a phase-change memory layer 314, a second electrode 313, a gate layer 312, and a first electrode 311 sequentially stacked and distributed along the third direction; and the distance between two of the phase change memory layers 314 in the at least two phase change memory cells 310 is smaller than the distance between two of the pass layers.

Referring to fig. 4, it can be seen that the nth phase change memory cell 310 includes a third electrode 315, a phase change memory layer 314, a second electrode 313, a gate layer 312, and a first electrode 311 which are sequentially stacked and distributed along a third direction, the n-1 th phase change memory cell 310 adjacent to the nth phase change memory cell 310 includes a first electrode 311, a gate layer 312, a second electrode 313, a phase change memory layer 314, and a third electrode 315 which are sequentially stacked and distributed along the third direction, and a distance D between two phase change memory layers 314 of the nth phase change memory cell 310 and the n-1 th phase change memory cell 310 is smaller than a distance D between two gate layers 312 of the nth phase change memory cell 310 and the n-1 th phase change memory cell 310.

When current flows along the direction from the gate layer 312 to the phase change memory layer 314, the interface between the phase change memory layer 314 and the third electrode 315 in the nth phase change memory cell 310 is a hot side, the interface between the gate layer 312 and the first electrode 311 is a cold side, the interface between the phase change memory layer 314 and the third electrode 315 in the n-1 th phase change memory cell 310 is a hot side, and the interface between the gate layer 312 and the first electrode 311 is a cold side. By setting the stacking manner of the layers in the nth phase change memory cell 310 and the n-1 th phase change memory cell 310 to be opposite, and setting the phase change memory layers 314 of two adjacent phase change memory cells to be close to each other, the hot ends of two adjacent phase change memory cells can be close to each other, so that cold-hot-cold distribution is formed, which can further inhibit the heat dissipation effect and reduce the loss caused by heat dissipation.

In a more preferred embodiment, one of any two phase change memory cells 310 adjacent to each other in the third direction includes a first electrode 311, a gate layer 312, a second electrode 313, a phase change memory layer 314 and a third electrode 315 that are sequentially stacked and distributed in the third direction, and the other of any two phase change memory cells 310 adjacent to each other in the third direction includes a third electrode 315, a phase change memory layer 314, a second electrode 313, a gate layer 312 and a first electrode 311 that are sequentially stacked and distributed in the third direction; and the distance between the two phase change memory layers 314 of any two phase change memory cells 310 adjacent in the third direction is smaller than the distance between the two pass layers 312.

In this way, the hot ends of adjacent phase change memory cells are close together, thereby further suppressing the heat dissipation effect.

The embodiment of the present invention further provides a method for controlling a three-dimensional phase change memory, as shown in fig. 5, including:

step S501 provides a three-dimensional phase change memory, which includes: at least two conductive lines and at least one phase change memory cell which are sequentially and alternately stacked and distributed along a third direction, wherein each phase change memory cell is positioned between two adjacent conductive lines, odd conductive lines extend along the first direction, even conductive lines extend along the second direction, and the first direction, the second direction and the third direction are perpendicular to each other; the phase change memory unit comprises a first electrode, a gating layer, a second electrode, a phase change memory layer and a third electrode which are sequentially stacked and distributed; wherein an absolute value of a relative seebeck coefficient between the third electrode and the phase-change memory layer is larger than an absolute value of a relative seebeck coefficient between the second electrode and the phase-change memory layer;

step S502 applies a voltage to the conductive line, the voltage being controlled such that a current direction in the three-dimensional phase-change memory flows from the gate layer to the phase-change storage layer.

As shown in fig. 6a, when a current flows along a direction from the phase-change storage layer 314 to the gate layer 312, a pletier heat release effect is generated at interfaces between the phase-change storage layer 314 and the second electrode 313 and between the gate layer 312 and the first electrode 311, a pletier heat absorption effect is generated at interfaces between the phase-change storage layer 314 and the third electrode 315 and between the gate layer 312 and the second electrode 313, one side of the gate layer 312 close to the phase-change storage layer 314 is a cold side, and the cold side is close to the hot side of the phase-change storage layer 314, which inevitably causes heat at the hot side of the phase-change storage layer 314 to be absorbed by the cold side, thereby causing unnecessary heat loss and a problem of low energy utilization rate. However, as shown in fig. 6b, in the control method of the three-dimensional phase-change memory according to the embodiment of the present invention, the current flows along the direction from the gate layer 312 to the phase-change memory layer 314, the pletier heat release effect is generated at the interfaces between the phase-change memory layer 314 and the third electrode 315, and between the gate layer 312 and the second electrode 313, and the pletier heat absorption effect is generated at the interfaces between the gate layer 312 and the first electrode 311, and between the phase-change memory layer 314 and the second electrode 313, then the side of the gate layer 312 away from the phase-change memory layer 314 is a cold side, and the side close to the phase-change memory layer 314 is a hot side, so that a certain heating effect can be generated on the phase-change memory layer 314, which is beneficial to strengthen the thermal environment near the phase-change memory layer 314 and reduce power consumption.

In an embodiment, as shown in fig. 4, the at least one phase-change memory cell includes at least two phase-change memory cells adjacently disposed along a third direction, one of the at least two phase-change memory cells includes a first electrode 311, a gate layer 312, a second electrode 313, a phase-change memory layer 314, and a third electrode 315 sequentially stacked and distributed along the third direction, and another of the at least two phase-change memory cells includes a third electrode 315, a phase-change memory layer 314, a second electrode 313, a gate layer 312, and a first electrode 311 sequentially stacked and distributed along the third direction; and the distance between two of the phase change memory layers 314 in the at least two phase change memory cells 310 is smaller than the distance between two of the pass layers 312.

Referring to fig. 4, it can be seen that the nth phase change memory cell 310 includes a third electrode 315, a phase change memory layer 314, a second electrode 313, a gate layer 312, and a first electrode 311 which are sequentially stacked and distributed along the third direction, the n-1 th phase change memory cell 310 adjacent to the nth phase change memory cell 310 includes a first electrode 311, a gate layer 312, a second electrode 313, a phase change memory layer 314, and a third electrode 315 which are sequentially stacked and distributed along the third direction, and a distance D between two phase change memory layers 314 of the nth phase change memory cell 310 and the n-1 th phase change memory cell 310 is smaller than a distance D between two gate layers 312 of the nth phase change memory cell 310 and the n-1 th phase change memory cell 310.

In a more preferred embodiment, one of any two phase change memory cells 310 adjacent to each other in the third direction includes a first electrode 311, a gate layer 312, a second electrode 313, a phase change memory layer 314 and a third electrode 315 that are sequentially stacked and distributed in the third direction, and the other of any two phase change memory cells 310 adjacent to each other in the third direction includes a third electrode 315, a phase change memory layer 314, a second electrode 313, a gate layer 312 and a first electrode 311 that are sequentially stacked and distributed in the third direction; and the distance between the two phase change memory layers 314 of any two phase change memory cells 310 adjacent in the third direction is smaller than the distance between the two pass layers 312.

In some embodiments, the hot ends of at least two adjacent phase change memory cells are close together, so that the heat dissipation effect can be further suppressed.

In an embodiment, to control a current direction in the three-dimensional phase-change memory 300 provided in the above embodiments from a gate layer to a phase-change memory cell, the applying a voltage to a conductive line includes:

and the conductive lines which are positioned between two adjacent phase change storage layers and are close to the two phase change storage layers are grounded or negatively biased, and the other conductive lines are positively biased.

The above operation will be specifically explained with reference to fig. 4. As shown in FIG. 4, in actual operation, the conductive lines between the nth phase change memory layer 314 in the nth phase change memory cell 310 and the (n + 1) th phase change memory layer 314 in the (n + 1) th phase change memory cell 310 and closer to the two phase change memory layers 314, i.e., the even numbered conductive lines 301-2 in FIG. 4 are grounded or negatively biased, and the other odd numbered conductive lines 301-1 are positively biased.

Specifically, for example, the voltage on even conductive line 301-2 is grounded or the voltage on even conductive line 301-2 is reduced below a first threshold, and the voltage on odd conductive line 301-1 is increased above a second threshold voltage. In actual practice, the first threshold may range, for example, from-6 to-19V, and the second threshold may range, for example, from 6-19V.

In some embodiments, the absolute value of the relative seebeck coefficient between the second electrode 313 and the pass layer 312 is greater than the absolute value of the relative seebeck coefficient between the second electrode 313 and the phase change storage layer 314. In the three-dimensional phase change memory 300 provided in the embodiment of the present invention, the absolute value of the relative seebeck coefficient between the third electrode 315 and the phase change memory layer 314 is set to be greater than the absolute value of the relative seebeck coefficient between the second electrode 313 and the phase change memory layer 314, so that the heat released at the interface between the third electrode 315 and the phase change memory layer 314 is greater than the heat absorbed at the interface between the phase change memory layer 314 and the second electrode 313, and thus, for the phase change memory layer 314, the heating effect can be ensured to be greater than the cooling effect, and finally, the heating effect beneficial to enhancing the thermal environment is obtained, so that the energy utilization efficiency of heating and quenching is improved, the operating voltage can be reduced, the memory efficiency is improved, and the power consumption is reduced.

In one embodiment, the absolute value of the relative seebeck coefficient between the second electrode 313 and the gating layer 312 is greater than the absolute value of the relative seebeck coefficient between the first electrode 311 and the gating layer 312. In the three-dimensional phase change memory 300 provided in the embodiment of the present invention, the absolute value of the relative seebeck coefficient between the second electrode 313 and the gating layer 312 is set to be greater than the absolute value of the relative seebeck coefficient between the second electrode 313 and the phase change memory layer 314, so that the heat released at the interface between the second electrode 313 and the gating layer 312 is greater than the heat absorbed at the interface between the phase change memory layer 314 and the second electrode 313, thereby canceling out the adverse refrigeration effect at the interface between the phase change memory layer 314 and the second electrode 313, facilitating to strengthen the thermal environment around the phase change memory layer 314, and improving the utilization efficiency of energy.

In an embodiment, the absolute value of the relative seebeck coefficient between the phase-change memory layer 314 and the third electrode 315 and/or the absolute value of the relative seebeck coefficient between the gate layer 312 and the second electrode 313 is greater than 200 mV/K; in a preferred embodiment, the absolute value of the relative seebeck coefficient between the phase-change memory layer 314 and the third electrode 315 and/or the absolute value of the relative seebeck coefficient between the gate layer 312 and the second electrode 313 is larger than 500 mV/K. Through the parameter setting, the pleiter heat release effect at the interface of the third electrode 315 and the phase-change memory layer 314 and at the interface of the second electrode 313 and the gate layer 312 can be enhanced, so that the power consumption is reduced.

In one embodiment, the absolute value of the relative seebeck coefficient between the second electrode 313 and the phase-change memory layer 314 and/or the absolute value of the relative seebeck coefficient between the first electrode 311 and the gate layer 312 is less than 100 mV/K; in a preferred embodiment, the absolute value of the relative seebeck coefficient between the second electrode 313 and the phase-change memory layer 314 and/or the absolute value of the relative seebeck coefficient between the first electrode 311 and the gate layer 312 is less than 20 mV/K. Through the parameter setting, the refrigeration effect on the interface of the second electrode 313 and the gating layer 315 and the interface of the second electrode 313 and the phase change storage layer 314 can be reduced as much as possible, and unnecessary heat loss is avoided, so that the energy utilization efficiency is improved, and the power consumption is reduced.

It should be noted that the embodiments of the three-dimensional phase change memory and the control method thereof provided by the invention belong to the same concept; the technical features of the technical means described in the embodiments may be arbitrarily combined without conflict.

The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements, etc. that are within the spirit and principle of the present invention should be included in the present invention.